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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sys_timer.vhd] - Blame information for rev 184

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Line No. Rev Author Line
1 180 jshamlet
-- Copyright (c)2006, 2016, 2019 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Units :  o8_sys_timer
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-- Description:  Provides an 8-bit microsecond resolution timer for generating
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--            :   periodic interrupts for the Open8 CPU.
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--
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-- Notes      :  It is possible to set the value to zero, resulting in the
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--            :   output staying high indefinitely. This may cause an issue if
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--            :   the output is connected to an interrupt input.
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--            :  Also provides uSec_Tick as an output
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--
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-- Revision History
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-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry      07/28/11 Design Start
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-- Seth Henry      12/19/19 Renamed Tmr_Out to Interrupt
38 167 jshamlet
 
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library ieee;
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use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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  use ieee.std_logic_arith.all;
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  use ieee.std_logic_misc.all;
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library work;
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  use work.open8_pkg.all;
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entity o8_sys_timer is
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generic(
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  Sys_Freq              : real;
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  Reset_Level           : std_logic;
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  Address               : ADDRESS_TYPE
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);
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port(
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  Clock                 : in  std_logic;
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  Reset                 : in  std_logic;
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  uSec_Tick             : out std_logic;
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  --
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  Bus_Address           : in  ADDRESS_TYPE;
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  Wr_Enable             : in  std_logic;
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  Wr_Data               : in  DATA_TYPE;
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  Rd_Enable             : in  std_logic;
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  Rd_Data               : out DATA_TYPE;
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  Interrupt             : out std_logic
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);
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end entity;
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architecture behave of o8_sys_timer is
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  constant User_Addr    : ADDRESS_TYPE := Address;
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  alias  Comp_Addr      is Bus_Address(15 downto 0);
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  signal Addr_Match     : std_logic;
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  signal Wr_En          : std_logic;
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  signal Wr_Data_q      : DATA_TYPE;
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  signal Rd_En          : std_logic;
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  signal Rd_En_q        : std_logic;
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  signal Interval       : DATA_TYPE;
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  signal Timer_Cnt      : DATA_TYPE;
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  -- The ceil_log2 function returns the minimum register width required to
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  --  hold the supplied integer.
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  function ceil_log2 (x : in natural) return natural is
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    variable retval          : natural;
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  begin
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    retval                   := 1;
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    while ((2**retval) - 1) < x loop
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      retval                 := retval + 1;
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    end loop;
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    return retval;
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  end ceil_log2;
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  constant DLY_1USEC_VAL: integer := integer(Sys_Freq / 1000000.0);
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  constant DLY_1USEC_WDT: integer := ceil_log2(DLY_1USEC_VAL - 1);
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  constant DLY_1USEC    : std_logic_vector :=
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                      conv_std_logic_vector(DLY_1USEC_VAL - 1, DLY_1USEC_WDT);
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  signal uSec_Cntr      : std_logic_vector( DLY_1USEC_WDT - 1 downto 0 )
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                          := (others => '0');
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  signal uSec_Tick_i      : std_logic;
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begin
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  uSec_Tick             <= uSec_Tick_i;
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  Addr_Match            <= '1' when Comp_Addr = User_Addr else '0';
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  io_reg: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Wr_En             <= '0';
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      Wr_Data_q         <= x"00";
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      Rd_En             <= '0';
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      Rd_Data           <= x"00";
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      Interval          <= x"00";
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    elsif( rising_edge( Clock ) )then
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      Wr_En             <= Addr_Match and Wr_Enable;
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      Wr_Data_q         <= Wr_Data;
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      if( Wr_En = '1' )then
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        Interval        <= Wr_Data_q;
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      end if;
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      Rd_Data           <= (others => '0');
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      Rd_En             <= Addr_Match and Rd_Enable;
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      if( Rd_En = '1' )then
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        Rd_Data         <= Interval;
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      end if;
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    end if;
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  end process;
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  uSec_Tick_i_proc: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      uSec_Cntr         <= (others => '0');
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      uSec_Tick_i       <= '0';
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    elsif( rising_edge( Clock ) )then
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      uSec_Cntr         <= uSec_Cntr - 1;
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      uSec_Tick_i       <= '0';
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      if( uSec_Cntr = 0 )then
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        uSec_Cntr       <= DLY_1USEC;
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        uSec_Tick_i     <= '1';
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      end if;
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    end if;
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  end process;
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  Interval_proc: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Timer_Cnt         <= x"00";
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      Interrupt         <= '0';
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    elsif( rising_edge(Clock) )then
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      Interrupt         <= '0';
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      Timer_Cnt         <= Timer_Cnt - uSec_Tick_i;
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      if( or_reduce(Timer_Cnt) = '0' )then
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        Timer_Cnt       <= Interval;
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        Interrupt       <= or_reduce(Interval); -- Only trigger on Int > 0
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      end if;
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    end if;
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  end process;
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end architecture;

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