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-- Copyright (c)2006, 2016, 2019, 2020 Jeremy Seth Henry

-- All rights reserved.

--

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-- modification, are permitted provided that the following conditions are met:

--     * Redistributions of source code must retain the above copyright

--       notice, this list of conditions and the following disclaimer.

--     * Redistributions in binary form must reproduce the above copyright

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--       where applicable (as part of a user interface, debugging port, etc.)

--

-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY

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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY

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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

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--

-- VHDL Units :  o8_sys_timer

-- Description:  Provides an 8-bit microsecond resolution timer for generating

--            :   periodic interrupts for the Open8 CPU.

--

--

-- Revision History

-- Author          Date     Change

------------------ -------- ---------------------------------------------------

-- Seth Henry      07/28/11 Design Start

-- Seth Henry      12/19/19 Renamed Tmr_Out to Interrupt

-- Seth Henry      04/09/20 Modified timer update logic to reset the timer on

--                           interval write.

-- Seth Henry      04/16/20 Modified to use Open8 bus record

-- Seth Henry      05/18/20 Added write qualification input

library ieee;

use ieee.std_logic_1164.all;

  use ieee.std_logic_unsigned.all;

  use ieee.std_logic_arith.all;

  use ieee.std_logic_misc.all;

library work;

  use work.open8_pkg.all;

entity o8_sys_timer is

generic(

  mSec_Resolution            : boolean := FALSE;

  Address                    : ADDRESS_TYPE

);

port(

  Open8_Bus                  : in  OPEN8_BUS_TYPE;

  Write_Qual                 : in  std_logic := '1';

  Rd_Data                    : out DATA_TYPE;

  Interrupt                  : out std_logic

);

end entity;

architecture behave of o8_sys_timer is

  alias Clock                is Open8_Bus.Clock;

  alias Reset                is Open8_Bus.Reset;

  alias uSec_Tick            is Open8_Bus.uSec_Tick;

  constant User_Addr         : ADDRESS_TYPE := Address;

  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);

  signal Addr_Match          : std_logic := '0';

  signal Wr_En_d             : std_logic;

  signal Wr_En_q             : std_logic := '0';

  alias  Wr_Data_d           is Open8_Bus.Wr_Data;

  signal Wr_Data_q           : DATA_TYPE := x"00";

  signal Rd_En_d               : std_logic := '0';

  signal Rd_En_q             : std_logic := '0';

  signal Interval            : DATA_TYPE := x"00";

  signal Update_Interval     : std_logic;

  signal Timer_Cnt           : DATA_TYPE := x"00";

  constant MSEC_DELAY        : std_logic_vector(9 downto 0) :=

                                conv_std_logic_vector(1000,10);

  signal mSec_Timer          : std_logic_vector(9 downto 0) := (others => '0');

  signal Timer_Tick          : std_logic := '0';

begin

  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';

  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En;

  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;

mSec_Resolution_enabled : if( mSec_Resolution )generate

  mSec_Tick_proc: process( Clock, Reset )

  begin

    if( Reset = Reset_Level )then

      mSec_Timer             <= (others => '0');

      Timer_Tick             <= '0';

    elsif( rising_edge(Clock) )then

      mSec_Timer             <= mSec_Timer - uSec_Tick;

      Timer_Tick             <= '0';

      if( mSec_Timer = 0 )then

        mSec_Timer           <= MSEC_DELAY;

        Timer_Tick           <= '1';

      end if;

    end if;

  end process;

end generate;

uSec_Resolution_enabled : if( not mSec_Resolution )generate

  Timer_Tick                 <= uSec_Tick;

end generate;

  io_reg: process( Clock, Reset )

  begin

    if( Reset = Reset_Level )then

      Wr_En_q                <= '0';

      Wr_Data_q              <= x"00";

      Rd_En_q                <= '0';

      Rd_Data                <= OPEN8_NULLBUS;

      Interval               <= x"00";

      Update_Interval        <= '0';

    elsif( rising_edge( Clock ) )then

      Wr_En_q                <= Wr_En_d;

      Wr_Data_q              <= Wr_Data_d;

      Update_Interval        <= Wr_En_q and Write_Qual;

      if( Wr_En_q = '1' and Write_Qual = '1' )then

        Interval             <= Wr_Data_q;

      end if;

      Rd_Data                <= (others => '0');

      Rd_En_q                <= Rd_En_d;

      if( Rd_En_q = '1' )then

        Rd_Data              <= Interval;

      end if;

    end if;

  end process;

  Interval_proc: process( Clock, Reset )

  begin

    if( Reset = Reset_Level )then

      Timer_Cnt              <= x"00";

      Interrupt              <= '0';

    elsif( rising_edge(Clock) )then

      Interrupt              <= '0';

      Timer_Cnt              <= Timer_Cnt - Timer_Tick;

      if( Update_Interval = '1' )then

        Timer_Cnt            <= Interval;

      elsif( or_reduce(Timer_Cnt) = '0' )then

        Timer_Cnt            <= Interval;

        Interrupt            <= or_reduce(Interval); -- Only trigger on Int > 0

      end if;

    end if;

  end process;

end architecture;