OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sys_timer.vhd] - Blame information for rev 284

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 246 jshamlet
-- Copyright (c)2006, 2016, 2019, 2020 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL Units :  o8_sys_timer
25 273 jshamlet
-- Description:  Provides an 8-bit milli/microsecond resolution timer for
26
--            :   generating periodic interrupts for the Open8 CPU.
27 246 jshamlet
--
28
--
29
-- Revision History
30
-- Author          Date     Change
31
------------------ -------- ---------------------------------------------------
32
-- Seth Henry      07/28/11 Design Start
33
-- Seth Henry      12/19/19 Renamed Tmr_Out to Interrupt
34
-- Seth Henry      04/09/20 Modified timer update logic to reset the timer on
35
--                           interval write.
36
-- Seth Henry      04/16/20 Modified to use Open8 bus record
37
-- Seth Henry      05/18/20 Added write qualification input
38 273 jshamlet
-- Seth Henry      11/01/20 Changed description to note different resolutions
39 246 jshamlet
 
40
library ieee;
41
use ieee.std_logic_1164.all;
42
  use ieee.std_logic_unsigned.all;
43
  use ieee.std_logic_arith.all;
44
  use ieee.std_logic_misc.all;
45
 
46
library work;
47
  use work.open8_pkg.all;
48
 
49
entity o8_sys_timer is
50
generic(
51
  mSec_Resolution            : boolean := FALSE;
52
  Address                    : ADDRESS_TYPE
53
);
54
port(
55
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
56
  Write_Qual                 : in  std_logic := '1';
57
  Rd_Data                    : out DATA_TYPE;
58
  Interrupt                  : out std_logic
59
);
60
end entity;
61
 
62
architecture behave of o8_sys_timer is
63
 
64
  alias Clock                is Open8_Bus.Clock;
65
  alias Reset                is Open8_Bus.Reset;
66
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
67
 
68
  constant User_Addr         : ADDRESS_TYPE := Address;
69
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);
70
  signal Addr_Match          : std_logic := '0';
71
 
72
  signal Wr_En_d             : std_logic;
73
  signal Wr_En_q             : std_logic := '0';
74
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
75
  signal Wr_Data_q           : DATA_TYPE := x"00";
76
  signal Rd_En_d               : std_logic := '0';
77
  signal Rd_En_q             : std_logic := '0';
78
 
79
  signal Interval            : DATA_TYPE := x"00";
80
  signal Update_Interval     : std_logic;
81
  signal Timer_Cnt           : DATA_TYPE := x"00";
82
 
83
  constant MSEC_DELAY        : std_logic_vector(9 downto 0) :=
84
                                conv_std_logic_vector(1000,10);
85
 
86
  signal mSec_Timer          : std_logic_vector(9 downto 0) := (others => '0');
87
 
88
  signal Timer_Tick          : std_logic := '0';
89
 
90
begin
91
 
92
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
93
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En;
94
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
95
 
96
mSec_Resolution_enabled : if( mSec_Resolution )generate
97
 
98
  mSec_Tick_proc: process( Clock, Reset )
99
  begin
100
    if( Reset = Reset_Level )then
101
      mSec_Timer             <= (others => '0');
102
      Timer_Tick             <= '0';
103
    elsif( rising_edge(Clock) )then
104
      mSec_Timer             <= mSec_Timer - uSec_Tick;
105
      Timer_Tick             <= '0';
106
      if( mSec_Timer = 0 )then
107
        mSec_Timer           <= MSEC_DELAY;
108
        Timer_Tick           <= '1';
109
      end if;
110
    end if;
111
  end process;
112
 
113
end generate;
114
 
115
uSec_Resolution_enabled : if( not mSec_Resolution )generate
116
 
117
  Timer_Tick                 <= uSec_Tick;
118
 
119
end generate;
120
 
121
  io_reg: process( Clock, Reset )
122
  begin
123
    if( Reset = Reset_Level )then
124
      Wr_En_q                <= '0';
125
      Wr_Data_q              <= x"00";
126
      Rd_En_q                <= '0';
127
      Rd_Data                <= OPEN8_NULLBUS;
128
      Interval               <= x"00";
129
      Update_Interval        <= '0';
130
    elsif( rising_edge( Clock ) )then
131
      Wr_En_q                <= Wr_En_d;
132
      Wr_Data_q              <= Wr_Data_d;
133
 
134
      Update_Interval        <= Wr_En_q and Write_Qual;
135
      if( Wr_En_q = '1' and Write_Qual = '1' )then
136
        Interval             <= Wr_Data_q;
137
      end if;
138
 
139
      Rd_Data                <= (others => '0');
140
      Rd_En_q                <= Rd_En_d;
141
      if( Rd_En_q = '1' )then
142
        Rd_Data              <= Interval;
143
      end if;
144
    end if;
145
  end process;
146
 
147
  Interval_proc: process( Clock, Reset )
148
  begin
149
    if( Reset = Reset_Level )then
150
      Timer_Cnt              <= x"00";
151
      Interrupt              <= '0';
152
    elsif( rising_edge(Clock) )then
153
      Interrupt              <= '0';
154
      Timer_Cnt              <= Timer_Cnt - Timer_Tick;
155
      if( Update_Interval = '1' )then
156
        Timer_Cnt            <= Interval;
157
      elsif( or_reduce(Timer_Cnt) = '0' )then
158
        Timer_Cnt            <= Interval;
159
        Interrupt            <= or_reduce(Interval); -- Only trigger on Int > 0
160
      end if;
161
    end if;
162
  end process;
163
 
164
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.