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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_vdsm12.vhd] - Blame information for rev 224

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Line No. Rev Author Line
1 194 jshamlet
-- Copyright (c)2019, 2020 Jeremy Seth Henry
2 180 jshamlet
-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
12
--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 194 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 180 jshamlet
--
24
-- VHDL Units :  o8_vdsm12
25
-- Description:  12-bit variable delta-sigma modulator. Requires Open8_pkg.vhd
26
--
27
-- Register Map:
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-- Offset  Bitfield Description                        Read/Write
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--   0x0   AAAAAAAA Pending DAC Level (7:0)            (R/W)
30 213 jshamlet
--   0x1   ----AAAA Pending DAC Level (11:8)           (R/W)
31 180 jshamlet
--   0x2   -------- Clear DAC Output (on write)        (WO)
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--   0x3   AAAAAAAA Update DAC Output (on write)       (RO)
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--
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-- Revision History
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-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
37
-- Seth Henry      12/18/19 Design start
38 213 jshamlet
-- Seth Henry      04/10/20 Code Cleanup
39 224 jshamlet
-- Seth Henry      04/16/20 Modified to use Open8 bus record
40 180 jshamlet
 
41
library ieee;
42
use ieee.std_logic_1164.all;
43
use ieee.std_logic_unsigned.all;
44
use ieee.std_logic_arith.all;
45
 
46
library work;
47
  use work.open8_pkg.all;
48
 
49
entity o8_vdsm12 is
50
generic(
51 224 jshamlet
  Default_Value              : std_logic_vector(11 downto 0) := x"000";
52 217 jshamlet
  Address                    : ADDRESS_TYPE
53 180 jshamlet
);
54
port(
55 223 jshamlet
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
56 217 jshamlet
  Rd_Data                    : out DATA_TYPE;
57 180 jshamlet
  --
58 224 jshamlet
  DACOut                     : out std_logic
59 180 jshamlet
);
60
end entity;
61
 
62
architecture behave of o8_vdsm12 is
63
 
64 224 jshamlet
  alias Clock                is Open8_Bus.Clock;
65
  alias Reset                is Open8_Bus.Reset;
66
 
67 217 jshamlet
  constant User_Addr         : std_logic_vector(15 downto 2)
68
                               := Address(15 downto 2);
69 223 jshamlet
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
70
  alias  Reg_Addr            is Open8_Bus.Address(1 downto 0);
71 217 jshamlet
  signal Reg_Sel             : std_logic_vector(1 downto 0) := "00";
72
  signal Addr_Match          : std_logic := '0';
73
  signal Wr_En               : std_logic := '0';
74
  signal Wr_Data_q           : DATA_TYPE := x"00";
75
  signal Rd_En               : std_logic := '0';
76 180 jshamlet
 
77 217 jshamlet
  constant DAC_Width         : integer := 12;
78 180 jshamlet
 
79 217 jshamlet
  signal DAC_Val_LB          : std_logic_vector(7 downto 0) := x"00";
80
  signal DAC_Val_UB          : std_logic_vector(3 downto 0) := x"0";
81
  signal DAC_Val             : std_logic_vector(DAC_Width-1 downto 0)  :=
82
                                (others => '0');
83 180 jshamlet
 
84 217 jshamlet
  constant DELTA_1_I         : integer := 1;
85
  constant DELTA_2_I         : integer := 5;
86
  constant DELTA_3_I         : integer := 25;
87
  constant DELTA_4_I         : integer := 75;
88
  constant DELTA_5_I         : integer := 125;
89
  constant DELTA_6_I         : integer := 250;
90
  constant DELTA_7_I         : integer := 500;
91
  constant DELTA_8_I         : integer := 1000;
92
  constant DELTA_9_I         : integer := 2000;
93
  constant DELTA_10_I        : integer := 3000;
94 180 jshamlet
 
95 217 jshamlet
  constant DELTA_1           : std_logic_vector(DAC_Width-1 downto 0) :=
96
                                conv_std_logic_vector(DELTA_1_I, DAC_Width);
97
  constant DELTA_2           : std_logic_vector(DAC_Width-1 downto 0) :=
98
                                conv_std_logic_vector(DELTA_2_I, DAC_Width);
99
  constant DELTA_3           : std_logic_vector(DAC_Width-1 downto 0) :=
100
                                conv_std_logic_vector(DELTA_3_I, DAC_Width);
101
  constant DELTA_4           : std_logic_vector(DAC_Width-1 downto 0) :=
102
                                conv_std_logic_vector(DELTA_4_I, DAC_Width);
103
  constant DELTA_5           : std_logic_vector(DAC_Width-1 downto 0) :=
104
                                conv_std_logic_vector(DELTA_5_I, DAC_Width);
105
  constant DELTA_6           : std_logic_vector(DAC_Width-1 downto 0) :=
106
                                conv_std_logic_vector(DELTA_6_I, DAC_Width);
107
  constant DELTA_7           : std_logic_vector(DAC_Width-1 downto 0) :=
108
                                conv_std_logic_vector(DELTA_7_I, DAC_Width);
109
  constant DELTA_8           : std_logic_vector(DAC_Width-1 downto 0) :=
110
                                conv_std_logic_vector(DELTA_8_I, DAC_Width);
111
  constant DELTA_9           : std_logic_vector(DAC_Width-1 downto 0) :=
112
                                conv_std_logic_vector(DELTA_9_I, DAC_Width);
113
  constant DELTA_10          : std_logic_vector(DAC_Width-1 downto 0) :=
114
                                conv_std_logic_vector(DELTA_10_I, DAC_Width);
115 180 jshamlet
 
116 217 jshamlet
  constant MAX_PERIOD        : integer := 2**DAC_Width;
117
  constant DIV_WIDTH         : integer := DAC_Width * 2;
118 180 jshamlet
 
119 217 jshamlet
  constant PADJ_1_I          : integer := DELTA_1_I * MAX_PERIOD;
120
  constant PADJ_2_I          : integer := DELTA_2_I * MAX_PERIOD;
121
  constant PADJ_3_I          : integer := DELTA_3_I * MAX_PERIOD;
122
  constant PADJ_4_I          : integer := DELTA_4_I * MAX_PERIOD;
123
  constant PADJ_5_I          : integer := DELTA_5_I * MAX_PERIOD;
124
  constant PADJ_6_I          : integer := DELTA_6_I * MAX_PERIOD;
125
  constant PADJ_7_I          : integer := DELTA_7_I * MAX_PERIOD;
126
  constant PADJ_8_I          : integer := DELTA_8_I * MAX_PERIOD;
127
  constant PADJ_9_I          : integer := DELTA_9_I * MAX_PERIOD;
128
  constant PADJ_10_I         : integer := DELTA_10_I * MAX_PERIOD;
129 180 jshamlet
 
130 217 jshamlet
  constant PADJ_1            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
131
                                conv_std_logic_vector(PADJ_1_I,DIV_WIDTH);
132
  constant PADJ_2            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
133
                                conv_std_logic_vector(PADJ_2_I,DIV_WIDTH);
134
  constant PADJ_3            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
135
                                conv_std_logic_vector(PADJ_3_I,DIV_WIDTH);
136
  constant PADJ_4            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
137
                                conv_std_logic_vector(PADJ_4_I,DIV_WIDTH);
138
  constant PADJ_5            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
139
                                conv_std_logic_vector(PADJ_5_I,DIV_WIDTH);
140
  constant PADJ_6            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
141
                                conv_std_logic_vector(PADJ_6_I,DIV_WIDTH);
142
  constant PADJ_7            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
143
                                conv_std_logic_vector(PADJ_7_I,DIV_WIDTH);
144
  constant PADJ_8            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
145
                                conv_std_logic_vector(PADJ_8_I,DIV_WIDTH);
146
  constant PADJ_9            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
147
                                conv_std_logic_vector(PADJ_9_I,DIV_WIDTH);
148
  constant PADJ_10           : std_logic_vector(DIV_WIDTH-1 downto 0) :=
149
                                conv_std_logic_vector(PADJ_10_I,DIV_WIDTH);
150 180 jshamlet
 
151 217 jshamlet
  signal DACin_q             : std_logic_vector(DAC_Width-1 downto 0) :=
152
                                (others => '0');
153 180 jshamlet
 
154 217 jshamlet
  signal Divisor             : std_logic_vector(DIV_WIDTH-1 downto 0) :=
155
                                (others => '0');
156 180 jshamlet
 
157 217 jshamlet
  signal Dividend            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
158
                                (others => '0');
159 180 jshamlet
 
160 217 jshamlet
  signal q                   : std_logic_vector(DIV_WIDTH*2-1 downto 0) :=
161
                                (others => '0');
162 213 jshamlet
 
163 217 jshamlet
  signal diff                : std_logic_vector(DIV_WIDTH downto 0) :=
164
                                (others => '0');
165 213 jshamlet
 
166 217 jshamlet
  constant CB                : integer := ceil_log2(DIV_WIDTH);
167
  signal count               : std_logic_vector(CB-1 downto 0) :=
168
                                (others => '0');
169 180 jshamlet
 
170 217 jshamlet
  signal Next_Width          : std_logic_vector(DAC_Width-1 downto 0) :=
171
                                (others => '0');
172 180 jshamlet
 
173 217 jshamlet
  signal Next_Period         : std_logic_vector(DAC_Width-1 downto 0) :=
174
                                (others => '0');
175 180 jshamlet
 
176 217 jshamlet
  signal PWM_Width           : std_logic_vector(DAC_Width-1 downto 0) :=
177
                                (others => '0');
178 180 jshamlet
 
179 217 jshamlet
  signal PWM_Period          : std_logic_vector(DAC_Width-1 downto 0) :=
180
                                (others => '0');
181 180 jshamlet
 
182 217 jshamlet
  signal Width_Ctr           : std_logic_vector(DAC_Width-1 downto 0) :=
183
                                (others => '0');
184 213 jshamlet
 
185 217 jshamlet
  signal Period_Ctr          : std_logic_vector(DAC_Width-1 downto 0) :=
186
                                (others => '0');
187 213 jshamlet
 
188 180 jshamlet
begin
189
 
190 217 jshamlet
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
191 180 jshamlet
 
192
  io_reg: process( Clock, Reset )
193
  begin
194
    if( Reset = Reset_Level )then
195 217 jshamlet
      Reg_Sel                <= "00";
196
      Rd_En                  <= '0';
197
      Rd_Data                <= OPEN8_NULLBUS;
198
      Wr_En                  <= '0';
199
      Wr_Data_q              <= x"00";
200
      DAC_Val_LB             <= x"00";
201
      DAC_Val_UB             <= x"0";
202 224 jshamlet
      DAC_Val                <= Default_Value;
203 180 jshamlet
    elsif( rising_edge( Clock ) )then
204 217 jshamlet
      Reg_Sel                <= Reg_Addr;
205 180 jshamlet
 
206 223 jshamlet
      Wr_En                  <= Addr_Match and Open8_Bus.Wr_En;
207
      Wr_Data_q              <= Open8_Bus.Wr_Data;
208 180 jshamlet
      if( Wr_En = '1' )then
209
        case( Reg_Sel )is
210
          when "00" =>
211 217 jshamlet
            DAC_Val_LB       <= Wr_Data_q;
212 180 jshamlet
          when "01" =>
213 217 jshamlet
            DAC_Val_UB       <= Wr_Data_q(3 downto 0);
214 180 jshamlet
          when "10" =>
215 217 jshamlet
            DAC_Val          <= (others => '0');
216 180 jshamlet
          when "11" =>
217 217 jshamlet
            DAC_Val          <= DAC_Val_UB & DAC_Val_LB;
218 180 jshamlet
          when others => null;
219
        end case;
220
      end if;
221
 
222 217 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
223 223 jshamlet
      Rd_En                  <= Addr_Match and Open8_Bus.Rd_En;
224 180 jshamlet
      if( Rd_En = '1' )then
225
        case( Reg_Sel )is
226
          when "00" =>
227 217 jshamlet
            Rd_Data          <= DAC_Val_LB;
228 180 jshamlet
          when "01" =>
229 217 jshamlet
            Rd_Data          <= x"0" & DAC_Val_UB;
230 180 jshamlet
          when others => null;
231
        end case;
232
      end if;
233
    end if;
234
  end process;
235
 
236 217 jshamlet
  diff                       <= ('0' & q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
237
                                ('0' & Divisor);
238 180 jshamlet
 
239
  Dividend   <= PADJ_2  when DACin_q >= DELTA_2_I and DACin_q < DELTA_3_I else
240
                PADJ_3  when DACin_q >= DELTA_3_I and DACin_q < DELTA_4_I else
241
                PADJ_4  when DACin_q >= DELTA_4_I and DACin_q < DELTA_5_I else
242
                PADJ_5  when DACin_q >= DELTA_5_I and DACin_q < DELTA_6_I else
243
                PADJ_6  when DACin_q >= DELTA_6_I and DACin_q < DELTA_7_I else
244
                PADJ_7  when DACin_q >= DELTA_7_I and DACin_q < DELTA_8_I else
245
                PADJ_8  when DACin_q >= DELTA_8_I and DACin_q < DELTA_9_I else
246
                PADJ_9  when DACin_q >= DELTA_9_I and DACin_q < DELTA_10_I else
247
                PADJ_10 when DACin_q >= DELTA_10_I else
248
                PADJ_1;
249
 
250
  Next_Width <= DELTA_1  when DACin_q >= DELTA_1_I and DACin_q < DELTA_2_I else
251
                DELTA_2  when DACin_q >= DELTA_2_I and DACin_q < DELTA_3_I else
252
                DELTA_3  when DACin_q >= DELTA_3_I and DACin_q < DELTA_4_I else
253
                DELTA_4  when DACin_q >= DELTA_4_I and DACin_q < DELTA_5_I else
254
                DELTA_5  when DACin_q >= DELTA_5_I and DACin_q < DELTA_6_I else
255
                DELTA_6  when DACin_q >= DELTA_6_I and DACin_q < DELTA_7_I else
256
                DELTA_7  when DACin_q >= DELTA_7_I and DACin_q < DELTA_8_I else
257
                DELTA_8  when DACin_q >= DELTA_8_I and DACin_q < DELTA_9_I else
258
                DELTA_9  when DACin_q >= DELTA_9_I and DACin_q < DELTA_10_I else
259
                DELTA_10 when DACin_q >= DELTA_10_I else
260
                (others => '0');
261
 
262 217 jshamlet
  Next_Period                <= q(DAC_Width-1 downto 0) - 1;
263 191 jshamlet
 
264 180 jshamlet
  vDSM_proc: process( Clock, Reset )
265
  begin
266
    if( Reset = Reset_Level )then
267 217 jshamlet
      q                      <= (others => '0');
268
      count                  <= (others => '1');
269
      Divisor                <= (others => '0');
270
      DACin_q                <= (others => '0');
271
      PWM_Width              <= (others => '0');
272
      PWM_Period             <= (others => '0');
273
      Period_Ctr             <= (others => '0');
274
      Width_Ctr              <= (others => '0');
275 224 jshamlet
      DACOut                 <= '0';
276 180 jshamlet
    elsif( rising_edge(Clock) )then
277 217 jshamlet
      q                      <= diff(DIV_WIDTH-1 downto 0) &
278
                                q(DIV_WIDTH-2 downto 0) & '1';
279 180 jshamlet
      if( diff(DIV_WIDTH) = '1' )then
280 217 jshamlet
        q                    <= q(DIV_WIDTH*2-2 downto 0) & '0';
281 180 jshamlet
      end if;
282
 
283 217 jshamlet
      count                  <= count + 1;
284 180 jshamlet
      if( count = DIV_WIDTH )then
285 217 jshamlet
        PWM_Width            <= Next_Width;
286
        PWM_Period           <= Next_Period;
287
        DACin_q              <= DAC_val;
288
        Divisor              <= (others => '0');
289 180 jshamlet
        Divisor(DAC_Width-1 downto 0) <= DACin_q;
290 217 jshamlet
        q                   <= conv_std_logic_vector(0,DIV_WIDTH) & Dividend;
291
        count               <= (others => '0');
292 180 jshamlet
      end if;
293
 
294 217 jshamlet
      Period_Ctr            <= Period_Ctr - 1;
295
      Width_Ctr             <= Width_Ctr - 1;
296 180 jshamlet
 
297 224 jshamlet
      DACOut                <= '1';
298 180 jshamlet
      if( Width_Ctr = 0 )then
299 224 jshamlet
        DACOut              <= '0';
300 217 jshamlet
        Width_Ctr           <= (others => '0');
301 180 jshamlet
      end if;
302
 
303
      if( Period_Ctr = 0 )then
304 217 jshamlet
        Period_Ctr          <= PWM_Period;
305
        Width_Ctr           <= PWM_Width;
306 180 jshamlet
      end if;
307
 
308
    end if;
309
  end process;
310
 
311
end architecture;

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