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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_vdsm12.vhd] - Blame information for rev 279

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Line No. Rev Author Line
1 194 jshamlet
-- Copyright (c)2019, 2020 Jeremy Seth Henry
2 180 jshamlet
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 194 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 180 jshamlet
--
24
-- VHDL Units :  o8_vdsm12
25
-- Description:  12-bit variable delta-sigma modulator. Requires Open8_pkg.vhd
26
--
27
-- Register Map:
28
-- Offset  Bitfield Description                        Read/Write
29
--   0x0   AAAAAAAA Pending DAC Level (7:0)            (R/W)
30 213 jshamlet
--   0x1   ----AAAA Pending DAC Level (11:8)           (R/W)
31 180 jshamlet
--   0x2   -------- Clear DAC Output (on write)        (WO)
32
--   0x3   AAAAAAAA Update DAC Output (on write)       (RO)
33
--
34
-- Revision History
35
-- Author          Date     Change
36
------------------ -------- ---------------------------------------------------
37
-- Seth Henry      12/18/19 Design start
38 213 jshamlet
-- Seth Henry      04/10/20 Code Cleanup
39 224 jshamlet
-- Seth Henry      04/16/20 Modified to use Open8 bus record
40 244 jshamlet
-- Seth Henry      05/18/20 Added write qualification input
41 180 jshamlet
 
42
library ieee;
43
use ieee.std_logic_1164.all;
44
use ieee.std_logic_unsigned.all;
45
use ieee.std_logic_arith.all;
46 268 jshamlet
use ieee.std_logic_misc.all;
47 180 jshamlet
 
48
library work;
49
  use work.open8_pkg.all;
50
 
51
entity o8_vdsm12 is
52
generic(
53 268 jshamlet
  Invert_Output              : boolean := FALSE;
54 224 jshamlet
  Default_Value              : std_logic_vector(11 downto 0) := x"000";
55 217 jshamlet
  Address                    : ADDRESS_TYPE
56 180 jshamlet
);
57
port(
58 223 jshamlet
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
59 244 jshamlet
  Write_Qual                 : in  std_logic := '1';
60 217 jshamlet
  Rd_Data                    : out DATA_TYPE;
61 180 jshamlet
  --
62 224 jshamlet
  DACOut                     : out std_logic
63 180 jshamlet
);
64
end entity;
65
 
66
architecture behave of o8_vdsm12 is
67
 
68 224 jshamlet
  alias Clock                is Open8_Bus.Clock;
69
  alias Reset                is Open8_Bus.Reset;
70
 
71 217 jshamlet
  constant User_Addr         : std_logic_vector(15 downto 2)
72
                               := Address(15 downto 2);
73 223 jshamlet
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
74 244 jshamlet
  signal Addr_Match          : std_logic;
75
 
76
  alias  Reg_Sel_d           is Open8_Bus.Address(1 downto 0);
77
  signal Reg_Sel_q           : std_logic_vector(1 downto 0) := "00";
78
  signal Wr_En_d             : std_logic := '0';
79
  signal Wr_En_q             : std_logic := '0';
80
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
81 217 jshamlet
  signal Wr_Data_q           : DATA_TYPE := x"00";
82 244 jshamlet
  signal Rd_En_d             : std_logic := '0';
83
  signal Rd_En_q             : std_logic := '0';
84 180 jshamlet
 
85 217 jshamlet
  constant DAC_Width         : integer := 12;
86 180 jshamlet
 
87 217 jshamlet
  signal DAC_Val_LB          : std_logic_vector(7 downto 0) := x"00";
88
  signal DAC_Val_UB          : std_logic_vector(3 downto 0) := x"0";
89
  signal DAC_Val             : std_logic_vector(DAC_Width-1 downto 0)  :=
90
                                (others => '0');
91 180 jshamlet
 
92 217 jshamlet
  constant DELTA_1_I         : integer := 1;
93
  constant DELTA_2_I         : integer := 5;
94
  constant DELTA_3_I         : integer := 25;
95
  constant DELTA_4_I         : integer := 75;
96
  constant DELTA_5_I         : integer := 125;
97
  constant DELTA_6_I         : integer := 250;
98
  constant DELTA_7_I         : integer := 500;
99
  constant DELTA_8_I         : integer := 1000;
100
  constant DELTA_9_I         : integer := 2000;
101
  constant DELTA_10_I        : integer := 3000;
102 180 jshamlet
 
103 217 jshamlet
  constant DELTA_1           : std_logic_vector(DAC_Width-1 downto 0) :=
104
                                conv_std_logic_vector(DELTA_1_I, DAC_Width);
105
  constant DELTA_2           : std_logic_vector(DAC_Width-1 downto 0) :=
106
                                conv_std_logic_vector(DELTA_2_I, DAC_Width);
107
  constant DELTA_3           : std_logic_vector(DAC_Width-1 downto 0) :=
108
                                conv_std_logic_vector(DELTA_3_I, DAC_Width);
109
  constant DELTA_4           : std_logic_vector(DAC_Width-1 downto 0) :=
110
                                conv_std_logic_vector(DELTA_4_I, DAC_Width);
111
  constant DELTA_5           : std_logic_vector(DAC_Width-1 downto 0) :=
112
                                conv_std_logic_vector(DELTA_5_I, DAC_Width);
113
  constant DELTA_6           : std_logic_vector(DAC_Width-1 downto 0) :=
114
                                conv_std_logic_vector(DELTA_6_I, DAC_Width);
115
  constant DELTA_7           : std_logic_vector(DAC_Width-1 downto 0) :=
116
                                conv_std_logic_vector(DELTA_7_I, DAC_Width);
117
  constant DELTA_8           : std_logic_vector(DAC_Width-1 downto 0) :=
118
                                conv_std_logic_vector(DELTA_8_I, DAC_Width);
119
  constant DELTA_9           : std_logic_vector(DAC_Width-1 downto 0) :=
120
                                conv_std_logic_vector(DELTA_9_I, DAC_Width);
121
  constant DELTA_10          : std_logic_vector(DAC_Width-1 downto 0) :=
122
                                conv_std_logic_vector(DELTA_10_I, DAC_Width);
123 180 jshamlet
 
124 217 jshamlet
  constant MAX_PERIOD        : integer := 2**DAC_Width;
125
  constant DIV_WIDTH         : integer := DAC_Width * 2;
126 180 jshamlet
 
127 217 jshamlet
  constant PADJ_1_I          : integer := DELTA_1_I * MAX_PERIOD;
128
  constant PADJ_2_I          : integer := DELTA_2_I * MAX_PERIOD;
129
  constant PADJ_3_I          : integer := DELTA_3_I * MAX_PERIOD;
130
  constant PADJ_4_I          : integer := DELTA_4_I * MAX_PERIOD;
131
  constant PADJ_5_I          : integer := DELTA_5_I * MAX_PERIOD;
132
  constant PADJ_6_I          : integer := DELTA_6_I * MAX_PERIOD;
133
  constant PADJ_7_I          : integer := DELTA_7_I * MAX_PERIOD;
134
  constant PADJ_8_I          : integer := DELTA_8_I * MAX_PERIOD;
135
  constant PADJ_9_I          : integer := DELTA_9_I * MAX_PERIOD;
136
  constant PADJ_10_I         : integer := DELTA_10_I * MAX_PERIOD;
137 180 jshamlet
 
138 217 jshamlet
  constant PADJ_1            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
139
                                conv_std_logic_vector(PADJ_1_I,DIV_WIDTH);
140
  constant PADJ_2            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
141
                                conv_std_logic_vector(PADJ_2_I,DIV_WIDTH);
142
  constant PADJ_3            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
143
                                conv_std_logic_vector(PADJ_3_I,DIV_WIDTH);
144
  constant PADJ_4            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
145
                                conv_std_logic_vector(PADJ_4_I,DIV_WIDTH);
146
  constant PADJ_5            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
147
                                conv_std_logic_vector(PADJ_5_I,DIV_WIDTH);
148
  constant PADJ_6            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
149
                                conv_std_logic_vector(PADJ_6_I,DIV_WIDTH);
150
  constant PADJ_7            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
151
                                conv_std_logic_vector(PADJ_7_I,DIV_WIDTH);
152
  constant PADJ_8            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
153
                                conv_std_logic_vector(PADJ_8_I,DIV_WIDTH);
154
  constant PADJ_9            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
155
                                conv_std_logic_vector(PADJ_9_I,DIV_WIDTH);
156
  constant PADJ_10           : std_logic_vector(DIV_WIDTH-1 downto 0) :=
157
                                conv_std_logic_vector(PADJ_10_I,DIV_WIDTH);
158 180 jshamlet
 
159 217 jshamlet
  signal DACin_q             : std_logic_vector(DAC_Width-1 downto 0) :=
160
                                (others => '0');
161 180 jshamlet
 
162 217 jshamlet
  signal Divisor             : std_logic_vector(DIV_WIDTH-1 downto 0) :=
163
                                (others => '0');
164 180 jshamlet
 
165 217 jshamlet
  signal Dividend            : std_logic_vector(DIV_WIDTH-1 downto 0) :=
166
                                (others => '0');
167 180 jshamlet
 
168 217 jshamlet
  signal q                   : std_logic_vector(DIV_WIDTH*2-1 downto 0) :=
169
                                (others => '0');
170 213 jshamlet
 
171 217 jshamlet
  signal diff                : std_logic_vector(DIV_WIDTH downto 0) :=
172
                                (others => '0');
173 213 jshamlet
 
174 217 jshamlet
  constant CB                : integer := ceil_log2(DIV_WIDTH);
175
  signal count               : std_logic_vector(CB-1 downto 0) :=
176
                                (others => '0');
177 180 jshamlet
 
178 217 jshamlet
  signal Next_Width          : std_logic_vector(DAC_Width-1 downto 0) :=
179
                                (others => '0');
180 180 jshamlet
 
181 217 jshamlet
  signal Next_Period         : std_logic_vector(DAC_Width-1 downto 0) :=
182
                                (others => '0');
183 180 jshamlet
 
184 217 jshamlet
  signal PWM_Width           : std_logic_vector(DAC_Width-1 downto 0) :=
185
                                (others => '0');
186 180 jshamlet
 
187 217 jshamlet
  signal PWM_Period          : std_logic_vector(DAC_Width-1 downto 0) :=
188
                                (others => '0');
189 180 jshamlet
 
190 217 jshamlet
  signal Width_Ctr           : std_logic_vector(DAC_Width-1 downto 0) :=
191
                                (others => '0');
192 213 jshamlet
 
193 217 jshamlet
  signal Period_Ctr          : std_logic_vector(DAC_Width-1 downto 0) :=
194
                                (others => '0');
195 213 jshamlet
 
196 180 jshamlet
begin
197
 
198 217 jshamlet
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
199 244 jshamlet
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En;
200
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
201 180 jshamlet
 
202
  io_reg: process( Clock, Reset )
203
  begin
204
    if( Reset = Reset_Level )then
205 244 jshamlet
      Reg_Sel_q              <= "00";
206
      Wr_En_q                <= '0';
207
      Wr_Data_q              <= x"00";
208
      Rd_En_q                <= '0';
209 217 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
210 244 jshamlet
 
211 217 jshamlet
      DAC_Val_LB             <= x"00";
212
      DAC_Val_UB             <= x"0";
213 224 jshamlet
      DAC_Val                <= Default_Value;
214 180 jshamlet
    elsif( rising_edge( Clock ) )then
215 244 jshamlet
      Reg_Sel_q              <= Reg_Sel_d;
216 180 jshamlet
 
217 244 jshamlet
      Wr_En_q                <= Wr_En_d;
218
      Wr_Data_q              <= Wr_Data_d;
219
      if( Wr_En_q = '1' and Write_Qual = '1' )then
220
        case( Reg_Sel_q )is
221 180 jshamlet
          when "00" =>
222 217 jshamlet
            DAC_Val_LB       <= Wr_Data_q;
223 180 jshamlet
          when "01" =>
224 217 jshamlet
            DAC_Val_UB       <= Wr_Data_q(3 downto 0);
225 180 jshamlet
          when "10" =>
226 217 jshamlet
            DAC_Val          <= (others => '0');
227 180 jshamlet
          when "11" =>
228 217 jshamlet
            DAC_Val          <= DAC_Val_UB & DAC_Val_LB;
229 180 jshamlet
          when others => null;
230
        end case;
231
      end if;
232
 
233 244 jshamlet
      Rd_En_q                <= Rd_En_d;
234 217 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
235 244 jshamlet
      if( Rd_En_q = '1' )then
236
        case( Reg_Sel_q )is
237 180 jshamlet
          when "00" =>
238 217 jshamlet
            Rd_Data          <= DAC_Val_LB;
239 180 jshamlet
          when "01" =>
240 217 jshamlet
            Rd_Data          <= x"0" & DAC_Val_UB;
241 180 jshamlet
          when others => null;
242
        end case;
243
      end if;
244
    end if;
245
  end process;
246
 
247 217 jshamlet
  diff                       <= ('0' & q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
248
                                ('0' & Divisor);
249 180 jshamlet
 
250
  Dividend   <= PADJ_2  when DACin_q >= DELTA_2_I and DACin_q < DELTA_3_I else
251
                PADJ_3  when DACin_q >= DELTA_3_I and DACin_q < DELTA_4_I else
252
                PADJ_4  when DACin_q >= DELTA_4_I and DACin_q < DELTA_5_I else
253
                PADJ_5  when DACin_q >= DELTA_5_I and DACin_q < DELTA_6_I else
254
                PADJ_6  when DACin_q >= DELTA_6_I and DACin_q < DELTA_7_I else
255
                PADJ_7  when DACin_q >= DELTA_7_I and DACin_q < DELTA_8_I else
256
                PADJ_8  when DACin_q >= DELTA_8_I and DACin_q < DELTA_9_I else
257
                PADJ_9  when DACin_q >= DELTA_9_I and DACin_q < DELTA_10_I else
258
                PADJ_10 when DACin_q >= DELTA_10_I else
259
                PADJ_1;
260
 
261
  Next_Width <= DELTA_1  when DACin_q >= DELTA_1_I and DACin_q < DELTA_2_I else
262
                DELTA_2  when DACin_q >= DELTA_2_I and DACin_q < DELTA_3_I else
263
                DELTA_3  when DACin_q >= DELTA_3_I and DACin_q < DELTA_4_I else
264
                DELTA_4  when DACin_q >= DELTA_4_I and DACin_q < DELTA_5_I else
265
                DELTA_5  when DACin_q >= DELTA_5_I and DACin_q < DELTA_6_I else
266
                DELTA_6  when DACin_q >= DELTA_6_I and DACin_q < DELTA_7_I else
267
                DELTA_7  when DACin_q >= DELTA_7_I and DACin_q < DELTA_8_I else
268
                DELTA_8  when DACin_q >= DELTA_8_I and DACin_q < DELTA_9_I else
269
                DELTA_9  when DACin_q >= DELTA_9_I and DACin_q < DELTA_10_I else
270
                DELTA_10 when DACin_q >= DELTA_10_I else
271
                (others => '0');
272
 
273 217 jshamlet
  Next_Period                <= q(DAC_Width-1 downto 0) - 1;
274 191 jshamlet
 
275 180 jshamlet
  vDSM_proc: process( Clock, Reset )
276
  begin
277
    if( Reset = Reset_Level )then
278 217 jshamlet
      q                      <= (others => '0');
279
      count                  <= (others => '1');
280
      Divisor                <= (others => '0');
281
      DACin_q                <= (others => '0');
282
      PWM_Width              <= (others => '0');
283
      PWM_Period             <= (others => '0');
284
      Period_Ctr             <= (others => '0');
285
      Width_Ctr              <= (others => '0');
286 224 jshamlet
      DACOut                 <= '0';
287 180 jshamlet
    elsif( rising_edge(Clock) )then
288 217 jshamlet
      q                      <= diff(DIV_WIDTH-1 downto 0) &
289
                                q(DIV_WIDTH-2 downto 0) & '1';
290 180 jshamlet
      if( diff(DIV_WIDTH) = '1' )then
291 217 jshamlet
        q                    <= q(DIV_WIDTH*2-2 downto 0) & '0';
292 180 jshamlet
      end if;
293
 
294 217 jshamlet
      count                  <= count + 1;
295 180 jshamlet
      if( count = DIV_WIDTH )then
296 217 jshamlet
        PWM_Width            <= Next_Width;
297
        PWM_Period           <= Next_Period;
298
        DACin_q              <= DAC_val;
299
        Divisor              <= (others => '0');
300 180 jshamlet
        Divisor(DAC_Width-1 downto 0) <= DACin_q;
301 217 jshamlet
        q                   <= conv_std_logic_vector(0,DIV_WIDTH) & Dividend;
302
        count               <= (others => '0');
303 180 jshamlet
      end if;
304
 
305 217 jshamlet
      Period_Ctr            <= Period_Ctr - 1;
306
      Width_Ctr             <= Width_Ctr - 1;
307 180 jshamlet
 
308 268 jshamlet
      if( Invert_Output )then
309
        DACOut              <= or_reduce(Width_Ctr);
310
      else
311
        DACOut              <= nor_reduce(Width_Ctr);
312
      end if;
313
 
314 180 jshamlet
      if( Width_Ctr = 0 )then
315 217 jshamlet
        Width_Ctr           <= (others => '0');
316 180 jshamlet
      end if;
317
 
318
      if( Period_Ctr = 0 )then
319 217 jshamlet
        Period_Ctr          <= PWM_Period;
320
        Width_Ctr           <= PWM_Width;
321 180 jshamlet
      end if;
322
 
323
    end if;
324
  end process;
325
 
326
end architecture;

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