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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_watchdog.vhd] - Blame information for rev 332

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1 331 jshamlet
-- Copyright (c)2013, 2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Units :  o8_watchdog
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-- Description:  Provides a millisecond resolution watchdog timer
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--
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-- Register Map:
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-- Offset  Bitfield Description                        Read/Write
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--   0x00  AAAAAAAA Watchdog Passcode                     (W*)
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--
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-- Notes      :  User code must write the passcode specified in the generic
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--            :   before expiration to avoid PLL_Locked_Out going low.
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--
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-- Revision History
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-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry      10/04/23 Creation
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library ieee;
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use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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  use ieee.std_logic_arith.all;
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  use ieee.std_logic_misc.all;
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library work;
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  use work.open8_pkg.all;
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entity o8_watchdog is
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generic(
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  Clock_Frequency            : real;
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  WDOG_Interval              : integer := 1; -- milliseconds
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  WDOG_Passcode              : DATA_TYPE := x"21";
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  Address                    : ADDRESS_TYPE
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);
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port(
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  Open8_Bus                  : in  OPEN8_BUS_TYPE;
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  --
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  PLL_Locked_In              : in  std_logic;
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  PLL_Locked_Out             : out std_logic
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);
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end entity;
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architecture behave of o8_watchdog is
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  alias  Clock               is Open8_Bus.Clock;
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  alias  Reset               is Open8_Bus.Reset;
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  alias  CPU_ISR_En          is Open8_Bus.GP_Flags(EXT_ISR);
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  alias  CPU_Wr_En           is Open8_Bus.Wr_En;
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  constant User_Addr         : std_logic_vector(15 downto 0) :=
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                                Address(15 downto 0);
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  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);
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  signal Addr_Match          : std_logic := '0';
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  signal Wr_En_d             : std_logic;
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  signal Wr_En_q             : std_logic := '0';
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  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
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  signal Wr_Data_q           : DATA_TYPE := x"00";
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  signal WDOG_Reset_d        : std_logic;
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  signal WDOG_Reset          : std_logic := '0';
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  signal Timer_Tick          : std_logic := '0';
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  constant WDOG_USER         : real := real(WDOG_Interval) * 0.001;
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  constant WDOG_VAL          : integer := integer(Clock_Frequency * WDOG_USER);
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  constant WDOG_WDT          : integer := ceil_log2(WDOG_VAL - 1);
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  constant WDOG_DLY          : std_logic_vector :=
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                                conv_std_logic_vector(WDOG_VAL - 1, WDOG_WDT);
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  signal WDOG_Cntr           : std_logic_vector( WDOG_WDT - 1 downto 0 ) :=
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                                (others => '0');
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  signal WDOG_Expired_SR     : std_logic_vector(3 downto 0) := (others => '0');
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begin
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  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
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  Wr_En_d                    <= Addr_Match and CPU_ISR_En and CPU_Wr_En;
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  io_reg: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Wr_En_q                <= '0';
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      Wr_Data_q              <= x"00";
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      WDOG_Reset             <= '0';
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    elsif( rising_edge( Clock ) )then
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      Wr_En_q                <= Wr_En_d;
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      Wr_Data_q              <= Wr_Data_d;
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      WDOG_Reset             <= '0';
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      if( Wr_En_q = '1' and WDOG_Passcode = Wr_Data_q )then
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        WDOG_Reset           <= '1';
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      end if;
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    end if;
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  end process;
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  WDOG_proc: process( Clock, PLL_Locked_In )
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  begin
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    if( PLL_Locked_In = '0' )then
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      WDOG_Cntr              <= WDOG_DLY;
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      WDOG_Expired_SR        <= (others => '0');
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      PLL_Locked_Out         <= '0';
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    elsif( rising_edge( Clock ) )then
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      WDOG_Cntr              <= WDOG_Cntr - 1;
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      if( or_reduce(WDOG_Cntr) = '0' or WDOG_Reset = '1' )then
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        WDOG_Cntr            <= WDOG_DLY;
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      end if;
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      WDOG_Expired_SR        <= WDOG_Expired_SR(2 downto 0) &
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                                or_reduce(WDOG_Cntr);
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      PLL_Locked_Out         <= and_reduce(WDOG_Expired_SR);
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    end if;
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  end process;
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end architecture;

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