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-- Copyright (c)2013, 2020 Jeremy Seth Henry

-- All rights reserved.

--

-- Redistribution and use in source and binary forms, with or without

-- modification, are permitted provided that the following conditions are met:

--     * Redistributions of source code must retain the above copyright

--       notice, this list of conditions and the following disclaimer.

--     * Redistributions in binary form must reproduce the above copyright

--       notice, this list of conditions and the following disclaimer in the

--       documentation and/or other materials provided with the distribution,

--       where applicable (as part of a user interface, debugging port, etc.)

--

-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY

-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY

-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

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--

-- VHDL Units :  o8_watchdog

-- Description:  Provides a millisecond resolution watchdog timer

--

-- Register Map:

-- Offset  Bitfield Description                        Read/Write

--   0x00  AAAAAAAA Watchdog Passcode                     (W*)

--

-- Notes      :  User code must write the passcode specified in the generic

--            :   before expiration to avoid PLL_Locked_Out going low.

--

-- Revision History

-- Author          Date     Change

------------------ -------- ---------------------------------------------------

-- Seth Henry      10/04/23 Creation

library ieee;

use ieee.std_logic_1164.all;

  use ieee.std_logic_unsigned.all;

  use ieee.std_logic_arith.all;

  use ieee.std_logic_misc.all;

library work;

  use work.open8_pkg.all;

entity o8_watchdog is

generic(

  Clock_Frequency            : real;

  WDOG_Interval              : integer := 1; -- milliseconds

  WDOG_Passcode              : DATA_TYPE := x"21";

  Address                    : ADDRESS_TYPE

);

port(

  Open8_Bus                  : in  OPEN8_BUS_TYPE;

  --

  PLL_Locked_In              : in  std_logic;

  PLL_Locked_Out             : out std_logic

);

end entity;

architecture behave of o8_watchdog is

  alias  Clock               is Open8_Bus.Clock;

  alias  Reset               is Open8_Bus.Reset;

  alias  CPU_ISR_En          is Open8_Bus.GP_Flags(EXT_ISR);

  alias  CPU_Wr_En           is Open8_Bus.Wr_En;

  constant User_Addr         : std_logic_vector(15 downto 0) :=

                                Address(15 downto 0);

  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);

  signal Addr_Match          : std_logic := '0';

  signal Wr_En_d             : std_logic;

  signal Wr_En_q             : std_logic := '0';

  alias  Wr_Data_d           is Open8_Bus.Wr_Data;

  signal Wr_Data_q           : DATA_TYPE := x"00";

  signal WDOG_Reset_d        : std_logic;

  signal WDOG_Reset          : std_logic := '0';

  signal Timer_Tick          : std_logic := '0';

  constant WDOG_USER         : real := real(WDOG_Interval) * 0.001;

  constant WDOG_VAL          : integer := integer(Clock_Frequency * WDOG_USER);

  constant WDOG_WDT          : integer := ceil_log2(WDOG_VAL - 1);

  constant WDOG_DLY          : std_logic_vector :=

                                conv_std_logic_vector(WDOG_VAL - 1, WDOG_WDT);

  signal WDOG_Cntr           : std_logic_vector( WDOG_WDT - 1 downto 0 ) :=

                                (others => '0');

  signal WDOG_Expired_SR     : std_logic_vector(3 downto 0) := (others => '0');

begin

  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';

  Wr_En_d                    <= Addr_Match and CPU_ISR_En and CPU_Wr_En;

  io_reg: process( Clock, Reset )

  begin

    if( Reset = Reset_Level )then

      Wr_En_q                <= '0';

      Wr_Data_q              <= x"00";

      WDOG_Reset             <= '0';

    elsif( rising_edge( Clock ) )then

      Wr_En_q                <= Wr_En_d;

      Wr_Data_q              <= Wr_Data_d;

      WDOG_Reset             <= '0';

      if( Wr_En_q = '1' and WDOG_Passcode = Wr_Data_q )then

        WDOG_Reset           <= '1';

      end if;

    end if;

  end process;

  WDOG_proc: process( Clock, PLL_Locked_In )

  begin

    if( PLL_Locked_In = '0' )then

      WDOG_Cntr              <= WDOG_DLY;

      WDOG_Expired_SR        <= (others => '0');

      PLL_Locked_Out         <= '0';

    elsif( rising_edge( Clock ) )then

      WDOG_Cntr              <= WDOG_Cntr - 1;

      if( or_reduce(WDOG_Cntr) = '0' or WDOG_Reset = '1' )then

        WDOG_Cntr            <= WDOG_DLY;

      end if;

      WDOG_Expired_SR        <= WDOG_Expired_SR(2 downto 0) &

                                or_reduce(WDOG_Cntr);

      PLL_Locked_Out         <= and_reduce(WDOG_Expired_SR);

    end if;

  end process;

end architecture;