Subversion Repositories open8_urisc

-- megafunction wizard: %RAM: 1-PORT%

-- GENERATION: STANDARD

-- VERSION: WM1.0

-- MODULE: altsyncram 

-- ============================================================

-- File Name: ram_4k_core.vhd

-- Megafunction Name(s):

--                      altsyncram

--

-- Simulation Library Files(s):

--                      altera_mf

-- ============================================================

-- ************************************************************

-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

--

-- 13.1.0 Build 162 10/23/2013 SJ Web Edition

-- ************************************************************

--Copyright (C) 1991-2013 Altera Corporation

--Your use of Altera Corporation's design tools, logic functions 

--and other software and tools, and its AMPP partner logic 

--functions, and any output files from any of the foregoing 

--(including device programming or simulation files), and any 

--associated documentation or information are expressly subject 

--to the terms and conditions of the Altera Program License 

--Subscription Agreement, Altera MegaCore Function License 

--Agreement, or other applicable license agreement, including, 

--without limitation, that your use is for the sole purpose of 

--programming logic devices manufactured by Altera and sold by 

--Altera or its authorized distributors.  Please refer to the 

--applicable agreement for further details.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera_mf;

USE altera_mf.altera_mf_components.all;

ENTITY ram_4k_core IS

        PORT

        (

                address         : IN STD_LOGIC_VECTOR (11 DOWNTO 0);

                clock           : IN STD_LOGIC  := '1';

                data            : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

                wren            : IN STD_LOGIC ;

                q               : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

        );

END ram_4k_core;

ARCHITECTURE SYN OF ram_4k_core IS

        SIGNAL sub_wire0        : STD_LOGIC_VECTOR (7 DOWNTO 0);

BEGIN

        q    <= sub_wire0(7 DOWNTO 0);

        altsyncram_component : altsyncram

        GENERIC MAP (

                clock_enable_input_a => "BYPASS",

                clock_enable_output_a => "BYPASS",

                intended_device_family => "Cyclone III",

                lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=LRAM",

                lpm_type => "altsyncram",

                numwords_a => 4096,

                operation_mode => "SINGLE_PORT",

                outdata_aclr_a => "NONE",

                outdata_reg_a => "UNREGISTERED",

                power_up_uninitialized => "FALSE",

                read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",

                widthad_a => 12,

                width_a => 8,

                width_byteena_a => 1

        )

        PORT MAP (

                address_a => address,

                clock0 => clock,

                data_a => data,

                wren_a => wren,

                q_a => sub_wire0

        );

END SYN;

-- ============================================================

-- CNX file retrieval info

-- ============================================================

-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"

-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"

-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"

-- Retrieval info: PRIVATE: AclrData NUMERIC "0"

-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"

-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"

-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"

-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"

-- Retrieval info: PRIVATE: Clken NUMERIC "0"

-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"

-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"

-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"

-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"

-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"

-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"

-- Retrieval info: PRIVATE: JTAG_ID STRING "LRAM"

-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"

-- Retrieval info: PRIVATE: MIFfilename STRING ""

-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"

-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"

-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"

-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"

-- Retrieval info: PRIVATE: RegData NUMERIC "1"

-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"

-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"

-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"

-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"

-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"

-- Retrieval info: PRIVATE: WidthAddr NUMERIC "12"

-- Retrieval info: PRIVATE: WidthData NUMERIC "8"

-- Retrieval info: PRIVATE: rden NUMERIC "0"

-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"

-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"

-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"

-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=LRAM"

-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"

-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"

-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"

-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"

-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"

-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"

-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"

-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"

-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"

-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"

-- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"

-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"

-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"

-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"

-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"

-- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0

-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0

-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0

-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0

-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0

-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_4k_core.vhd TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_4k_core.inc FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_4k_core.cmp FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_4k_core.bsf FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_4k_core_inst.vhd FALSE

-- Retrieval info: LIB_FILE: altera_mf