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[/] [open8_urisc/] [trunk/] [VHDL/] [sdlc_dp512b_ram.vhd] - Blame information for rev 301

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Line No. Rev Author Line
1 195 jshamlet
-- megafunction wizard: %RAM: 2-PORT%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: altsyncram 
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-- ============================================================
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-- File Name: sdlc_dp512b_ram.vhd
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-- Megafunction Name(s):
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--                      altsyncram
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--
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-- Simulation Library Files(s):
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--                      altera_mf
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 13.1.0 Build 162 10/23/2013 SJ Full Version
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-- ************************************************************
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--Copyright (C) 1991-2013 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions 
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--and other software and tools, and its AMPP partner logic 
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--functions, and any output files from any of the foregoing 
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--(including device programming or simulation files), and any 
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--associated documentation or information are expressly subject 
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--to the terms and conditions of the Altera Program License 
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--Subscription Agreement, Altera MegaCore Function License 
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--Agreement, or other applicable license agreement, including, 
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--without limitation, that your use is for the sole purpose of 
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--programming logic devices manufactured by Altera and sold by 
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--Altera or its authorized distributors.  Please refer to the 
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--applicable agreement for further details.
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.altera_mf_components.all;
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ENTITY sdlc_dp512b_ram IS
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        PORT
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        (
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                address_a               : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
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                address_b               : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
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                clock           : IN STD_LOGIC  := '1';
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                data_a          : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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                data_b          : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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                wren_a          : IN STD_LOGIC  := '0';
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                wren_b          : IN STD_LOGIC  := '0';
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                q_a             : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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                q_b             : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
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        );
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END sdlc_dp512b_ram;
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ARCHITECTURE SYN OF sdlc_dp512b_ram IS
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        SIGNAL sub_wire0        : STD_LOGIC_VECTOR (7 DOWNTO 0);
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        SIGNAL sub_wire1        : STD_LOGIC_VECTOR (7 DOWNTO 0);
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BEGIN
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        q_a    <= sub_wire0(7 DOWNTO 0);
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        q_b    <= sub_wire1(7 DOWNTO 0);
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        altsyncram_component : altsyncram
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        GENERIC MAP (
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                address_reg_b => "CLOCK0",
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                clock_enable_input_a => "BYPASS",
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                clock_enable_input_b => "BYPASS",
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                clock_enable_output_a => "BYPASS",
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                clock_enable_output_b => "BYPASS",
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                indata_reg_b => "CLOCK0",
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                intended_device_family => "Cyclone IV E",
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                lpm_type => "altsyncram",
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                numwords_a => 512,
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                numwords_b => 512,
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                operation_mode => "BIDIR_DUAL_PORT",
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                outdata_aclr_a => "NONE",
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                outdata_aclr_b => "NONE",
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                outdata_reg_a => "UNREGISTERED",
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                outdata_reg_b => "UNREGISTERED",
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                power_up_uninitialized => "FALSE",
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                read_during_write_mode_mixed_ports => "OLD_DATA",
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                read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
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                read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
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                widthad_a => 9,
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                widthad_b => 9,
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                width_a => 8,
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                width_b => 8,
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                width_byteena_a => 1,
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                width_byteena_b => 1,
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                wrcontrol_wraddress_reg_b => "CLOCK0"
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        )
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        PORT MAP (
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                clock0 => clock,
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                wren_a => wren_a,
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                address_b => address_b,
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                data_b => data_b,
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                wren_b => wren_b,
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                address_a => address_a,
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                data_a => data_a,
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                q_a => sub_wire0,
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                q_b => sub_wire1
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        );
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END SYN;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
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-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
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-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
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-- Retrieval info: PRIVATE: Clock NUMERIC "0"
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-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
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-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
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-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
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-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
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-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
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-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
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-- Retrieval info: PRIVATE: MIFfilename STRING ""
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-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
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-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
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-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
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-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
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-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
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-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
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-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
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-- Retrieval info: PRIVATE: REGq NUMERIC "0"
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-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
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-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
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-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
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-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
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-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
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-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
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-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
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-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
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-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
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-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
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-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
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-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
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-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
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-- Retrieval info: PRIVATE: enable NUMERIC "0"
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-- Retrieval info: PRIVATE: rden NUMERIC "0"
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-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
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-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
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-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
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-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
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-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
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-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
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-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
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-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
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-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
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-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
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-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
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-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
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-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
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-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
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-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
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-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
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-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
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-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
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-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
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-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
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-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
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-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
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-- Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
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-- Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
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-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
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-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
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-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
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-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
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-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
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-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
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-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
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-- Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
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-- Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
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-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
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-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
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-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
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-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
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-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
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-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
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-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dp1kb_core.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dp1kb_core.inc FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dp1kb_core.cmp FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dp1kb_core.bsf FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_256b_core_inst.vhd FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dp1kb_core_inst.vhd FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL sdlc_dp512b_ram.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL sdlc_dp512b_ram.inc FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL sdlc_dp512b_ram.cmp FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL sdlc_dp512b_ram.bsf FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL sdlc_dp512b_ram_inst.vhd FALSE
230 195 jshamlet
-- Retrieval info: LIB_FILE: altera_mf

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