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[/] [open8_urisc/] [trunk/] [VHDL/] [status_led.vhd] - Blame information for rev 251

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1 249 jshamlet
-- Copyright (c)2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Units :  status_led
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-- Description:  Provides a multi-state status LED controller
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--
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-- LED Modes:
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-- 0x0 - LED is fully off
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-- 0x1 - LED is fully on
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-- 0x2 - LED is dimmed to 50%
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-- 0x3 - LED Toggles at 1Hz
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-- 0x4 - LED fades in and out
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--
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-- Revision History
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-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry      05/24/20 Created as a separate sub-component
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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  use ieee.std_logic_arith.all;
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  use ieee.std_logic_misc.all;
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entity status_led is
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generic(
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  Sys_Freq                   : real;
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  Reset_Level                : std_logic
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);
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port(
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  Clock                      : in  std_logic;
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  Reset                      : in  std_logic;
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  LED_Mode                   : in  std_logic_vector(2 downto 0);
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  LED_Out                    : out std_logic
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);
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end entity;
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architecture behave of status_led is
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  --  hold the supplied integer.
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  function ceil_log2 (x : in natural) return natural is
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    variable retval          : natural;
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  begin
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    retval                   := 1;
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    while ((2**retval) - 1) < x loop
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      retval                 := retval + 1;
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    end loop;
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    return retval;
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  end function;
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  signal Dim50Pct_Out        : std_logic := '0';
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  constant TAP1              : integer := 16;
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  constant TAP2              : integer := 21;
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  constant TAP3              : integer := 22;
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  constant TAP4              : integer := 23;
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  constant Init_Seed         : std_logic_vector(23 downto 0) := x"000001";
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  signal d0                  : std_logic := '0';
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  signal LFSR_poly           : std_logic_vector(23 downto 0) := (others => '0');
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  signal Cycle_Toggle        : std_logic;
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  constant TIMER_MSB         : integer range 9 to 20 := 18;
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  signal Fade_Timer1         : std_logic_vector(TIMER_MSB downto 0) :=
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                                (others => '0');
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  signal Fade_Timer2         : std_logic_vector(TIMER_MSB downto 0) :=
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                                (others => '0');
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  signal Fade_Out            : std_logic := '0';
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begin
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  Output_FF: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      LED_Out                <= '0';
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    elsif( rising_edge(Clock) )then
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      LED_Out                <= '0';
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      case( LED_Mode )is
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        when "001" =>
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          LED_Out            <= '1';
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        when "010" =>
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          LED_Out            <= Dim50Pct_Out;
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        when "011" =>
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          LED_Out            <= Cycle_Toggle;
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        when "100" =>
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          LED_Out            <= Fade_out;
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        when others => null;
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      end case;
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    end if;
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  end process;
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  d0                         <= LFSR_poly(TAP4) xnor LFSR_poly(TAP3) xnor
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                                LFSR_poly(TAP2) xnor LFSR_poly(TAP1);
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  Timer_proc: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Dim50Pct_Out           <= '0';
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      LFSR_poly              <= Init_Seed;
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      Cycle_Toggle           <= '0';
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      Fade_Timer1            <= (others => '0');
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      Fade_Timer2            <= (others => '0');
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      Fade_out               <= '0';
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    elsif( rising_edge(Clock) )then
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      Dim50Pct_Out           <= not Dim50Pct_Out;
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      LFSR_poly              <= LFSR_poly(22 downto 0) & d0;
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      if( LFSR_poly = Init_Seed )then
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        Cycle_Toggle         <= not Cycle_Toggle;
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      end if;
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      Fade_Timer1            <= Fade_Timer1 - 1;
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      Fade_Timer2            <= Fade_Timer2 - 1;
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      if( or_reduce(Fade_Timer2) = '0' )then
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        Fade_Timer2(TIMER_MSB downto TIMER_MSB - 8) <= (others => '1');
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        Fade_Timer2(TIMER_MSB - 9 downto 0 )        <= (others => '0');
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      end if;
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      Fade_out               <= Fade_Timer1(TIMER_MSB) xor
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                                Fade_Timer2(TIMER_MSB);
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    end if;
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  end process;
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end architecture;

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