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[/] [open8_urisc/] [trunk/] [VHDL/] [sys_tick.vhd] - Blame information for rev 301

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Line No. Rev Author Line
1 258 jshamlet
-- Copyright (c)2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Entity: sys_tick
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-- Description: Provides a single clock tick every microsecond and millisecond.
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--               Requires that the system clock frequency be passed as a real.
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--
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-- Revision History
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-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry      04/16/20 Code cleanup and revision section added
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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  use ieee.std_logic_arith.all;
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  use ieee.std_logic_misc.all;
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entity sys_tick is
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generic(
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  Reset_Level           : std_logic;
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  Sys_Freq              : real := 50000000.0
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);
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port(
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  Clock                 : in  std_logic;
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  Reset                 : in  std_logic;
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  uSec_Tick             : out std_logic;
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  mSec_Tick             : out std_logic
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);
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end entity;
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architecture behave of sys_tick is
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  -- The ceil_log2 function returns the minimum register width required to
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  --  hold the supplied integer.
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  function ceil_log2 (x : in natural) return natural is
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    variable retval          : natural;
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  begin
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    retval                   := 1;
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    while ((2**retval) - 1) < x loop
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      retval                 := retval + 1;
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    end loop;
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    return retval;
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  end ceil_log2;
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  constant DLY_1USEC_VAL     : integer := integer(Sys_Freq / 1000000.0);
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  constant DLY_1USEC_WDT     : integer := ceil_log2(DLY_1USEC_VAL - 1);
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  constant DLY_1USEC         : std_logic_vector :=
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                                conv_std_logic_vector( DLY_1USEC_VAL - 1, DLY_1USEC_WDT);
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  signal uSec_Cntr           : std_logic_vector( DLY_1USEC_WDT - 1 downto 0 );
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  constant MSEC_DELAY        : std_logic_vector(9 downto 0) :=
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                                conv_std_logic_vector(1000,10);
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  signal mSec_Timer          : std_logic_vector(9 downto 0) := (others => '0');
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begin
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  Tick_proc: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      uSec_Cntr              <= DLY_1USEC;
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      uSec_Tick              <= '0';
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      mSec_Timer             <= (others => '0');
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      mSec_Tick              <= '0';
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    elsif( rising_edge( Clock ) )then
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      uSec_Cntr              <= uSec_Cntr - 1;
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      uSec_Tick              <= '0';
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      if( or_reduce(uSec_Cntr) = '0' )then
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        uSec_Cntr            <= DLY_1USEC;
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        uSec_Tick            <= '1';
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        mSec_Timer           <= mSec_Timer - 1;
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      end if;
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      mSec_Tick              <= '0';
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      if( mSec_Timer = 0 )then
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        mSec_Timer           <= MSEC_DELAY;
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        mSec_Tick            <= '1';
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      end if;
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    end if;
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  end process;
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end architecture;

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