Subversion Repositories open8_urisc

; Renesas M32R CPU description.  -*- Scheme -*-

;

; Copyright 1998, 1999, 2000, 2001, 2003, 2007, 2009

; Free Software Foundation, Inc.

;

; Contributed by Red Hat Inc; developed under contract from Mitsubishi

; Electric Corporation.

;

; This file is part of the GNU Binutils.

;

; This program is free software; you can redistribute it and/or modify

; it under the terms of the GNU General Public License as published by

; the Free Software Foundation; either version 3 of the License, or

; (at your option) any later version.

;

; This program is distributed in the hope that it will be useful,

; but WITHOUT ANY WARRANTY; without even the implied warranty of

; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

; GNU General Public License for more details.

;

; You should have received a copy of the GNU General Public License

; along with this program; if not, write to the Free Software

; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,

; MA 02110-1301, USA.

(include "simplify.inc")

; FIXME: Delete sign extension of accumulator results.

; Sign extension is done when accumulator is read.

; define-arch must appear first

(define-arch

  (name m32r) ; name of cpu family

  (comment "Renesas M32R")

  (default-alignment aligned)

  (insn-lsb0? #f)

  (machs m32r m32rx m32r2)

  (isas m32r)

)

; Attributes.

; An attribute to describe which pipeline an insn runs in.

; O_OS is a special attribute for sll, sra, sla, slli, srai, slai.

; These instructions have O attribute for m32rx and OS attribute for m32r2.

(define-attr

  (for insn)

  (type enum)

  (name PIPE)

  (comment "parallel execution pipeline selection")

  (values NONE O S OS O_OS)

)

; A derived attribute that says which insns can be executed in parallel

; with others.  This is a required attribute for architectures with

; parallel execution.

(define-attr

  (for insn)

  (type enum)

  (name PARALLEL)

  (attrs META) ; do not define in any generated file for now

  (values NO YES)

  (default (if (eq-attr (current-insn) PIPE NONE) (symbol NO) (symbol YES)))

)

; Instruction set parameters.

(define-isa

  (name m32r)

  ; This is 32 because 16 bit insns always appear as pairs.

  ; ??? See if this can go away.  It's only used by the disassembler (right?)

  ; to decide how long an unknown insn is.  One value isn't sufficient (e.g. if

  ; on a 16 bit (and not 32 bit) boundary, will only want to advance pc by 16.)

  (default-insn-bitsize 32)

  ; Number of bytes of insn we can initially fetch.

  ; The M32R is tricky in that insns are either two 16-bit insns

  ; (executed sequentially or in parallel) or one 32-bit insn.

  ; So on one hand the base insn size is 16 bits, but on another it's 32.

  ; 32 is chosen because:

  ; - if the chip were ever bi-endian it is believed that the byte order would

  ;   be based on 32 bit quantities

  ; - 32 bit insns are always aligned on 32 bit boundaries

  ; - the pc will never stop on a 16 bit (and not 32 bit) boundary

  ;   [well actually it can, but there are no branches to such places]

  (base-insn-bitsize 32)

  ; Used in computing bit numbers.

  (default-insn-word-bitsize 32)

  ; The m32r fetches 2 insns at a time.

  (liw-insns 2)

  ; While the m32r can execute insns in parallel, the base mach can't

  ; (other than nop).  The base mach is greatly handicapped by this, but

  ; we still need to cleanly handle it.

  (parallel-insns 2)

  ; Initial bitnumbers to decode insns by.

  (decode-assist (0 1 2 3 8 9 10 11))

  ; Classification of instructions that fit in the various frames.

  ; wip, not currently used

  (insn-types (long ; name

               31 ; length

               (eq-attr (current-insn) LENGTH 31) ; matching insns

               (0 1 2 7 8 9 10) ; decode-assist

               )

              (short

               15

               (eq-attr (current-insn) LENGTH 15) ; matching insns

               (0 1 2 7 8 9 10)

               )

              )

  ; Instruction framing.

  ; Each m32r insn is either one 32 bit insn, two 16 bit insns executed

  ; serially (left->right), or two 16 bit insns executed parallelly.

  ; wip, not currently used

  (frame long32 ; name

         ((long)) ; list of insns in frame, plus constraint

         "$0"   ; assembler

         (+ (1 1) (31 $0)) ; value

         (sequence () (execute $0)) ; action

         )

  (frame serial2x16

         ((short)

          (short))

         "$0 -> $1"

         (+ (1 0) (15 $0) (1 0) (15 $1))

         (sequence ()

                   (execute $0)

                   (execute $1))

         )

  (frame parallel2x16

         ((short (eq-attr (current-insn) PIPE "O,BOTH"))

          (short (eq-attr (current-insn) PIPE "S,BOTH")))

         "$0 || $1"

         (+ (1 0) (15 $0) (1 1) (15 $1))

         (parallel ()

                   (execute $0)

                   (execute $1))

         )

)

; Cpu family definitions.

; ??? define-cpu-family [and in general "cpu-family"] might be clearer than

; define-cpu.

; ??? Have define-arch provide defaults for architecture that define-cpu can

; then override [reduces duplication in define-cpu].

; ??? Another way to go is to delete cpu-families entirely and have one mach

; able to inherit things from another mach (would also need the ability to

; not only override specific inherited things but also disable some,

; e.g. if an insn wasn't supported).

(define-cpu

  ; cpu names must be distinct from the architecture name and machine names.

  ; The "b" suffix stands for "base" and is the convention.

  ; The "f" suffix stands for "family" and is the convention.

  (name m32rbf)

  (comment "Renesas M32R base family")

  (endian either)

  (word-bitsize 32)

  ; Override isa spec (??? keeps things simpler, though it was more true

  ; in the early days and not so much now).

  (parallel-insns 1)

)

(define-cpu

  (name m32rxf)

  (comment "Renesas M32Rx family")

  (endian either)

  (word-bitsize 32)

  ; Generated files have an "x" suffix.

  (file-transform "x")

)

(define-cpu

  (name m32r2f)

  (comment "Renesas M32R2 family")

  (endian either)

  (word-bitsize 32)

  ; Generated files have an "2" suffix.

  (file-transform "2")

)

(define-mach

  (name m32r)

  (comment "Generic M32R cpu")

  (cpu m32rbf)

)

(define-mach

  (name m32rx)

  (comment "M32RX cpu")

  (cpu m32rxf)

)

(define-mach

  (name m32r2)

  (comment "M32R2 cpu")

  (cpu m32r2f)

)

; Model descriptions.

; The meaning of this value is wip but at the moment it's intended to describe

; the implementation (i.e. what -mtune=foo does in sparc gcc).

;

; Notes while wip:

; - format of pipeline entry:

;   (pipeline name (stage1-name ...) (stage2-name ...) ...)

;   The contents of a stage description is wip.

; - each mach must have at least one model

; - the default model must be the first one

;- maybe have `retire' support update total cycle count to handle current

;  parallel insn cycle counting problems

(define-model

  (name m32r/d) (comment "m32r/d") (attrs)

  (mach m32r)

  ;(prefetch)

  ;(retire)

  (pipeline p-non-mem "" () ((fetch) (decode) (execute) (writeback)))

  (pipeline p-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))

  ; `state' is a list of variables for recording model state

  (state

   ; bit mask of h-gr registers, =1 means value being loaded from memory

   (h-gr UINT)

   )

  (unit u-exec "Execution Unit" ()

        1 1 ; issue done

        () ; state

        ((sr INT -1) (dr INT -1)) ; inputs

        ((dr INT -1)) ; outputs

        () ; profile action (default)

        )

  (unit u-cmp "Compare Unit" ()

        1 1 ; issue done

        () ; state

        ((src1 INT -1) (src2 INT -1)) ; inputs

        () ; outputs

        () ; profile action (default)

        )

  (unit u-mac "Multiply/Accumulate Unit" ()

        1 1 ; issue done

        () ; state

        ((src1 INT -1) (src2 INT -1)) ; inputs

        () ; outputs

        () ; profile action (default)

        )

  (unit u-cti "Branch Unit" ()

        1 1 ; issue done

        () ; state

        ((sr INT -1)) ; inputs

        ((pc)) ; outputs

        () ; profile action (default)

        )

  (unit u-load "Memory Load Unit" ()

        1 1 ; issue done

        () ; state

        ((sr INT)

         ;(ld-mem AI)

         ) ; inputs

        ((dr INT)) ; outputs

        () ; profile action (default)

        )

  (unit u-store "Memory Store Unit" ()

        1 1 ; issue done

        () ; state

        ((src1 INT) (src2 INT)) ; inputs

        () ; ((st-mem AI)) ; outputs

        () ; profile action (default)

        )

)

(define-model

  (name test) (comment "test") (attrs)

  (mach m32r)

  (pipeline all "" () ((fetch) (decode) (execute) (writeback)))

  (unit u-exec "Execution Unit" ()

        1 1 ; issue done

        () () () ())

)

; Each mach must have at least one model.

(define-model

  (name m32rx) (comment "m32rx") (attrs)

  (mach m32rx)

  ; ??? It's 6 stages but I forget the details right now.

  (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))

  (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))

  (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))

  (unit u-exec "Execution Unit" ()

        1 1 ; issue done

        () ; state

        ((sr INT -1) (dr INT -1)) ; inputs

        ((dr INT -1)) ; outputs

        () ; profile action (default)

        )

  (unit u-cmp "Compare Unit" ()

        1 1 ; issue done

        () ; state

        ((src1 INT -1) (src2 INT -1)) ; inputs

        () ; outputs

        () ; profile action (default)

        )

  (unit u-mac "Multiply/Accumulate Unit" ()

        1 1 ; issue done

        () ; state

        ((src1 INT -1) (src2 INT -1)) ; inputs

        () ; outputs

        () ; profile action (default)

        )

  (unit u-cti "Branch Unit" ()

        1 1 ; issue done

        () ; state

        ((sr INT -1)) ; inputs

        ((pc)) ; outputs

        () ; profile action (default)

        )

  (unit u-load "Memory Load Unit" ()

        1 1 ; issue done

        () ; state

        ((sr INT)) ; inputs

        ((dr INT)) ; outputs

        () ; profile action (default)

        )

  (unit u-store "Memory Store Unit" ()

        1 1 ; issue done

        () ; state

        ((src1 INT) (src2 INT)) ; inputs

        () ; outputs

        () ; profile action (default)

        )

)

(define-model

  (name m32r2) (comment "m32r2") (attrs)

  (mach m32r2)

  ; ??? It's 6 stages but I forget the details right now.

  (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))

  (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))

  (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))

  (unit u-exec "Execution Unit" ()

        1 1 ; issue done

        () ; state

        ((sr INT -1) (dr INT -1)) ; inputs

        ((dr INT -1)) ; outputs

        () ; profile action (default)

        )

  (unit u-cmp "Compare Unit" ()

        1 1 ; issue done

        () ; state

        ((src1 INT -1) (src2 INT -1)) ; inputs

        () ; outputs

        () ; profile action (default)

        )

  (unit u-mac "Multiply/Accumulate Unit" ()

        1 1 ; issue done

        () ; state

        ((src1 INT -1) (src2 INT -1)) ; inputs

        () ; outputs

        () ; profile action (default)

        )

  (unit u-cti "Branch Unit" ()

        1 1 ; issue done

        () ; state

        ((sr INT -1)) ; inputs

        ((pc)) ; outputs

        () ; profile action (default)

        )

  (unit u-load "Memory Load Unit" ()

        1 1 ; issue done

        () ; state

        ((sr INT)) ; inputs

        ((dr INT)) ; outputs

        () ; profile action (default)

        )

  (unit u-store "Memory Store Unit" ()

        1 1 ; issue done

        () ; state

        ((src1 INT) (src2 INT)) ; inputs

        () ; outputs

        () ; profile action (default)

        )

)

; The instruction fetch/execute cycle.

; This is split into two parts as sometimes more than one instruction is

; decoded at once.

; The `const SI' argument to decode/execute is used to distinguish

; multiple instructions processed at the same time (e.g. m32r).

;

; ??? This is wip, and not currently used.

; ??? Needs to be moved to define-isa.

; This is how to fetch and decode an instruction.

;(define-extract

;  (sequence VOID

;           (if VOID (ne AI (and AI pc (const AI 3)) (const AI 0))

;               (sequence VOID

;                         (set-quiet USI (scratch UHI insn1) (ifetch UHI pc))

;                         (decode VOID pc (and UHI insn1 (const UHI #x7fff))

;                                 (const SI 0)))

;               (sequence VOID

;                         (set-quiet USI (scratch USI insn) (ifetch USI pc))

;                         (if VOID (ne USI (and USI insn (const USI #x80000000))

;                                    (const USI 0))

;                             (decode VOID pc (srl USI insn (const WI 16)) (const SI 0))

;                             (sequence VOID

;                                       ; ??? parallel support

;                                       (decode VOID pc (srl USI insn (const WI 16))

;                                               (const SI 0))

;                                       (decode VOID (add AI pc (const AI 2))

;                                               (and USI insn (const WI #x7fff))

;                                               (const SI 1))))))

;           )

;)

; This is how to execute a decoded instruction.

;(define-execute

;  (sequence VOID () ; () is empty option list

;            ((AI new_pc))

;            (set AI new_pc (execute: AI (const 0)) #:quiet)

;            (set AI pc new_pc #:direct)

;            )

;)

; FIXME: It might simplify things to separate the execute process from the

; one that updates the PC.

; Instruction fields.

;

; Attributes:

; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)

; ABS-ADDR: absolute address (for reloc and disassembly purposes?)

; RESERVED: bits are not used to decode insn, must be all 0

; RELOC: there is a relocation associated with this field (experiment)

(define-attr

  (for ifield operand)

  (type boolean)

  (name RELOC)

  (comment "there is a reloc associated with this field (experiment)")

)

(dnf f-op1       "op1"                 () 0 4)

(dnf f-op2       "op2"                 () 8 4)

(dnf f-cond      "cond"                () 4 4)

(dnf f-r1        "r1"                  () 4 4)

(dnf f-r2        "r2"                  () 12 4)

(df f-simm8      "simm8"               () 8 8 INT #f #f)

(df f-simm16     "simm16"              () 16 16 INT #f #f)

(dnf f-shift-op2 "shift op2"           () 8 3)

(dnf f-uimm3     "uimm3"               () 5 3)

(dnf f-uimm4     "uimm4"               () 12 4)

(dnf f-uimm5     "uimm5"               () 11 5)

(dnf f-uimm8     "uimm8"               () 8 8)

(dnf f-uimm16    "uimm16"              () 16 16)

(dnf f-uimm24    "uimm24"              (ABS-ADDR RELOC) 8 24)

(dnf f-hi16      "high 16 bits"        (SIGN-OPT) 16 16)

(df f-disp8      "disp8, slot unknown" (PCREL-ADDR RELOC) 8 8 INT

    ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2)))

    ((value pc) (add WI (sll WI value (const 2)) (and WI pc (const -4)))))

(df f-disp16     "disp16"              (PCREL-ADDR RELOC) 16 16 INT

    ((value pc) (sra WI (sub WI value pc) (const 2)))

    ((value pc) (add WI (sll WI value (const 2)) pc)))

(df f-disp24     "disp24"              (PCREL-ADDR RELOC) 8 24 INT

    ((value pc) (sra WI (sub WI value pc) (const 2)))

    ((value pc) (add WI (sll WI value (const 2)) pc)))

(dnf f-op23      "op2.3"               ()  9 3)

(dnf f-op3       "op3"                 () 14 2)

(dnf f-acc       "acc"                 ()  8 1)

(dnf f-accs      "accs"                () 12 2)

(dnf f-accd      "accd"                ()  4 2)

(dnf f-bits67    "bits67"              ()  6 2)

(dnf f-bit4      "bit4"                ()  4 1)

(dnf f-bit14     "bit14"               () 14 1)

(define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2")

  (attrs)

  (start 15) (length 1)

  (encode (value pc) (sub WI value (const WI 1)))

  (decode (value pc) (add WI value (const WI 1)))

)

; Enums.

; insn-op1: bits 0-3

; FIXME: should use die macro or some such

(define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1

  ("0" "1" "2" "3" "4" "5" "6" "7"

   "8" "9" "10" "11" "12" "13" "14" "15")

)

; insn-op2: bits 8-11

; FIXME: should use die macro or some such

(define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2

  ("0" "1" "2" "3" "4" "5" "6" "7"

   "8" "9" "10" "11" "12" "13" "14" "15")

)

; Hardware pieces.

; These entries list the elements of the raw hardware.

; They're also used to provide tables and other elements of the assembly

; language.

(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())

(dnh h-hi16 "high 16 bits" ()

     (immediate (UINT 16))

     () () ()

)

; These two aren't technically needed.

; They're here for illustration sake mostly.

; Plus they cause the value to be stored in the extraction buffers to only

; be 16 bits wide (vs 32 or 64).  Whoopie ding.  But it's fun.

(dnh h-slo16 "signed low 16 bits" ()

     (immediate (INT 16))

     () () ()

)

(dnh h-ulo16 "unsigned low 16 bits" ()

     (immediate (UINT 16))

     () () ()

)

(define-keyword

  (name gr-names)

  (print-name h-gr)

  (prefix "")

  (values (fp 13) (lr 14) (sp 15)

          (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)

          (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15))

)

(define-hardware

  (name h-gr)

  (comment "general registers")

  (attrs PROFILE CACHE-ADDR)

  (type register WI (16))

  (indices extern-keyword gr-names)

)

(define-keyword

  (name cr-names)

  (print-name h-cr)

  (prefix "")

  (values (psw 0)   (cbr 1)   (spi 2)   (spu 3)

          (bpc 6)   (bbpsw 8) (bbpc 14) (evb 5)

          (cr0 0)   (cr1 1)   (cr2 2)   (cr3 3)

          (cr4 4)   (cr5 5)   (cr6 6)   (cr7 7)

          (cr8 8)   (cr9 9)   (cr10 10) (cr11 11)

          (cr12 12) (cr13 13) (cr14 14) (cr15 15))

)

(define-hardware

  (name h-cr)

  (comment "control registers")

  (type register UWI (16))

  (indices extern-keyword cr-names)

  (get (index) (c-call UWI "@cpu@_h_cr_get_handler" index))

  (set (index newval) (c-call VOID "@cpu@_h_cr_set_handler" index newval))

)

; The actual accumulator is only 56 bits.

; The top 8 bits are sign extended from bit 8 (when counting msb = bit 0).

; To simplify the accumulator instructions, no attempt is made to keep the

; top 8 bits properly sign extended (currently there's no point since they

; all ignore them).  When the value is read it is properly sign extended

; [in the `get' handler].

(define-hardware

  (name h-accum)

  (comment "accumulator")

  (type register DI)

  (get () (c-call DI "@cpu@_h_accum_get_handler"))

  (set (newval) (c-call VOID "@cpu@_h_accum_set_handler" newval))

)

; FIXME: Revisit after sanitization can be removed.  Remove h-accum.

(define-hardware

  (name h-accums)

  (comment "accumulators")

  (attrs (MACH m32rx,m32r2))

  (type register DI (2))

  (indices keyword "" ((a0 0) (a1 1)))

  ; get/set so a0 accesses are redirected to h-accum.

  ; They're also so reads can properly sign extend the value.

  ; FIXME: Needn't be a function call.

  (get (index) (c-call DI "@cpu@_h_accums_get_handler" index))

  (set (index newval) (c-call VOID "@cpu@_h_accums_set_handler" index newval))

)

; For condbit operand.  FIXME: Need to allow spec of get/set of operands.

; Having this separate from h-psw keeps the parts that use it simpler

; [since they greatly outnumber those that use h-psw].

(dsh h-cond "condition bit" () (register BI))

; The actual values of psw,bpsw,bbpsw are recorded here to allow access

; to them as a unit.

(define-hardware

  (name h-psw)

  (comment "psw part of psw")

  (type register UQI)

  ; get/set to handle cond bit.

  ; FIXME: missing: use's and clobber's

  ; FIXME: remove c-call?

  (get () (c-call UQI "@cpu@_h_psw_get_handler"))

  (set (newval) (c-call VOID "@cpu@_h_psw_set_handler" newval))

)

(dsh h-bpsw  "backup psw"      () (register UQI))

(dsh h-bbpsw "backup bpsw"     () (register UQI))

; FIXME: Later make add get/set specs and support SMP.

(dsh h-lock  "lock"  () (register BI))

; Instruction Operands.

; These entries provide a layer between the assembler and the raw hardware

; description, and are used to refer to hardware elements in the semantic

; code.  Usually there's a bit of over-specification, but in more complicated

; instruction sets there isn't.

;; Print some operands take a hash prefix.

;; ??? Why don't we also handle one when parsing?

(define-pmacro (duhpo x-name x-comment x-attrs x-type x-index)

  (define-operand (name x-name) (comment x-comment)

    (.splice attrs (.unsplice x-attrs))

    (type x-type) (index x-index)

    (handlers (print "unsigned_with_hash_prefix")))

)

(define-pmacro (dshpo x-name x-comment x-attrs x-type x-index)

  (define-operand (name x-name) (comment x-comment)

    (.splice attrs (.unsplice x-attrs))

    (type x-type) (index x-index)

    (handlers (print "signed_with_hash_prefix")))

)

; ??? Convention says this should be o-sr, but then the insn definitions

; should refer to o-sr which is clumsy.  The "o-" could be implicit, but

; then it should be implicit for all the symbols here, but then there would

; be confusion between (f-)simm8 and (h-)simm8.

; So for now the rule is exactly as it appears here.

(dnop sr     "source register"              () h-gr   f-r2)

(dnop dr     "destination register"         () h-gr   f-r1)

;; The assembler relies upon the fact that dr and src1 are the same field.

;; FIXME: Revisit.

(dnop src1   "source register 1"            () h-gr   f-r1)

(dnop src2   "source register 2"            () h-gr   f-r2)

(dnop scr    "source control register"      () h-cr   f-r2)

(dnop dcr    "destination control register" () h-cr   f-r1)

(dshpo simm8  "8 bit signed immediate"       () h-sint f-simm8)

(dshpo simm16 "16 bit signed immediate"      () h-sint f-simm16)

(duhpo uimm3  "3 bit unsigned number"        () h-uint f-uimm3)

(duhpo uimm4  "4 bit trap number"            () h-uint f-uimm4)

(duhpo uimm5  "5 bit shift count"            () h-uint f-uimm5)

(duhpo uimm8  "8 bit unsigned immediate"     () h-uint f-uimm8)

(duhpo uimm16 "16 bit unsigned immediate"    () h-uint f-uimm16)

(duhpo imm1 "1 bit immediate" ((MACH m32rx,m32r2)) h-uint f-imm1)

(dnop accd   "accumulator destination register" ((MACH m32rx,m32r2)) h-accums f-accd)

(dnop accs   "accumulator source register"  ((MACH m32rx,m32r2))     h-accums f-accs)

(dnop acc    "accumulator reg (d)"          ((MACH m32rx,m32r2))     h-accums f-acc)

; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases.

; e.g. add3 r3,r3,#1 and ld r3,@(4,r4).  We could use special handlers on

; the operands themselves.

; Instead we create a fake operand `hash'.  The m32r is an illustration port,

; so we often try out various ways of doing things.

(define-operand (name hash) (comment "# prefix") (attrs)

  (type h-sint) ; doesn't really matter

  (index f-nil)

  (handlers (parse "hash") (print "hash"))

)

; For high(foo),shigh(foo).

(define-operand

  (name hi16)

  (comment "high 16 bit immediate, sign optional")

  (attrs)

  (type h-hi16)

  (index f-hi16)

  (handlers (parse "hi16"))

)

; For low(foo),sda(foo).

(define-operand

  (name slo16)

  (comment "16 bit signed immediate, for low()")

  (attrs)

  (type h-slo16)

  (index f-simm16)

  (handlers (parse "slo16"))

)

; For low(foo).

(define-operand

  (name ulo16)

  (comment "16 bit unsigned immediate, for low()")

  (attrs)

  (type h-ulo16)

  (index f-uimm16)

  (handlers (parse "ulo16"))

)

(dnop uimm24 "24 bit address" () h-addr f-uimm24)

(define-operand

  (name disp8)

  (comment "8 bit displacement")

  (attrs RELAX)

  (type h-iaddr)

  (index f-disp8)

  ; ??? Early experiments had insert/extract fields here.

  ; Moving these to f-disp8 made things cleaner, but may wish to re-introduce

  ; fields here to handle more complicated cases.

)

(dnop disp16 "16 bit displacement" () h-iaddr f-disp16)

(dnop disp24 "24 bit displacement" (RELAX) h-iaddr f-disp24)

; These hardware elements are refered to frequently.

(dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil)

(dnop accum "accumulator" (SEM-ONLY) h-accum f-nil)

; Instruction definitions.

;

; Notes while wip:

; - dni is a cover macro to the real "this is an instruction" keyword.

;   The syntax of the real one is yet to be determined.

;   At the lowest level (i.e. the "real" one) it will probably take a variable

;   list of arguments where each argument [perhaps after the standard three of

;   name, comment, attrs] is "(keyword arg-to-keyword)".  This syntax is simple

;   and yet completely upward extensible.  And given the macro facility, one

;   needn't code at that low a level so even though it'll be more verbose than

;   necessary it won't matter.  This same reasoning can be applied to most

;   types of entries in this file.

; M32R specific instruction attributes:

; FILL-SLOT: Need next insn to begin on 32 bit boundary.

; (A "slot" as used here is a 32 bit quantity that can either be filled with

; one 32 bit insn or two 16 bit insns which go in the "left bin" and "right

; bin" where the left bin is the one with a lower address).

(define-attr

  (for insn)

  (type boolean)

  (name FILL-SLOT)

  (comment "fill right bin with `nop' if insn is in left bin")

)

(define-attr

  (for insn)

  (type boolean)

  (name SPECIAL)

  (comment "non-public m32rx insn")

)

(define-attr

  (for insn)

  (type boolean)

  (name SPECIAL_M32R)

  (comment "non-public m32r insn")

)

(define-attr

  (for insn)

  (type boolean)

  (name SPECIAL_FLOAT)

  (comment "floating point insn")

)

; IDOC attribute for instruction documentation.

(define-attr

  (for insn)

  (type enum)

  (name IDOC)

  (comment "insn kind for documentation")

  (attrs META)

  (values

   (MEM - () "Memory")

   (ALU - () "ALU")

   (BR - () "Branch")

   (ACCUM - () "Accumulator")

   (MAC - () "Multiply/Accumulate")

   (MISC - () "Miscellaneous")

  )

)

(define-pmacro (bin-op mnemonic op2-op sem-op imm-prefix imm)

  (begin

     (dni mnemonic

          (.str mnemonic " reg/reg")

          ((PIPE OS) (IDOC ALU))

          (.str mnemonic " $dr,$sr")

          (+ OP1_0 op2-op dr sr)

          (set dr (sem-op dr sr))

          ()

     )

     (dni (.sym mnemonic "3")

          (.str mnemonic " reg/" imm)

          ((IDOC ALU))

          (.str mnemonic "3 $dr,$sr," imm-prefix "$" imm)

          (+ OP1_8 op2-op dr sr imm)

          (set dr (sem-op sr imm))

          ()

     )

   )

)

(bin-op add OP2_10 add "$hash" slo16)

; sub isn't present because sub3 doesn't exist.

(bin-op and OP2_12 and "" uimm16)

(bin-op or OP2_14 or "$hash" ulo16)

(bin-op xor OP2_13 xor "" uimm16)

(dni addi "addi"

     ((PIPE OS) (IDOC ALU))

     ;#.(string-append "addi " "$dr,$simm8") ; #. experiment

     "addi $dr,$simm8"

     (+ OP1_4 dr simm8)

     (set dr (add dr simm8))

     ((m32r/d (unit u-exec))

      (m32rx (unit u-exec))

      (m32r2 (unit u-exec)))

)

(dni addv "addv"

     ((PIPE OS) (IDOC ALU))

     "addv $dr,$sr"

     (+ OP1_0 OP2_8 dr sr)

     (parallel ()

               (set dr (add dr sr))

               (set condbit (add-oflag dr sr (const 0))))

     ()

)

(dni addv3 "addv3"

     ((IDOC ALU))

     "addv3 $dr,$sr,$simm16"

     (+ OP1_8 OP2_8 dr sr simm16)

     (parallel ()

               (set dr (add sr simm16))

               (set condbit (add-oflag sr simm16 (const 0))))

     ()

)

(dni addx "addx"

     ((PIPE OS) (IDOC ALU))

     "addx $dr,$sr"

     (+ OP1_0 OP2_9 dr sr)

     (parallel ()

               (set dr (addc dr sr condbit))

               (set condbit (add-cflag dr sr condbit)))

     ()

)

(dni bc8 "bc with 8 bit displacement"

     (COND-CTI (PIPE O) (IDOC BR))

     "bc.s $disp8"

     (+ OP1_7 (f-r1 12) disp8)

     (if condbit (set pc disp8))

     ((m32r/d (unit u-cti))

      (m32rx (unit u-cti))

      (m32r2 (unit u-cti)))

)

(dnmi bc8r "relaxable bc8"

     (COND-CTI RELAXABLE (PIPE O) (IDOC BR))

     "bc $disp8"

     (emit bc8 disp8)

)

(dni bc24 "bc with 24 bit displacement"

     (COND-CTI (IDOC BR))

     "bc.l $disp24"

     (+ OP1_15 (f-r1 12) disp24)

     (if condbit (set pc disp24))

     ((m32r/d (unit u-cti))

      (m32rx (unit u-cti))

      (m32r2 (unit u-cti)))

)

(dnmi bc24r "relaxable bc24"

     (COND-CTI RELAXED (IDOC BR))

     "bc $disp24"

     (emit bc24 disp24)

)

(dni beq "beq"

     (COND-CTI (IDOC BR))

     "beq $src1,$src2,$disp16"

     (+ OP1_11 OP2_0 src1 src2 disp16)

     (if (eq src1 src2) (set pc disp16))

     ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))

      (m32rx (unit u-cti) (unit u-cmp (cycles 0)))

      (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))

)

(define-pmacro (cbranch sym comment op2-op comp-op)

  (dni sym comment (COND-CTI (IDOC BR))

        (.str sym " $src2,$disp16")

        (+ OP1_11 op2-op (f-r1 0) src2 disp16)

        (if (comp-op src2 (const WI 0)) (set pc disp16))

        ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))

         (m32rx (unit u-cti) (unit u-cmp (cycles 0)))

         (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))

        )

)

(cbranch beqz "beqz" OP2_8 eq)

(cbranch bgez "bgez" OP2_11 ge)