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[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [gas/] [config/] [m68k-parse.h] - Blame information for rev 299

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/* m68k-parse.h -- header file for m68k assembler
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   Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
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   2003, 2004, 2005, 2006, 2007, 2009 Free Software Foundation, Inc.
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   This file is part of GAS, the GNU Assembler.
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   GAS is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License as published by
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   the Free Software Foundation; either version 3, or (at your option)
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   any later version.
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   GAS is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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   GNU General Public License for more details.
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   You should have received a copy of the GNU General Public License
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   along with GAS; see the file COPYING.  If not, write to the Free
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   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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   02110-1301, USA.  */
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#ifndef M68K_PARSE_H
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#define M68K_PARSE_H
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/* This header file defines things which are shared between the
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   operand parser in m68k.y and the m68k assembler proper in
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   tc-m68k.c.  */
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/* The various m68k registers.  */
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/* DATA and ADDR have to be contiguous, so that reg-DATA gives
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   0-7==data reg, 8-15==addr reg for operands that take both types.
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   We don't use forms like "ADDR0 = ADDR" here because this file is
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   likely to be used on an Apollo, and the broken Apollo compiler
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   gives an `undefined variable' error if we do that, according to
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   troy@cbme.unsw.edu.au.  */
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#define DATA DATA0
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#define ADDR ADDR0
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#define SP ADDR7
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#define BAD BAD0
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#define BAC BAC0
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enum m68k_register
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{
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  DATA0 = 1,                    /*   1- 8 == data registers 0-7 */
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  DATA1,
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  DATA2,
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  DATA3,
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  DATA4,
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  DATA5,
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  DATA6,
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  DATA7,
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  ADDR0,
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  ADDR1,
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  ADDR2,
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  ADDR3,
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  ADDR4,
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  ADDR5,
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  ADDR6,
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  ADDR7,
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  FP0,                          /* Eight FP registers */
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  FP1,
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  FP2,
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  FP3,
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  FP4,
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  FP5,
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  FP6,
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  FP7,
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  COP0,                         /* Co-processor #0-#7 */
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  COP1,
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  COP2,
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  COP3,
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  COP4,
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  COP5,
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  COP6,
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  COP7,
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  PC,                           /* Program counter */
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  ZPC,                          /* Hack for Program space, but 0 addressing */
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  SR,                           /* Status Reg */
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  CCR,                          /* Condition code Reg */
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  ACC,                          /* Accumulator Reg0 (EMAC or ACC on MAC).  */
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  ACC1,                         /* Accumulator Reg 1 (EMAC).  */
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  ACC2,                         /* Accumulator Reg 2 (EMAC).  */
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  ACC3,                         /* Accumulator Reg 3 (EMAC).  */
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  ACCEXT01,                     /* Accumulator extension 0&1 (EMAC).  */
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  ACCEXT23,                     /* Accumulator extension 2&3 (EMAC).  */
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  MACSR,                        /* MAC Status Reg */
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  MASK,                         /* Modulus Reg */
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  /* These have to be grouped together for the movec instruction to work.  */
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  USP,                          /*  User Stack Pointer */
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  ISP,                          /*  Interrupt stack pointer */
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  SFC,
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  DFC,
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  CACR,
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  VBR,
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  CAAR,
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  CPUCR,
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  MSP,
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  ITT0,
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  ITT1,
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  DTT0,
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  DTT1,
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  MMUSR,
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  TC,
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  SRP,
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  URP,
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  BUSCR,                        /* 68060 added these.  */
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  PCR,
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  ROMBAR,                       /* mcf5200 added these.  */
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  RAMBAR_ALT,                   /* Some CF chips have RAMBAR using
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                                   RAMBAR0's number */
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  RAMBAR0,
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  RAMBAR1,
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  MMUBAR,                       /* mcfv4e added these.  */
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  ROMBAR0,                      /* mcfv4e added these.  */
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  ROMBAR1,                      /* mcfv4e added these.  */
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  MPCR, EDRAMBAR, SECMBAR,      /* mcfv4e added these.  */
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  PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these.  */
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  PCR2U0, PCR2L0, PCR2U1, PCR2L1,/* mcfv4e added these.  */
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  PCR3U0, PCR3L0, PCR3U1, PCR3L1,/* mcfv4e added these.  */
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  MBAR0, MBAR1,                 /* mcfv4e added these.  */
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  ACR0, ACR1, ACR2, ACR3,       /* mcf5200 added these.  */
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  ACR4, ACR5, ACR6, ACR7,       /* mcf54418 added these.  */
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  FLASHBAR, RAMBAR,             /* mcf528x added these.  */
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  MBAR2,                        /* mcf5249 added this.  */
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  MBAR,
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  RGPIOBAR,                     /* mcf54418 added this.  */
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  ASID,                         /* m5475.  */
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  CAC,                          /* fido added this.  */
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  MBO,
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#define last_movec_reg MBO
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  /* End of movec ordering constraints.  */
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  FPI,
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  FPS,
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  FPC,
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  DRP,                          /* 68851 or 68030 MMU regs */
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  CRP,
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  CAL,
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  VAL,
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  SCC,
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  AC,
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  BAD0,
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  BAD1,
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  BAD2,
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  BAD3,
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  BAD4,
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  BAD5,
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  BAD6,
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  BAD7,
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  BAC0,
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  BAC1,
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  BAC2,
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  BAC3,
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  BAC4,
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  BAC5,
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  BAC6,
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  BAC7,
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  PSR,                          /* aka MMUSR on 68030 (but not MMUSR on 68040)
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                                   and ACUSR on 68ec030 */
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  PCSR,
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  IC,                           /* instruction cache token */
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  DC,                           /* data cache token */
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  NC,                           /* no cache token */
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  BC,                           /* both caches token */
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  TT0,                          /* 68030 access control unit regs */
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  TT1,
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  ZDATA0,                       /* suppressed data registers.  */
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  ZDATA1,
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  ZDATA2,
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  ZDATA3,
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  ZDATA4,
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  ZDATA5,
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  ZDATA6,
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  ZDATA7,
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  ZADDR0,                       /* suppressed address registers.  */
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  ZADDR1,
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  ZADDR2,
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  ZADDR3,
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  ZADDR4,
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  ZADDR5,
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  ZADDR6,
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  ZADDR7,
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  /* Upper and lower half of data and address registers.  Order *must*
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     be DATAxL, ADDRxL, DATAxU, ADDRxU.  */
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  DATA0L,                       /* lower half of data registers */
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  DATA1L,
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  DATA2L,
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  DATA3L,
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  DATA4L,
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  DATA5L,
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  DATA6L,
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  DATA7L,
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  ADDR0L,                       /* lower half of address registers */
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  ADDR1L,
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  ADDR2L,
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  ADDR3L,
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  ADDR4L,
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  ADDR5L,
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  ADDR6L,
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  ADDR7L,
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  DATA0U,                       /* upper half of data registers */
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  DATA1U,
219
  DATA2U,
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  DATA3U,
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  DATA4U,
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  DATA5U,
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  DATA6U,
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  DATA7U,
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  ADDR0U,                       /* upper half of address registers */
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  ADDR1U,
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  ADDR2U,
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  ADDR3U,
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  ADDR4U,
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  ADDR5U,
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  ADDR6U,
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  ADDR7U,
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};
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/* Size information.  */
237
 
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enum m68k_size
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{
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  /* Unspecified.  */
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  SIZE_UNSPEC,
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  /* Byte.  */
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  SIZE_BYTE,
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  /* Word (2 bytes).  */
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  SIZE_WORD,
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  /* Longword (4 bytes).  */
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  SIZE_LONG
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};
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/* The structure used to hold information about an index register.  */
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struct m68k_indexreg
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{
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  /* The index register itself.  */
258
  enum m68k_register reg;
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  /* The size to use.  */
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  enum m68k_size size;
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  /* The value to scale by.  */
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  int scale;
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};
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#ifdef OBJ_ELF
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/* The type of a PIC expression.  */
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enum pic_relocation
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{
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  pic_none,                     /* not pic */
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  pic_plt_pcrel,                /* @PLTPC */
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  pic_got_pcrel,                /* @GOTPC */
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  pic_plt_off,                  /* @PLT */
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  pic_got_off,                  /* @GOT */
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  pic_tls_gd,                   /* @TLSGD */
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  pic_tls_ldm,                  /* @TLSLDM */
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  pic_tls_ldo,                  /* @TLSLDO */
280
  pic_tls_ie,                   /* @TLSIE */
281
  pic_tls_le                    /* @TLSLE */
282
};
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#endif
284
 
285
/* The structure used to hold information about an expression.  */
286
 
287
struct m68k_exp
288
{
289
  /* The size to use.  */
290
  enum m68k_size size;
291
 
292
#ifdef OBJ_ELF
293
  /* The type of pic relocation if any.  */
294
  enum pic_relocation pic_reloc;
295
#endif
296
 
297
  /* The expression itself.  */
298
  expressionS exp;
299
};
300
 
301
/* The operand modes.  */
302
 
303
enum m68k_operand_type
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{
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  IMMED = 1,
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  ABSL,
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  DREG,
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  AREG,
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  FPREG,
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  CONTROL,
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  AINDR,
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  AINC,
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  ADEC,
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  DISP,
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  BASE,
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  POST,
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  PRE,
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  LSH,  /* MAC/EMAC scalefactor '<<'.  */
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  RSH,  /* MAC/EMAC scalefactor '>>'.  */
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  REGLST
321
};
322
 
323
/* The structure used to hold a parsed operand.  */
324
 
325
struct m68k_op
326
{
327
  /* The type of operand.  */
328
  enum m68k_operand_type mode;
329
 
330
  /* The main register.  */
331
  enum m68k_register reg;
332
 
333
  /* The register mask for mode REGLST.  */
334
  unsigned long mask;
335
 
336
  /* An error message.  */
337
  const char *error;
338
 
339
  /* The index register.  */
340
  struct m68k_indexreg index;
341
 
342
  /* The displacement.  */
343
  struct m68k_exp disp;
344
 
345
  /* The outer displacement.  */
346
  struct m68k_exp odisp;
347
 
348
  /* Is a trailing '&' added to an <ea>? (for MAC/EMAC mask addressing).  */
349
  int trailing_ampersand;
350
};
351
 
352
#endif /* ! defined (M68K_PARSE_H) */
353
 
354
/* The parsing function.  */
355
 
356
extern int m68k_ip_op (char *, struct m68k_op *);
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/* Whether register prefixes are optional.  */
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extern int flag_reg_prefix_optional;

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