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khays |
/* tc-arm.c -- Assemble for the ARM
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Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
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2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
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Free Software Foundation, Inc.
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Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
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Modified by David Taylor (dtaylor@armltd.co.uk)
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Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
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Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
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Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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#include "as.h"
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#include <limits.h>
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#include <stdarg.h>
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#define NO_RELOC 0
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#include "safe-ctype.h"
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#include "subsegs.h"
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#include "obstack.h"
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#include "opcode/arm.h"
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#ifdef OBJ_ELF
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#include "elf/arm.h"
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#include "dw2gencfi.h"
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#endif
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#include "dwarf2dbg.h"
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#ifdef OBJ_ELF
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/* Must be at least the size of the largest unwind opcode (currently two). */
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#define ARM_OPCODE_CHUNK_SIZE 8
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/* This structure holds the unwinding state. */
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static struct
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{
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symbolS * proc_start;
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symbolS * table_entry;
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symbolS * personality_routine;
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int personality_index;
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/* The segment containing the function. */
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segT saved_seg;
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subsegT saved_subseg;
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/* Opcodes generated from this function. */
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unsigned char * opcodes;
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int opcode_count;
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int opcode_alloc;
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/* The number of bytes pushed to the stack. */
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offsetT frame_size;
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/* We don't add stack adjustment opcodes immediately so that we can merge
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multiple adjustments. We can also omit the final adjustment
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when using a frame pointer. */
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offsetT pending_offset;
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/* These two fields are set by both unwind_movsp and unwind_setfp. They
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hold the reg+offset to use when restoring sp from a frame pointer. */
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offsetT fp_offset;
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int fp_reg;
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/* Nonzero if an unwind_setfp directive has been seen. */
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unsigned fp_used:1;
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/* Nonzero if the last opcode restores sp from fp_reg. */
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unsigned sp_restored:1;
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} unwind;
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#endif /* OBJ_ELF */
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/* Results from operand parsing worker functions. */
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typedef enum
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{
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PARSE_OPERAND_SUCCESS,
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PARSE_OPERAND_FAIL,
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PARSE_OPERAND_FAIL_NO_BACKTRACK
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} parse_operand_result;
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enum arm_float_abi
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{
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ARM_FLOAT_ABI_HARD,
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ARM_FLOAT_ABI_SOFTFP,
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ARM_FLOAT_ABI_SOFT
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};
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/* Types of processor to assemble for. */
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#ifndef CPU_DEFAULT
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/* The code that was here used to select a default CPU depending on compiler
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pre-defines which were only present when doing native builds, thus
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changing gas' default behaviour depending upon the build host.
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If you have a target that requires a default CPU option then the you
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should define CPU_DEFAULT here. */
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#endif
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#ifndef FPU_DEFAULT
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# ifdef TE_LINUX
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# define FPU_DEFAULT FPU_ARCH_FPA
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# elif defined (TE_NetBSD)
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# ifdef OBJ_ELF
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# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
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# else
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/* Legacy a.out format. */
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# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
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# endif
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# elif defined (TE_VXWORKS)
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# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
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# else
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/* For backwards compatibility, default to FPA. */
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# define FPU_DEFAULT FPU_ARCH_FPA
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# endif
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#endif /* ifndef FPU_DEFAULT */
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#define streq(a, b) (strcmp (a, b) == 0)
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static arm_feature_set cpu_variant;
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static arm_feature_set arm_arch_used;
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static arm_feature_set thumb_arch_used;
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/* Flags stored in private area of BFD structure. */
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static int uses_apcs_26 = FALSE;
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static int atpcs = FALSE;
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static int support_interwork = FALSE;
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static int uses_apcs_float = FALSE;
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static int pic_code = FALSE;
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static int fix_v4bx = FALSE;
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/* Warn on using deprecated features. */
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static int warn_on_deprecated = TRUE;
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/* Variables that we set while parsing command-line options. Once all
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options have been read we re-process these values to set the real
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assembly flags. */
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static const arm_feature_set *legacy_cpu = NULL;
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static const arm_feature_set *legacy_fpu = NULL;
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static const arm_feature_set *mcpu_cpu_opt = NULL;
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static const arm_feature_set *mcpu_fpu_opt = NULL;
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static const arm_feature_set *march_cpu_opt = NULL;
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static const arm_feature_set *march_fpu_opt = NULL;
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static const arm_feature_set *mfpu_opt = NULL;
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static const arm_feature_set *object_arch = NULL;
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/* Constants for known architecture features. */
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static const arm_feature_set fpu_default = FPU_DEFAULT;
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static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
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static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
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static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
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static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
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static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
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static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
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static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
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static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
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#ifdef CPU_DEFAULT
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static const arm_feature_set cpu_default = CPU_DEFAULT;
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#endif
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static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
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static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
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static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
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static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
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static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
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static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
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static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
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static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
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static const arm_feature_set arm_ext_v4t_5 =
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ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
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static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
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static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
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static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
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static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
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static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
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static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
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static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
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static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
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static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
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static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
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static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
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static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
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static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
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static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
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static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
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static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
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static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
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static const arm_feature_set arm_ext_m =
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ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
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static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
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static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
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static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
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static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
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static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
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static const arm_feature_set arm_arch_any = ARM_ANY;
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static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
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static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
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static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
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static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
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static const arm_feature_set arm_cext_iwmmxt2 =
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ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
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static const arm_feature_set arm_cext_iwmmxt =
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ARM_FEATURE (0, ARM_CEXT_IWMMXT);
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static const arm_feature_set arm_cext_xscale =
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ARM_FEATURE (0, ARM_CEXT_XSCALE);
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static const arm_feature_set arm_cext_maverick =
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ARM_FEATURE (0, ARM_CEXT_MAVERICK);
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static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
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static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
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static const arm_feature_set fpu_vfp_ext_v1xd =
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ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
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static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
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static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
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static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
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static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
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static const arm_feature_set fpu_vfp_ext_d32 =
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ARM_FEATURE (0, FPU_VFP_EXT_D32);
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static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
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static const arm_feature_set fpu_vfp_v3_or_neon_ext =
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ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
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static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
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static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
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static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
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237 |
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static int mfloat_abi_opt = -1;
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/* Record user cpu selection for object attributes. */
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static arm_feature_set selected_cpu = ARM_ARCH_NONE;
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/* Must be long enough to hold any of the names in arm_cpus. */
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241 |
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static char selected_cpu_name[16];
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242 |
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243 |
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/* Return if no cpu was selected on command-line. */
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244 |
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static bfd_boolean
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no_cpu_selected (void)
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{
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247 |
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return selected_cpu.core == arm_arch_none.core
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&& selected_cpu.coproc == arm_arch_none.coproc;
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249 |
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}
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250 |
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251 |
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#ifdef OBJ_ELF
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252 |
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# ifdef EABI_DEFAULT
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253 |
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static int meabi_flags = EABI_DEFAULT;
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# else
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static int meabi_flags = EF_ARM_EABI_UNKNOWN;
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# endif
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257 |
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258 |
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static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
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259 |
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260 |
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bfd_boolean
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261 |
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arm_is_eabi (void)
|
262 |
|
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{
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263 |
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return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
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264 |
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}
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265 |
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#endif
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266 |
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267 |
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#ifdef OBJ_ELF
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/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
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|
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symbolS * GOT_symbol;
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270 |
|
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#endif
|
271 |
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272 |
|
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/* 0: assemble for ARM,
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|
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1: assemble for Thumb,
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|
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2: assemble for Thumb even though target CPU does not support thumb
|
275 |
|
|
instructions. */
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276 |
|
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static int thumb_mode = 0;
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277 |
|
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/* A value distinct from the possible values for thumb_mode that we
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278 |
|
|
can use to record whether thumb_mode has been copied into the
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279 |
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|
tc_frag_data field of a frag. */
|
280 |
|
|
#define MODE_RECORDED (1 << 4)
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281 |
|
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|
282 |
|
|
/* Specifies the intrinsic IT insn behavior mode. */
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283 |
|
|
enum implicit_it_mode
|
284 |
|
|
{
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285 |
|
|
IMPLICIT_IT_MODE_NEVER = 0x00,
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|
|
IMPLICIT_IT_MODE_ARM = 0x01,
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|
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IMPLICIT_IT_MODE_THUMB = 0x02,
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|
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IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
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};
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290 |
|
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static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
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291 |
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292 |
|
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/* If unified_syntax is true, we are processing the new unified
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293 |
|
|
ARM/Thumb syntax. Important differences from the old ARM mode:
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294 |
|
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|
295 |
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|
- Immediate operands do not require a # prefix.
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296 |
|
|
- Conditional affixes always appear at the end of the
|
297 |
|
|
instruction. (For backward compatibility, those instructions
|
298 |
|
|
that formerly had them in the middle, continue to accept them
|
299 |
|
|
there.)
|
300 |
|
|
- The IT instruction may appear, and if it does is validated
|
301 |
|
|
against subsequent conditional affixes. It does not generate
|
302 |
|
|
machine code.
|
303 |
|
|
|
304 |
|
|
Important differences from the old Thumb mode:
|
305 |
|
|
|
306 |
|
|
- Immediate operands do not require a # prefix.
|
307 |
|
|
- Most of the V6T2 instructions are only available in unified mode.
|
308 |
|
|
- The .N and .W suffixes are recognized and honored (it is an error
|
309 |
|
|
if they cannot be honored).
|
310 |
|
|
- All instructions set the flags if and only if they have an 's' affix.
|
311 |
|
|
- Conditional affixes may be used. They are validated against
|
312 |
|
|
preceding IT instructions. Unlike ARM mode, you cannot use a
|
313 |
|
|
conditional affix except in the scope of an IT instruction. */
|
314 |
|
|
|
315 |
|
|
static bfd_boolean unified_syntax = FALSE;
|
316 |
|
|
|
317 |
|
|
enum neon_el_type
|
318 |
|
|
{
|
319 |
|
|
NT_invtype,
|
320 |
|
|
NT_untyped,
|
321 |
|
|
NT_integer,
|
322 |
|
|
NT_float,
|
323 |
|
|
NT_poly,
|
324 |
|
|
NT_signed,
|
325 |
|
|
NT_unsigned
|
326 |
|
|
};
|
327 |
|
|
|
328 |
|
|
struct neon_type_el
|
329 |
|
|
{
|
330 |
|
|
enum neon_el_type type;
|
331 |
|
|
unsigned size;
|
332 |
|
|
};
|
333 |
|
|
|
334 |
|
|
#define NEON_MAX_TYPE_ELS 4
|
335 |
|
|
|
336 |
|
|
struct neon_type
|
337 |
|
|
{
|
338 |
|
|
struct neon_type_el el[NEON_MAX_TYPE_ELS];
|
339 |
|
|
unsigned elems;
|
340 |
|
|
};
|
341 |
|
|
|
342 |
|
|
enum it_instruction_type
|
343 |
|
|
{
|
344 |
|
|
OUTSIDE_IT_INSN,
|
345 |
|
|
INSIDE_IT_INSN,
|
346 |
|
|
INSIDE_IT_LAST_INSN,
|
347 |
|
|
IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
|
348 |
|
|
if inside, should be the last one. */
|
349 |
|
|
NEUTRAL_IT_INSN, /* This could be either inside or outside,
|
350 |
|
|
i.e. BKPT and NOP. */
|
351 |
|
|
IT_INSN /* The IT insn has been parsed. */
|
352 |
|
|
};
|
353 |
|
|
|
354 |
|
|
struct arm_it
|
355 |
|
|
{
|
356 |
|
|
const char * error;
|
357 |
|
|
unsigned long instruction;
|
358 |
|
|
int size;
|
359 |
|
|
int size_req;
|
360 |
|
|
int cond;
|
361 |
|
|
/* "uncond_value" is set to the value in place of the conditional field in
|
362 |
|
|
unconditional versions of the instruction, or -1 if nothing is
|
363 |
|
|
appropriate. */
|
364 |
|
|
int uncond_value;
|
365 |
|
|
struct neon_type vectype;
|
366 |
|
|
/* This does not indicate an actual NEON instruction, only that
|
367 |
|
|
the mnemonic accepts neon-style type suffixes. */
|
368 |
|
|
int is_neon;
|
369 |
|
|
/* Set to the opcode if the instruction needs relaxation.
|
370 |
|
|
Zero if the instruction is not relaxed. */
|
371 |
|
|
unsigned long relax;
|
372 |
|
|
struct
|
373 |
|
|
{
|
374 |
|
|
bfd_reloc_code_real_type type;
|
375 |
|
|
expressionS exp;
|
376 |
|
|
int pc_rel;
|
377 |
|
|
} reloc;
|
378 |
|
|
|
379 |
|
|
enum it_instruction_type it_insn_type;
|
380 |
|
|
|
381 |
|
|
struct
|
382 |
|
|
{
|
383 |
|
|
unsigned reg;
|
384 |
|
|
signed int imm;
|
385 |
|
|
struct neon_type_el vectype;
|
386 |
|
|
unsigned present : 1; /* Operand present. */
|
387 |
|
|
unsigned isreg : 1; /* Operand was a register. */
|
388 |
|
|
unsigned immisreg : 1; /* .imm field is a second register. */
|
389 |
|
|
unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
|
390 |
|
|
unsigned immisalign : 1; /* Immediate is an alignment specifier. */
|
391 |
|
|
unsigned immisfloat : 1; /* Immediate was parsed as a float. */
|
392 |
|
|
/* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
|
393 |
|
|
instructions. This allows us to disambiguate ARM <-> vector insns. */
|
394 |
|
|
unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
|
395 |
|
|
unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
|
396 |
|
|
unsigned isquad : 1; /* Operand is Neon quad-precision register. */
|
397 |
|
|
unsigned issingle : 1; /* Operand is VFP single-precision register. */
|
398 |
|
|
unsigned hasreloc : 1; /* Operand has relocation suffix. */
|
399 |
|
|
unsigned writeback : 1; /* Operand has trailing ! */
|
400 |
|
|
unsigned preind : 1; /* Preindexed address. */
|
401 |
|
|
unsigned postind : 1; /* Postindexed address. */
|
402 |
|
|
unsigned negative : 1; /* Index register was negated. */
|
403 |
|
|
unsigned shifted : 1; /* Shift applied to operation. */
|
404 |
|
|
unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
|
405 |
|
|
} operands[6];
|
406 |
|
|
};
|
407 |
|
|
|
408 |
|
|
static struct arm_it inst;
|
409 |
|
|
|
410 |
|
|
#define NUM_FLOAT_VALS 8
|
411 |
|
|
|
412 |
|
|
const char * fp_const[] =
|
413 |
|
|
{
|
414 |
|
|
"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
|
415 |
|
|
};
|
416 |
|
|
|
417 |
|
|
/* Number of littlenums required to hold an extended precision number. */
|
418 |
|
|
#define MAX_LITTLENUMS 6
|
419 |
|
|
|
420 |
|
|
LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
|
421 |
|
|
|
422 |
|
|
#define FAIL (-1)
|
423 |
|
|
#define SUCCESS (0)
|
424 |
|
|
|
425 |
|
|
#define SUFF_S 1
|
426 |
|
|
#define SUFF_D 2
|
427 |
|
|
#define SUFF_E 3
|
428 |
|
|
#define SUFF_P 4
|
429 |
|
|
|
430 |
|
|
#define CP_T_X 0x00008000
|
431 |
|
|
#define CP_T_Y 0x00400000
|
432 |
|
|
|
433 |
|
|
#define CONDS_BIT 0x00100000
|
434 |
|
|
#define LOAD_BIT 0x00100000
|
435 |
|
|
|
436 |
|
|
#define DOUBLE_LOAD_FLAG 0x00000001
|
437 |
|
|
|
438 |
|
|
struct asm_cond
|
439 |
|
|
{
|
440 |
|
|
const char * template_name;
|
441 |
|
|
unsigned long value;
|
442 |
|
|
};
|
443 |
|
|
|
444 |
|
|
#define COND_ALWAYS 0xE
|
445 |
|
|
|
446 |
|
|
struct asm_psr
|
447 |
|
|
{
|
448 |
|
|
const char * template_name;
|
449 |
|
|
unsigned long field;
|
450 |
|
|
};
|
451 |
|
|
|
452 |
|
|
struct asm_barrier_opt
|
453 |
|
|
{
|
454 |
|
|
const char * template_name;
|
455 |
|
|
unsigned long value;
|
456 |
|
|
};
|
457 |
|
|
|
458 |
|
|
/* The bit that distinguishes CPSR and SPSR. */
|
459 |
|
|
#define SPSR_BIT (1 << 22)
|
460 |
|
|
|
461 |
|
|
/* The individual PSR flag bits. */
|
462 |
|
|
#define PSR_c (1 << 16)
|
463 |
|
|
#define PSR_x (1 << 17)
|
464 |
|
|
#define PSR_s (1 << 18)
|
465 |
|
|
#define PSR_f (1 << 19)
|
466 |
|
|
|
467 |
|
|
struct reloc_entry
|
468 |
|
|
{
|
469 |
|
|
char * name;
|
470 |
|
|
bfd_reloc_code_real_type reloc;
|
471 |
|
|
};
|
472 |
|
|
|
473 |
|
|
enum vfp_reg_pos
|
474 |
|
|
{
|
475 |
|
|
VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
|
476 |
|
|
VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
|
477 |
|
|
};
|
478 |
|
|
|
479 |
|
|
enum vfp_ldstm_type
|
480 |
|
|
{
|
481 |
|
|
VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
|
482 |
|
|
};
|
483 |
|
|
|
484 |
|
|
/* Bits for DEFINED field in neon_typed_alias. */
|
485 |
|
|
#define NTA_HASTYPE 1
|
486 |
|
|
#define NTA_HASINDEX 2
|
487 |
|
|
|
488 |
|
|
struct neon_typed_alias
|
489 |
|
|
{
|
490 |
|
|
unsigned char defined;
|
491 |
|
|
unsigned char index;
|
492 |
|
|
struct neon_type_el eltype;
|
493 |
|
|
};
|
494 |
|
|
|
495 |
|
|
/* ARM register categories. This includes coprocessor numbers and various
|
496 |
|
|
architecture extensions' registers. */
|
497 |
|
|
enum arm_reg_type
|
498 |
|
|
{
|
499 |
|
|
REG_TYPE_RN,
|
500 |
|
|
REG_TYPE_CP,
|
501 |
|
|
REG_TYPE_CN,
|
502 |
|
|
REG_TYPE_FN,
|
503 |
|
|
REG_TYPE_VFS,
|
504 |
|
|
REG_TYPE_VFD,
|
505 |
|
|
REG_TYPE_NQ,
|
506 |
|
|
REG_TYPE_VFSD,
|
507 |
|
|
REG_TYPE_NDQ,
|
508 |
|
|
REG_TYPE_NSDQ,
|
509 |
|
|
REG_TYPE_VFC,
|
510 |
|
|
REG_TYPE_MVF,
|
511 |
|
|
REG_TYPE_MVD,
|
512 |
|
|
REG_TYPE_MVFX,
|
513 |
|
|
REG_TYPE_MVDX,
|
514 |
|
|
REG_TYPE_MVAX,
|
515 |
|
|
REG_TYPE_DSPSC,
|
516 |
|
|
REG_TYPE_MMXWR,
|
517 |
|
|
REG_TYPE_MMXWC,
|
518 |
|
|
REG_TYPE_MMXWCG,
|
519 |
|
|
REG_TYPE_XSCALE,
|
520 |
|
|
REG_TYPE_RNB
|
521 |
|
|
};
|
522 |
|
|
|
523 |
|
|
/* Structure for a hash table entry for a register.
|
524 |
|
|
If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
|
525 |
|
|
information which states whether a vector type or index is specified (for a
|
526 |
|
|
register alias created with .dn or .qn). Otherwise NEON should be NULL. */
|
527 |
|
|
struct reg_entry
|
528 |
|
|
{
|
529 |
|
|
const char * name;
|
530 |
|
|
unsigned int number;
|
531 |
|
|
unsigned char type;
|
532 |
|
|
unsigned char builtin;
|
533 |
|
|
struct neon_typed_alias * neon;
|
534 |
|
|
};
|
535 |
|
|
|
536 |
|
|
/* Diagnostics used when we don't get a register of the expected type. */
|
537 |
|
|
const char * const reg_expected_msgs[] =
|
538 |
|
|
{
|
539 |
|
|
N_("ARM register expected"),
|
540 |
|
|
N_("bad or missing co-processor number"),
|
541 |
|
|
N_("co-processor register expected"),
|
542 |
|
|
N_("FPA register expected"),
|
543 |
|
|
N_("VFP single precision register expected"),
|
544 |
|
|
N_("VFP/Neon double precision register expected"),
|
545 |
|
|
N_("Neon quad precision register expected"),
|
546 |
|
|
N_("VFP single or double precision register expected"),
|
547 |
|
|
N_("Neon double or quad precision register expected"),
|
548 |
|
|
N_("VFP single, double or Neon quad precision register expected"),
|
549 |
|
|
N_("VFP system register expected"),
|
550 |
|
|
N_("Maverick MVF register expected"),
|
551 |
|
|
N_("Maverick MVD register expected"),
|
552 |
|
|
N_("Maverick MVFX register expected"),
|
553 |
|
|
N_("Maverick MVDX register expected"),
|
554 |
|
|
N_("Maverick MVAX register expected"),
|
555 |
|
|
N_("Maverick DSPSC register expected"),
|
556 |
|
|
N_("iWMMXt data register expected"),
|
557 |
|
|
N_("iWMMXt control register expected"),
|
558 |
|
|
N_("iWMMXt scalar register expected"),
|
559 |
|
|
N_("XScale accumulator register expected"),
|
560 |
|
|
};
|
561 |
|
|
|
562 |
|
|
/* Some well known registers that we refer to directly elsewhere. */
|
563 |
|
|
#define REG_SP 13
|
564 |
|
|
#define REG_LR 14
|
565 |
|
|
#define REG_PC 15
|
566 |
|
|
|
567 |
|
|
/* ARM instructions take 4bytes in the object file, Thumb instructions
|
568 |
|
|
take 2: */
|
569 |
|
|
#define INSN_SIZE 4
|
570 |
|
|
|
571 |
|
|
struct asm_opcode
|
572 |
|
|
{
|
573 |
|
|
/* Basic string to match. */
|
574 |
|
|
const char * template_name;
|
575 |
|
|
|
576 |
|
|
/* Parameters to instruction. */
|
577 |
|
|
unsigned int operands[8];
|
578 |
|
|
|
579 |
|
|
/* Conditional tag - see opcode_lookup. */
|
580 |
|
|
unsigned int tag : 4;
|
581 |
|
|
|
582 |
|
|
/* Basic instruction code. */
|
583 |
|
|
unsigned int avalue : 28;
|
584 |
|
|
|
585 |
|
|
/* Thumb-format instruction code. */
|
586 |
|
|
unsigned int tvalue;
|
587 |
|
|
|
588 |
|
|
/* Which architecture variant provides this instruction. */
|
589 |
|
|
const arm_feature_set * avariant;
|
590 |
|
|
const arm_feature_set * tvariant;
|
591 |
|
|
|
592 |
|
|
/* Function to call to encode instruction in ARM format. */
|
593 |
|
|
void (* aencode) (void);
|
594 |
|
|
|
595 |
|
|
/* Function to call to encode instruction in Thumb format. */
|
596 |
|
|
void (* tencode) (void);
|
597 |
|
|
};
|
598 |
|
|
|
599 |
|
|
/* Defines for various bits that we will want to toggle. */
|
600 |
|
|
#define INST_IMMEDIATE 0x02000000
|
601 |
|
|
#define OFFSET_REG 0x02000000
|
602 |
|
|
#define HWOFFSET_IMM 0x00400000
|
603 |
|
|
#define SHIFT_BY_REG 0x00000010
|
604 |
|
|
#define PRE_INDEX 0x01000000
|
605 |
|
|
#define INDEX_UP 0x00800000
|
606 |
|
|
#define WRITE_BACK 0x00200000
|
607 |
|
|
#define LDM_TYPE_2_OR_3 0x00400000
|
608 |
|
|
#define CPSI_MMOD 0x00020000
|
609 |
|
|
|
610 |
|
|
#define LITERAL_MASK 0xf000f000
|
611 |
|
|
#define OPCODE_MASK 0xfe1fffff
|
612 |
|
|
#define V4_STR_BIT 0x00000020
|
613 |
|
|
|
614 |
|
|
#define T2_SUBS_PC_LR 0xf3de8f00
|
615 |
|
|
|
616 |
|
|
#define DATA_OP_SHIFT 21
|
617 |
|
|
|
618 |
|
|
#define T2_OPCODE_MASK 0xfe1fffff
|
619 |
|
|
#define T2_DATA_OP_SHIFT 21
|
620 |
|
|
|
621 |
|
|
/* Codes to distinguish the arithmetic instructions. */
|
622 |
|
|
#define OPCODE_AND 0
|
623 |
|
|
#define OPCODE_EOR 1
|
624 |
|
|
#define OPCODE_SUB 2
|
625 |
|
|
#define OPCODE_RSB 3
|
626 |
|
|
#define OPCODE_ADD 4
|
627 |
|
|
#define OPCODE_ADC 5
|
628 |
|
|
#define OPCODE_SBC 6
|
629 |
|
|
#define OPCODE_RSC 7
|
630 |
|
|
#define OPCODE_TST 8
|
631 |
|
|
#define OPCODE_TEQ 9
|
632 |
|
|
#define OPCODE_CMP 10
|
633 |
|
|
#define OPCODE_CMN 11
|
634 |
|
|
#define OPCODE_ORR 12
|
635 |
|
|
#define OPCODE_MOV 13
|
636 |
|
|
#define OPCODE_BIC 14
|
637 |
|
|
#define OPCODE_MVN 15
|
638 |
|
|
|
639 |
|
|
#define T2_OPCODE_AND 0
|
640 |
|
|
#define T2_OPCODE_BIC 1
|
641 |
|
|
#define T2_OPCODE_ORR 2
|
642 |
|
|
#define T2_OPCODE_ORN 3
|
643 |
|
|
#define T2_OPCODE_EOR 4
|
644 |
|
|
#define T2_OPCODE_ADD 8
|
645 |
|
|
#define T2_OPCODE_ADC 10
|
646 |
|
|
#define T2_OPCODE_SBC 11
|
647 |
|
|
#define T2_OPCODE_SUB 13
|
648 |
|
|
#define T2_OPCODE_RSB 14
|
649 |
|
|
|
650 |
|
|
#define T_OPCODE_MUL 0x4340
|
651 |
|
|
#define T_OPCODE_TST 0x4200
|
652 |
|
|
#define T_OPCODE_CMN 0x42c0
|
653 |
|
|
#define T_OPCODE_NEG 0x4240
|
654 |
|
|
#define T_OPCODE_MVN 0x43c0
|
655 |
|
|
|
656 |
|
|
#define T_OPCODE_ADD_R3 0x1800
|
657 |
|
|
#define T_OPCODE_SUB_R3 0x1a00
|
658 |
|
|
#define T_OPCODE_ADD_HI 0x4400
|
659 |
|
|
#define T_OPCODE_ADD_ST 0xb000
|
660 |
|
|
#define T_OPCODE_SUB_ST 0xb080
|
661 |
|
|
#define T_OPCODE_ADD_SP 0xa800
|
662 |
|
|
#define T_OPCODE_ADD_PC 0xa000
|
663 |
|
|
#define T_OPCODE_ADD_I8 0x3000
|
664 |
|
|
#define T_OPCODE_SUB_I8 0x3800
|
665 |
|
|
#define T_OPCODE_ADD_I3 0x1c00
|
666 |
|
|
#define T_OPCODE_SUB_I3 0x1e00
|
667 |
|
|
|
668 |
|
|
#define T_OPCODE_ASR_R 0x4100
|
669 |
|
|
#define T_OPCODE_LSL_R 0x4080
|
670 |
|
|
#define T_OPCODE_LSR_R 0x40c0
|
671 |
|
|
#define T_OPCODE_ROR_R 0x41c0
|
672 |
|
|
#define T_OPCODE_ASR_I 0x1000
|
673 |
|
|
#define T_OPCODE_LSL_I 0x0000
|
674 |
|
|
#define T_OPCODE_LSR_I 0x0800
|
675 |
|
|
|
676 |
|
|
#define T_OPCODE_MOV_I8 0x2000
|
677 |
|
|
#define T_OPCODE_CMP_I8 0x2800
|
678 |
|
|
#define T_OPCODE_CMP_LR 0x4280
|
679 |
|
|
#define T_OPCODE_MOV_HR 0x4600
|
680 |
|
|
#define T_OPCODE_CMP_HR 0x4500
|
681 |
|
|
|
682 |
|
|
#define T_OPCODE_LDR_PC 0x4800
|
683 |
|
|
#define T_OPCODE_LDR_SP 0x9800
|
684 |
|
|
#define T_OPCODE_STR_SP 0x9000
|
685 |
|
|
#define T_OPCODE_LDR_IW 0x6800
|
686 |
|
|
#define T_OPCODE_STR_IW 0x6000
|
687 |
|
|
#define T_OPCODE_LDR_IH 0x8800
|
688 |
|
|
#define T_OPCODE_STR_IH 0x8000
|
689 |
|
|
#define T_OPCODE_LDR_IB 0x7800
|
690 |
|
|
#define T_OPCODE_STR_IB 0x7000
|
691 |
|
|
#define T_OPCODE_LDR_RW 0x5800
|
692 |
|
|
#define T_OPCODE_STR_RW 0x5000
|
693 |
|
|
#define T_OPCODE_LDR_RH 0x5a00
|
694 |
|
|
#define T_OPCODE_STR_RH 0x5200
|
695 |
|
|
#define T_OPCODE_LDR_RB 0x5c00
|
696 |
|
|
#define T_OPCODE_STR_RB 0x5400
|
697 |
|
|
|
698 |
|
|
#define T_OPCODE_PUSH 0xb400
|
699 |
|
|
#define T_OPCODE_POP 0xbc00
|
700 |
|
|
|
701 |
|
|
#define T_OPCODE_BRANCH 0xe000
|
702 |
|
|
|
703 |
|
|
#define THUMB_SIZE 2 /* Size of thumb instruction. */
|
704 |
|
|
#define THUMB_PP_PC_LR 0x0100
|
705 |
|
|
#define THUMB_LOAD_BIT 0x0800
|
706 |
|
|
#define THUMB2_LOAD_BIT 0x00100000
|
707 |
|
|
|
708 |
|
|
#define BAD_ARGS _("bad arguments to instruction")
|
709 |
|
|
#define BAD_SP _("r13 not allowed here")
|
710 |
|
|
#define BAD_PC _("r15 not allowed here")
|
711 |
|
|
#define BAD_COND _("instruction cannot be conditional")
|
712 |
|
|
#define BAD_OVERLAP _("registers may not be the same")
|
713 |
|
|
#define BAD_HIREG _("lo register required")
|
714 |
|
|
#define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
|
715 |
|
|
#define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
|
716 |
|
|
#define BAD_BRANCH _("branch must be last instruction in IT block")
|
717 |
|
|
#define BAD_NOT_IT _("instruction not allowed in IT block")
|
718 |
|
|
#define BAD_FPU _("selected FPU does not support instruction")
|
719 |
|
|
#define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
|
720 |
|
|
#define BAD_IT_COND _("incorrect condition in IT block")
|
721 |
|
|
#define BAD_IT_IT _("IT falling in the range of a previous IT block")
|
722 |
|
|
#define MISSING_FNSTART _("missing .fnstart before unwinding directive")
|
723 |
|
|
#define BAD_PC_ADDRESSING \
|
724 |
|
|
_("cannot use register index with PC-relative addressing")
|
725 |
|
|
#define BAD_PC_WRITEBACK \
|
726 |
|
|
_("cannot use writeback with PC-relative addressing")
|
727 |
|
|
|
728 |
|
|
static struct hash_control * arm_ops_hsh;
|
729 |
|
|
static struct hash_control * arm_cond_hsh;
|
730 |
|
|
static struct hash_control * arm_shift_hsh;
|
731 |
|
|
static struct hash_control * arm_psr_hsh;
|
732 |
|
|
static struct hash_control * arm_v7m_psr_hsh;
|
733 |
|
|
static struct hash_control * arm_reg_hsh;
|
734 |
|
|
static struct hash_control * arm_reloc_hsh;
|
735 |
|
|
static struct hash_control * arm_barrier_opt_hsh;
|
736 |
|
|
|
737 |
|
|
/* Stuff needed to resolve the label ambiguity
|
738 |
|
|
As:
|
739 |
|
|
...
|
740 |
|
|
label: <insn>
|
741 |
|
|
may differ from:
|
742 |
|
|
...
|
743 |
|
|
label:
|
744 |
|
|
<insn> */
|
745 |
|
|
|
746 |
|
|
symbolS * last_label_seen;
|
747 |
|
|
static int label_is_thumb_function_name = FALSE;
|
748 |
|
|
|
749 |
|
|
/* Literal pool structure. Held on a per-section
|
750 |
|
|
and per-sub-section basis. */
|
751 |
|
|
|
752 |
|
|
#define MAX_LITERAL_POOL_SIZE 1024
|
753 |
|
|
typedef struct literal_pool
|
754 |
|
|
{
|
755 |
|
|
expressionS literals [MAX_LITERAL_POOL_SIZE];
|
756 |
|
|
unsigned int next_free_entry;
|
757 |
|
|
unsigned int id;
|
758 |
|
|
symbolS * symbol;
|
759 |
|
|
segT section;
|
760 |
|
|
subsegT sub_section;
|
761 |
|
|
struct literal_pool * next;
|
762 |
|
|
} literal_pool;
|
763 |
|
|
|
764 |
|
|
/* Pointer to a linked list of literal pools. */
|
765 |
|
|
literal_pool * list_of_pools = NULL;
|
766 |
|
|
|
767 |
|
|
#ifdef OBJ_ELF
|
768 |
|
|
# define now_it seg_info (now_seg)->tc_segment_info_data.current_it
|
769 |
|
|
#else
|
770 |
|
|
static struct current_it now_it;
|
771 |
|
|
#endif
|
772 |
|
|
|
773 |
|
|
static inline int
|
774 |
|
|
now_it_compatible (int cond)
|
775 |
|
|
{
|
776 |
|
|
return (cond & ~1) == (now_it.cc & ~1);
|
777 |
|
|
}
|
778 |
|
|
|
779 |
|
|
static inline int
|
780 |
|
|
conditional_insn (void)
|
781 |
|
|
{
|
782 |
|
|
return inst.cond != COND_ALWAYS;
|
783 |
|
|
}
|
784 |
|
|
|
785 |
|
|
static int in_it_block (void);
|
786 |
|
|
|
787 |
|
|
static int handle_it_state (void);
|
788 |
|
|
|
789 |
|
|
static void force_automatic_it_block_close (void);
|
790 |
|
|
|
791 |
|
|
static void it_fsm_post_encode (void);
|
792 |
|
|
|
793 |
|
|
#define set_it_insn_type(type) \
|
794 |
|
|
do \
|
795 |
|
|
{ \
|
796 |
|
|
inst.it_insn_type = type; \
|
797 |
|
|
if (handle_it_state () == FAIL) \
|
798 |
|
|
return; \
|
799 |
|
|
} \
|
800 |
|
|
while (0)
|
801 |
|
|
|
802 |
|
|
#define set_it_insn_type_nonvoid(type, failret) \
|
803 |
|
|
do \
|
804 |
|
|
{ \
|
805 |
|
|
inst.it_insn_type = type; \
|
806 |
|
|
if (handle_it_state () == FAIL) \
|
807 |
|
|
return failret; \
|
808 |
|
|
} \
|
809 |
|
|
while(0)
|
810 |
|
|
|
811 |
|
|
#define set_it_insn_type_last() \
|
812 |
|
|
do \
|
813 |
|
|
{ \
|
814 |
|
|
if (inst.cond == COND_ALWAYS) \
|
815 |
|
|
set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
|
816 |
|
|
else \
|
817 |
|
|
set_it_insn_type (INSIDE_IT_LAST_INSN); \
|
818 |
|
|
} \
|
819 |
|
|
while (0)
|
820 |
|
|
|
821 |
|
|
/* Pure syntax. */
|
822 |
|
|
|
823 |
|
|
/* This array holds the chars that always start a comment. If the
|
824 |
|
|
pre-processor is disabled, these aren't very useful. */
|
825 |
|
|
const char comment_chars[] = "@";
|
826 |
|
|
|
827 |
|
|
/* This array holds the chars that only start a comment at the beginning of
|
828 |
|
|
a line. If the line seems to have the form '# 123 filename'
|
829 |
|
|
.line and .file directives will appear in the pre-processed output. */
|
830 |
|
|
/* Note that input_file.c hand checks for '#' at the beginning of the
|
831 |
|
|
first line of the input file. This is because the compiler outputs
|
832 |
|
|
#NO_APP at the beginning of its output. */
|
833 |
|
|
/* Also note that comments like this one will always work. */
|
834 |
|
|
const char line_comment_chars[] = "#";
|
835 |
|
|
|
836 |
|
|
const char line_separator_chars[] = ";";
|
837 |
|
|
|
838 |
|
|
/* Chars that can be used to separate mant
|
839 |
|
|
from exp in floating point numbers. */
|
840 |
|
|
const char EXP_CHARS[] = "eE";
|
841 |
|
|
|
842 |
|
|
/* Chars that mean this number is a floating point constant. */
|
843 |
|
|
/* As in 0f12.456 */
|
844 |
|
|
/* or 0d1.2345e12 */
|
845 |
|
|
|
846 |
|
|
const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
|
847 |
|
|
|
848 |
|
|
/* Prefix characters that indicate the start of an immediate
|
849 |
|
|
value. */
|
850 |
|
|
#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
|
851 |
|
|
|
852 |
|
|
/* Separator character handling. */
|
853 |
|
|
|
854 |
|
|
#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
|
855 |
|
|
|
856 |
|
|
static inline int
|
857 |
|
|
skip_past_char (char ** str, char c)
|
858 |
|
|
{
|
859 |
|
|
if (**str == c)
|
860 |
|
|
{
|
861 |
|
|
(*str)++;
|
862 |
|
|
return SUCCESS;
|
863 |
|
|
}
|
864 |
|
|
else
|
865 |
|
|
return FAIL;
|
866 |
|
|
}
|
867 |
|
|
|
868 |
|
|
#define skip_past_comma(str) skip_past_char (str, ',')
|
869 |
|
|
|
870 |
|
|
/* Arithmetic expressions (possibly involving symbols). */
|
871 |
|
|
|
872 |
|
|
/* Return TRUE if anything in the expression is a bignum. */
|
873 |
|
|
|
874 |
|
|
static int
|
875 |
|
|
walk_no_bignums (symbolS * sp)
|
876 |
|
|
{
|
877 |
|
|
if (symbol_get_value_expression (sp)->X_op == O_big)
|
878 |
|
|
return 1;
|
879 |
|
|
|
880 |
|
|
if (symbol_get_value_expression (sp)->X_add_symbol)
|
881 |
|
|
{
|
882 |
|
|
return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
|
883 |
|
|
|| (symbol_get_value_expression (sp)->X_op_symbol
|
884 |
|
|
&& walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
|
885 |
|
|
}
|
886 |
|
|
|
887 |
|
|
return 0;
|
888 |
|
|
}
|
889 |
|
|
|
890 |
|
|
static int in_my_get_expression = 0;
|
891 |
|
|
|
892 |
|
|
/* Third argument to my_get_expression. */
|
893 |
|
|
#define GE_NO_PREFIX 0
|
894 |
|
|
#define GE_IMM_PREFIX 1
|
895 |
|
|
#define GE_OPT_PREFIX 2
|
896 |
|
|
/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
|
897 |
|
|
immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
|
898 |
|
|
#define GE_OPT_PREFIX_BIG 3
|
899 |
|
|
|
900 |
|
|
static int
|
901 |
|
|
my_get_expression (expressionS * ep, char ** str, int prefix_mode)
|
902 |
|
|
{
|
903 |
|
|
char * save_in;
|
904 |
|
|
segT seg;
|
905 |
|
|
|
906 |
|
|
/* In unified syntax, all prefixes are optional. */
|
907 |
|
|
if (unified_syntax)
|
908 |
|
|
prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
|
909 |
|
|
: GE_OPT_PREFIX;
|
910 |
|
|
|
911 |
|
|
switch (prefix_mode)
|
912 |
|
|
{
|
913 |
|
|
case GE_NO_PREFIX: break;
|
914 |
|
|
case GE_IMM_PREFIX:
|
915 |
|
|
if (!is_immediate_prefix (**str))
|
916 |
|
|
{
|
917 |
|
|
inst.error = _("immediate expression requires a # prefix");
|
918 |
|
|
return FAIL;
|
919 |
|
|
}
|
920 |
|
|
(*str)++;
|
921 |
|
|
break;
|
922 |
|
|
case GE_OPT_PREFIX:
|
923 |
|
|
case GE_OPT_PREFIX_BIG:
|
924 |
|
|
if (is_immediate_prefix (**str))
|
925 |
|
|
(*str)++;
|
926 |
|
|
break;
|
927 |
|
|
default: abort ();
|
928 |
|
|
}
|
929 |
|
|
|
930 |
|
|
memset (ep, 0, sizeof (expressionS));
|
931 |
|
|
|
932 |
|
|
save_in = input_line_pointer;
|
933 |
|
|
input_line_pointer = *str;
|
934 |
|
|
in_my_get_expression = 1;
|
935 |
|
|
seg = expression (ep);
|
936 |
|
|
in_my_get_expression = 0;
|
937 |
|
|
|
938 |
|
|
if (ep->X_op == O_illegal || ep->X_op == O_absent)
|
939 |
|
|
{
|
940 |
|
|
/* We found a bad or missing expression in md_operand(). */
|
941 |
|
|
*str = input_line_pointer;
|
942 |
|
|
input_line_pointer = save_in;
|
943 |
|
|
if (inst.error == NULL)
|
944 |
|
|
inst.error = (ep->X_op == O_absent
|
945 |
|
|
? _("missing expression") :_("bad expression"));
|
946 |
|
|
return 1;
|
947 |
|
|
}
|
948 |
|
|
|
949 |
|
|
#ifdef OBJ_AOUT
|
950 |
|
|
if (seg != absolute_section
|
951 |
|
|
&& seg != text_section
|
952 |
|
|
&& seg != data_section
|
953 |
|
|
&& seg != bss_section
|
954 |
|
|
&& seg != undefined_section)
|
955 |
|
|
{
|
956 |
|
|
inst.error = _("bad segment");
|
957 |
|
|
*str = input_line_pointer;
|
958 |
|
|
input_line_pointer = save_in;
|
959 |
|
|
return 1;
|
960 |
|
|
}
|
961 |
|
|
#else
|
962 |
|
|
(void) seg;
|
963 |
|
|
#endif
|
964 |
|
|
|
965 |
|
|
/* Get rid of any bignums now, so that we don't generate an error for which
|
966 |
|
|
we can't establish a line number later on. Big numbers are never valid
|
967 |
|
|
in instructions, which is where this routine is always called. */
|
968 |
|
|
if (prefix_mode != GE_OPT_PREFIX_BIG
|
969 |
|
|
&& (ep->X_op == O_big
|
970 |
|
|
|| (ep->X_add_symbol
|
971 |
|
|
&& (walk_no_bignums (ep->X_add_symbol)
|
972 |
|
|
|| (ep->X_op_symbol
|
973 |
|
|
&& walk_no_bignums (ep->X_op_symbol))))))
|
974 |
|
|
{
|
975 |
|
|
inst.error = _("invalid constant");
|
976 |
|
|
*str = input_line_pointer;
|
977 |
|
|
input_line_pointer = save_in;
|
978 |
|
|
return 1;
|
979 |
|
|
}
|
980 |
|
|
|
981 |
|
|
*str = input_line_pointer;
|
982 |
|
|
input_line_pointer = save_in;
|
983 |
|
|
return 0;
|
984 |
|
|
}
|
985 |
|
|
|
986 |
|
|
/* Turn a string in input_line_pointer into a floating point constant
|
987 |
|
|
of type TYPE, and store the appropriate bytes in *LITP. The number
|
988 |
|
|
of LITTLENUMS emitted is stored in *SIZEP. An error message is
|
989 |
|
|
returned, or NULL on OK.
|
990 |
|
|
|
991 |
|
|
Note that fp constants aren't represent in the normal way on the ARM.
|
992 |
|
|
In big endian mode, things are as expected. However, in little endian
|
993 |
|
|
mode fp constants are big-endian word-wise, and little-endian byte-wise
|
994 |
|
|
within the words. For example, (double) 1.1 in big endian mode is
|
995 |
|
|
the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
|
996 |
|
|
the byte sequence 99 99 f1 3f 9a 99 99 99.
|
997 |
|
|
|
998 |
|
|
??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
|
999 |
|
|
|
1000 |
|
|
char *
|
1001 |
|
|
md_atof (int type, char * litP, int * sizeP)
|
1002 |
|
|
{
|
1003 |
|
|
int prec;
|
1004 |
|
|
LITTLENUM_TYPE words[MAX_LITTLENUMS];
|
1005 |
|
|
char *t;
|
1006 |
|
|
int i;
|
1007 |
|
|
|
1008 |
|
|
switch (type)
|
1009 |
|
|
{
|
1010 |
|
|
case 'f':
|
1011 |
|
|
case 'F':
|
1012 |
|
|
case 's':
|
1013 |
|
|
case 'S':
|
1014 |
|
|
prec = 2;
|
1015 |
|
|
break;
|
1016 |
|
|
|
1017 |
|
|
case 'd':
|
1018 |
|
|
case 'D':
|
1019 |
|
|
case 'r':
|
1020 |
|
|
case 'R':
|
1021 |
|
|
prec = 4;
|
1022 |
|
|
break;
|
1023 |
|
|
|
1024 |
|
|
case 'x':
|
1025 |
|
|
case 'X':
|
1026 |
|
|
prec = 5;
|
1027 |
|
|
break;
|
1028 |
|
|
|
1029 |
|
|
case 'p':
|
1030 |
|
|
case 'P':
|
1031 |
|
|
prec = 5;
|
1032 |
|
|
break;
|
1033 |
|
|
|
1034 |
|
|
default:
|
1035 |
|
|
*sizeP = 0;
|
1036 |
|
|
return _("Unrecognized or unsupported floating point constant");
|
1037 |
|
|
}
|
1038 |
|
|
|
1039 |
|
|
t = atof_ieee (input_line_pointer, type, words);
|
1040 |
|
|
if (t)
|
1041 |
|
|
input_line_pointer = t;
|
1042 |
|
|
*sizeP = prec * sizeof (LITTLENUM_TYPE);
|
1043 |
|
|
|
1044 |
|
|
if (target_big_endian)
|
1045 |
|
|
{
|
1046 |
|
|
for (i = 0; i < prec; i++)
|
1047 |
|
|
{
|
1048 |
|
|
md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
|
1049 |
|
|
litP += sizeof (LITTLENUM_TYPE);
|
1050 |
|
|
}
|
1051 |
|
|
}
|
1052 |
|
|
else
|
1053 |
|
|
{
|
1054 |
|
|
if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
|
1055 |
|
|
for (i = prec - 1; i >= 0; i--)
|
1056 |
|
|
{
|
1057 |
|
|
md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
|
1058 |
|
|
litP += sizeof (LITTLENUM_TYPE);
|
1059 |
|
|
}
|
1060 |
|
|
else
|
1061 |
|
|
/* For a 4 byte float the order of elements in `words' is 1 0.
|
1062 |
|
|
For an 8 byte float the order is 1 0 3 2. */
|
1063 |
|
|
for (i = 0; i < prec; i += 2)
|
1064 |
|
|
{
|
1065 |
|
|
md_number_to_chars (litP, (valueT) words[i + 1],
|
1066 |
|
|
sizeof (LITTLENUM_TYPE));
|
1067 |
|
|
md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
|
1068 |
|
|
(valueT) words[i], sizeof (LITTLENUM_TYPE));
|
1069 |
|
|
litP += 2 * sizeof (LITTLENUM_TYPE);
|
1070 |
|
|
}
|
1071 |
|
|
}
|
1072 |
|
|
|
1073 |
|
|
return NULL;
|
1074 |
|
|
}
|
1075 |
|
|
|
1076 |
|
|
/* We handle all bad expressions here, so that we can report the faulty
|
1077 |
|
|
instruction in the error message. */
|
1078 |
|
|
void
|
1079 |
|
|
md_operand (expressionS * exp)
|
1080 |
|
|
{
|
1081 |
|
|
if (in_my_get_expression)
|
1082 |
|
|
exp->X_op = O_illegal;
|
1083 |
|
|
}
|
1084 |
|
|
|
1085 |
|
|
/* Immediate values. */
|
1086 |
|
|
|
1087 |
|
|
/* Generic immediate-value read function for use in directives.
|
1088 |
|
|
Accepts anything that 'expression' can fold to a constant.
|
1089 |
|
|
*val receives the number. */
|
1090 |
|
|
#ifdef OBJ_ELF
|
1091 |
|
|
static int
|
1092 |
|
|
immediate_for_directive (int *val)
|
1093 |
|
|
{
|
1094 |
|
|
expressionS exp;
|
1095 |
|
|
exp.X_op = O_illegal;
|
1096 |
|
|
|
1097 |
|
|
if (is_immediate_prefix (*input_line_pointer))
|
1098 |
|
|
{
|
1099 |
|
|
input_line_pointer++;
|
1100 |
|
|
expression (&exp);
|
1101 |
|
|
}
|
1102 |
|
|
|
1103 |
|
|
if (exp.X_op != O_constant)
|
1104 |
|
|
{
|
1105 |
|
|
as_bad (_("expected #constant"));
|
1106 |
|
|
ignore_rest_of_line ();
|
1107 |
|
|
return FAIL;
|
1108 |
|
|
}
|
1109 |
|
|
*val = exp.X_add_number;
|
1110 |
|
|
return SUCCESS;
|
1111 |
|
|
}
|
1112 |
|
|
#endif
|
1113 |
|
|
|
1114 |
|
|
/* Register parsing. */
|
1115 |
|
|
|
1116 |
|
|
/* Generic register parser. CCP points to what should be the
|
1117 |
|
|
beginning of a register name. If it is indeed a valid register
|
1118 |
|
|
name, advance CCP over it and return the reg_entry structure;
|
1119 |
|
|
otherwise return NULL. Does not issue diagnostics. */
|
1120 |
|
|
|
1121 |
|
|
static struct reg_entry *
|
1122 |
|
|
arm_reg_parse_multi (char **ccp)
|
1123 |
|
|
{
|
1124 |
|
|
char *start = *ccp;
|
1125 |
|
|
char *p;
|
1126 |
|
|
struct reg_entry *reg;
|
1127 |
|
|
|
1128 |
|
|
#ifdef REGISTER_PREFIX
|
1129 |
|
|
if (*start != REGISTER_PREFIX)
|
1130 |
|
|
return NULL;
|
1131 |
|
|
start++;
|
1132 |
|
|
#endif
|
1133 |
|
|
#ifdef OPTIONAL_REGISTER_PREFIX
|
1134 |
|
|
if (*start == OPTIONAL_REGISTER_PREFIX)
|
1135 |
|
|
start++;
|
1136 |
|
|
#endif
|
1137 |
|
|
|
1138 |
|
|
p = start;
|
1139 |
|
|
if (!ISALPHA (*p) || !is_name_beginner (*p))
|
1140 |
|
|
return NULL;
|
1141 |
|
|
|
1142 |
|
|
do
|
1143 |
|
|
p++;
|
1144 |
|
|
while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
|
1145 |
|
|
|
1146 |
|
|
reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
|
1147 |
|
|
|
1148 |
|
|
if (!reg)
|
1149 |
|
|
return NULL;
|
1150 |
|
|
|
1151 |
|
|
*ccp = p;
|
1152 |
|
|
return reg;
|
1153 |
|
|
}
|
1154 |
|
|
|
1155 |
|
|
static int
|
1156 |
|
|
arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
|
1157 |
|
|
enum arm_reg_type type)
|
1158 |
|
|
{
|
1159 |
|
|
/* Alternative syntaxes are accepted for a few register classes. */
|
1160 |
|
|
switch (type)
|
1161 |
|
|
{
|
1162 |
|
|
case REG_TYPE_MVF:
|
1163 |
|
|
case REG_TYPE_MVD:
|
1164 |
|
|
case REG_TYPE_MVFX:
|
1165 |
|
|
case REG_TYPE_MVDX:
|
1166 |
|
|
/* Generic coprocessor register names are allowed for these. */
|
1167 |
|
|
if (reg && reg->type == REG_TYPE_CN)
|
1168 |
|
|
return reg->number;
|
1169 |
|
|
break;
|
1170 |
|
|
|
1171 |
|
|
case REG_TYPE_CP:
|
1172 |
|
|
/* For backward compatibility, a bare number is valid here. */
|
1173 |
|
|
{
|
1174 |
|
|
unsigned long processor = strtoul (start, ccp, 10);
|
1175 |
|
|
if (*ccp != start && processor <= 15)
|
1176 |
|
|
return processor;
|
1177 |
|
|
}
|
1178 |
|
|
|
1179 |
|
|
case REG_TYPE_MMXWC:
|
1180 |
|
|
/* WC includes WCG. ??? I'm not sure this is true for all
|
1181 |
|
|
instructions that take WC registers. */
|
1182 |
|
|
if (reg && reg->type == REG_TYPE_MMXWCG)
|
1183 |
|
|
return reg->number;
|
1184 |
|
|
break;
|
1185 |
|
|
|
1186 |
|
|
default:
|
1187 |
|
|
break;
|
1188 |
|
|
}
|
1189 |
|
|
|
1190 |
|
|
return FAIL;
|
1191 |
|
|
}
|
1192 |
|
|
|
1193 |
|
|
/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
|
1194 |
|
|
return value is the register number or FAIL. */
|
1195 |
|
|
|
1196 |
|
|
static int
|
1197 |
|
|
arm_reg_parse (char **ccp, enum arm_reg_type type)
|
1198 |
|
|
{
|
1199 |
|
|
char *start = *ccp;
|
1200 |
|
|
struct reg_entry *reg = arm_reg_parse_multi (ccp);
|
1201 |
|
|
int ret;
|
1202 |
|
|
|
1203 |
|
|
/* Do not allow a scalar (reg+index) to parse as a register. */
|
1204 |
|
|
if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
|
1205 |
|
|
return FAIL;
|
1206 |
|
|
|
1207 |
|
|
if (reg && reg->type == type)
|
1208 |
|
|
return reg->number;
|
1209 |
|
|
|
1210 |
|
|
if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
|
1211 |
|
|
return ret;
|
1212 |
|
|
|
1213 |
|
|
*ccp = start;
|
1214 |
|
|
return FAIL;
|
1215 |
|
|
}
|
1216 |
|
|
|
1217 |
|
|
/* Parse a Neon type specifier. *STR should point at the leading '.'
|
1218 |
|
|
character. Does no verification at this stage that the type fits the opcode
|
1219 |
|
|
properly. E.g.,
|
1220 |
|
|
|
1221 |
|
|
.i32.i32.s16
|
1222 |
|
|
.s32.f32
|
1223 |
|
|
.u16
|
1224 |
|
|
|
1225 |
|
|
Can all be legally parsed by this function.
|
1226 |
|
|
|
1227 |
|
|
Fills in neon_type struct pointer with parsed information, and updates STR
|
1228 |
|
|
to point after the parsed type specifier. Returns SUCCESS if this was a legal
|
1229 |
|
|
type, FAIL if not. */
|
1230 |
|
|
|
1231 |
|
|
static int
|
1232 |
|
|
parse_neon_type (struct neon_type *type, char **str)
|
1233 |
|
|
{
|
1234 |
|
|
char *ptr = *str;
|
1235 |
|
|
|
1236 |
|
|
if (type)
|
1237 |
|
|
type->elems = 0;
|
1238 |
|
|
|
1239 |
|
|
while (type->elems < NEON_MAX_TYPE_ELS)
|
1240 |
|
|
{
|
1241 |
|
|
enum neon_el_type thistype = NT_untyped;
|
1242 |
|
|
unsigned thissize = -1u;
|
1243 |
|
|
|
1244 |
|
|
if (*ptr != '.')
|
1245 |
|
|
break;
|
1246 |
|
|
|
1247 |
|
|
ptr++;
|
1248 |
|
|
|
1249 |
|
|
/* Just a size without an explicit type. */
|
1250 |
|
|
if (ISDIGIT (*ptr))
|
1251 |
|
|
goto parsesize;
|
1252 |
|
|
|
1253 |
|
|
switch (TOLOWER (*ptr))
|
1254 |
|
|
{
|
1255 |
|
|
case 'i': thistype = NT_integer; break;
|
1256 |
|
|
case 'f': thistype = NT_float; break;
|
1257 |
|
|
case 'p': thistype = NT_poly; break;
|
1258 |
|
|
case 's': thistype = NT_signed; break;
|
1259 |
|
|
case 'u': thistype = NT_unsigned; break;
|
1260 |
|
|
case 'd':
|
1261 |
|
|
thistype = NT_float;
|
1262 |
|
|
thissize = 64;
|
1263 |
|
|
ptr++;
|
1264 |
|
|
goto done;
|
1265 |
|
|
default:
|
1266 |
|
|
as_bad (_("unexpected character `%c' in type specifier"), *ptr);
|
1267 |
|
|
return FAIL;
|
1268 |
|
|
}
|
1269 |
|
|
|
1270 |
|
|
ptr++;
|
1271 |
|
|
|
1272 |
|
|
/* .f is an abbreviation for .f32. */
|
1273 |
|
|
if (thistype == NT_float && !ISDIGIT (*ptr))
|
1274 |
|
|
thissize = 32;
|
1275 |
|
|
else
|
1276 |
|
|
{
|
1277 |
|
|
parsesize:
|
1278 |
|
|
thissize = strtoul (ptr, &ptr, 10);
|
1279 |
|
|
|
1280 |
|
|
if (thissize != 8 && thissize != 16 && thissize != 32
|
1281 |
|
|
&& thissize != 64)
|
1282 |
|
|
{
|
1283 |
|
|
as_bad (_("bad size %d in type specifier"), thissize);
|
1284 |
|
|
return FAIL;
|
1285 |
|
|
}
|
1286 |
|
|
}
|
1287 |
|
|
|
1288 |
|
|
done:
|
1289 |
|
|
if (type)
|
1290 |
|
|
{
|
1291 |
|
|
type->el[type->elems].type = thistype;
|
1292 |
|
|
type->el[type->elems].size = thissize;
|
1293 |
|
|
type->elems++;
|
1294 |
|
|
}
|
1295 |
|
|
}
|
1296 |
|
|
|
1297 |
|
|
/* Empty/missing type is not a successful parse. */
|
1298 |
|
|
if (type->elems == 0)
|
1299 |
|
|
return FAIL;
|
1300 |
|
|
|
1301 |
|
|
*str = ptr;
|
1302 |
|
|
|
1303 |
|
|
return SUCCESS;
|
1304 |
|
|
}
|
1305 |
|
|
|
1306 |
|
|
/* Errors may be set multiple times during parsing or bit encoding
|
1307 |
|
|
(particularly in the Neon bits), but usually the earliest error which is set
|
1308 |
|
|
will be the most meaningful. Avoid overwriting it with later (cascading)
|
1309 |
|
|
errors by calling this function. */
|
1310 |
|
|
|
1311 |
|
|
static void
|
1312 |
|
|
first_error (const char *err)
|
1313 |
|
|
{
|
1314 |
|
|
if (!inst.error)
|
1315 |
|
|
inst.error = err;
|
1316 |
|
|
}
|
1317 |
|
|
|
1318 |
|
|
/* Parse a single type, e.g. ".s32", leading period included. */
|
1319 |
|
|
static int
|
1320 |
|
|
parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
|
1321 |
|
|
{
|
1322 |
|
|
char *str = *ccp;
|
1323 |
|
|
struct neon_type optype;
|
1324 |
|
|
|
1325 |
|
|
if (*str == '.')
|
1326 |
|
|
{
|
1327 |
|
|
if (parse_neon_type (&optype, &str) == SUCCESS)
|
1328 |
|
|
{
|
1329 |
|
|
if (optype.elems == 1)
|
1330 |
|
|
*vectype = optype.el[0];
|
1331 |
|
|
else
|
1332 |
|
|
{
|
1333 |
|
|
first_error (_("only one type should be specified for operand"));
|
1334 |
|
|
return FAIL;
|
1335 |
|
|
}
|
1336 |
|
|
}
|
1337 |
|
|
else
|
1338 |
|
|
{
|
1339 |
|
|
first_error (_("vector type expected"));
|
1340 |
|
|
return FAIL;
|
1341 |
|
|
}
|
1342 |
|
|
}
|
1343 |
|
|
else
|
1344 |
|
|
return FAIL;
|
1345 |
|
|
|
1346 |
|
|
*ccp = str;
|
1347 |
|
|
|
1348 |
|
|
return SUCCESS;
|
1349 |
|
|
}
|
1350 |
|
|
|
1351 |
|
|
/* Special meanings for indices (which have a range of 0-7), which will fit into
|
1352 |
|
|
a 4-bit integer. */
|
1353 |
|
|
|
1354 |
|
|
#define NEON_ALL_LANES 15
|
1355 |
|
|
#define NEON_INTERLEAVE_LANES 14
|
1356 |
|
|
|
1357 |
|
|
/* Parse either a register or a scalar, with an optional type. Return the
|
1358 |
|
|
register number, and optionally fill in the actual type of the register
|
1359 |
|
|
when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
|
1360 |
|
|
type/index information in *TYPEINFO. */
|
1361 |
|
|
|
1362 |
|
|
static int
|
1363 |
|
|
parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
|
1364 |
|
|
enum arm_reg_type *rtype,
|
1365 |
|
|
struct neon_typed_alias *typeinfo)
|
1366 |
|
|
{
|
1367 |
|
|
char *str = *ccp;
|
1368 |
|
|
struct reg_entry *reg = arm_reg_parse_multi (&str);
|
1369 |
|
|
struct neon_typed_alias atype;
|
1370 |
|
|
struct neon_type_el parsetype;
|
1371 |
|
|
|
1372 |
|
|
atype.defined = 0;
|
1373 |
|
|
atype.index = -1;
|
1374 |
|
|
atype.eltype.type = NT_invtype;
|
1375 |
|
|
atype.eltype.size = -1;
|
1376 |
|
|
|
1377 |
|
|
/* Try alternate syntax for some types of register. Note these are mutually
|
1378 |
|
|
exclusive with the Neon syntax extensions. */
|
1379 |
|
|
if (reg == NULL)
|
1380 |
|
|
{
|
1381 |
|
|
int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
|
1382 |
|
|
if (altreg != FAIL)
|
1383 |
|
|
*ccp = str;
|
1384 |
|
|
if (typeinfo)
|
1385 |
|
|
*typeinfo = atype;
|
1386 |
|
|
return altreg;
|
1387 |
|
|
}
|
1388 |
|
|
|
1389 |
|
|
/* Undo polymorphism when a set of register types may be accepted. */
|
1390 |
|
|
if ((type == REG_TYPE_NDQ
|
1391 |
|
|
&& (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
|
1392 |
|
|
|| (type == REG_TYPE_VFSD
|
1393 |
|
|
&& (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
|
1394 |
|
|
|| (type == REG_TYPE_NSDQ
|
1395 |
|
|
&& (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
|
1396 |
|
|
|| reg->type == REG_TYPE_NQ))
|
1397 |
|
|
|| (type == REG_TYPE_MMXWC
|
1398 |
|
|
&& (reg->type == REG_TYPE_MMXWCG)))
|
1399 |
|
|
type = (enum arm_reg_type) reg->type;
|
1400 |
|
|
|
1401 |
|
|
if (type != reg->type)
|
1402 |
|
|
return FAIL;
|
1403 |
|
|
|
1404 |
|
|
if (reg->neon)
|
1405 |
|
|
atype = *reg->neon;
|
1406 |
|
|
|
1407 |
|
|
if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
|
1408 |
|
|
{
|
1409 |
|
|
if ((atype.defined & NTA_HASTYPE) != 0)
|
1410 |
|
|
{
|
1411 |
|
|
first_error (_("can't redefine type for operand"));
|
1412 |
|
|
return FAIL;
|
1413 |
|
|
}
|
1414 |
|
|
atype.defined |= NTA_HASTYPE;
|
1415 |
|
|
atype.eltype = parsetype;
|
1416 |
|
|
}
|
1417 |
|
|
|
1418 |
|
|
if (skip_past_char (&str, '[') == SUCCESS)
|
1419 |
|
|
{
|
1420 |
|
|
if (type != REG_TYPE_VFD)
|
1421 |
|
|
{
|
1422 |
|
|
first_error (_("only D registers may be indexed"));
|
1423 |
|
|
return FAIL;
|
1424 |
|
|
}
|
1425 |
|
|
|
1426 |
|
|
if ((atype.defined & NTA_HASINDEX) != 0)
|
1427 |
|
|
{
|
1428 |
|
|
first_error (_("can't change index for operand"));
|
1429 |
|
|
return FAIL;
|
1430 |
|
|
}
|
1431 |
|
|
|
1432 |
|
|
atype.defined |= NTA_HASINDEX;
|
1433 |
|
|
|
1434 |
|
|
if (skip_past_char (&str, ']') == SUCCESS)
|
1435 |
|
|
atype.index = NEON_ALL_LANES;
|
1436 |
|
|
else
|
1437 |
|
|
{
|
1438 |
|
|
expressionS exp;
|
1439 |
|
|
|
1440 |
|
|
my_get_expression (&exp, &str, GE_NO_PREFIX);
|
1441 |
|
|
|
1442 |
|
|
if (exp.X_op != O_constant)
|
1443 |
|
|
{
|
1444 |
|
|
first_error (_("constant expression required"));
|
1445 |
|
|
return FAIL;
|
1446 |
|
|
}
|
1447 |
|
|
|
1448 |
|
|
if (skip_past_char (&str, ']') == FAIL)
|
1449 |
|
|
return FAIL;
|
1450 |
|
|
|
1451 |
|
|
atype.index = exp.X_add_number;
|
1452 |
|
|
}
|
1453 |
|
|
}
|
1454 |
|
|
|
1455 |
|
|
if (typeinfo)
|
1456 |
|
|
*typeinfo = atype;
|
1457 |
|
|
|
1458 |
|
|
if (rtype)
|
1459 |
|
|
*rtype = type;
|
1460 |
|
|
|
1461 |
|
|
*ccp = str;
|
1462 |
|
|
|
1463 |
|
|
return reg->number;
|
1464 |
|
|
}
|
1465 |
|
|
|
1466 |
|
|
/* Like arm_reg_parse, but allow allow the following extra features:
|
1467 |
|
|
- If RTYPE is non-zero, return the (possibly restricted) type of the
|
1468 |
|
|
register (e.g. Neon double or quad reg when either has been requested).
|
1469 |
|
|
- If this is a Neon vector type with additional type information, fill
|
1470 |
|
|
in the struct pointed to by VECTYPE (if non-NULL).
|
1471 |
|
|
This function will fault on encountering a scalar. */
|
1472 |
|
|
|
1473 |
|
|
static int
|
1474 |
|
|
arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
|
1475 |
|
|
enum arm_reg_type *rtype, struct neon_type_el *vectype)
|
1476 |
|
|
{
|
1477 |
|
|
struct neon_typed_alias atype;
|
1478 |
|
|
char *str = *ccp;
|
1479 |
|
|
int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
|
1480 |
|
|
|
1481 |
|
|
if (reg == FAIL)
|
1482 |
|
|
return FAIL;
|
1483 |
|
|
|
1484 |
|
|
/* Do not allow regname(... to parse as a register. */
|
1485 |
|
|
if (*str == '(')
|
1486 |
|
|
return FAIL;
|
1487 |
|
|
|
1488 |
|
|
/* Do not allow a scalar (reg+index) to parse as a register. */
|
1489 |
|
|
if ((atype.defined & NTA_HASINDEX) != 0)
|
1490 |
|
|
{
|
1491 |
|
|
first_error (_("register operand expected, but got scalar"));
|
1492 |
|
|
return FAIL;
|
1493 |
|
|
}
|
1494 |
|
|
|
1495 |
|
|
if (vectype)
|
1496 |
|
|
*vectype = atype.eltype;
|
1497 |
|
|
|
1498 |
|
|
*ccp = str;
|
1499 |
|
|
|
1500 |
|
|
return reg;
|
1501 |
|
|
}
|
1502 |
|
|
|
1503 |
|
|
#define NEON_SCALAR_REG(X) ((X) >> 4)
|
1504 |
|
|
#define NEON_SCALAR_INDEX(X) ((X) & 15)
|
1505 |
|
|
|
1506 |
|
|
/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
|
1507 |
|
|
have enough information to be able to do a good job bounds-checking. So, we
|
1508 |
|
|
just do easy checks here, and do further checks later. */
|
1509 |
|
|
|
1510 |
|
|
static int
|
1511 |
|
|
parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
|
1512 |
|
|
{
|
1513 |
|
|
int reg;
|
1514 |
|
|
char *str = *ccp;
|
1515 |
|
|
struct neon_typed_alias atype;
|
1516 |
|
|
|
1517 |
|
|
reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
|
1518 |
|
|
|
1519 |
|
|
if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
|
1520 |
|
|
return FAIL;
|
1521 |
|
|
|
1522 |
|
|
if (atype.index == NEON_ALL_LANES)
|
1523 |
|
|
{
|
1524 |
|
|
first_error (_("scalar must have an index"));
|
1525 |
|
|
return FAIL;
|
1526 |
|
|
}
|
1527 |
|
|
else if (atype.index >= 64 / elsize)
|
1528 |
|
|
{
|
1529 |
|
|
first_error (_("scalar index out of range"));
|
1530 |
|
|
return FAIL;
|
1531 |
|
|
}
|
1532 |
|
|
|
1533 |
|
|
if (type)
|
1534 |
|
|
*type = atype.eltype;
|
1535 |
|
|
|
1536 |
|
|
*ccp = str;
|
1537 |
|
|
|
1538 |
|
|
return reg * 16 + atype.index;
|
1539 |
|
|
}
|
1540 |
|
|
|
1541 |
|
|
/* Parse an ARM register list. Returns the bitmask, or FAIL. */
|
1542 |
|
|
|
1543 |
|
|
static long
|
1544 |
|
|
parse_reg_list (char ** strp)
|
1545 |
|
|
{
|
1546 |
|
|
char * str = * strp;
|
1547 |
|
|
long range = 0;
|
1548 |
|
|
int another_range;
|
1549 |
|
|
|
1550 |
|
|
/* We come back here if we get ranges concatenated by '+' or '|'. */
|
1551 |
|
|
do
|
1552 |
|
|
{
|
1553 |
|
|
another_range = 0;
|
1554 |
|
|
|
1555 |
|
|
if (*str == '{')
|
1556 |
|
|
{
|
1557 |
|
|
int in_range = 0;
|
1558 |
|
|
int cur_reg = -1;
|
1559 |
|
|
|
1560 |
|
|
str++;
|
1561 |
|
|
do
|
1562 |
|
|
{
|
1563 |
|
|
int reg;
|
1564 |
|
|
|
1565 |
|
|
if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
|
1566 |
|
|
{
|
1567 |
|
|
first_error (_(reg_expected_msgs[REG_TYPE_RN]));
|
1568 |
|
|
return FAIL;
|
1569 |
|
|
}
|
1570 |
|
|
|
1571 |
|
|
if (in_range)
|
1572 |
|
|
{
|
1573 |
|
|
int i;
|
1574 |
|
|
|
1575 |
|
|
if (reg <= cur_reg)
|
1576 |
|
|
{
|
1577 |
|
|
first_error (_("bad range in register list"));
|
1578 |
|
|
return FAIL;
|
1579 |
|
|
}
|
1580 |
|
|
|
1581 |
|
|
for (i = cur_reg + 1; i < reg; i++)
|
1582 |
|
|
{
|
1583 |
|
|
if (range & (1 << i))
|
1584 |
|
|
as_tsktsk
|
1585 |
|
|
(_("Warning: duplicated register (r%d) in register list"),
|
1586 |
|
|
i);
|
1587 |
|
|
else
|
1588 |
|
|
range |= 1 << i;
|
1589 |
|
|
}
|
1590 |
|
|
in_range = 0;
|
1591 |
|
|
}
|
1592 |
|
|
|
1593 |
|
|
if (range & (1 << reg))
|
1594 |
|
|
as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
|
1595 |
|
|
reg);
|
1596 |
|
|
else if (reg <= cur_reg)
|
1597 |
|
|
as_tsktsk (_("Warning: register range not in ascending order"));
|
1598 |
|
|
|
1599 |
|
|
range |= 1 << reg;
|
1600 |
|
|
cur_reg = reg;
|
1601 |
|
|
}
|
1602 |
|
|
while (skip_past_comma (&str) != FAIL
|
1603 |
|
|
|| (in_range = 1, *str++ == '-'));
|
1604 |
|
|
str--;
|
1605 |
|
|
|
1606 |
|
|
if (*str++ != '}')
|
1607 |
|
|
{
|
1608 |
|
|
first_error (_("missing `}'"));
|
1609 |
|
|
return FAIL;
|
1610 |
|
|
}
|
1611 |
|
|
}
|
1612 |
|
|
else
|
1613 |
|
|
{
|
1614 |
|
|
expressionS exp;
|
1615 |
|
|
|
1616 |
|
|
if (my_get_expression (&exp, &str, GE_NO_PREFIX))
|
1617 |
|
|
return FAIL;
|
1618 |
|
|
|
1619 |
|
|
if (exp.X_op == O_constant)
|
1620 |
|
|
{
|
1621 |
|
|
if (exp.X_add_number
|
1622 |
|
|
!= (exp.X_add_number & 0x0000ffff))
|
1623 |
|
|
{
|
1624 |
|
|
inst.error = _("invalid register mask");
|
1625 |
|
|
return FAIL;
|
1626 |
|
|
}
|
1627 |
|
|
|
1628 |
|
|
if ((range & exp.X_add_number) != 0)
|
1629 |
|
|
{
|
1630 |
|
|
int regno = range & exp.X_add_number;
|
1631 |
|
|
|
1632 |
|
|
regno &= -regno;
|
1633 |
|
|
regno = (1 << regno) - 1;
|
1634 |
|
|
as_tsktsk
|
1635 |
|
|
(_("Warning: duplicated register (r%d) in register list"),
|
1636 |
|
|
regno);
|
1637 |
|
|
}
|
1638 |
|
|
|
1639 |
|
|
range |= exp.X_add_number;
|
1640 |
|
|
}
|
1641 |
|
|
else
|
1642 |
|
|
{
|
1643 |
|
|
if (inst.reloc.type != 0)
|
1644 |
|
|
{
|
1645 |
|
|
inst.error = _("expression too complex");
|
1646 |
|
|
return FAIL;
|
1647 |
|
|
}
|
1648 |
|
|
|
1649 |
|
|
memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
|
1650 |
|
|
inst.reloc.type = BFD_RELOC_ARM_MULTI;
|
1651 |
|
|
inst.reloc.pc_rel = 0;
|
1652 |
|
|
}
|
1653 |
|
|
}
|
1654 |
|
|
|
1655 |
|
|
if (*str == '|' || *str == '+')
|
1656 |
|
|
{
|
1657 |
|
|
str++;
|
1658 |
|
|
another_range = 1;
|
1659 |
|
|
}
|
1660 |
|
|
}
|
1661 |
|
|
while (another_range);
|
1662 |
|
|
|
1663 |
|
|
*strp = str;
|
1664 |
|
|
return range;
|
1665 |
|
|
}
|
1666 |
|
|
|
1667 |
|
|
/* Types of registers in a list. */
|
1668 |
|
|
|
1669 |
|
|
enum reg_list_els
|
1670 |
|
|
{
|
1671 |
|
|
REGLIST_VFP_S,
|
1672 |
|
|
REGLIST_VFP_D,
|
1673 |
|
|
REGLIST_NEON_D
|
1674 |
|
|
};
|
1675 |
|
|
|
1676 |
|
|
/* Parse a VFP register list. If the string is invalid return FAIL.
|
1677 |
|
|
Otherwise return the number of registers, and set PBASE to the first
|
1678 |
|
|
register. Parses registers of type ETYPE.
|
1679 |
|
|
If REGLIST_NEON_D is used, several syntax enhancements are enabled:
|
1680 |
|
|
- Q registers can be used to specify pairs of D registers
|
1681 |
|
|
- { } can be omitted from around a singleton register list
|
1682 |
|
|
FIXME: This is not implemented, as it would require backtracking in
|
1683 |
|
|
some cases, e.g.:
|
1684 |
|
|
vtbl.8 d3,d4,d5
|
1685 |
|
|
This could be done (the meaning isn't really ambiguous), but doesn't
|
1686 |
|
|
fit in well with the current parsing framework.
|
1687 |
|
|
- 32 D registers may be used (also true for VFPv3).
|
1688 |
|
|
FIXME: Types are ignored in these register lists, which is probably a
|
1689 |
|
|
bug. */
|
1690 |
|
|
|
1691 |
|
|
static int
|
1692 |
|
|
parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
|
1693 |
|
|
{
|
1694 |
|
|
char *str = *ccp;
|
1695 |
|
|
int base_reg;
|
1696 |
|
|
int new_base;
|
1697 |
|
|
enum arm_reg_type regtype = (enum arm_reg_type) 0;
|
1698 |
|
|
int max_regs = 0;
|
1699 |
|
|
int count = 0;
|
1700 |
|
|
int warned = 0;
|
1701 |
|
|
unsigned long mask = 0;
|
1702 |
|
|
int i;
|
1703 |
|
|
|
1704 |
|
|
if (*str != '{')
|
1705 |
|
|
{
|
1706 |
|
|
inst.error = _("expecting {");
|
1707 |
|
|
return FAIL;
|
1708 |
|
|
}
|
1709 |
|
|
|
1710 |
|
|
str++;
|
1711 |
|
|
|
1712 |
|
|
switch (etype)
|
1713 |
|
|
{
|
1714 |
|
|
case REGLIST_VFP_S:
|
1715 |
|
|
regtype = REG_TYPE_VFS;
|
1716 |
|
|
max_regs = 32;
|
1717 |
|
|
break;
|
1718 |
|
|
|
1719 |
|
|
case REGLIST_VFP_D:
|
1720 |
|
|
regtype = REG_TYPE_VFD;
|
1721 |
|
|
break;
|
1722 |
|
|
|
1723 |
|
|
case REGLIST_NEON_D:
|
1724 |
|
|
regtype = REG_TYPE_NDQ;
|
1725 |
|
|
break;
|
1726 |
|
|
}
|
1727 |
|
|
|
1728 |
|
|
if (etype != REGLIST_VFP_S)
|
1729 |
|
|
{
|
1730 |
|
|
/* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
|
1731 |
|
|
if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
|
1732 |
|
|
{
|
1733 |
|
|
max_regs = 32;
|
1734 |
|
|
if (thumb_mode)
|
1735 |
|
|
ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
|
1736 |
|
|
fpu_vfp_ext_d32);
|
1737 |
|
|
else
|
1738 |
|
|
ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
|
1739 |
|
|
fpu_vfp_ext_d32);
|
1740 |
|
|
}
|
1741 |
|
|
else
|
1742 |
|
|
max_regs = 16;
|
1743 |
|
|
}
|
1744 |
|
|
|
1745 |
|
|
base_reg = max_regs;
|
1746 |
|
|
|
1747 |
|
|
do
|
1748 |
|
|
{
|
1749 |
|
|
int setmask = 1, addregs = 1;
|
1750 |
|
|
|
1751 |
|
|
new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
|
1752 |
|
|
|
1753 |
|
|
if (new_base == FAIL)
|
1754 |
|
|
{
|
1755 |
|
|
first_error (_(reg_expected_msgs[regtype]));
|
1756 |
|
|
return FAIL;
|
1757 |
|
|
}
|
1758 |
|
|
|
1759 |
|
|
if (new_base >= max_regs)
|
1760 |
|
|
{
|
1761 |
|
|
first_error (_("register out of range in list"));
|
1762 |
|
|
return FAIL;
|
1763 |
|
|
}
|
1764 |
|
|
|
1765 |
|
|
/* Note: a value of 2 * n is returned for the register Q<n>. */
|
1766 |
|
|
if (regtype == REG_TYPE_NQ)
|
1767 |
|
|
{
|
1768 |
|
|
setmask = 3;
|
1769 |
|
|
addregs = 2;
|
1770 |
|
|
}
|
1771 |
|
|
|
1772 |
|
|
if (new_base < base_reg)
|
1773 |
|
|
base_reg = new_base;
|
1774 |
|
|
|
1775 |
|
|
if (mask & (setmask << new_base))
|
1776 |
|
|
{
|
1777 |
|
|
first_error (_("invalid register list"));
|
1778 |
|
|
return FAIL;
|
1779 |
|
|
}
|
1780 |
|
|
|
1781 |
|
|
if ((mask >> new_base) != 0 && ! warned)
|
1782 |
|
|
{
|
1783 |
|
|
as_tsktsk (_("register list not in ascending order"));
|
1784 |
|
|
warned = 1;
|
1785 |
|
|
}
|
1786 |
|
|
|
1787 |
|
|
mask |= setmask << new_base;
|
1788 |
|
|
count += addregs;
|
1789 |
|
|
|
1790 |
|
|
if (*str == '-') /* We have the start of a range expression */
|
1791 |
|
|
{
|
1792 |
|
|
int high_range;
|
1793 |
|
|
|
1794 |
|
|
str++;
|
1795 |
|
|
|
1796 |
|
|
if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
|
1797 |
|
|
== FAIL)
|
1798 |
|
|
{
|
1799 |
|
|
inst.error = gettext (reg_expected_msgs[regtype]);
|
1800 |
|
|
return FAIL;
|
1801 |
|
|
}
|
1802 |
|
|
|
1803 |
|
|
if (high_range >= max_regs)
|
1804 |
|
|
{
|
1805 |
|
|
first_error (_("register out of range in list"));
|
1806 |
|
|
return FAIL;
|
1807 |
|
|
}
|
1808 |
|
|
|
1809 |
|
|
if (regtype == REG_TYPE_NQ)
|
1810 |
|
|
high_range = high_range + 1;
|
1811 |
|
|
|
1812 |
|
|
if (high_range <= new_base)
|
1813 |
|
|
{
|
1814 |
|
|
inst.error = _("register range not in ascending order");
|
1815 |
|
|
return FAIL;
|
1816 |
|
|
}
|
1817 |
|
|
|
1818 |
|
|
for (new_base += addregs; new_base <= high_range; new_base += addregs)
|
1819 |
|
|
{
|
1820 |
|
|
if (mask & (setmask << new_base))
|
1821 |
|
|
{
|
1822 |
|
|
inst.error = _("invalid register list");
|
1823 |
|
|
return FAIL;
|
1824 |
|
|
}
|
1825 |
|
|
|
1826 |
|
|
mask |= setmask << new_base;
|
1827 |
|
|
count += addregs;
|
1828 |
|
|
}
|
1829 |
|
|
}
|
1830 |
|
|
}
|
1831 |
|
|
while (skip_past_comma (&str) != FAIL);
|
1832 |
|
|
|
1833 |
|
|
str++;
|
1834 |
|
|
|
1835 |
|
|
/* Sanity check -- should have raised a parse error above. */
|
1836 |
|
|
if (count == 0 || count > max_regs)
|
1837 |
|
|
abort ();
|
1838 |
|
|
|
1839 |
|
|
*pbase = base_reg;
|
1840 |
|
|
|
1841 |
|
|
/* Final test -- the registers must be consecutive. */
|
1842 |
|
|
mask >>= base_reg;
|
1843 |
|
|
for (i = 0; i < count; i++)
|
1844 |
|
|
{
|
1845 |
|
|
if ((mask & (1u << i)) == 0)
|
1846 |
|
|
{
|
1847 |
|
|
inst.error = _("non-contiguous register range");
|
1848 |
|
|
return FAIL;
|
1849 |
|
|
}
|
1850 |
|
|
}
|
1851 |
|
|
|
1852 |
|
|
*ccp = str;
|
1853 |
|
|
|
1854 |
|
|
return count;
|
1855 |
|
|
}
|
1856 |
|
|
|
1857 |
|
|
/* True if two alias types are the same. */
|
1858 |
|
|
|
1859 |
|
|
static bfd_boolean
|
1860 |
|
|
neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
|
1861 |
|
|
{
|
1862 |
|
|
if (!a && !b)
|
1863 |
|
|
return TRUE;
|
1864 |
|
|
|
1865 |
|
|
if (!a || !b)
|
1866 |
|
|
return FALSE;
|
1867 |
|
|
|
1868 |
|
|
if (a->defined != b->defined)
|
1869 |
|
|
return FALSE;
|
1870 |
|
|
|
1871 |
|
|
if ((a->defined & NTA_HASTYPE) != 0
|
1872 |
|
|
&& (a->eltype.type != b->eltype.type
|
1873 |
|
|
|| a->eltype.size != b->eltype.size))
|
1874 |
|
|
return FALSE;
|
1875 |
|
|
|
1876 |
|
|
if ((a->defined & NTA_HASINDEX) != 0
|
1877 |
|
|
&& (a->index != b->index))
|
1878 |
|
|
return FALSE;
|
1879 |
|
|
|
1880 |
|
|
return TRUE;
|
1881 |
|
|
}
|
1882 |
|
|
|
1883 |
|
|
/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
|
1884 |
|
|
The base register is put in *PBASE.
|
1885 |
|
|
The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
|
1886 |
|
|
the return value.
|
1887 |
|
|
The register stride (minus one) is put in bit 4 of the return value.
|
1888 |
|
|
Bits [6:5] encode the list length (minus one).
|
1889 |
|
|
The type of the list elements is put in *ELTYPE, if non-NULL. */
|
1890 |
|
|
|
1891 |
|
|
#define NEON_LANE(X) ((X) & 0xf)
|
1892 |
|
|
#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
|
1893 |
|
|
#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
|
1894 |
|
|
|
1895 |
|
|
static int
|
1896 |
|
|
parse_neon_el_struct_list (char **str, unsigned *pbase,
|
1897 |
|
|
struct neon_type_el *eltype)
|
1898 |
|
|
{
|
1899 |
|
|
char *ptr = *str;
|
1900 |
|
|
int base_reg = -1;
|
1901 |
|
|
int reg_incr = -1;
|
1902 |
|
|
int count = 0;
|
1903 |
|
|
int lane = -1;
|
1904 |
|
|
int leading_brace = 0;
|
1905 |
|
|
enum arm_reg_type rtype = REG_TYPE_NDQ;
|
1906 |
|
|
const char *const incr_error = _("register stride must be 1 or 2");
|
1907 |
|
|
const char *const type_error = _("mismatched element/structure types in list");
|
1908 |
|
|
struct neon_typed_alias firsttype;
|
1909 |
|
|
|
1910 |
|
|
if (skip_past_char (&ptr, '{') == SUCCESS)
|
1911 |
|
|
leading_brace = 1;
|
1912 |
|
|
|
1913 |
|
|
do
|
1914 |
|
|
{
|
1915 |
|
|
struct neon_typed_alias atype;
|
1916 |
|
|
int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
|
1917 |
|
|
|
1918 |
|
|
if (getreg == FAIL)
|
1919 |
|
|
{
|
1920 |
|
|
first_error (_(reg_expected_msgs[rtype]));
|
1921 |
|
|
return FAIL;
|
1922 |
|
|
}
|
1923 |
|
|
|
1924 |
|
|
if (base_reg == -1)
|
1925 |
|
|
{
|
1926 |
|
|
base_reg = getreg;
|
1927 |
|
|
if (rtype == REG_TYPE_NQ)
|
1928 |
|
|
{
|
1929 |
|
|
reg_incr = 1;
|
1930 |
|
|
}
|
1931 |
|
|
firsttype = atype;
|
1932 |
|
|
}
|
1933 |
|
|
else if (reg_incr == -1)
|
1934 |
|
|
{
|
1935 |
|
|
reg_incr = getreg - base_reg;
|
1936 |
|
|
if (reg_incr < 1 || reg_incr > 2)
|
1937 |
|
|
{
|
1938 |
|
|
first_error (_(incr_error));
|
1939 |
|
|
return FAIL;
|
1940 |
|
|
}
|
1941 |
|
|
}
|
1942 |
|
|
else if (getreg != base_reg + reg_incr * count)
|
1943 |
|
|
{
|
1944 |
|
|
first_error (_(incr_error));
|
1945 |
|
|
return FAIL;
|
1946 |
|
|
}
|
1947 |
|
|
|
1948 |
|
|
if (! neon_alias_types_same (&atype, &firsttype))
|
1949 |
|
|
{
|
1950 |
|
|
first_error (_(type_error));
|
1951 |
|
|
return FAIL;
|
1952 |
|
|
}
|
1953 |
|
|
|
1954 |
|
|
/* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
|
1955 |
|
|
modes. */
|
1956 |
|
|
if (ptr[0] == '-')
|
1957 |
|
|
{
|
1958 |
|
|
struct neon_typed_alias htype;
|
1959 |
|
|
int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
|
1960 |
|
|
if (lane == -1)
|
1961 |
|
|
lane = NEON_INTERLEAVE_LANES;
|
1962 |
|
|
else if (lane != NEON_INTERLEAVE_LANES)
|
1963 |
|
|
{
|
1964 |
|
|
first_error (_(type_error));
|
1965 |
|
|
return FAIL;
|
1966 |
|
|
}
|
1967 |
|
|
if (reg_incr == -1)
|
1968 |
|
|
reg_incr = 1;
|
1969 |
|
|
else if (reg_incr != 1)
|
1970 |
|
|
{
|
1971 |
|
|
first_error (_("don't use Rn-Rm syntax with non-unit stride"));
|
1972 |
|
|
return FAIL;
|
1973 |
|
|
}
|
1974 |
|
|
ptr++;
|
1975 |
|
|
hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
|
1976 |
|
|
if (hireg == FAIL)
|
1977 |
|
|
{
|
1978 |
|
|
first_error (_(reg_expected_msgs[rtype]));
|
1979 |
|
|
return FAIL;
|
1980 |
|
|
}
|
1981 |
|
|
if (! neon_alias_types_same (&htype, &firsttype))
|
1982 |
|
|
{
|
1983 |
|
|
first_error (_(type_error));
|
1984 |
|
|
return FAIL;
|
1985 |
|
|
}
|
1986 |
|
|
count += hireg + dregs - getreg;
|
1987 |
|
|
continue;
|
1988 |
|
|
}
|
1989 |
|
|
|
1990 |
|
|
/* If we're using Q registers, we can't use [] or [n] syntax. */
|
1991 |
|
|
if (rtype == REG_TYPE_NQ)
|
1992 |
|
|
{
|
1993 |
|
|
count += 2;
|
1994 |
|
|
continue;
|
1995 |
|
|
}
|
1996 |
|
|
|
1997 |
|
|
if ((atype.defined & NTA_HASINDEX) != 0)
|
1998 |
|
|
{
|
1999 |
|
|
if (lane == -1)
|
2000 |
|
|
lane = atype.index;
|
2001 |
|
|
else if (lane != atype.index)
|
2002 |
|
|
{
|
2003 |
|
|
first_error (_(type_error));
|
2004 |
|
|
return FAIL;
|
2005 |
|
|
}
|
2006 |
|
|
}
|
2007 |
|
|
else if (lane == -1)
|
2008 |
|
|
lane = NEON_INTERLEAVE_LANES;
|
2009 |
|
|
else if (lane != NEON_INTERLEAVE_LANES)
|
2010 |
|
|
{
|
2011 |
|
|
first_error (_(type_error));
|
2012 |
|
|
return FAIL;
|
2013 |
|
|
}
|
2014 |
|
|
count++;
|
2015 |
|
|
}
|
2016 |
|
|
while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
|
2017 |
|
|
|
2018 |
|
|
/* No lane set by [x]. We must be interleaving structures. */
|
2019 |
|
|
if (lane == -1)
|
2020 |
|
|
lane = NEON_INTERLEAVE_LANES;
|
2021 |
|
|
|
2022 |
|
|
/* Sanity check. */
|
2023 |
|
|
if (lane == -1 || base_reg == -1 || count < 1 || count > 4
|
2024 |
|
|
|| (count > 1 && reg_incr == -1))
|
2025 |
|
|
{
|
2026 |
|
|
first_error (_("error parsing element/structure list"));
|
2027 |
|
|
return FAIL;
|
2028 |
|
|
}
|
2029 |
|
|
|
2030 |
|
|
if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
|
2031 |
|
|
{
|
2032 |
|
|
first_error (_("expected }"));
|
2033 |
|
|
return FAIL;
|
2034 |
|
|
}
|
2035 |
|
|
|
2036 |
|
|
if (reg_incr == -1)
|
2037 |
|
|
reg_incr = 1;
|
2038 |
|
|
|
2039 |
|
|
if (eltype)
|
2040 |
|
|
*eltype = firsttype.eltype;
|
2041 |
|
|
|
2042 |
|
|
*pbase = base_reg;
|
2043 |
|
|
*str = ptr;
|
2044 |
|
|
|
2045 |
|
|
return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
|
2046 |
|
|
}
|
2047 |
|
|
|
2048 |
|
|
/* Parse an explicit relocation suffix on an expression. This is
|
2049 |
|
|
either nothing, or a word in parentheses. Note that if !OBJ_ELF,
|
2050 |
|
|
arm_reloc_hsh contains no entries, so this function can only
|
2051 |
|
|
succeed if there is no () after the word. Returns -1 on error,
|
2052 |
|
|
BFD_RELOC_UNUSED if there wasn't any suffix. */
|
2053 |
|
|
static int
|
2054 |
|
|
parse_reloc (char **str)
|
2055 |
|
|
{
|
2056 |
|
|
struct reloc_entry *r;
|
2057 |
|
|
char *p, *q;
|
2058 |
|
|
|
2059 |
|
|
if (**str != '(')
|
2060 |
|
|
return BFD_RELOC_UNUSED;
|
2061 |
|
|
|
2062 |
|
|
p = *str + 1;
|
2063 |
|
|
q = p;
|
2064 |
|
|
|
2065 |
|
|
while (*q && *q != ')' && *q != ',')
|
2066 |
|
|
q++;
|
2067 |
|
|
if (*q != ')')
|
2068 |
|
|
return -1;
|
2069 |
|
|
|
2070 |
|
|
if ((r = (struct reloc_entry *)
|
2071 |
|
|
hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
|
2072 |
|
|
return -1;
|
2073 |
|
|
|
2074 |
|
|
*str = q + 1;
|
2075 |
|
|
return r->reloc;
|
2076 |
|
|
}
|
2077 |
|
|
|
2078 |
|
|
/* Directives: register aliases. */
|
2079 |
|
|
|
2080 |
|
|
static struct reg_entry *
|
2081 |
|
|
insert_reg_alias (char *str, unsigned number, int type)
|
2082 |
|
|
{
|
2083 |
|
|
struct reg_entry *new_reg;
|
2084 |
|
|
const char *name;
|
2085 |
|
|
|
2086 |
|
|
if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
|
2087 |
|
|
{
|
2088 |
|
|
if (new_reg->builtin)
|
2089 |
|
|
as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
|
2090 |
|
|
|
2091 |
|
|
/* Only warn about a redefinition if it's not defined as the
|
2092 |
|
|
same register. */
|
2093 |
|
|
else if (new_reg->number != number || new_reg->type != type)
|
2094 |
|
|
as_warn (_("ignoring redefinition of register alias '%s'"), str);
|
2095 |
|
|
|
2096 |
|
|
return NULL;
|
2097 |
|
|
}
|
2098 |
|
|
|
2099 |
|
|
name = xstrdup (str);
|
2100 |
|
|
new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
|
2101 |
|
|
|
2102 |
|
|
new_reg->name = name;
|
2103 |
|
|
new_reg->number = number;
|
2104 |
|
|
new_reg->type = type;
|
2105 |
|
|
new_reg->builtin = FALSE;
|
2106 |
|
|
new_reg->neon = NULL;
|
2107 |
|
|
|
2108 |
|
|
if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
|
2109 |
|
|
abort ();
|
2110 |
|
|
|
2111 |
|
|
return new_reg;
|
2112 |
|
|
}
|
2113 |
|
|
|
2114 |
|
|
static void
|
2115 |
|
|
insert_neon_reg_alias (char *str, int number, int type,
|
2116 |
|
|
struct neon_typed_alias *atype)
|
2117 |
|
|
{
|
2118 |
|
|
struct reg_entry *reg = insert_reg_alias (str, number, type);
|
2119 |
|
|
|
2120 |
|
|
if (!reg)
|
2121 |
|
|
{
|
2122 |
|
|
first_error (_("attempt to redefine typed alias"));
|
2123 |
|
|
return;
|
2124 |
|
|
}
|
2125 |
|
|
|
2126 |
|
|
if (atype)
|
2127 |
|
|
{
|
2128 |
|
|
reg->neon = (struct neon_typed_alias *)
|
2129 |
|
|
xmalloc (sizeof (struct neon_typed_alias));
|
2130 |
|
|
*reg->neon = *atype;
|
2131 |
|
|
}
|
2132 |
|
|
}
|
2133 |
|
|
|
2134 |
|
|
/* Look for the .req directive. This is of the form:
|
2135 |
|
|
|
2136 |
|
|
new_register_name .req existing_register_name
|
2137 |
|
|
|
2138 |
|
|
If we find one, or if it looks sufficiently like one that we want to
|
2139 |
|
|
handle any error here, return TRUE. Otherwise return FALSE. */
|
2140 |
|
|
|
2141 |
|
|
static bfd_boolean
|
2142 |
|
|
create_register_alias (char * newname, char *p)
|
2143 |
|
|
{
|
2144 |
|
|
struct reg_entry *old;
|
2145 |
|
|
char *oldname, *nbuf;
|
2146 |
|
|
size_t nlen;
|
2147 |
|
|
|
2148 |
|
|
/* The input scrubber ensures that whitespace after the mnemonic is
|
2149 |
|
|
collapsed to single spaces. */
|
2150 |
|
|
oldname = p;
|
2151 |
|
|
if (strncmp (oldname, " .req ", 6) != 0)
|
2152 |
|
|
return FALSE;
|
2153 |
|
|
|
2154 |
|
|
oldname += 6;
|
2155 |
|
|
if (*oldname == '\0')
|
2156 |
|
|
return FALSE;
|
2157 |
|
|
|
2158 |
|
|
old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
|
2159 |
|
|
if (!old)
|
2160 |
|
|
{
|
2161 |
|
|
as_warn (_("unknown register '%s' -- .req ignored"), oldname);
|
2162 |
|
|
return TRUE;
|
2163 |
|
|
}
|
2164 |
|
|
|
2165 |
|
|
/* If TC_CASE_SENSITIVE is defined, then newname already points to
|
2166 |
|
|
the desired alias name, and p points to its end. If not, then
|
2167 |
|
|
the desired alias name is in the global original_case_string. */
|
2168 |
|
|
#ifdef TC_CASE_SENSITIVE
|
2169 |
|
|
nlen = p - newname;
|
2170 |
|
|
#else
|
2171 |
|
|
newname = original_case_string;
|
2172 |
|
|
nlen = strlen (newname);
|
2173 |
|
|
#endif
|
2174 |
|
|
|
2175 |
|
|
nbuf = (char *) alloca (nlen + 1);
|
2176 |
|
|
memcpy (nbuf, newname, nlen);
|
2177 |
|
|
nbuf[nlen] = '\0';
|
2178 |
|
|
|
2179 |
|
|
/* Create aliases under the new name as stated; an all-lowercase
|
2180 |
|
|
version of the new name; and an all-uppercase version of the new
|
2181 |
|
|
name. */
|
2182 |
|
|
if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
|
2183 |
|
|
{
|
2184 |
|
|
for (p = nbuf; *p; p++)
|
2185 |
|
|
*p = TOUPPER (*p);
|
2186 |
|
|
|
2187 |
|
|
if (strncmp (nbuf, newname, nlen))
|
2188 |
|
|
{
|
2189 |
|
|
/* If this attempt to create an additional alias fails, do not bother
|
2190 |
|
|
trying to create the all-lower case alias. We will fail and issue
|
2191 |
|
|
a second, duplicate error message. This situation arises when the
|
2192 |
|
|
programmer does something like:
|
2193 |
|
|
foo .req r0
|
2194 |
|
|
Foo .req r1
|
2195 |
|
|
The second .req creates the "Foo" alias but then fails to create
|
2196 |
|
|
the artificial FOO alias because it has already been created by the
|
2197 |
|
|
first .req. */
|
2198 |
|
|
if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
|
2199 |
|
|
return TRUE;
|
2200 |
|
|
}
|
2201 |
|
|
|
2202 |
|
|
for (p = nbuf; *p; p++)
|
2203 |
|
|
*p = TOLOWER (*p);
|
2204 |
|
|
|
2205 |
|
|
if (strncmp (nbuf, newname, nlen))
|
2206 |
|
|
insert_reg_alias (nbuf, old->number, old->type);
|
2207 |
|
|
}
|
2208 |
|
|
|
2209 |
|
|
return TRUE;
|
2210 |
|
|
}
|
2211 |
|
|
|
2212 |
|
|
/* Create a Neon typed/indexed register alias using directives, e.g.:
|
2213 |
|
|
X .dn d5.s32[1]
|
2214 |
|
|
Y .qn 6.s16
|
2215 |
|
|
Z .dn d7
|
2216 |
|
|
T .dn Z[0]
|
2217 |
|
|
These typed registers can be used instead of the types specified after the
|
2218 |
|
|
Neon mnemonic, so long as all operands given have types. Types can also be
|
2219 |
|
|
specified directly, e.g.:
|
2220 |
|
|
vadd d0.s32, d1.s32, d2.s32 */
|
2221 |
|
|
|
2222 |
|
|
static bfd_boolean
|
2223 |
|
|
create_neon_reg_alias (char *newname, char *p)
|
2224 |
|
|
{
|
2225 |
|
|
enum arm_reg_type basetype;
|
2226 |
|
|
struct reg_entry *basereg;
|
2227 |
|
|
struct reg_entry mybasereg;
|
2228 |
|
|
struct neon_type ntype;
|
2229 |
|
|
struct neon_typed_alias typeinfo;
|
2230 |
|
|
char *namebuf, *nameend ATTRIBUTE_UNUSED;
|
2231 |
|
|
int namelen;
|
2232 |
|
|
|
2233 |
|
|
typeinfo.defined = 0;
|
2234 |
|
|
typeinfo.eltype.type = NT_invtype;
|
2235 |
|
|
typeinfo.eltype.size = -1;
|
2236 |
|
|
typeinfo.index = -1;
|
2237 |
|
|
|
2238 |
|
|
nameend = p;
|
2239 |
|
|
|
2240 |
|
|
if (strncmp (p, " .dn ", 5) == 0)
|
2241 |
|
|
basetype = REG_TYPE_VFD;
|
2242 |
|
|
else if (strncmp (p, " .qn ", 5) == 0)
|
2243 |
|
|
basetype = REG_TYPE_NQ;
|
2244 |
|
|
else
|
2245 |
|
|
return FALSE;
|
2246 |
|
|
|
2247 |
|
|
p += 5;
|
2248 |
|
|
|
2249 |
|
|
if (*p == '\0')
|
2250 |
|
|
return FALSE;
|
2251 |
|
|
|
2252 |
|
|
basereg = arm_reg_parse_multi (&p);
|
2253 |
|
|
|
2254 |
|
|
if (basereg && basereg->type != basetype)
|
2255 |
|
|
{
|
2256 |
|
|
as_bad (_("bad type for register"));
|
2257 |
|
|
return FALSE;
|
2258 |
|
|
}
|
2259 |
|
|
|
2260 |
|
|
if (basereg == NULL)
|
2261 |
|
|
{
|
2262 |
|
|
expressionS exp;
|
2263 |
|
|
/* Try parsing as an integer. */
|
2264 |
|
|
my_get_expression (&exp, &p, GE_NO_PREFIX);
|
2265 |
|
|
if (exp.X_op != O_constant)
|
2266 |
|
|
{
|
2267 |
|
|
as_bad (_("expression must be constant"));
|
2268 |
|
|
return FALSE;
|
2269 |
|
|
}
|
2270 |
|
|
basereg = &mybasereg;
|
2271 |
|
|
basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
|
2272 |
|
|
: exp.X_add_number;
|
2273 |
|
|
basereg->neon = 0;
|
2274 |
|
|
}
|
2275 |
|
|
|
2276 |
|
|
if (basereg->neon)
|
2277 |
|
|
typeinfo = *basereg->neon;
|
2278 |
|
|
|
2279 |
|
|
if (parse_neon_type (&ntype, &p) == SUCCESS)
|
2280 |
|
|
{
|
2281 |
|
|
/* We got a type. */
|
2282 |
|
|
if (typeinfo.defined & NTA_HASTYPE)
|
2283 |
|
|
{
|
2284 |
|
|
as_bad (_("can't redefine the type of a register alias"));
|
2285 |
|
|
return FALSE;
|
2286 |
|
|
}
|
2287 |
|
|
|
2288 |
|
|
typeinfo.defined |= NTA_HASTYPE;
|
2289 |
|
|
if (ntype.elems != 1)
|
2290 |
|
|
{
|
2291 |
|
|
as_bad (_("you must specify a single type only"));
|
2292 |
|
|
return FALSE;
|
2293 |
|
|
}
|
2294 |
|
|
typeinfo.eltype = ntype.el[0];
|
2295 |
|
|
}
|
2296 |
|
|
|
2297 |
|
|
if (skip_past_char (&p, '[') == SUCCESS)
|
2298 |
|
|
{
|
2299 |
|
|
expressionS exp;
|
2300 |
|
|
/* We got a scalar index. */
|
2301 |
|
|
|
2302 |
|
|
if (typeinfo.defined & NTA_HASINDEX)
|
2303 |
|
|
{
|
2304 |
|
|
as_bad (_("can't redefine the index of a scalar alias"));
|
2305 |
|
|
return FALSE;
|
2306 |
|
|
}
|
2307 |
|
|
|
2308 |
|
|
my_get_expression (&exp, &p, GE_NO_PREFIX);
|
2309 |
|
|
|
2310 |
|
|
if (exp.X_op != O_constant)
|
2311 |
|
|
{
|
2312 |
|
|
as_bad (_("scalar index must be constant"));
|
2313 |
|
|
return FALSE;
|
2314 |
|
|
}
|
2315 |
|
|
|
2316 |
|
|
typeinfo.defined |= NTA_HASINDEX;
|
2317 |
|
|
typeinfo.index = exp.X_add_number;
|
2318 |
|
|
|
2319 |
|
|
if (skip_past_char (&p, ']') == FAIL)
|
2320 |
|
|
{
|
2321 |
|
|
as_bad (_("expecting ]"));
|
2322 |
|
|
return FALSE;
|
2323 |
|
|
}
|
2324 |
|
|
}
|
2325 |
|
|
|
2326 |
|
|
/* If TC_CASE_SENSITIVE is defined, then newname already points to
|
2327 |
|
|
the desired alias name, and p points to its end. If not, then
|
2328 |
|
|
the desired alias name is in the global original_case_string. */
|
2329 |
|
|
#ifdef TC_CASE_SENSITIVE
|
2330 |
|
|
namelen = nameend - newname;
|
2331 |
|
|
#else
|
2332 |
|
|
newname = original_case_string;
|
2333 |
|
|
namelen = strlen (newname);
|
2334 |
|
|
#endif
|
2335 |
|
|
|
2336 |
|
|
namebuf = (char *) alloca (namelen + 1);
|
2337 |
|
|
strncpy (namebuf, newname, namelen);
|
2338 |
|
|
namebuf[namelen] = '\0';
|
2339 |
|
|
|
2340 |
|
|
insert_neon_reg_alias (namebuf, basereg->number, basetype,
|
2341 |
|
|
typeinfo.defined != 0 ? &typeinfo : NULL);
|
2342 |
|
|
|
2343 |
|
|
/* Insert name in all uppercase. */
|
2344 |
|
|
for (p = namebuf; *p; p++)
|
2345 |
|
|
*p = TOUPPER (*p);
|
2346 |
|
|
|
2347 |
|
|
if (strncmp (namebuf, newname, namelen))
|
2348 |
|
|
insert_neon_reg_alias (namebuf, basereg->number, basetype,
|
2349 |
|
|
typeinfo.defined != 0 ? &typeinfo : NULL);
|
2350 |
|
|
|
2351 |
|
|
/* Insert name in all lowercase. */
|
2352 |
|
|
for (p = namebuf; *p; p++)
|
2353 |
|
|
*p = TOLOWER (*p);
|
2354 |
|
|
|
2355 |
|
|
if (strncmp (namebuf, newname, namelen))
|
2356 |
|
|
insert_neon_reg_alias (namebuf, basereg->number, basetype,
|
2357 |
|
|
typeinfo.defined != 0 ? &typeinfo : NULL);
|
2358 |
|
|
|
2359 |
|
|
return TRUE;
|
2360 |
|
|
}
|
2361 |
|
|
|
2362 |
|
|
/* Should never be called, as .req goes between the alias and the
|
2363 |
|
|
register name, not at the beginning of the line. */
|
2364 |
|
|
|
2365 |
|
|
static void
|
2366 |
|
|
s_req (int a ATTRIBUTE_UNUSED)
|
2367 |
|
|
{
|
2368 |
|
|
as_bad (_("invalid syntax for .req directive"));
|
2369 |
|
|
}
|
2370 |
|
|
|
2371 |
|
|
static void
|
2372 |
|
|
s_dn (int a ATTRIBUTE_UNUSED)
|
2373 |
|
|
{
|
2374 |
|
|
as_bad (_("invalid syntax for .dn directive"));
|
2375 |
|
|
}
|
2376 |
|
|
|
2377 |
|
|
static void
|
2378 |
|
|
s_qn (int a ATTRIBUTE_UNUSED)
|
2379 |
|
|
{
|
2380 |
|
|
as_bad (_("invalid syntax for .qn directive"));
|
2381 |
|
|
}
|
2382 |
|
|
|
2383 |
|
|
/* The .unreq directive deletes an alias which was previously defined
|
2384 |
|
|
by .req. For example:
|
2385 |
|
|
|
2386 |
|
|
my_alias .req r11
|
2387 |
|
|
.unreq my_alias */
|
2388 |
|
|
|
2389 |
|
|
static void
|
2390 |
|
|
s_unreq (int a ATTRIBUTE_UNUSED)
|
2391 |
|
|
{
|
2392 |
|
|
char * name;
|
2393 |
|
|
char saved_char;
|
2394 |
|
|
|
2395 |
|
|
name = input_line_pointer;
|
2396 |
|
|
|
2397 |
|
|
while (*input_line_pointer != 0
|
2398 |
|
|
&& *input_line_pointer != ' '
|
2399 |
|
|
&& *input_line_pointer != '\n')
|
2400 |
|
|
++input_line_pointer;
|
2401 |
|
|
|
2402 |
|
|
saved_char = *input_line_pointer;
|
2403 |
|
|
*input_line_pointer = 0;
|
2404 |
|
|
|
2405 |
|
|
if (!*name)
|
2406 |
|
|
as_bad (_("invalid syntax for .unreq directive"));
|
2407 |
|
|
else
|
2408 |
|
|
{
|
2409 |
|
|
struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
|
2410 |
|
|
name);
|
2411 |
|
|
|
2412 |
|
|
if (!reg)
|
2413 |
|
|
as_bad (_("unknown register alias '%s'"), name);
|
2414 |
|
|
else if (reg->builtin)
|
2415 |
|
|
as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
|
2416 |
|
|
name);
|
2417 |
|
|
else
|
2418 |
|
|
{
|
2419 |
|
|
char * p;
|
2420 |
|
|
char * nbuf;
|
2421 |
|
|
|
2422 |
|
|
hash_delete (arm_reg_hsh, name, FALSE);
|
2423 |
|
|
free ((char *) reg->name);
|
2424 |
|
|
if (reg->neon)
|
2425 |
|
|
free (reg->neon);
|
2426 |
|
|
free (reg);
|
2427 |
|
|
|
2428 |
|
|
/* Also locate the all upper case and all lower case versions.
|
2429 |
|
|
Do not complain if we cannot find one or the other as it
|
2430 |
|
|
was probably deleted above. */
|
2431 |
|
|
|
2432 |
|
|
nbuf = strdup (name);
|
2433 |
|
|
for (p = nbuf; *p; p++)
|
2434 |
|
|
*p = TOUPPER (*p);
|
2435 |
|
|
reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
|
2436 |
|
|
if (reg)
|
2437 |
|
|
{
|
2438 |
|
|
hash_delete (arm_reg_hsh, nbuf, FALSE);
|
2439 |
|
|
free ((char *) reg->name);
|
2440 |
|
|
if (reg->neon)
|
2441 |
|
|
free (reg->neon);
|
2442 |
|
|
free (reg);
|
2443 |
|
|
}
|
2444 |
|
|
|
2445 |
|
|
for (p = nbuf; *p; p++)
|
2446 |
|
|
*p = TOLOWER (*p);
|
2447 |
|
|
reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
|
2448 |
|
|
if (reg)
|
2449 |
|
|
{
|
2450 |
|
|
hash_delete (arm_reg_hsh, nbuf, FALSE);
|
2451 |
|
|
free ((char *) reg->name);
|
2452 |
|
|
if (reg->neon)
|
2453 |
|
|
free (reg->neon);
|
2454 |
|
|
free (reg);
|
2455 |
|
|
}
|
2456 |
|
|
|
2457 |
|
|
free (nbuf);
|
2458 |
|
|
}
|
2459 |
|
|
}
|
2460 |
|
|
|
2461 |
|
|
*input_line_pointer = saved_char;
|
2462 |
|
|
demand_empty_rest_of_line ();
|
2463 |
|
|
}
|
2464 |
|
|
|
2465 |
|
|
/* Directives: Instruction set selection. */
|
2466 |
|
|
|
2467 |
|
|
#ifdef OBJ_ELF
|
2468 |
|
|
/* This code is to handle mapping symbols as defined in the ARM ELF spec.
|
2469 |
|
|
(See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
|
2470 |
|
|
Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
|
2471 |
|
|
and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
|
2472 |
|
|
|
2473 |
|
|
/* Create a new mapping symbol for the transition to STATE. */
|
2474 |
|
|
|
2475 |
|
|
static void
|
2476 |
|
|
make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
|
2477 |
|
|
{
|
2478 |
|
|
symbolS * symbolP;
|
2479 |
|
|
const char * symname;
|
2480 |
|
|
int type;
|
2481 |
|
|
|
2482 |
|
|
switch (state)
|
2483 |
|
|
{
|
2484 |
|
|
case MAP_DATA:
|
2485 |
|
|
symname = "$d";
|
2486 |
|
|
type = BSF_NO_FLAGS;
|
2487 |
|
|
break;
|
2488 |
|
|
case MAP_ARM:
|
2489 |
|
|
symname = "$a";
|
2490 |
|
|
type = BSF_NO_FLAGS;
|
2491 |
|
|
break;
|
2492 |
|
|
case MAP_THUMB:
|
2493 |
|
|
symname = "$t";
|
2494 |
|
|
type = BSF_NO_FLAGS;
|
2495 |
|
|
break;
|
2496 |
|
|
default:
|
2497 |
|
|
abort ();
|
2498 |
|
|
}
|
2499 |
|
|
|
2500 |
|
|
symbolP = symbol_new (symname, now_seg, value, frag);
|
2501 |
|
|
symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
|
2502 |
|
|
|
2503 |
|
|
switch (state)
|
2504 |
|
|
{
|
2505 |
|
|
case MAP_ARM:
|
2506 |
|
|
THUMB_SET_FUNC (symbolP, 0);
|
2507 |
|
|
ARM_SET_THUMB (symbolP, 0);
|
2508 |
|
|
ARM_SET_INTERWORK (symbolP, support_interwork);
|
2509 |
|
|
break;
|
2510 |
|
|
|
2511 |
|
|
case MAP_THUMB:
|
2512 |
|
|
THUMB_SET_FUNC (symbolP, 1);
|
2513 |
|
|
ARM_SET_THUMB (symbolP, 1);
|
2514 |
|
|
ARM_SET_INTERWORK (symbolP, support_interwork);
|
2515 |
|
|
break;
|
2516 |
|
|
|
2517 |
|
|
case MAP_DATA:
|
2518 |
|
|
default:
|
2519 |
|
|
break;
|
2520 |
|
|
}
|
2521 |
|
|
|
2522 |
|
|
/* Save the mapping symbols for future reference. Also check that
|
2523 |
|
|
we do not place two mapping symbols at the same offset within a
|
2524 |
|
|
frag. We'll handle overlap between frags in
|
2525 |
|
|
check_mapping_symbols.
|
2526 |
|
|
|
2527 |
|
|
If .fill or other data filling directive generates zero sized data,
|
2528 |
|
|
the mapping symbol for the following code will have the same value
|
2529 |
|
|
as the one generated for the data filling directive. In this case,
|
2530 |
|
|
we replace the old symbol with the new one at the same address. */
|
2531 |
|
|
if (value == 0)
|
2532 |
|
|
{
|
2533 |
|
|
if (frag->tc_frag_data.first_map != NULL)
|
2534 |
|
|
{
|
2535 |
|
|
know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
|
2536 |
|
|
symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
|
2537 |
|
|
}
|
2538 |
|
|
frag->tc_frag_data.first_map = symbolP;
|
2539 |
|
|
}
|
2540 |
|
|
if (frag->tc_frag_data.last_map != NULL)
|
2541 |
|
|
{
|
2542 |
|
|
know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
|
2543 |
|
|
if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
|
2544 |
|
|
symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
|
2545 |
|
|
}
|
2546 |
|
|
frag->tc_frag_data.last_map = symbolP;
|
2547 |
|
|
}
|
2548 |
|
|
|
2549 |
|
|
/* We must sometimes convert a region marked as code to data during
|
2550 |
|
|
code alignment, if an odd number of bytes have to be padded. The
|
2551 |
|
|
code mapping symbol is pushed to an aligned address. */
|
2552 |
|
|
|
2553 |
|
|
static void
|
2554 |
|
|
insert_data_mapping_symbol (enum mstate state,
|
2555 |
|
|
valueT value, fragS *frag, offsetT bytes)
|
2556 |
|
|
{
|
2557 |
|
|
/* If there was already a mapping symbol, remove it. */
|
2558 |
|
|
if (frag->tc_frag_data.last_map != NULL
|
2559 |
|
|
&& S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
|
2560 |
|
|
{
|
2561 |
|
|
symbolS *symp = frag->tc_frag_data.last_map;
|
2562 |
|
|
|
2563 |
|
|
if (value == 0)
|
2564 |
|
|
{
|
2565 |
|
|
know (frag->tc_frag_data.first_map == symp);
|
2566 |
|
|
frag->tc_frag_data.first_map = NULL;
|
2567 |
|
|
}
|
2568 |
|
|
frag->tc_frag_data.last_map = NULL;
|
2569 |
|
|
symbol_remove (symp, &symbol_rootP, &symbol_lastP);
|
2570 |
|
|
}
|
2571 |
|
|
|
2572 |
|
|
make_mapping_symbol (MAP_DATA, value, frag);
|
2573 |
|
|
make_mapping_symbol (state, value + bytes, frag);
|
2574 |
|
|
}
|
2575 |
|
|
|
2576 |
|
|
static void mapping_state_2 (enum mstate state, int max_chars);
|
2577 |
|
|
|
2578 |
|
|
/* Set the mapping state to STATE. Only call this when about to
|
2579 |
|
|
emit some STATE bytes to the file. */
|
2580 |
|
|
|
2581 |
|
|
void
|
2582 |
|
|
mapping_state (enum mstate state)
|
2583 |
|
|
{
|
2584 |
|
|
enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
|
2585 |
|
|
|
2586 |
|
|
#define TRANSITION(from, to) (mapstate == (from) && state == (to))
|
2587 |
|
|
|
2588 |
|
|
if (mapstate == state)
|
2589 |
|
|
/* The mapping symbol has already been emitted.
|
2590 |
|
|
There is nothing else to do. */
|
2591 |
|
|
return;
|
2592 |
|
|
else if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
|
2593 |
|
|
/* This case will be evaluated later in the next else. */
|
2594 |
|
|
return;
|
2595 |
|
|
else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
|
2596 |
|
|
|| TRANSITION (MAP_UNDEFINED, MAP_THUMB))
|
2597 |
|
|
{
|
2598 |
|
|
/* Only add the symbol if the offset is > 0:
|
2599 |
|
|
if we're at the first frag, check it's size > 0;
|
2600 |
|
|
if we're not at the first frag, then for sure
|
2601 |
|
|
the offset is > 0. */
|
2602 |
|
|
struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
|
2603 |
|
|
const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
|
2604 |
|
|
|
2605 |
|
|
if (add_symbol)
|
2606 |
|
|
make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
|
2607 |
|
|
}
|
2608 |
|
|
|
2609 |
|
|
mapping_state_2 (state, 0);
|
2610 |
|
|
#undef TRANSITION
|
2611 |
|
|
}
|
2612 |
|
|
|
2613 |
|
|
/* Same as mapping_state, but MAX_CHARS bytes have already been
|
2614 |
|
|
allocated. Put the mapping symbol that far back. */
|
2615 |
|
|
|
2616 |
|
|
static void
|
2617 |
|
|
mapping_state_2 (enum mstate state, int max_chars)
|
2618 |
|
|
{
|
2619 |
|
|
enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
|
2620 |
|
|
|
2621 |
|
|
if (!SEG_NORMAL (now_seg))
|
2622 |
|
|
return;
|
2623 |
|
|
|
2624 |
|
|
if (mapstate == state)
|
2625 |
|
|
/* The mapping symbol has already been emitted.
|
2626 |
|
|
There is nothing else to do. */
|
2627 |
|
|
return;
|
2628 |
|
|
|
2629 |
|
|
seg_info (now_seg)->tc_segment_info_data.mapstate = state;
|
2630 |
|
|
make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
|
2631 |
|
|
}
|
2632 |
|
|
#else
|
2633 |
|
|
#define mapping_state(x) ((void)0)
|
2634 |
|
|
#define mapping_state_2(x, y) ((void)0)
|
2635 |
|
|
#endif
|
2636 |
|
|
|
2637 |
|
|
/* Find the real, Thumb encoded start of a Thumb function. */
|
2638 |
|
|
|
2639 |
|
|
#ifdef OBJ_COFF
|
2640 |
|
|
static symbolS *
|
2641 |
|
|
find_real_start (symbolS * symbolP)
|
2642 |
|
|
{
|
2643 |
|
|
char * real_start;
|
2644 |
|
|
const char * name = S_GET_NAME (symbolP);
|
2645 |
|
|
symbolS * new_target;
|
2646 |
|
|
|
2647 |
|
|
/* This definition must agree with the one in gcc/config/arm/thumb.c. */
|
2648 |
|
|
#define STUB_NAME ".real_start_of"
|
2649 |
|
|
|
2650 |
|
|
if (name == NULL)
|
2651 |
|
|
abort ();
|
2652 |
|
|
|
2653 |
|
|
/* The compiler may generate BL instructions to local labels because
|
2654 |
|
|
it needs to perform a branch to a far away location. These labels
|
2655 |
|
|
do not have a corresponding ".real_start_of" label. We check
|
2656 |
|
|
both for S_IS_LOCAL and for a leading dot, to give a way to bypass
|
2657 |
|
|
the ".real_start_of" convention for nonlocal branches. */
|
2658 |
|
|
if (S_IS_LOCAL (symbolP) || name[0] == '.')
|
2659 |
|
|
return symbolP;
|
2660 |
|
|
|
2661 |
|
|
real_start = ACONCAT ((STUB_NAME, name, NULL));
|
2662 |
|
|
new_target = symbol_find (real_start);
|
2663 |
|
|
|
2664 |
|
|
if (new_target == NULL)
|
2665 |
|
|
{
|
2666 |
|
|
as_warn (_("Failed to find real start of function: %s\n"), name);
|
2667 |
|
|
new_target = symbolP;
|
2668 |
|
|
}
|
2669 |
|
|
|
2670 |
|
|
return new_target;
|
2671 |
|
|
}
|
2672 |
|
|
#endif
|
2673 |
|
|
|
2674 |
|
|
static void
|
2675 |
|
|
opcode_select (int width)
|
2676 |
|
|
{
|
2677 |
|
|
switch (width)
|
2678 |
|
|
{
|
2679 |
|
|
case 16:
|
2680 |
|
|
if (! thumb_mode)
|
2681 |
|
|
{
|
2682 |
|
|
if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
|
2683 |
|
|
as_bad (_("selected processor does not support THUMB opcodes"));
|
2684 |
|
|
|
2685 |
|
|
thumb_mode = 1;
|
2686 |
|
|
/* No need to force the alignment, since we will have been
|
2687 |
|
|
coming from ARM mode, which is word-aligned. */
|
2688 |
|
|
record_alignment (now_seg, 1);
|
2689 |
|
|
}
|
2690 |
|
|
break;
|
2691 |
|
|
|
2692 |
|
|
case 32:
|
2693 |
|
|
if (thumb_mode)
|
2694 |
|
|
{
|
2695 |
|
|
if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
|
2696 |
|
|
as_bad (_("selected processor does not support ARM opcodes"));
|
2697 |
|
|
|
2698 |
|
|
thumb_mode = 0;
|
2699 |
|
|
|
2700 |
|
|
if (!need_pass_2)
|
2701 |
|
|
frag_align (2, 0, 0);
|
2702 |
|
|
|
2703 |
|
|
record_alignment (now_seg, 1);
|
2704 |
|
|
}
|
2705 |
|
|
break;
|
2706 |
|
|
|
2707 |
|
|
default:
|
2708 |
|
|
as_bad (_("invalid instruction size selected (%d)"), width);
|
2709 |
|
|
}
|
2710 |
|
|
}
|
2711 |
|
|
|
2712 |
|
|
static void
|
2713 |
|
|
s_arm (int ignore ATTRIBUTE_UNUSED)
|
2714 |
|
|
{
|
2715 |
|
|
opcode_select (32);
|
2716 |
|
|
demand_empty_rest_of_line ();
|
2717 |
|
|
}
|
2718 |
|
|
|
2719 |
|
|
static void
|
2720 |
|
|
s_thumb (int ignore ATTRIBUTE_UNUSED)
|
2721 |
|
|
{
|
2722 |
|
|
opcode_select (16);
|
2723 |
|
|
demand_empty_rest_of_line ();
|
2724 |
|
|
}
|
2725 |
|
|
|
2726 |
|
|
static void
|
2727 |
|
|
s_code (int unused ATTRIBUTE_UNUSED)
|
2728 |
|
|
{
|
2729 |
|
|
int temp;
|
2730 |
|
|
|
2731 |
|
|
temp = get_absolute_expression ();
|
2732 |
|
|
switch (temp)
|
2733 |
|
|
{
|
2734 |
|
|
case 16:
|
2735 |
|
|
case 32:
|
2736 |
|
|
opcode_select (temp);
|
2737 |
|
|
break;
|
2738 |
|
|
|
2739 |
|
|
default:
|
2740 |
|
|
as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
|
2741 |
|
|
}
|
2742 |
|
|
}
|
2743 |
|
|
|
2744 |
|
|
static void
|
2745 |
|
|
s_force_thumb (int ignore ATTRIBUTE_UNUSED)
|
2746 |
|
|
{
|
2747 |
|
|
/* If we are not already in thumb mode go into it, EVEN if
|
2748 |
|
|
the target processor does not support thumb instructions.
|
2749 |
|
|
This is used by gcc/config/arm/lib1funcs.asm for example
|
2750 |
|
|
to compile interworking support functions even if the
|
2751 |
|
|
target processor should not support interworking. */
|
2752 |
|
|
if (! thumb_mode)
|
2753 |
|
|
{
|
2754 |
|
|
thumb_mode = 2;
|
2755 |
|
|
record_alignment (now_seg, 1);
|
2756 |
|
|
}
|
2757 |
|
|
|
2758 |
|
|
demand_empty_rest_of_line ();
|
2759 |
|
|
}
|
2760 |
|
|
|
2761 |
|
|
static void
|
2762 |
|
|
s_thumb_func (int ignore ATTRIBUTE_UNUSED)
|
2763 |
|
|
{
|
2764 |
|
|
s_thumb (0);
|
2765 |
|
|
|
2766 |
|
|
/* The following label is the name/address of the start of a Thumb function.
|
2767 |
|
|
We need to know this for the interworking support. */
|
2768 |
|
|
label_is_thumb_function_name = TRUE;
|
2769 |
|
|
}
|
2770 |
|
|
|
2771 |
|
|
/* Perform a .set directive, but also mark the alias as
|
2772 |
|
|
being a thumb function. */
|
2773 |
|
|
|
2774 |
|
|
static void
|
2775 |
|
|
s_thumb_set (int equiv)
|
2776 |
|
|
{
|
2777 |
|
|
/* XXX the following is a duplicate of the code for s_set() in read.c
|
2778 |
|
|
We cannot just call that code as we need to get at the symbol that
|
2779 |
|
|
is created. */
|
2780 |
|
|
char * name;
|
2781 |
|
|
char delim;
|
2782 |
|
|
char * end_name;
|
2783 |
|
|
symbolS * symbolP;
|
2784 |
|
|
|
2785 |
|
|
/* Especial apologies for the random logic:
|
2786 |
|
|
This just grew, and could be parsed much more simply!
|
2787 |
|
|
Dean - in haste. */
|
2788 |
|
|
name = input_line_pointer;
|
2789 |
|
|
delim = get_symbol_end ();
|
2790 |
|
|
end_name = input_line_pointer;
|
2791 |
|
|
*end_name = delim;
|
2792 |
|
|
|
2793 |
|
|
if (*input_line_pointer != ',')
|
2794 |
|
|
{
|
2795 |
|
|
*end_name = 0;
|
2796 |
|
|
as_bad (_("expected comma after name \"%s\""), name);
|
2797 |
|
|
*end_name = delim;
|
2798 |
|
|
ignore_rest_of_line ();
|
2799 |
|
|
return;
|
2800 |
|
|
}
|
2801 |
|
|
|
2802 |
|
|
input_line_pointer++;
|
2803 |
|
|
*end_name = 0;
|
2804 |
|
|
|
2805 |
|
|
if (name[0] == '.' && name[1] == '\0')
|
2806 |
|
|
{
|
2807 |
|
|
/* XXX - this should not happen to .thumb_set. */
|
2808 |
|
|
abort ();
|
2809 |
|
|
}
|
2810 |
|
|
|
2811 |
|
|
if ((symbolP = symbol_find (name)) == NULL
|
2812 |
|
|
&& (symbolP = md_undefined_symbol (name)) == NULL)
|
2813 |
|
|
{
|
2814 |
|
|
#ifndef NO_LISTING
|
2815 |
|
|
/* When doing symbol listings, play games with dummy fragments living
|
2816 |
|
|
outside the normal fragment chain to record the file and line info
|
2817 |
|
|
for this symbol. */
|
2818 |
|
|
if (listing & LISTING_SYMBOLS)
|
2819 |
|
|
{
|
2820 |
|
|
extern struct list_info_struct * listing_tail;
|
2821 |
|
|
fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
|
2822 |
|
|
|
2823 |
|
|
memset (dummy_frag, 0, sizeof (fragS));
|
2824 |
|
|
dummy_frag->fr_type = rs_fill;
|
2825 |
|
|
dummy_frag->line = listing_tail;
|
2826 |
|
|
symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
|
2827 |
|
|
dummy_frag->fr_symbol = symbolP;
|
2828 |
|
|
}
|
2829 |
|
|
else
|
2830 |
|
|
#endif
|
2831 |
|
|
symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
|
2832 |
|
|
|
2833 |
|
|
#ifdef OBJ_COFF
|
2834 |
|
|
/* "set" symbols are local unless otherwise specified. */
|
2835 |
|
|
SF_SET_LOCAL (symbolP);
|
2836 |
|
|
#endif /* OBJ_COFF */
|
2837 |
|
|
} /* Make a new symbol. */
|
2838 |
|
|
|
2839 |
|
|
symbol_table_insert (symbolP);
|
2840 |
|
|
|
2841 |
|
|
* end_name = delim;
|
2842 |
|
|
|
2843 |
|
|
if (equiv
|
2844 |
|
|
&& S_IS_DEFINED (symbolP)
|
2845 |
|
|
&& S_GET_SEGMENT (symbolP) != reg_section)
|
2846 |
|
|
as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
|
2847 |
|
|
|
2848 |
|
|
pseudo_set (symbolP);
|
2849 |
|
|
|
2850 |
|
|
demand_empty_rest_of_line ();
|
2851 |
|
|
|
2852 |
|
|
/* XXX Now we come to the Thumb specific bit of code. */
|
2853 |
|
|
|
2854 |
|
|
THUMB_SET_FUNC (symbolP, 1);
|
2855 |
|
|
ARM_SET_THUMB (symbolP, 1);
|
2856 |
|
|
#if defined OBJ_ELF || defined OBJ_COFF
|
2857 |
|
|
ARM_SET_INTERWORK (symbolP, support_interwork);
|
2858 |
|
|
#endif
|
2859 |
|
|
}
|
2860 |
|
|
|
2861 |
|
|
/* Directives: Mode selection. */
|
2862 |
|
|
|
2863 |
|
|
/* .syntax [unified|divided] - choose the new unified syntax
|
2864 |
|
|
(same for Arm and Thumb encoding, modulo slight differences in what
|
2865 |
|
|
can be represented) or the old divergent syntax for each mode. */
|
2866 |
|
|
static void
|
2867 |
|
|
s_syntax (int unused ATTRIBUTE_UNUSED)
|
2868 |
|
|
{
|
2869 |
|
|
char *name, delim;
|
2870 |
|
|
|
2871 |
|
|
name = input_line_pointer;
|
2872 |
|
|
delim = get_symbol_end ();
|
2873 |
|
|
|
2874 |
|
|
if (!strcasecmp (name, "unified"))
|
2875 |
|
|
unified_syntax = TRUE;
|
2876 |
|
|
else if (!strcasecmp (name, "divided"))
|
2877 |
|
|
unified_syntax = FALSE;
|
2878 |
|
|
else
|
2879 |
|
|
{
|
2880 |
|
|
as_bad (_("unrecognized syntax mode \"%s\""), name);
|
2881 |
|
|
return;
|
2882 |
|
|
}
|
2883 |
|
|
*input_line_pointer = delim;
|
2884 |
|
|
demand_empty_rest_of_line ();
|
2885 |
|
|
}
|
2886 |
|
|
|
2887 |
|
|
/* Directives: sectioning and alignment. */
|
2888 |
|
|
|
2889 |
|
|
/* Same as s_align_ptwo but align 0 => align 2. */
|
2890 |
|
|
|
2891 |
|
|
static void
|
2892 |
|
|
s_align (int unused ATTRIBUTE_UNUSED)
|
2893 |
|
|
{
|
2894 |
|
|
int temp;
|
2895 |
|
|
bfd_boolean fill_p;
|
2896 |
|
|
long temp_fill;
|
2897 |
|
|
long max_alignment = 15;
|
2898 |
|
|
|
2899 |
|
|
temp = get_absolute_expression ();
|
2900 |
|
|
if (temp > max_alignment)
|
2901 |
|
|
as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
|
2902 |
|
|
else if (temp < 0)
|
2903 |
|
|
{
|
2904 |
|
|
as_bad (_("alignment negative. 0 assumed."));
|
2905 |
|
|
temp = 0;
|
2906 |
|
|
}
|
2907 |
|
|
|
2908 |
|
|
if (*input_line_pointer == ',')
|
2909 |
|
|
{
|
2910 |
|
|
input_line_pointer++;
|
2911 |
|
|
temp_fill = get_absolute_expression ();
|
2912 |
|
|
fill_p = TRUE;
|
2913 |
|
|
}
|
2914 |
|
|
else
|
2915 |
|
|
{
|
2916 |
|
|
fill_p = FALSE;
|
2917 |
|
|
temp_fill = 0;
|
2918 |
|
|
}
|
2919 |
|
|
|
2920 |
|
|
if (!temp)
|
2921 |
|
|
temp = 2;
|
2922 |
|
|
|
2923 |
|
|
/* Only make a frag if we HAVE to. */
|
2924 |
|
|
if (temp && !need_pass_2)
|
2925 |
|
|
{
|
2926 |
|
|
if (!fill_p && subseg_text_p (now_seg))
|
2927 |
|
|
frag_align_code (temp, 0);
|
2928 |
|
|
else
|
2929 |
|
|
frag_align (temp, (int) temp_fill, 0);
|
2930 |
|
|
}
|
2931 |
|
|
demand_empty_rest_of_line ();
|
2932 |
|
|
|
2933 |
|
|
record_alignment (now_seg, temp);
|
2934 |
|
|
}
|
2935 |
|
|
|
2936 |
|
|
static void
|
2937 |
|
|
s_bss (int ignore ATTRIBUTE_UNUSED)
|
2938 |
|
|
{
|
2939 |
|
|
/* We don't support putting frags in the BSS segment, we fake it by
|
2940 |
|
|
marking in_bss, then looking at s_skip for clues. */
|
2941 |
|
|
subseg_set (bss_section, 0);
|
2942 |
|
|
demand_empty_rest_of_line ();
|
2943 |
|
|
|
2944 |
|
|
#ifdef md_elf_section_change_hook
|
2945 |
|
|
md_elf_section_change_hook ();
|
2946 |
|
|
#endif
|
2947 |
|
|
}
|
2948 |
|
|
|
2949 |
|
|
static void
|
2950 |
|
|
s_even (int ignore ATTRIBUTE_UNUSED)
|
2951 |
|
|
{
|
2952 |
|
|
/* Never make frag if expect extra pass. */
|
2953 |
|
|
if (!need_pass_2)
|
2954 |
|
|
frag_align (1, 0, 0);
|
2955 |
|
|
|
2956 |
|
|
record_alignment (now_seg, 1);
|
2957 |
|
|
|
2958 |
|
|
demand_empty_rest_of_line ();
|
2959 |
|
|
}
|
2960 |
|
|
|
2961 |
|
|
/* Directives: Literal pools. */
|
2962 |
|
|
|
2963 |
|
|
static literal_pool *
|
2964 |
|
|
find_literal_pool (void)
|
2965 |
|
|
{
|
2966 |
|
|
literal_pool * pool;
|
2967 |
|
|
|
2968 |
|
|
for (pool = list_of_pools; pool != NULL; pool = pool->next)
|
2969 |
|
|
{
|
2970 |
|
|
if (pool->section == now_seg
|
2971 |
|
|
&& pool->sub_section == now_subseg)
|
2972 |
|
|
break;
|
2973 |
|
|
}
|
2974 |
|
|
|
2975 |
|
|
return pool;
|
2976 |
|
|
}
|
2977 |
|
|
|
2978 |
|
|
static literal_pool *
|
2979 |
|
|
find_or_make_literal_pool (void)
|
2980 |
|
|
{
|
2981 |
|
|
/* Next literal pool ID number. */
|
2982 |
|
|
static unsigned int latest_pool_num = 1;
|
2983 |
|
|
literal_pool * pool;
|
2984 |
|
|
|
2985 |
|
|
pool = find_literal_pool ();
|
2986 |
|
|
|
2987 |
|
|
if (pool == NULL)
|
2988 |
|
|
{
|
2989 |
|
|
/* Create a new pool. */
|
2990 |
|
|
pool = (literal_pool *) xmalloc (sizeof (* pool));
|
2991 |
|
|
if (! pool)
|
2992 |
|
|
return NULL;
|
2993 |
|
|
|
2994 |
|
|
pool->next_free_entry = 0;
|
2995 |
|
|
pool->section = now_seg;
|
2996 |
|
|
pool->sub_section = now_subseg;
|
2997 |
|
|
pool->next = list_of_pools;
|
2998 |
|
|
pool->symbol = NULL;
|
2999 |
|
|
|
3000 |
|
|
/* Add it to the list. */
|
3001 |
|
|
list_of_pools = pool;
|
3002 |
|
|
}
|
3003 |
|
|
|
3004 |
|
|
/* New pools, and emptied pools, will have a NULL symbol. */
|
3005 |
|
|
if (pool->symbol == NULL)
|
3006 |
|
|
{
|
3007 |
|
|
pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
|
3008 |
|
|
(valueT) 0, &zero_address_frag);
|
3009 |
|
|
pool->id = latest_pool_num ++;
|
3010 |
|
|
}
|
3011 |
|
|
|
3012 |
|
|
/* Done. */
|
3013 |
|
|
return pool;
|
3014 |
|
|
}
|
3015 |
|
|
|
3016 |
|
|
/* Add the literal in the global 'inst'
|
3017 |
|
|
structure to the relevant literal pool. */
|
3018 |
|
|
|
3019 |
|
|
static int
|
3020 |
|
|
add_to_lit_pool (void)
|
3021 |
|
|
{
|
3022 |
|
|
literal_pool * pool;
|
3023 |
|
|
unsigned int entry;
|
3024 |
|
|
|
3025 |
|
|
pool = find_or_make_literal_pool ();
|
3026 |
|
|
|
3027 |
|
|
/* Check if this literal value is already in the pool. */
|
3028 |
|
|
for (entry = 0; entry < pool->next_free_entry; entry ++)
|
3029 |
|
|
{
|
3030 |
|
|
if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
|
3031 |
|
|
&& (inst.reloc.exp.X_op == O_constant)
|
3032 |
|
|
&& (pool->literals[entry].X_add_number
|
3033 |
|
|
== inst.reloc.exp.X_add_number)
|
3034 |
|
|
&& (pool->literals[entry].X_unsigned
|
3035 |
|
|
== inst.reloc.exp.X_unsigned))
|
3036 |
|
|
break;
|
3037 |
|
|
|
3038 |
|
|
if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
|
3039 |
|
|
&& (inst.reloc.exp.X_op == O_symbol)
|
3040 |
|
|
&& (pool->literals[entry].X_add_number
|
3041 |
|
|
== inst.reloc.exp.X_add_number)
|
3042 |
|
|
&& (pool->literals[entry].X_add_symbol
|
3043 |
|
|
== inst.reloc.exp.X_add_symbol)
|
3044 |
|
|
&& (pool->literals[entry].X_op_symbol
|
3045 |
|
|
== inst.reloc.exp.X_op_symbol))
|
3046 |
|
|
break;
|
3047 |
|
|
}
|
3048 |
|
|
|
3049 |
|
|
/* Do we need to create a new entry? */
|
3050 |
|
|
if (entry == pool->next_free_entry)
|
3051 |
|
|
{
|
3052 |
|
|
if (entry >= MAX_LITERAL_POOL_SIZE)
|
3053 |
|
|
{
|
3054 |
|
|
inst.error = _("literal pool overflow");
|
3055 |
|
|
return FAIL;
|
3056 |
|
|
}
|
3057 |
|
|
|
3058 |
|
|
pool->literals[entry] = inst.reloc.exp;
|
3059 |
|
|
pool->next_free_entry += 1;
|
3060 |
|
|
}
|
3061 |
|
|
|
3062 |
|
|
inst.reloc.exp.X_op = O_symbol;
|
3063 |
|
|
inst.reloc.exp.X_add_number = ((int) entry) * 4;
|
3064 |
|
|
inst.reloc.exp.X_add_symbol = pool->symbol;
|
3065 |
|
|
|
3066 |
|
|
return SUCCESS;
|
3067 |
|
|
}
|
3068 |
|
|
|
3069 |
|
|
/* Can't use symbol_new here, so have to create a symbol and then at
|
3070 |
|
|
a later date assign it a value. Thats what these functions do. */
|
3071 |
|
|
|
3072 |
|
|
static void
|
3073 |
|
|
symbol_locate (symbolS * symbolP,
|
3074 |
|
|
const char * name, /* It is copied, the caller can modify. */
|
3075 |
|
|
segT segment, /* Segment identifier (SEG_<something>). */
|
3076 |
|
|
valueT valu, /* Symbol value. */
|
3077 |
|
|
fragS * frag) /* Associated fragment. */
|
3078 |
|
|
{
|
3079 |
|
|
unsigned int name_length;
|
3080 |
|
|
char * preserved_copy_of_name;
|
3081 |
|
|
|
3082 |
|
|
name_length = strlen (name) + 1; /* +1 for \0. */
|
3083 |
|
|
obstack_grow (¬es, name, name_length);
|
3084 |
|
|
preserved_copy_of_name = (char *) obstack_finish (¬es);
|
3085 |
|
|
|
3086 |
|
|
#ifdef tc_canonicalize_symbol_name
|
3087 |
|
|
preserved_copy_of_name =
|
3088 |
|
|
tc_canonicalize_symbol_name (preserved_copy_of_name);
|
3089 |
|
|
#endif
|
3090 |
|
|
|
3091 |
|
|
S_SET_NAME (symbolP, preserved_copy_of_name);
|
3092 |
|
|
|
3093 |
|
|
S_SET_SEGMENT (symbolP, segment);
|
3094 |
|
|
S_SET_VALUE (symbolP, valu);
|
3095 |
|
|
symbol_clear_list_pointers (symbolP);
|
3096 |
|
|
|
3097 |
|
|
symbol_set_frag (symbolP, frag);
|
3098 |
|
|
|
3099 |
|
|
/* Link to end of symbol chain. */
|
3100 |
|
|
{
|
3101 |
|
|
extern int symbol_table_frozen;
|
3102 |
|
|
|
3103 |
|
|
if (symbol_table_frozen)
|
3104 |
|
|
abort ();
|
3105 |
|
|
}
|
3106 |
|
|
|
3107 |
|
|
symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
|
3108 |
|
|
|
3109 |
|
|
obj_symbol_new_hook (symbolP);
|
3110 |
|
|
|
3111 |
|
|
#ifdef tc_symbol_new_hook
|
3112 |
|
|
tc_symbol_new_hook (symbolP);
|
3113 |
|
|
#endif
|
3114 |
|
|
|
3115 |
|
|
#ifdef DEBUG_SYMS
|
3116 |
|
|
verify_symbol_chain (symbol_rootP, symbol_lastP);
|
3117 |
|
|
#endif /* DEBUG_SYMS */
|
3118 |
|
|
}
|
3119 |
|
|
|
3120 |
|
|
|
3121 |
|
|
static void
|
3122 |
|
|
s_ltorg (int ignored ATTRIBUTE_UNUSED)
|
3123 |
|
|
{
|
3124 |
|
|
unsigned int entry;
|
3125 |
|
|
literal_pool * pool;
|
3126 |
|
|
char sym_name[20];
|
3127 |
|
|
|
3128 |
|
|
pool = find_literal_pool ();
|
3129 |
|
|
if (pool == NULL
|
3130 |
|
|
|| pool->symbol == NULL
|
3131 |
|
|
|| pool->next_free_entry == 0)
|
3132 |
|
|
return;
|
3133 |
|
|
|
3134 |
|
|
mapping_state (MAP_DATA);
|
3135 |
|
|
|
3136 |
|
|
/* Align pool as you have word accesses.
|
3137 |
|
|
Only make a frag if we have to. */
|
3138 |
|
|
if (!need_pass_2)
|
3139 |
|
|
frag_align (2, 0, 0);
|
3140 |
|
|
|
3141 |
|
|
record_alignment (now_seg, 2);
|
3142 |
|
|
|
3143 |
|
|
sprintf (sym_name, "$$lit_\002%x", pool->id);
|
3144 |
|
|
|
3145 |
|
|
symbol_locate (pool->symbol, sym_name, now_seg,
|
3146 |
|
|
(valueT) frag_now_fix (), frag_now);
|
3147 |
|
|
symbol_table_insert (pool->symbol);
|
3148 |
|
|
|
3149 |
|
|
ARM_SET_THUMB (pool->symbol, thumb_mode);
|
3150 |
|
|
|
3151 |
|
|
#if defined OBJ_COFF || defined OBJ_ELF
|
3152 |
|
|
ARM_SET_INTERWORK (pool->symbol, support_interwork);
|
3153 |
|
|
#endif
|
3154 |
|
|
|
3155 |
|
|
for (entry = 0; entry < pool->next_free_entry; entry ++)
|
3156 |
|
|
/* First output the expression in the instruction to the pool. */
|
3157 |
|
|
emit_expr (&(pool->literals[entry]), 4); /* .word */
|
3158 |
|
|
|
3159 |
|
|
/* Mark the pool as empty. */
|
3160 |
|
|
pool->next_free_entry = 0;
|
3161 |
|
|
pool->symbol = NULL;
|
3162 |
|
|
}
|
3163 |
|
|
|
3164 |
|
|
#ifdef OBJ_ELF
|
3165 |
|
|
/* Forward declarations for functions below, in the MD interface
|
3166 |
|
|
section. */
|
3167 |
|
|
static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
|
3168 |
|
|
static valueT create_unwind_entry (int);
|
3169 |
|
|
static void start_unwind_section (const segT, int);
|
3170 |
|
|
static void add_unwind_opcode (valueT, int);
|
3171 |
|
|
static void flush_pending_unwind (void);
|
3172 |
|
|
|
3173 |
|
|
/* Directives: Data. */
|
3174 |
|
|
|
3175 |
|
|
static void
|
3176 |
|
|
s_arm_elf_cons (int nbytes)
|
3177 |
|
|
{
|
3178 |
|
|
expressionS exp;
|
3179 |
|
|
|
3180 |
|
|
#ifdef md_flush_pending_output
|
3181 |
|
|
md_flush_pending_output ();
|
3182 |
|
|
#endif
|
3183 |
|
|
|
3184 |
|
|
if (is_it_end_of_statement ())
|
3185 |
|
|
{
|
3186 |
|
|
demand_empty_rest_of_line ();
|
3187 |
|
|
return;
|
3188 |
|
|
}
|
3189 |
|
|
|
3190 |
|
|
#ifdef md_cons_align
|
3191 |
|
|
md_cons_align (nbytes);
|
3192 |
|
|
#endif
|
3193 |
|
|
|
3194 |
|
|
mapping_state (MAP_DATA);
|
3195 |
|
|
do
|
3196 |
|
|
{
|
3197 |
|
|
int reloc;
|
3198 |
|
|
char *base = input_line_pointer;
|
3199 |
|
|
|
3200 |
|
|
expression (& exp);
|
3201 |
|
|
|
3202 |
|
|
if (exp.X_op != O_symbol)
|
3203 |
|
|
emit_expr (&exp, (unsigned int) nbytes);
|
3204 |
|
|
else
|
3205 |
|
|
{
|
3206 |
|
|
char *before_reloc = input_line_pointer;
|
3207 |
|
|
reloc = parse_reloc (&input_line_pointer);
|
3208 |
|
|
if (reloc == -1)
|
3209 |
|
|
{
|
3210 |
|
|
as_bad (_("unrecognized relocation suffix"));
|
3211 |
|
|
ignore_rest_of_line ();
|
3212 |
|
|
return;
|
3213 |
|
|
}
|
3214 |
|
|
else if (reloc == BFD_RELOC_UNUSED)
|
3215 |
|
|
emit_expr (&exp, (unsigned int) nbytes);
|
3216 |
|
|
else
|
3217 |
|
|
{
|
3218 |
|
|
reloc_howto_type *howto = (reloc_howto_type *)
|
3219 |
|
|
bfd_reloc_type_lookup (stdoutput,
|
3220 |
|
|
(bfd_reloc_code_real_type) reloc);
|
3221 |
|
|
int size = bfd_get_reloc_size (howto);
|
3222 |
|
|
|
3223 |
|
|
if (reloc == BFD_RELOC_ARM_PLT32)
|
3224 |
|
|
{
|
3225 |
|
|
as_bad (_("(plt) is only valid on branch targets"));
|
3226 |
|
|
reloc = BFD_RELOC_UNUSED;
|
3227 |
|
|
size = 0;
|
3228 |
|
|
}
|
3229 |
|
|
|
3230 |
|
|
if (size > nbytes)
|
3231 |
|
|
as_bad (_("%s relocations do not fit in %d bytes"),
|
3232 |
|
|
howto->name, nbytes);
|
3233 |
|
|
else
|
3234 |
|
|
{
|
3235 |
|
|
/* We've parsed an expression stopping at O_symbol.
|
3236 |
|
|
But there may be more expression left now that we
|
3237 |
|
|
have parsed the relocation marker. Parse it again.
|
3238 |
|
|
XXX Surely there is a cleaner way to do this. */
|
3239 |
|
|
char *p = input_line_pointer;
|
3240 |
|
|
int offset;
|
3241 |
|
|
char *save_buf = (char *) alloca (input_line_pointer - base);
|
3242 |
|
|
memcpy (save_buf, base, input_line_pointer - base);
|
3243 |
|
|
memmove (base + (input_line_pointer - before_reloc),
|
3244 |
|
|
base, before_reloc - base);
|
3245 |
|
|
|
3246 |
|
|
input_line_pointer = base + (input_line_pointer-before_reloc);
|
3247 |
|
|
expression (&exp);
|
3248 |
|
|
memcpy (base, save_buf, p - base);
|
3249 |
|
|
|
3250 |
|
|
offset = nbytes - size;
|
3251 |
|
|
p = frag_more ((int) nbytes);
|
3252 |
|
|
fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
|
3253 |
|
|
size, &exp, 0, (enum bfd_reloc_code_real) reloc);
|
3254 |
|
|
}
|
3255 |
|
|
}
|
3256 |
|
|
}
|
3257 |
|
|
}
|
3258 |
|
|
while (*input_line_pointer++ == ',');
|
3259 |
|
|
|
3260 |
|
|
/* Put terminator back into stream. */
|
3261 |
|
|
input_line_pointer --;
|
3262 |
|
|
demand_empty_rest_of_line ();
|
3263 |
|
|
}
|
3264 |
|
|
|
3265 |
|
|
/* Emit an expression containing a 32-bit thumb instruction.
|
3266 |
|
|
Implementation based on put_thumb32_insn. */
|
3267 |
|
|
|
3268 |
|
|
static void
|
3269 |
|
|
emit_thumb32_expr (expressionS * exp)
|
3270 |
|
|
{
|
3271 |
|
|
expressionS exp_high = *exp;
|
3272 |
|
|
|
3273 |
|
|
exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
|
3274 |
|
|
emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
|
3275 |
|
|
exp->X_add_number &= 0xffff;
|
3276 |
|
|
emit_expr (exp, (unsigned int) THUMB_SIZE);
|
3277 |
|
|
}
|
3278 |
|
|
|
3279 |
|
|
/* Guess the instruction size based on the opcode. */
|
3280 |
|
|
|
3281 |
|
|
static int
|
3282 |
|
|
thumb_insn_size (int opcode)
|
3283 |
|
|
{
|
3284 |
|
|
if ((unsigned int) opcode < 0xe800u)
|
3285 |
|
|
return 2;
|
3286 |
|
|
else if ((unsigned int) opcode >= 0xe8000000u)
|
3287 |
|
|
return 4;
|
3288 |
|
|
else
|
3289 |
|
|
return 0;
|
3290 |
|
|
}
|
3291 |
|
|
|
3292 |
|
|
static bfd_boolean
|
3293 |
|
|
emit_insn (expressionS *exp, int nbytes)
|
3294 |
|
|
{
|
3295 |
|
|
int size = 0;
|
3296 |
|
|
|
3297 |
|
|
if (exp->X_op == O_constant)
|
3298 |
|
|
{
|
3299 |
|
|
size = nbytes;
|
3300 |
|
|
|
3301 |
|
|
if (size == 0)
|
3302 |
|
|
size = thumb_insn_size (exp->X_add_number);
|
3303 |
|
|
|
3304 |
|
|
if (size != 0)
|
3305 |
|
|
{
|
3306 |
|
|
if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
|
3307 |
|
|
{
|
3308 |
|
|
as_bad (_(".inst.n operand too big. "\
|
3309 |
|
|
"Use .inst.w instead"));
|
3310 |
|
|
size = 0;
|
3311 |
|
|
}
|
3312 |
|
|
else
|
3313 |
|
|
{
|
3314 |
|
|
if (now_it.state == AUTOMATIC_IT_BLOCK)
|
3315 |
|
|
set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
|
3316 |
|
|
else
|
3317 |
|
|
set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
|
3318 |
|
|
|
3319 |
|
|
if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
|
3320 |
|
|
emit_thumb32_expr (exp);
|
3321 |
|
|
else
|
3322 |
|
|
emit_expr (exp, (unsigned int) size);
|
3323 |
|
|
|
3324 |
|
|
it_fsm_post_encode ();
|
3325 |
|
|
}
|
3326 |
|
|
}
|
3327 |
|
|
else
|
3328 |
|
|
as_bad (_("cannot determine Thumb instruction size. " \
|
3329 |
|
|
"Use .inst.n/.inst.w instead"));
|
3330 |
|
|
}
|
3331 |
|
|
else
|
3332 |
|
|
as_bad (_("constant expression required"));
|
3333 |
|
|
|
3334 |
|
|
return (size != 0);
|
3335 |
|
|
}
|
3336 |
|
|
|
3337 |
|
|
/* Like s_arm_elf_cons but do not use md_cons_align and
|
3338 |
|
|
set the mapping state to MAP_ARM/MAP_THUMB. */
|
3339 |
|
|
|
3340 |
|
|
static void
|
3341 |
|
|
s_arm_elf_inst (int nbytes)
|
3342 |
|
|
{
|
3343 |
|
|
if (is_it_end_of_statement ())
|
3344 |
|
|
{
|
3345 |
|
|
demand_empty_rest_of_line ();
|
3346 |
|
|
return;
|
3347 |
|
|
}
|
3348 |
|
|
|
3349 |
|
|
/* Calling mapping_state () here will not change ARM/THUMB,
|
3350 |
|
|
but will ensure not to be in DATA state. */
|
3351 |
|
|
|
3352 |
|
|
if (thumb_mode)
|
3353 |
|
|
mapping_state (MAP_THUMB);
|
3354 |
|
|
else
|
3355 |
|
|
{
|
3356 |
|
|
if (nbytes != 0)
|
3357 |
|
|
{
|
3358 |
|
|
as_bad (_("width suffixes are invalid in ARM mode"));
|
3359 |
|
|
ignore_rest_of_line ();
|
3360 |
|
|
return;
|
3361 |
|
|
}
|
3362 |
|
|
|
3363 |
|
|
nbytes = 4;
|
3364 |
|
|
|
3365 |
|
|
mapping_state (MAP_ARM);
|
3366 |
|
|
}
|
3367 |
|
|
|
3368 |
|
|
do
|
3369 |
|
|
{
|
3370 |
|
|
expressionS exp;
|
3371 |
|
|
|
3372 |
|
|
expression (& exp);
|
3373 |
|
|
|
3374 |
|
|
if (! emit_insn (& exp, nbytes))
|
3375 |
|
|
{
|
3376 |
|
|
ignore_rest_of_line ();
|
3377 |
|
|
return;
|
3378 |
|
|
}
|
3379 |
|
|
}
|
3380 |
|
|
while (*input_line_pointer++ == ',');
|
3381 |
|
|
|
3382 |
|
|
/* Put terminator back into stream. */
|
3383 |
|
|
input_line_pointer --;
|
3384 |
|
|
demand_empty_rest_of_line ();
|
3385 |
|
|
}
|
3386 |
|
|
|
3387 |
|
|
/* Parse a .rel31 directive. */
|
3388 |
|
|
|
3389 |
|
|
static void
|
3390 |
|
|
s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
|
3391 |
|
|
{
|
3392 |
|
|
expressionS exp;
|
3393 |
|
|
char *p;
|
3394 |
|
|
valueT highbit;
|
3395 |
|
|
|
3396 |
|
|
highbit = 0;
|
3397 |
|
|
if (*input_line_pointer == '1')
|
3398 |
|
|
highbit = 0x80000000;
|
3399 |
|
|
else if (*input_line_pointer != '0')
|
3400 |
|
|
as_bad (_("expected 0 or 1"));
|
3401 |
|
|
|
3402 |
|
|
input_line_pointer++;
|
3403 |
|
|
if (*input_line_pointer != ',')
|
3404 |
|
|
as_bad (_("missing comma"));
|
3405 |
|
|
input_line_pointer++;
|
3406 |
|
|
|
3407 |
|
|
#ifdef md_flush_pending_output
|
3408 |
|
|
md_flush_pending_output ();
|
3409 |
|
|
#endif
|
3410 |
|
|
|
3411 |
|
|
#ifdef md_cons_align
|
3412 |
|
|
md_cons_align (4);
|
3413 |
|
|
#endif
|
3414 |
|
|
|
3415 |
|
|
mapping_state (MAP_DATA);
|
3416 |
|
|
|
3417 |
|
|
expression (&exp);
|
3418 |
|
|
|
3419 |
|
|
p = frag_more (4);
|
3420 |
|
|
md_number_to_chars (p, highbit, 4);
|
3421 |
|
|
fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
|
3422 |
|
|
BFD_RELOC_ARM_PREL31);
|
3423 |
|
|
|
3424 |
|
|
demand_empty_rest_of_line ();
|
3425 |
|
|
}
|
3426 |
|
|
|
3427 |
|
|
/* Directives: AEABI stack-unwind tables. */
|
3428 |
|
|
|
3429 |
|
|
/* Parse an unwind_fnstart directive. Simply records the current location. */
|
3430 |
|
|
|
3431 |
|
|
static void
|
3432 |
|
|
s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
|
3433 |
|
|
{
|
3434 |
|
|
demand_empty_rest_of_line ();
|
3435 |
|
|
if (unwind.proc_start)
|
3436 |
|
|
{
|
3437 |
|
|
as_bad (_("duplicate .fnstart directive"));
|
3438 |
|
|
return;
|
3439 |
|
|
}
|
3440 |
|
|
|
3441 |
|
|
/* Mark the start of the function. */
|
3442 |
|
|
unwind.proc_start = expr_build_dot ();
|
3443 |
|
|
|
3444 |
|
|
/* Reset the rest of the unwind info. */
|
3445 |
|
|
unwind.opcode_count = 0;
|
3446 |
|
|
unwind.table_entry = NULL;
|
3447 |
|
|
unwind.personality_routine = NULL;
|
3448 |
|
|
unwind.personality_index = -1;
|
3449 |
|
|
unwind.frame_size = 0;
|
3450 |
|
|
unwind.fp_offset = 0;
|
3451 |
|
|
unwind.fp_reg = REG_SP;
|
3452 |
|
|
unwind.fp_used = 0;
|
3453 |
|
|
unwind.sp_restored = 0;
|
3454 |
|
|
}
|
3455 |
|
|
|
3456 |
|
|
|
3457 |
|
|
/* Parse a handlerdata directive. Creates the exception handling table entry
|
3458 |
|
|
for the function. */
|
3459 |
|
|
|
3460 |
|
|
static void
|
3461 |
|
|
s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
|
3462 |
|
|
{
|
3463 |
|
|
demand_empty_rest_of_line ();
|
3464 |
|
|
if (!unwind.proc_start)
|
3465 |
|
|
as_bad (MISSING_FNSTART);
|
3466 |
|
|
|
3467 |
|
|
if (unwind.table_entry)
|
3468 |
|
|
as_bad (_("duplicate .handlerdata directive"));
|
3469 |
|
|
|
3470 |
|
|
create_unwind_entry (1);
|
3471 |
|
|
}
|
3472 |
|
|
|
3473 |
|
|
/* Parse an unwind_fnend directive. Generates the index table entry. */
|
3474 |
|
|
|
3475 |
|
|
static void
|
3476 |
|
|
s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
|
3477 |
|
|
{
|
3478 |
|
|
long where;
|
3479 |
|
|
char *ptr;
|
3480 |
|
|
valueT val;
|
3481 |
|
|
unsigned int marked_pr_dependency;
|
3482 |
|
|
|
3483 |
|
|
demand_empty_rest_of_line ();
|
3484 |
|
|
|
3485 |
|
|
if (!unwind.proc_start)
|
3486 |
|
|
{
|
3487 |
|
|
as_bad (_(".fnend directive without .fnstart"));
|
3488 |
|
|
return;
|
3489 |
|
|
}
|
3490 |
|
|
|
3491 |
|
|
/* Add eh table entry. */
|
3492 |
|
|
if (unwind.table_entry == NULL)
|
3493 |
|
|
val = create_unwind_entry (0);
|
3494 |
|
|
else
|
3495 |
|
|
val = 0;
|
3496 |
|
|
|
3497 |
|
|
/* Add index table entry. This is two words. */
|
3498 |
|
|
start_unwind_section (unwind.saved_seg, 1);
|
3499 |
|
|
frag_align (2, 0, 0);
|
3500 |
|
|
record_alignment (now_seg, 2);
|
3501 |
|
|
|
3502 |
|
|
ptr = frag_more (8);
|
3503 |
|
|
where = frag_now_fix () - 8;
|
3504 |
|
|
|
3505 |
|
|
/* Self relative offset of the function start. */
|
3506 |
|
|
fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
|
3507 |
|
|
BFD_RELOC_ARM_PREL31);
|
3508 |
|
|
|
3509 |
|
|
/* Indicate dependency on EHABI-defined personality routines to the
|
3510 |
|
|
linker, if it hasn't been done already. */
|
3511 |
|
|
marked_pr_dependency
|
3512 |
|
|
= seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
|
3513 |
|
|
if (unwind.personality_index >= 0 && unwind.personality_index < 3
|
3514 |
|
|
&& !(marked_pr_dependency & (1 << unwind.personality_index)))
|
3515 |
|
|
{
|
3516 |
|
|
static const char *const name[] =
|
3517 |
|
|
{
|
3518 |
|
|
"__aeabi_unwind_cpp_pr0",
|
3519 |
|
|
"__aeabi_unwind_cpp_pr1",
|
3520 |
|
|
"__aeabi_unwind_cpp_pr2"
|
3521 |
|
|
};
|
3522 |
|
|
symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
|
3523 |
|
|
fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
|
3524 |
|
|
seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
|
3525 |
|
|
|= 1 << unwind.personality_index;
|
3526 |
|
|
}
|
3527 |
|
|
|
3528 |
|
|
if (val)
|
3529 |
|
|
/* Inline exception table entry. */
|
3530 |
|
|
md_number_to_chars (ptr + 4, val, 4);
|
3531 |
|
|
else
|
3532 |
|
|
/* Self relative offset of the table entry. */
|
3533 |
|
|
fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
|
3534 |
|
|
BFD_RELOC_ARM_PREL31);
|
3535 |
|
|
|
3536 |
|
|
/* Restore the original section. */
|
3537 |
|
|
subseg_set (unwind.saved_seg, unwind.saved_subseg);
|
3538 |
|
|
|
3539 |
|
|
unwind.proc_start = NULL;
|
3540 |
|
|
}
|
3541 |
|
|
|
3542 |
|
|
|
3543 |
|
|
/* Parse an unwind_cantunwind directive. */
|
3544 |
|
|
|
3545 |
|
|
static void
|
3546 |
|
|
s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
|
3547 |
|
|
{
|
3548 |
|
|
demand_empty_rest_of_line ();
|
3549 |
|
|
if (!unwind.proc_start)
|
3550 |
|
|
as_bad (MISSING_FNSTART);
|
3551 |
|
|
|
3552 |
|
|
if (unwind.personality_routine || unwind.personality_index != -1)
|
3553 |
|
|
as_bad (_("personality routine specified for cantunwind frame"));
|
3554 |
|
|
|
3555 |
|
|
unwind.personality_index = -2;
|
3556 |
|
|
}
|
3557 |
|
|
|
3558 |
|
|
|
3559 |
|
|
/* Parse a personalityindex directive. */
|
3560 |
|
|
|
3561 |
|
|
static void
|
3562 |
|
|
s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
|
3563 |
|
|
{
|
3564 |
|
|
expressionS exp;
|
3565 |
|
|
|
3566 |
|
|
if (!unwind.proc_start)
|
3567 |
|
|
as_bad (MISSING_FNSTART);
|
3568 |
|
|
|
3569 |
|
|
if (unwind.personality_routine || unwind.personality_index != -1)
|
3570 |
|
|
as_bad (_("duplicate .personalityindex directive"));
|
3571 |
|
|
|
3572 |
|
|
expression (&exp);
|
3573 |
|
|
|
3574 |
|
|
if (exp.X_op != O_constant
|
3575 |
|
|
|| exp.X_add_number < 0 || exp.X_add_number > 15)
|
3576 |
|
|
{
|
3577 |
|
|
as_bad (_("bad personality routine number"));
|
3578 |
|
|
ignore_rest_of_line ();
|
3579 |
|
|
return;
|
3580 |
|
|
}
|
3581 |
|
|
|
3582 |
|
|
unwind.personality_index = exp.X_add_number;
|
3583 |
|
|
|
3584 |
|
|
demand_empty_rest_of_line ();
|
3585 |
|
|
}
|
3586 |
|
|
|
3587 |
|
|
|
3588 |
|
|
/* Parse a personality directive. */
|
3589 |
|
|
|
3590 |
|
|
static void
|
3591 |
|
|
s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
|
3592 |
|
|
{
|
3593 |
|
|
char *name, *p, c;
|
3594 |
|
|
|
3595 |
|
|
if (!unwind.proc_start)
|
3596 |
|
|
as_bad (MISSING_FNSTART);
|
3597 |
|
|
|
3598 |
|
|
if (unwind.personality_routine || unwind.personality_index != -1)
|
3599 |
|
|
as_bad (_("duplicate .personality directive"));
|
3600 |
|
|
|
3601 |
|
|
name = input_line_pointer;
|
3602 |
|
|
c = get_symbol_end ();
|
3603 |
|
|
p = input_line_pointer;
|
3604 |
|
|
unwind.personality_routine = symbol_find_or_make (name);
|
3605 |
|
|
*p = c;
|
3606 |
|
|
demand_empty_rest_of_line ();
|
3607 |
|
|
}
|
3608 |
|
|
|
3609 |
|
|
|
3610 |
|
|
/* Parse a directive saving core registers. */
|
3611 |
|
|
|
3612 |
|
|
static void
|
3613 |
|
|
s_arm_unwind_save_core (void)
|
3614 |
|
|
{
|
3615 |
|
|
valueT op;
|
3616 |
|
|
long range;
|
3617 |
|
|
int n;
|
3618 |
|
|
|
3619 |
|
|
range = parse_reg_list (&input_line_pointer);
|
3620 |
|
|
if (range == FAIL)
|
3621 |
|
|
{
|
3622 |
|
|
as_bad (_("expected register list"));
|
3623 |
|
|
ignore_rest_of_line ();
|
3624 |
|
|
return;
|
3625 |
|
|
}
|
3626 |
|
|
|
3627 |
|
|
demand_empty_rest_of_line ();
|
3628 |
|
|
|
3629 |
|
|
/* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
|
3630 |
|
|
into .unwind_save {..., sp...}. We aren't bothered about the value of
|
3631 |
|
|
ip because it is clobbered by calls. */
|
3632 |
|
|
if (unwind.sp_restored && unwind.fp_reg == 12
|
3633 |
|
|
&& (range & 0x3000) == 0x1000)
|
3634 |
|
|
{
|
3635 |
|
|
unwind.opcode_count--;
|
3636 |
|
|
unwind.sp_restored = 0;
|
3637 |
|
|
range = (range | 0x2000) & ~0x1000;
|
3638 |
|
|
unwind.pending_offset = 0;
|
3639 |
|
|
}
|
3640 |
|
|
|
3641 |
|
|
/* Pop r4-r15. */
|
3642 |
|
|
if (range & 0xfff0)
|
3643 |
|
|
{
|
3644 |
|
|
/* See if we can use the short opcodes. These pop a block of up to 8
|
3645 |
|
|
registers starting with r4, plus maybe r14. */
|
3646 |
|
|
for (n = 0; n < 8; n++)
|
3647 |
|
|
{
|
3648 |
|
|
/* Break at the first non-saved register. */
|
3649 |
|
|
if ((range & (1 << (n + 4))) == 0)
|
3650 |
|
|
break;
|
3651 |
|
|
}
|
3652 |
|
|
/* See if there are any other bits set. */
|
3653 |
|
|
if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
|
3654 |
|
|
{
|
3655 |
|
|
/* Use the long form. */
|
3656 |
|
|
op = 0x8000 | ((range >> 4) & 0xfff);
|
3657 |
|
|
add_unwind_opcode (op, 2);
|
3658 |
|
|
}
|
3659 |
|
|
else
|
3660 |
|
|
{
|
3661 |
|
|
/* Use the short form. */
|
3662 |
|
|
if (range & 0x4000)
|
3663 |
|
|
op = 0xa8; /* Pop r14. */
|
3664 |
|
|
else
|
3665 |
|
|
op = 0xa0; /* Do not pop r14. */
|
3666 |
|
|
op |= (n - 1);
|
3667 |
|
|
add_unwind_opcode (op, 1);
|
3668 |
|
|
}
|
3669 |
|
|
}
|
3670 |
|
|
|
3671 |
|
|
/* Pop r0-r3. */
|
3672 |
|
|
if (range & 0xf)
|
3673 |
|
|
{
|
3674 |
|
|
op = 0xb100 | (range & 0xf);
|
3675 |
|
|
add_unwind_opcode (op, 2);
|
3676 |
|
|
}
|
3677 |
|
|
|
3678 |
|
|
/* Record the number of bytes pushed. */
|
3679 |
|
|
for (n = 0; n < 16; n++)
|
3680 |
|
|
{
|
3681 |
|
|
if (range & (1 << n))
|
3682 |
|
|
unwind.frame_size += 4;
|
3683 |
|
|
}
|
3684 |
|
|
}
|
3685 |
|
|
|
3686 |
|
|
|
3687 |
|
|
/* Parse a directive saving FPA registers. */
|
3688 |
|
|
|
3689 |
|
|
static void
|
3690 |
|
|
s_arm_unwind_save_fpa (int reg)
|
3691 |
|
|
{
|
3692 |
|
|
expressionS exp;
|
3693 |
|
|
int num_regs;
|
3694 |
|
|
valueT op;
|
3695 |
|
|
|
3696 |
|
|
/* Get Number of registers to transfer. */
|
3697 |
|
|
if (skip_past_comma (&input_line_pointer) != FAIL)
|
3698 |
|
|
expression (&exp);
|
3699 |
|
|
else
|
3700 |
|
|
exp.X_op = O_illegal;
|
3701 |
|
|
|
3702 |
|
|
if (exp.X_op != O_constant)
|
3703 |
|
|
{
|
3704 |
|
|
as_bad (_("expected , <constant>"));
|
3705 |
|
|
ignore_rest_of_line ();
|
3706 |
|
|
return;
|
3707 |
|
|
}
|
3708 |
|
|
|
3709 |
|
|
num_regs = exp.X_add_number;
|
3710 |
|
|
|
3711 |
|
|
if (num_regs < 1 || num_regs > 4)
|
3712 |
|
|
{
|
3713 |
|
|
as_bad (_("number of registers must be in the range [1:4]"));
|
3714 |
|
|
ignore_rest_of_line ();
|
3715 |
|
|
return;
|
3716 |
|
|
}
|
3717 |
|
|
|
3718 |
|
|
demand_empty_rest_of_line ();
|
3719 |
|
|
|
3720 |
|
|
if (reg == 4)
|
3721 |
|
|
{
|
3722 |
|
|
/* Short form. */
|
3723 |
|
|
op = 0xb4 | (num_regs - 1);
|
3724 |
|
|
add_unwind_opcode (op, 1);
|
3725 |
|
|
}
|
3726 |
|
|
else
|
3727 |
|
|
{
|
3728 |
|
|
/* Long form. */
|
3729 |
|
|
op = 0xc800 | (reg << 4) | (num_regs - 1);
|
3730 |
|
|
add_unwind_opcode (op, 2);
|
3731 |
|
|
}
|
3732 |
|
|
unwind.frame_size += num_regs * 12;
|
3733 |
|
|
}
|
3734 |
|
|
|
3735 |
|
|
|
3736 |
|
|
/* Parse a directive saving VFP registers for ARMv6 and above. */
|
3737 |
|
|
|
3738 |
|
|
static void
|
3739 |
|
|
s_arm_unwind_save_vfp_armv6 (void)
|
3740 |
|
|
{
|
3741 |
|
|
int count;
|
3742 |
|
|
unsigned int start;
|
3743 |
|
|
valueT op;
|
3744 |
|
|
int num_vfpv3_regs = 0;
|
3745 |
|
|
int num_regs_below_16;
|
3746 |
|
|
|
3747 |
|
|
count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
|
3748 |
|
|
if (count == FAIL)
|
3749 |
|
|
{
|
3750 |
|
|
as_bad (_("expected register list"));
|
3751 |
|
|
ignore_rest_of_line ();
|
3752 |
|
|
return;
|
3753 |
|
|
}
|
3754 |
|
|
|
3755 |
|
|
demand_empty_rest_of_line ();
|
3756 |
|
|
|
3757 |
|
|
/* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
|
3758 |
|
|
than FSTMX/FLDMX-style ones). */
|
3759 |
|
|
|
3760 |
|
|
/* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
|
3761 |
|
|
if (start >= 16)
|
3762 |
|
|
num_vfpv3_regs = count;
|
3763 |
|
|
else if (start + count > 16)
|
3764 |
|
|
num_vfpv3_regs = start + count - 16;
|
3765 |
|
|
|
3766 |
|
|
if (num_vfpv3_regs > 0)
|
3767 |
|
|
{
|
3768 |
|
|
int start_offset = start > 16 ? start - 16 : 0;
|
3769 |
|
|
op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
|
3770 |
|
|
add_unwind_opcode (op, 2);
|
3771 |
|
|
}
|
3772 |
|
|
|
3773 |
|
|
/* Generate opcode for registers numbered in the range 0 .. 15. */
|
3774 |
|
|
num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
|
3775 |
|
|
gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
|
3776 |
|
|
if (num_regs_below_16 > 0)
|
3777 |
|
|
{
|
3778 |
|
|
op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
|
3779 |
|
|
add_unwind_opcode (op, 2);
|
3780 |
|
|
}
|
3781 |
|
|
|
3782 |
|
|
unwind.frame_size += count * 8;
|
3783 |
|
|
}
|
3784 |
|
|
|
3785 |
|
|
|
3786 |
|
|
/* Parse a directive saving VFP registers for pre-ARMv6. */
|
3787 |
|
|
|
3788 |
|
|
static void
|
3789 |
|
|
s_arm_unwind_save_vfp (void)
|
3790 |
|
|
{
|
3791 |
|
|
int count;
|
3792 |
|
|
unsigned int reg;
|
3793 |
|
|
valueT op;
|
3794 |
|
|
|
3795 |
|
|
count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
|
3796 |
|
|
if (count == FAIL)
|
3797 |
|
|
{
|
3798 |
|
|
as_bad (_("expected register list"));
|
3799 |
|
|
ignore_rest_of_line ();
|
3800 |
|
|
return;
|
3801 |
|
|
}
|
3802 |
|
|
|
3803 |
|
|
demand_empty_rest_of_line ();
|
3804 |
|
|
|
3805 |
|
|
if (reg == 8)
|
3806 |
|
|
{
|
3807 |
|
|
/* Short form. */
|
3808 |
|
|
op = 0xb8 | (count - 1);
|
3809 |
|
|
add_unwind_opcode (op, 1);
|
3810 |
|
|
}
|
3811 |
|
|
else
|
3812 |
|
|
{
|
3813 |
|
|
/* Long form. */
|
3814 |
|
|
op = 0xb300 | (reg << 4) | (count - 1);
|
3815 |
|
|
add_unwind_opcode (op, 2);
|
3816 |
|
|
}
|
3817 |
|
|
unwind.frame_size += count * 8 + 4;
|
3818 |
|
|
}
|
3819 |
|
|
|
3820 |
|
|
|
3821 |
|
|
/* Parse a directive saving iWMMXt data registers. */
|
3822 |
|
|
|
3823 |
|
|
static void
|
3824 |
|
|
s_arm_unwind_save_mmxwr (void)
|
3825 |
|
|
{
|
3826 |
|
|
int reg;
|
3827 |
|
|
int hi_reg;
|
3828 |
|
|
int i;
|
3829 |
|
|
unsigned mask = 0;
|
3830 |
|
|
valueT op;
|
3831 |
|
|
|
3832 |
|
|
if (*input_line_pointer == '{')
|
3833 |
|
|
input_line_pointer++;
|
3834 |
|
|
|
3835 |
|
|
do
|
3836 |
|
|
{
|
3837 |
|
|
reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
|
3838 |
|
|
|
3839 |
|
|
if (reg == FAIL)
|
3840 |
|
|
{
|
3841 |
|
|
as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
|
3842 |
|
|
goto error;
|
3843 |
|
|
}
|
3844 |
|
|
|
3845 |
|
|
if (mask >> reg)
|
3846 |
|
|
as_tsktsk (_("register list not in ascending order"));
|
3847 |
|
|
mask |= 1 << reg;
|
3848 |
|
|
|
3849 |
|
|
if (*input_line_pointer == '-')
|
3850 |
|
|
{
|
3851 |
|
|
input_line_pointer++;
|
3852 |
|
|
hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
|
3853 |
|
|
if (hi_reg == FAIL)
|
3854 |
|
|
{
|
3855 |
|
|
as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
|
3856 |
|
|
goto error;
|
3857 |
|
|
}
|
3858 |
|
|
else if (reg >= hi_reg)
|
3859 |
|
|
{
|
3860 |
|
|
as_bad (_("bad register range"));
|
3861 |
|
|
goto error;
|
3862 |
|
|
}
|
3863 |
|
|
for (; reg < hi_reg; reg++)
|
3864 |
|
|
mask |= 1 << reg;
|
3865 |
|
|
}
|
3866 |
|
|
}
|
3867 |
|
|
while (skip_past_comma (&input_line_pointer) != FAIL);
|
3868 |
|
|
|
3869 |
|
|
if (*input_line_pointer == '}')
|
3870 |
|
|
input_line_pointer++;
|
3871 |
|
|
|
3872 |
|
|
demand_empty_rest_of_line ();
|
3873 |
|
|
|
3874 |
|
|
/* Generate any deferred opcodes because we're going to be looking at
|
3875 |
|
|
the list. */
|
3876 |
|
|
flush_pending_unwind ();
|
3877 |
|
|
|
3878 |
|
|
for (i = 0; i < 16; i++)
|
3879 |
|
|
{
|
3880 |
|
|
if (mask & (1 << i))
|
3881 |
|
|
unwind.frame_size += 8;
|
3882 |
|
|
}
|
3883 |
|
|
|
3884 |
|
|
/* Attempt to combine with a previous opcode. We do this because gcc
|
3885 |
|
|
likes to output separate unwind directives for a single block of
|
3886 |
|
|
registers. */
|
3887 |
|
|
if (unwind.opcode_count > 0)
|
3888 |
|
|
{
|
3889 |
|
|
i = unwind.opcodes[unwind.opcode_count - 1];
|
3890 |
|
|
if ((i & 0xf8) == 0xc0)
|
3891 |
|
|
{
|
3892 |
|
|
i &= 7;
|
3893 |
|
|
/* Only merge if the blocks are contiguous. */
|
3894 |
|
|
if (i < 6)
|
3895 |
|
|
{
|
3896 |
|
|
if ((mask & 0xfe00) == (1 << 9))
|
3897 |
|
|
{
|
3898 |
|
|
mask |= ((1 << (i + 11)) - 1) & 0xfc00;
|
3899 |
|
|
unwind.opcode_count--;
|
3900 |
|
|
}
|
3901 |
|
|
}
|
3902 |
|
|
else if (i == 6 && unwind.opcode_count >= 2)
|
3903 |
|
|
{
|
3904 |
|
|
i = unwind.opcodes[unwind.opcode_count - 2];
|
3905 |
|
|
reg = i >> 4;
|
3906 |
|
|
i &= 0xf;
|
3907 |
|
|
|
3908 |
|
|
op = 0xffff << (reg - 1);
|
3909 |
|
|
if (reg > 0
|
3910 |
|
|
&& ((mask & op) == (1u << (reg - 1))))
|
3911 |
|
|
{
|
3912 |
|
|
op = (1 << (reg + i + 1)) - 1;
|
3913 |
|
|
op &= ~((1 << reg) - 1);
|
3914 |
|
|
mask |= op;
|
3915 |
|
|
unwind.opcode_count -= 2;
|
3916 |
|
|
}
|
3917 |
|
|
}
|
3918 |
|
|
}
|
3919 |
|
|
}
|
3920 |
|
|
|
3921 |
|
|
hi_reg = 15;
|
3922 |
|
|
/* We want to generate opcodes in the order the registers have been
|
3923 |
|
|
saved, ie. descending order. */
|
3924 |
|
|
for (reg = 15; reg >= -1; reg--)
|
3925 |
|
|
{
|
3926 |
|
|
/* Save registers in blocks. */
|
3927 |
|
|
if (reg < 0
|
3928 |
|
|
|| !(mask & (1 << reg)))
|
3929 |
|
|
{
|
3930 |
|
|
/* We found an unsaved reg. Generate opcodes to save the
|
3931 |
|
|
preceding block. */
|
3932 |
|
|
if (reg != hi_reg)
|
3933 |
|
|
{
|
3934 |
|
|
if (reg == 9)
|
3935 |
|
|
{
|
3936 |
|
|
/* Short form. */
|
3937 |
|
|
op = 0xc0 | (hi_reg - 10);
|
3938 |
|
|
add_unwind_opcode (op, 1);
|
3939 |
|
|
}
|
3940 |
|
|
else
|
3941 |
|
|
{
|
3942 |
|
|
/* Long form. */
|
3943 |
|
|
op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
|
3944 |
|
|
add_unwind_opcode (op, 2);
|
3945 |
|
|
}
|
3946 |
|
|
}
|
3947 |
|
|
hi_reg = reg - 1;
|
3948 |
|
|
}
|
3949 |
|
|
}
|
3950 |
|
|
|
3951 |
|
|
return;
|
3952 |
|
|
error:
|
3953 |
|
|
ignore_rest_of_line ();
|
3954 |
|
|
}
|
3955 |
|
|
|
3956 |
|
|
static void
|
3957 |
|
|
s_arm_unwind_save_mmxwcg (void)
|
3958 |
|
|
{
|
3959 |
|
|
int reg;
|
3960 |
|
|
int hi_reg;
|
3961 |
|
|
unsigned mask = 0;
|
3962 |
|
|
valueT op;
|
3963 |
|
|
|
3964 |
|
|
if (*input_line_pointer == '{')
|
3965 |
|
|
input_line_pointer++;
|
3966 |
|
|
|
3967 |
|
|
do
|
3968 |
|
|
{
|
3969 |
|
|
reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
|
3970 |
|
|
|
3971 |
|
|
if (reg == FAIL)
|
3972 |
|
|
{
|
3973 |
|
|
as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
|
3974 |
|
|
goto error;
|
3975 |
|
|
}
|
3976 |
|
|
|
3977 |
|
|
reg -= 8;
|
3978 |
|
|
if (mask >> reg)
|
3979 |
|
|
as_tsktsk (_("register list not in ascending order"));
|
3980 |
|
|
mask |= 1 << reg;
|
3981 |
|
|
|
3982 |
|
|
if (*input_line_pointer == '-')
|
3983 |
|
|
{
|
3984 |
|
|
input_line_pointer++;
|
3985 |
|
|
hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
|
3986 |
|
|
if (hi_reg == FAIL)
|
3987 |
|
|
{
|
3988 |
|
|
as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
|
3989 |
|
|
goto error;
|
3990 |
|
|
}
|
3991 |
|
|
else if (reg >= hi_reg)
|
3992 |
|
|
{
|
3993 |
|
|
as_bad (_("bad register range"));
|
3994 |
|
|
goto error;
|
3995 |
|
|
}
|
3996 |
|
|
for (; reg < hi_reg; reg++)
|
3997 |
|
|
mask |= 1 << reg;
|
3998 |
|
|
}
|
3999 |
|
|
}
|
4000 |
|
|
while (skip_past_comma (&input_line_pointer) != FAIL);
|
4001 |
|
|
|
4002 |
|
|
if (*input_line_pointer == '}')
|
4003 |
|
|
input_line_pointer++;
|
4004 |
|
|
|
4005 |
|
|
demand_empty_rest_of_line ();
|
4006 |
|
|
|
4007 |
|
|
/* Generate any deferred opcodes because we're going to be looking at
|
4008 |
|
|
the list. */
|
4009 |
|
|
flush_pending_unwind ();
|
4010 |
|
|
|
4011 |
|
|
for (reg = 0; reg < 16; reg++)
|
4012 |
|
|
{
|
4013 |
|
|
if (mask & (1 << reg))
|
4014 |
|
|
unwind.frame_size += 4;
|
4015 |
|
|
}
|
4016 |
|
|
op = 0xc700 | mask;
|
4017 |
|
|
add_unwind_opcode (op, 2);
|
4018 |
|
|
return;
|
4019 |
|
|
error:
|
4020 |
|
|
ignore_rest_of_line ();
|
4021 |
|
|
}
|
4022 |
|
|
|
4023 |
|
|
|
4024 |
|
|
/* Parse an unwind_save directive.
|
4025 |
|
|
If the argument is non-zero, this is a .vsave directive. */
|
4026 |
|
|
|
4027 |
|
|
static void
|
4028 |
|
|
s_arm_unwind_save (int arch_v6)
|
4029 |
|
|
{
|
4030 |
|
|
char *peek;
|
4031 |
|
|
struct reg_entry *reg;
|
4032 |
|
|
bfd_boolean had_brace = FALSE;
|
4033 |
|
|
|
4034 |
|
|
if (!unwind.proc_start)
|
4035 |
|
|
as_bad (MISSING_FNSTART);
|
4036 |
|
|
|
4037 |
|
|
/* Figure out what sort of save we have. */
|
4038 |
|
|
peek = input_line_pointer;
|
4039 |
|
|
|
4040 |
|
|
if (*peek == '{')
|
4041 |
|
|
{
|
4042 |
|
|
had_brace = TRUE;
|
4043 |
|
|
peek++;
|
4044 |
|
|
}
|
4045 |
|
|
|
4046 |
|
|
reg = arm_reg_parse_multi (&peek);
|
4047 |
|
|
|
4048 |
|
|
if (!reg)
|
4049 |
|
|
{
|
4050 |
|
|
as_bad (_("register expected"));
|
4051 |
|
|
ignore_rest_of_line ();
|
4052 |
|
|
return;
|
4053 |
|
|
}
|
4054 |
|
|
|
4055 |
|
|
switch (reg->type)
|
4056 |
|
|
{
|
4057 |
|
|
case REG_TYPE_FN:
|
4058 |
|
|
if (had_brace)
|
4059 |
|
|
{
|
4060 |
|
|
as_bad (_("FPA .unwind_save does not take a register list"));
|
4061 |
|
|
ignore_rest_of_line ();
|
4062 |
|
|
return;
|
4063 |
|
|
}
|
4064 |
|
|
input_line_pointer = peek;
|
4065 |
|
|
s_arm_unwind_save_fpa (reg->number);
|
4066 |
|
|
return;
|
4067 |
|
|
|
4068 |
|
|
case REG_TYPE_RN: s_arm_unwind_save_core (); return;
|
4069 |
|
|
case REG_TYPE_VFD:
|
4070 |
|
|
if (arch_v6)
|
4071 |
|
|
s_arm_unwind_save_vfp_armv6 ();
|
4072 |
|
|
else
|
4073 |
|
|
s_arm_unwind_save_vfp ();
|
4074 |
|
|
return;
|
4075 |
|
|
case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
|
4076 |
|
|
case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
|
4077 |
|
|
|
4078 |
|
|
default:
|
4079 |
|
|
as_bad (_(".unwind_save does not support this kind of register"));
|
4080 |
|
|
ignore_rest_of_line ();
|
4081 |
|
|
}
|
4082 |
|
|
}
|
4083 |
|
|
|
4084 |
|
|
|
4085 |
|
|
/* Parse an unwind_movsp directive. */
|
4086 |
|
|
|
4087 |
|
|
static void
|
4088 |
|
|
s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
|
4089 |
|
|
{
|
4090 |
|
|
int reg;
|
4091 |
|
|
valueT op;
|
4092 |
|
|
int offset;
|
4093 |
|
|
|
4094 |
|
|
if (!unwind.proc_start)
|
4095 |
|
|
as_bad (MISSING_FNSTART);
|
4096 |
|
|
|
4097 |
|
|
reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
|
4098 |
|
|
if (reg == FAIL)
|
4099 |
|
|
{
|
4100 |
|
|
as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
|
4101 |
|
|
ignore_rest_of_line ();
|
4102 |
|
|
return;
|
4103 |
|
|
}
|
4104 |
|
|
|
4105 |
|
|
/* Optional constant. */
|
4106 |
|
|
if (skip_past_comma (&input_line_pointer) != FAIL)
|
4107 |
|
|
{
|
4108 |
|
|
if (immediate_for_directive (&offset) == FAIL)
|
4109 |
|
|
return;
|
4110 |
|
|
}
|
4111 |
|
|
else
|
4112 |
|
|
offset = 0;
|
4113 |
|
|
|
4114 |
|
|
demand_empty_rest_of_line ();
|
4115 |
|
|
|
4116 |
|
|
if (reg == REG_SP || reg == REG_PC)
|
4117 |
|
|
{
|
4118 |
|
|
as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
|
4119 |
|
|
return;
|
4120 |
|
|
}
|
4121 |
|
|
|
4122 |
|
|
if (unwind.fp_reg != REG_SP)
|
4123 |
|
|
as_bad (_("unexpected .unwind_movsp directive"));
|
4124 |
|
|
|
4125 |
|
|
/* Generate opcode to restore the value. */
|
4126 |
|
|
op = 0x90 | reg;
|
4127 |
|
|
add_unwind_opcode (op, 1);
|
4128 |
|
|
|
4129 |
|
|
/* Record the information for later. */
|
4130 |
|
|
unwind.fp_reg = reg;
|
4131 |
|
|
unwind.fp_offset = unwind.frame_size - offset;
|
4132 |
|
|
unwind.sp_restored = 1;
|
4133 |
|
|
}
|
4134 |
|
|
|
4135 |
|
|
/* Parse an unwind_pad directive. */
|
4136 |
|
|
|
4137 |
|
|
static void
|
4138 |
|
|
s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
|
4139 |
|
|
{
|
4140 |
|
|
int offset;
|
4141 |
|
|
|
4142 |
|
|
if (!unwind.proc_start)
|
4143 |
|
|
as_bad (MISSING_FNSTART);
|
4144 |
|
|
|
4145 |
|
|
if (immediate_for_directive (&offset) == FAIL)
|
4146 |
|
|
return;
|
4147 |
|
|
|
4148 |
|
|
if (offset & 3)
|
4149 |
|
|
{
|
4150 |
|
|
as_bad (_("stack increment must be multiple of 4"));
|
4151 |
|
|
ignore_rest_of_line ();
|
4152 |
|
|
return;
|
4153 |
|
|
}
|
4154 |
|
|
|
4155 |
|
|
/* Don't generate any opcodes, just record the details for later. */
|
4156 |
|
|
unwind.frame_size += offset;
|
4157 |
|
|
unwind.pending_offset += offset;
|
4158 |
|
|
|
4159 |
|
|
demand_empty_rest_of_line ();
|
4160 |
|
|
}
|
4161 |
|
|
|
4162 |
|
|
/* Parse an unwind_setfp directive. */
|
4163 |
|
|
|
4164 |
|
|
static void
|
4165 |
|
|
s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
|
4166 |
|
|
{
|
4167 |
|
|
int sp_reg;
|
4168 |
|
|
int fp_reg;
|
4169 |
|
|
int offset;
|
4170 |
|
|
|
4171 |
|
|
if (!unwind.proc_start)
|
4172 |
|
|
as_bad (MISSING_FNSTART);
|
4173 |
|
|
|
4174 |
|
|
fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
|
4175 |
|
|
if (skip_past_comma (&input_line_pointer) == FAIL)
|
4176 |
|
|
sp_reg = FAIL;
|
4177 |
|
|
else
|
4178 |
|
|
sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
|
4179 |
|
|
|
4180 |
|
|
if (fp_reg == FAIL || sp_reg == FAIL)
|
4181 |
|
|
{
|
4182 |
|
|
as_bad (_("expected <reg>, <reg>"));
|
4183 |
|
|
ignore_rest_of_line ();
|
4184 |
|
|
return;
|
4185 |
|
|
}
|
4186 |
|
|
|
4187 |
|
|
/* Optional constant. */
|
4188 |
|
|
if (skip_past_comma (&input_line_pointer) != FAIL)
|
4189 |
|
|
{
|
4190 |
|
|
if (immediate_for_directive (&offset) == FAIL)
|
4191 |
|
|
return;
|
4192 |
|
|
}
|
4193 |
|
|
else
|
4194 |
|
|
offset = 0;
|
4195 |
|
|
|
4196 |
|
|
demand_empty_rest_of_line ();
|
4197 |
|
|
|
4198 |
|
|
if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
|
4199 |
|
|
{
|
4200 |
|
|
as_bad (_("register must be either sp or set by a previous"
|
4201 |
|
|
"unwind_movsp directive"));
|
4202 |
|
|
return;
|
4203 |
|
|
}
|
4204 |
|
|
|
4205 |
|
|
/* Don't generate any opcodes, just record the information for later. */
|
4206 |
|
|
unwind.fp_reg = fp_reg;
|
4207 |
|
|
unwind.fp_used = 1;
|
4208 |
|
|
if (sp_reg == REG_SP)
|
4209 |
|
|
unwind.fp_offset = unwind.frame_size - offset;
|
4210 |
|
|
else
|
4211 |
|
|
unwind.fp_offset -= offset;
|
4212 |
|
|
}
|
4213 |
|
|
|
4214 |
|
|
/* Parse an unwind_raw directive. */
|
4215 |
|
|
|
4216 |
|
|
static void
|
4217 |
|
|
s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
|
4218 |
|
|
{
|
4219 |
|
|
expressionS exp;
|
4220 |
|
|
/* This is an arbitrary limit. */
|
4221 |
|
|
unsigned char op[16];
|
4222 |
|
|
int count;
|
4223 |
|
|
|
4224 |
|
|
if (!unwind.proc_start)
|
4225 |
|
|
as_bad (MISSING_FNSTART);
|
4226 |
|
|
|
4227 |
|
|
expression (&exp);
|
4228 |
|
|
if (exp.X_op == O_constant
|
4229 |
|
|
&& skip_past_comma (&input_line_pointer) != FAIL)
|
4230 |
|
|
{
|
4231 |
|
|
unwind.frame_size += exp.X_add_number;
|
4232 |
|
|
expression (&exp);
|
4233 |
|
|
}
|
4234 |
|
|
else
|
4235 |
|
|
exp.X_op = O_illegal;
|
4236 |
|
|
|
4237 |
|
|
if (exp.X_op != O_constant)
|
4238 |
|
|
{
|
4239 |
|
|
as_bad (_("expected <offset>, <opcode>"));
|
4240 |
|
|
ignore_rest_of_line ();
|
4241 |
|
|
return;
|
4242 |
|
|
}
|
4243 |
|
|
|
4244 |
|
|
count = 0;
|
4245 |
|
|
|
4246 |
|
|
/* Parse the opcode. */
|
4247 |
|
|
for (;;)
|
4248 |
|
|
{
|
4249 |
|
|
if (count >= 16)
|
4250 |
|
|
{
|
4251 |
|
|
as_bad (_("unwind opcode too long"));
|
4252 |
|
|
ignore_rest_of_line ();
|
4253 |
|
|
}
|
4254 |
|
|
if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
|
4255 |
|
|
{
|
4256 |
|
|
as_bad (_("invalid unwind opcode"));
|
4257 |
|
|
ignore_rest_of_line ();
|
4258 |
|
|
return;
|
4259 |
|
|
}
|
4260 |
|
|
op[count++] = exp.X_add_number;
|
4261 |
|
|
|
4262 |
|
|
/* Parse the next byte. */
|
4263 |
|
|
if (skip_past_comma (&input_line_pointer) == FAIL)
|
4264 |
|
|
break;
|
4265 |
|
|
|
4266 |
|
|
expression (&exp);
|
4267 |
|
|
}
|
4268 |
|
|
|
4269 |
|
|
/* Add the opcode bytes in reverse order. */
|
4270 |
|
|
while (count--)
|
4271 |
|
|
add_unwind_opcode (op[count], 1);
|
4272 |
|
|
|
4273 |
|
|
demand_empty_rest_of_line ();
|
4274 |
|
|
}
|
4275 |
|
|
|
4276 |
|
|
|
4277 |
|
|
/* Parse a .eabi_attribute directive. */
|
4278 |
|
|
|
4279 |
|
|
static void
|
4280 |
|
|
s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
|
4281 |
|
|
{
|
4282 |
|
|
int tag = s_vendor_attribute (OBJ_ATTR_PROC);
|
4283 |
|
|
|
4284 |
|
|
if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
|
4285 |
|
|
attributes_set_explicitly[tag] = 1;
|
4286 |
|
|
}
|
4287 |
|
|
|
4288 |
|
|
/* Emit a tls fix for the symbol. */
|
4289 |
|
|
|
4290 |
|
|
static void
|
4291 |
|
|
s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
|
4292 |
|
|
{
|
4293 |
|
|
char *p;
|
4294 |
|
|
expressionS exp;
|
4295 |
|
|
#ifdef md_flush_pending_output
|
4296 |
|
|
md_flush_pending_output ();
|
4297 |
|
|
#endif
|
4298 |
|
|
|
4299 |
|
|
#ifdef md_cons_align
|
4300 |
|
|
md_cons_align (4);
|
4301 |
|
|
#endif
|
4302 |
|
|
|
4303 |
|
|
/* Since we're just labelling the code, there's no need to define a
|
4304 |
|
|
mapping symbol. */
|
4305 |
|
|
expression (&exp);
|
4306 |
|
|
p = obstack_next_free (&frchain_now->frch_obstack);
|
4307 |
|
|
fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
|
4308 |
|
|
thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
|
4309 |
|
|
: BFD_RELOC_ARM_TLS_DESCSEQ);
|
4310 |
|
|
}
|
4311 |
|
|
#endif /* OBJ_ELF */
|
4312 |
|
|
|
4313 |
|
|
static void s_arm_arch (int);
|
4314 |
|
|
static void s_arm_object_arch (int);
|
4315 |
|
|
static void s_arm_cpu (int);
|
4316 |
|
|
static void s_arm_fpu (int);
|
4317 |
|
|
static void s_arm_arch_extension (int);
|
4318 |
|
|
|
4319 |
|
|
#ifdef TE_PE
|
4320 |
|
|
|
4321 |
|
|
static void
|
4322 |
|
|
pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
|
4323 |
|
|
{
|
4324 |
|
|
expressionS exp;
|
4325 |
|
|
|
4326 |
|
|
do
|
4327 |
|
|
{
|
4328 |
|
|
expression (&exp);
|
4329 |
|
|
if (exp.X_op == O_symbol)
|
4330 |
|
|
exp.X_op = O_secrel;
|
4331 |
|
|
|
4332 |
|
|
emit_expr (&exp, 4);
|
4333 |
|
|
}
|
4334 |
|
|
while (*input_line_pointer++ == ',');
|
4335 |
|
|
|
4336 |
|
|
input_line_pointer--;
|
4337 |
|
|
demand_empty_rest_of_line ();
|
4338 |
|
|
}
|
4339 |
|
|
#endif /* TE_PE */
|
4340 |
|
|
|
4341 |
|
|
/* This table describes all the machine specific pseudo-ops the assembler
|
4342 |
|
|
has to support. The fields are:
|
4343 |
|
|
pseudo-op name without dot
|
4344 |
|
|
function to call to execute this pseudo-op
|
4345 |
|
|
Integer arg to pass to the function. */
|
4346 |
|
|
|
4347 |
|
|
const pseudo_typeS md_pseudo_table[] =
|
4348 |
|
|
{
|
4349 |
|
|
/* Never called because '.req' does not start a line. */
|
4350 |
|
|
{ "req", s_req, 0 },
|
4351 |
|
|
/* Following two are likewise never called. */
|
4352 |
|
|
{ "dn", s_dn, 0 },
|
4353 |
|
|
{ "qn", s_qn, 0 },
|
4354 |
|
|
{ "unreq", s_unreq, 0 },
|
4355 |
|
|
{ "bss", s_bss, 0 },
|
4356 |
|
|
{ "align", s_align, 0 },
|
4357 |
|
|
{ "arm", s_arm, 0 },
|
4358 |
|
|
{ "thumb", s_thumb, 0 },
|
4359 |
|
|
{ "code", s_code, 0 },
|
4360 |
|
|
{ "force_thumb", s_force_thumb, 0 },
|
4361 |
|
|
{ "thumb_func", s_thumb_func, 0 },
|
4362 |
|
|
{ "thumb_set", s_thumb_set, 0 },
|
4363 |
|
|
{ "even", s_even, 0 },
|
4364 |
|
|
{ "ltorg", s_ltorg, 0 },
|
4365 |
|
|
{ "pool", s_ltorg, 0 },
|
4366 |
|
|
{ "syntax", s_syntax, 0 },
|
4367 |
|
|
{ "cpu", s_arm_cpu, 0 },
|
4368 |
|
|
{ "arch", s_arm_arch, 0 },
|
4369 |
|
|
{ "object_arch", s_arm_object_arch, 0 },
|
4370 |
|
|
{ "fpu", s_arm_fpu, 0 },
|
4371 |
|
|
{ "arch_extension", s_arm_arch_extension, 0 },
|
4372 |
|
|
#ifdef OBJ_ELF
|
4373 |
|
|
{ "word", s_arm_elf_cons, 4 },
|
4374 |
|
|
{ "long", s_arm_elf_cons, 4 },
|
4375 |
|
|
{ "inst.n", s_arm_elf_inst, 2 },
|
4376 |
|
|
{ "inst.w", s_arm_elf_inst, 4 },
|
4377 |
|
|
{ "inst", s_arm_elf_inst, 0 },
|
4378 |
|
|
{ "rel31", s_arm_rel31, 0 },
|
4379 |
|
|
{ "fnstart", s_arm_unwind_fnstart, 0 },
|
4380 |
|
|
{ "fnend", s_arm_unwind_fnend, 0 },
|
4381 |
|
|
{ "cantunwind", s_arm_unwind_cantunwind, 0 },
|
4382 |
|
|
{ "personality", s_arm_unwind_personality, 0 },
|
4383 |
|
|
{ "personalityindex", s_arm_unwind_personalityindex, 0 },
|
4384 |
|
|
{ "handlerdata", s_arm_unwind_handlerdata, 0 },
|
4385 |
|
|
{ "save", s_arm_unwind_save, 0 },
|
4386 |
|
|
{ "vsave", s_arm_unwind_save, 1 },
|
4387 |
|
|
{ "movsp", s_arm_unwind_movsp, 0 },
|
4388 |
|
|
{ "pad", s_arm_unwind_pad, 0 },
|
4389 |
|
|
{ "setfp", s_arm_unwind_setfp, 0 },
|
4390 |
|
|
{ "unwind_raw", s_arm_unwind_raw, 0 },
|
4391 |
|
|
{ "eabi_attribute", s_arm_eabi_attribute, 0 },
|
4392 |
|
|
{ "tlsdescseq", s_arm_tls_descseq, 0 },
|
4393 |
|
|
#else
|
4394 |
|
|
{ "word", cons, 4},
|
4395 |
|
|
|
4396 |
|
|
/* These are used for dwarf. */
|
4397 |
|
|
{"2byte", cons, 2},
|
4398 |
|
|
{"4byte", cons, 4},
|
4399 |
|
|
{"8byte", cons, 8},
|
4400 |
|
|
/* These are used for dwarf2. */
|
4401 |
|
|
{ "file", (void (*) (int)) dwarf2_directive_file, 0 },
|
4402 |
|
|
{ "loc", dwarf2_directive_loc, 0 },
|
4403 |
|
|
{ "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
|
4404 |
|
|
#endif
|
4405 |
|
|
{ "extend", float_cons, 'x' },
|
4406 |
|
|
{ "ldouble", float_cons, 'x' },
|
4407 |
|
|
{ "packed", float_cons, 'p' },
|
4408 |
|
|
#ifdef TE_PE
|
4409 |
|
|
{"secrel32", pe_directive_secrel, 0},
|
4410 |
|
|
#endif
|
4411 |
|
|
{ 0, 0, 0 }
|
4412 |
|
|
};
|
4413 |
|
|
|
4414 |
|
|
/* Parser functions used exclusively in instruction operands. */
|
4415 |
|
|
|
4416 |
|
|
/* Generic immediate-value read function for use in insn parsing.
|
4417 |
|
|
STR points to the beginning of the immediate (the leading #);
|
4418 |
|
|
VAL receives the value; if the value is outside [MIN, MAX]
|
4419 |
|
|
issue an error. PREFIX_OPT is true if the immediate prefix is
|
4420 |
|
|
optional. */
|
4421 |
|
|
|
4422 |
|
|
static int
|
4423 |
|
|
parse_immediate (char **str, int *val, int min, int max,
|
4424 |
|
|
bfd_boolean prefix_opt)
|
4425 |
|
|
{
|
4426 |
|
|
expressionS exp;
|
4427 |
|
|
my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
|
4428 |
|
|
if (exp.X_op != O_constant)
|
4429 |
|
|
{
|
4430 |
|
|
inst.error = _("constant expression required");
|
4431 |
|
|
return FAIL;
|
4432 |
|
|
}
|
4433 |
|
|
|
4434 |
|
|
if (exp.X_add_number < min || exp.X_add_number > max)
|
4435 |
|
|
{
|
4436 |
|
|
inst.error = _("immediate value out of range");
|
4437 |
|
|
return FAIL;
|
4438 |
|
|
}
|
4439 |
|
|
|
4440 |
|
|
*val = exp.X_add_number;
|
4441 |
|
|
return SUCCESS;
|
4442 |
|
|
}
|
4443 |
|
|
|
4444 |
|
|
/* Less-generic immediate-value read function with the possibility of loading a
|
4445 |
|
|
big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
|
4446 |
|
|
instructions. Puts the result directly in inst.operands[i]. */
|
4447 |
|
|
|
4448 |
|
|
static int
|
4449 |
|
|
parse_big_immediate (char **str, int i)
|
4450 |
|
|
{
|
4451 |
|
|
expressionS exp;
|
4452 |
|
|
char *ptr = *str;
|
4453 |
|
|
|
4454 |
|
|
my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
|
4455 |
|
|
|
4456 |
|
|
if (exp.X_op == O_constant)
|
4457 |
|
|
{
|
4458 |
|
|
inst.operands[i].imm = exp.X_add_number & 0xffffffff;
|
4459 |
|
|
/* If we're on a 64-bit host, then a 64-bit number can be returned using
|
4460 |
|
|
O_constant. We have to be careful not to break compilation for
|
4461 |
|
|
32-bit X_add_number, though. */
|
4462 |
|
|
if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
|
4463 |
|
|
{
|
4464 |
|
|
/* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
|
4465 |
|
|
inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
|
4466 |
|
|
inst.operands[i].regisimm = 1;
|
4467 |
|
|
}
|
4468 |
|
|
}
|
4469 |
|
|
else if (exp.X_op == O_big
|
4470 |
|
|
&& LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
|
4471 |
|
|
{
|
4472 |
|
|
unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
|
4473 |
|
|
|
4474 |
|
|
/* Bignums have their least significant bits in
|
4475 |
|
|
generic_bignum[0]. Make sure we put 32 bits in imm and
|
4476 |
|
|
32 bits in reg, in a (hopefully) portable way. */
|
4477 |
|
|
gas_assert (parts != 0);
|
4478 |
|
|
|
4479 |
|
|
/* Make sure that the number is not too big.
|
4480 |
|
|
PR 11972: Bignums can now be sign-extended to the
|
4481 |
|
|
size of a .octa so check that the out of range bits
|
4482 |
|
|
are all zero or all one. */
|
4483 |
|
|
if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
|
4484 |
|
|
{
|
4485 |
|
|
LITTLENUM_TYPE m = -1;
|
4486 |
|
|
|
4487 |
|
|
if (generic_bignum[parts * 2] != 0
|
4488 |
|
|
&& generic_bignum[parts * 2] != m)
|
4489 |
|
|
return FAIL;
|
4490 |
|
|
|
4491 |
|
|
for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
|
4492 |
|
|
if (generic_bignum[j] != generic_bignum[j-1])
|
4493 |
|
|
return FAIL;
|
4494 |
|
|
}
|
4495 |
|
|
|
4496 |
|
|
inst.operands[i].imm = 0;
|
4497 |
|
|
for (j = 0; j < parts; j++, idx++)
|
4498 |
|
|
inst.operands[i].imm |= generic_bignum[idx]
|
4499 |
|
|
<< (LITTLENUM_NUMBER_OF_BITS * j);
|
4500 |
|
|
inst.operands[i].reg = 0;
|
4501 |
|
|
for (j = 0; j < parts; j++, idx++)
|
4502 |
|
|
inst.operands[i].reg |= generic_bignum[idx]
|
4503 |
|
|
<< (LITTLENUM_NUMBER_OF_BITS * j);
|
4504 |
|
|
inst.operands[i].regisimm = 1;
|
4505 |
|
|
}
|
4506 |
|
|
else
|
4507 |
|
|
return FAIL;
|
4508 |
|
|
|
4509 |
|
|
*str = ptr;
|
4510 |
|
|
|
4511 |
|
|
return SUCCESS;
|
4512 |
|
|
}
|
4513 |
|
|
|
4514 |
|
|
/* Returns the pseudo-register number of an FPA immediate constant,
|
4515 |
|
|
or FAIL if there isn't a valid constant here. */
|
4516 |
|
|
|
4517 |
|
|
static int
|
4518 |
|
|
parse_fpa_immediate (char ** str)
|
4519 |
|
|
{
|
4520 |
|
|
LITTLENUM_TYPE words[MAX_LITTLENUMS];
|
4521 |
|
|
char * save_in;
|
4522 |
|
|
expressionS exp;
|
4523 |
|
|
int i;
|
4524 |
|
|
int j;
|
4525 |
|
|
|
4526 |
|
|
/* First try and match exact strings, this is to guarantee
|
4527 |
|
|
that some formats will work even for cross assembly. */
|
4528 |
|
|
|
4529 |
|
|
for (i = 0; fp_const[i]; i++)
|
4530 |
|
|
{
|
4531 |
|
|
if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
|
4532 |
|
|
{
|
4533 |
|
|
char *start = *str;
|
4534 |
|
|
|
4535 |
|
|
*str += strlen (fp_const[i]);
|
4536 |
|
|
if (is_end_of_line[(unsigned char) **str])
|
4537 |
|
|
return i + 8;
|
4538 |
|
|
*str = start;
|
4539 |
|
|
}
|
4540 |
|
|
}
|
4541 |
|
|
|
4542 |
|
|
/* Just because we didn't get a match doesn't mean that the constant
|
4543 |
|
|
isn't valid, just that it is in a format that we don't
|
4544 |
|
|
automatically recognize. Try parsing it with the standard
|
4545 |
|
|
expression routines. */
|
4546 |
|
|
|
4547 |
|
|
memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
|
4548 |
|
|
|
4549 |
|
|
/* Look for a raw floating point number. */
|
4550 |
|
|
if ((save_in = atof_ieee (*str, 'x', words)) != NULL
|
4551 |
|
|
&& is_end_of_line[(unsigned char) *save_in])
|
4552 |
|
|
{
|
4553 |
|
|
for (i = 0; i < NUM_FLOAT_VALS; i++)
|
4554 |
|
|
{
|
4555 |
|
|
for (j = 0; j < MAX_LITTLENUMS; j++)
|
4556 |
|
|
{
|
4557 |
|
|
if (words[j] != fp_values[i][j])
|
4558 |
|
|
break;
|
4559 |
|
|
}
|
4560 |
|
|
|
4561 |
|
|
if (j == MAX_LITTLENUMS)
|
4562 |
|
|
{
|
4563 |
|
|
*str = save_in;
|
4564 |
|
|
return i + 8;
|
4565 |
|
|
}
|
4566 |
|
|
}
|
4567 |
|
|
}
|
4568 |
|
|
|
4569 |
|
|
/* Try and parse a more complex expression, this will probably fail
|
4570 |
|
|
unless the code uses a floating point prefix (eg "0f"). */
|
4571 |
|
|
save_in = input_line_pointer;
|
4572 |
|
|
input_line_pointer = *str;
|
4573 |
|
|
if (expression (&exp) == absolute_section
|
4574 |
|
|
&& exp.X_op == O_big
|
4575 |
|
|
&& exp.X_add_number < 0)
|
4576 |
|
|
{
|
4577 |
|
|
/* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
|
4578 |
|
|
Ditto for 15. */
|
4579 |
|
|
if (gen_to_words (words, 5, (long) 15) == 0)
|
4580 |
|
|
{
|
4581 |
|
|
for (i = 0; i < NUM_FLOAT_VALS; i++)
|
4582 |
|
|
{
|
4583 |
|
|
for (j = 0; j < MAX_LITTLENUMS; j++)
|
4584 |
|
|
{
|
4585 |
|
|
if (words[j] != fp_values[i][j])
|
4586 |
|
|
break;
|
4587 |
|
|
}
|
4588 |
|
|
|
4589 |
|
|
if (j == MAX_LITTLENUMS)
|
4590 |
|
|
{
|
4591 |
|
|
*str = input_line_pointer;
|
4592 |
|
|
input_line_pointer = save_in;
|
4593 |
|
|
return i + 8;
|
4594 |
|
|
}
|
4595 |
|
|
}
|
4596 |
|
|
}
|
4597 |
|
|
}
|
4598 |
|
|
|
4599 |
|
|
*str = input_line_pointer;
|
4600 |
|
|
input_line_pointer = save_in;
|
4601 |
|
|
inst.error = _("invalid FPA immediate expression");
|
4602 |
|
|
return FAIL;
|
4603 |
|
|
}
|
4604 |
|
|
|
4605 |
|
|
/* Returns 1 if a number has "quarter-precision" float format
|
4606 |
|
|
0baBbbbbbc defgh000 00000000 00000000. */
|
4607 |
|
|
|
4608 |
|
|
static int
|
4609 |
|
|
is_quarter_float (unsigned imm)
|
4610 |
|
|
{
|
4611 |
|
|
int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
|
4612 |
|
|
return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
|
4613 |
|
|
}
|
4614 |
|
|
|
4615 |
|
|
/* Parse an 8-bit "quarter-precision" floating point number of the form:
|
4616 |
|
|
0baBbbbbbc defgh000 00000000 00000000.
|
4617 |
|
|
The zero and minus-zero cases need special handling, since they can't be
|
4618 |
|
|
encoded in the "quarter-precision" float format, but can nonetheless be
|
4619 |
|
|
loaded as integer constants. */
|
4620 |
|
|
|
4621 |
|
|
static unsigned
|
4622 |
|
|
parse_qfloat_immediate (char **ccp, int *immed)
|
4623 |
|
|
{
|
4624 |
|
|
char *str = *ccp;
|
4625 |
|
|
char *fpnum;
|
4626 |
|
|
LITTLENUM_TYPE words[MAX_LITTLENUMS];
|
4627 |
|
|
int found_fpchar = 0;
|
4628 |
|
|
|
4629 |
|
|
skip_past_char (&str, '#');
|
4630 |
|
|
|
4631 |
|
|
/* We must not accidentally parse an integer as a floating-point number. Make
|
4632 |
|
|
sure that the value we parse is not an integer by checking for special
|
4633 |
|
|
characters '.' or 'e'.
|
4634 |
|
|
FIXME: This is a horrible hack, but doing better is tricky because type
|
4635 |
|
|
information isn't in a very usable state at parse time. */
|
4636 |
|
|
fpnum = str;
|
4637 |
|
|
skip_whitespace (fpnum);
|
4638 |
|
|
|
4639 |
|
|
if (strncmp (fpnum, "0x", 2) == 0)
|
4640 |
|
|
return FAIL;
|
4641 |
|
|
else
|
4642 |
|
|
{
|
4643 |
|
|
for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
|
4644 |
|
|
if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
|
4645 |
|
|
{
|
4646 |
|
|
found_fpchar = 1;
|
4647 |
|
|
break;
|
4648 |
|
|
}
|
4649 |
|
|
|
4650 |
|
|
if (!found_fpchar)
|
4651 |
|
|
return FAIL;
|
4652 |
|
|
}
|
4653 |
|
|
|
4654 |
|
|
if ((str = atof_ieee (str, 's', words)) != NULL)
|
4655 |
|
|
{
|
4656 |
|
|
unsigned fpword = 0;
|
4657 |
|
|
int i;
|
4658 |
|
|
|
4659 |
|
|
/* Our FP word must be 32 bits (single-precision FP). */
|
4660 |
|
|
for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
|
4661 |
|
|
{
|
4662 |
|
|
fpword <<= LITTLENUM_NUMBER_OF_BITS;
|
4663 |
|
|
fpword |= words[i];
|
4664 |
|
|
}
|
4665 |
|
|
|
4666 |
|
|
if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
|
4667 |
|
|
*immed = fpword;
|
4668 |
|
|
else
|
4669 |
|
|
return FAIL;
|
4670 |
|
|
|
4671 |
|
|
*ccp = str;
|
4672 |
|
|
|
4673 |
|
|
return SUCCESS;
|
4674 |
|
|
}
|
4675 |
|
|
|
4676 |
|
|
return FAIL;
|
4677 |
|
|
}
|
4678 |
|
|
|
4679 |
|
|
/* Shift operands. */
|
4680 |
|
|
enum shift_kind
|
4681 |
|
|
{
|
4682 |
|
|
SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
|
4683 |
|
|
};
|
4684 |
|
|
|
4685 |
|
|
struct asm_shift_name
|
4686 |
|
|
{
|
4687 |
|
|
const char *name;
|
4688 |
|
|
enum shift_kind kind;
|
4689 |
|
|
};
|
4690 |
|
|
|
4691 |
|
|
/* Third argument to parse_shift. */
|
4692 |
|
|
enum parse_shift_mode
|
4693 |
|
|
{
|
4694 |
|
|
NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
|
4695 |
|
|
SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
|
4696 |
|
|
SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
|
4697 |
|
|
SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
|
4698 |
|
|
SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
|
4699 |
|
|
};
|
4700 |
|
|
|
4701 |
|
|
/* Parse a <shift> specifier on an ARM data processing instruction.
|
4702 |
|
|
This has three forms:
|
4703 |
|
|
|
4704 |
|
|
(LSL|LSR|ASL|ASR|ROR) Rs
|
4705 |
|
|
(LSL|LSR|ASL|ASR|ROR) #imm
|
4706 |
|
|
RRX
|
4707 |
|
|
|
4708 |
|
|
Note that ASL is assimilated to LSL in the instruction encoding, and
|
4709 |
|
|
RRX to ROR #0 (which cannot be written as such). */
|
4710 |
|
|
|
4711 |
|
|
static int
|
4712 |
|
|
parse_shift (char **str, int i, enum parse_shift_mode mode)
|
4713 |
|
|
{
|
4714 |
|
|
const struct asm_shift_name *shift_name;
|
4715 |
|
|
enum shift_kind shift;
|
4716 |
|
|
char *s = *str;
|
4717 |
|
|
char *p = s;
|
4718 |
|
|
int reg;
|
4719 |
|
|
|
4720 |
|
|
for (p = *str; ISALPHA (*p); p++)
|
4721 |
|
|
;
|
4722 |
|
|
|
4723 |
|
|
if (p == *str)
|
4724 |
|
|
{
|
4725 |
|
|
inst.error = _("shift expression expected");
|
4726 |
|
|
return FAIL;
|
4727 |
|
|
}
|
4728 |
|
|
|
4729 |
|
|
shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
|
4730 |
|
|
p - *str);
|
4731 |
|
|
|
4732 |
|
|
if (shift_name == NULL)
|
4733 |
|
|
{
|
4734 |
|
|
inst.error = _("shift expression expected");
|
4735 |
|
|
return FAIL;
|
4736 |
|
|
}
|
4737 |
|
|
|
4738 |
|
|
shift = shift_name->kind;
|
4739 |
|
|
|
4740 |
|
|
switch (mode)
|
4741 |
|
|
{
|
4742 |
|
|
case NO_SHIFT_RESTRICT:
|
4743 |
|
|
case SHIFT_IMMEDIATE: break;
|
4744 |
|
|
|
4745 |
|
|
case SHIFT_LSL_OR_ASR_IMMEDIATE:
|
4746 |
|
|
if (shift != SHIFT_LSL && shift != SHIFT_ASR)
|
4747 |
|
|
{
|
4748 |
|
|
inst.error = _("'LSL' or 'ASR' required");
|
4749 |
|
|
return FAIL;
|
4750 |
|
|
}
|
4751 |
|
|
break;
|
4752 |
|
|
|
4753 |
|
|
case SHIFT_LSL_IMMEDIATE:
|
4754 |
|
|
if (shift != SHIFT_LSL)
|
4755 |
|
|
{
|
4756 |
|
|
inst.error = _("'LSL' required");
|
4757 |
|
|
return FAIL;
|
4758 |
|
|
}
|
4759 |
|
|
break;
|
4760 |
|
|
|
4761 |
|
|
case SHIFT_ASR_IMMEDIATE:
|
4762 |
|
|
if (shift != SHIFT_ASR)
|
4763 |
|
|
{
|
4764 |
|
|
inst.error = _("'ASR' required");
|
4765 |
|
|
return FAIL;
|
4766 |
|
|
}
|
4767 |
|
|
break;
|
4768 |
|
|
|
4769 |
|
|
default: abort ();
|
4770 |
|
|
}
|
4771 |
|
|
|
4772 |
|
|
if (shift != SHIFT_RRX)
|
4773 |
|
|
{
|
4774 |
|
|
/* Whitespace can appear here if the next thing is a bare digit. */
|
4775 |
|
|
skip_whitespace (p);
|
4776 |
|
|
|
4777 |
|
|
if (mode == NO_SHIFT_RESTRICT
|
4778 |
|
|
&& (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
|
4779 |
|
|
{
|
4780 |
|
|
inst.operands[i].imm = reg;
|
4781 |
|
|
inst.operands[i].immisreg = 1;
|
4782 |
|
|
}
|
4783 |
|
|
else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
|
4784 |
|
|
return FAIL;
|
4785 |
|
|
}
|
4786 |
|
|
inst.operands[i].shift_kind = shift;
|
4787 |
|
|
inst.operands[i].shifted = 1;
|
4788 |
|
|
*str = p;
|
4789 |
|
|
return SUCCESS;
|
4790 |
|
|
}
|
4791 |
|
|
|
4792 |
|
|
/* Parse a <shifter_operand> for an ARM data processing instruction:
|
4793 |
|
|
|
4794 |
|
|
#<immediate>
|
4795 |
|
|
#<immediate>, <rotate>
|
4796 |
|
|
<Rm>
|
4797 |
|
|
<Rm>, <shift>
|
4798 |
|
|
|
4799 |
|
|
where <shift> is defined by parse_shift above, and <rotate> is a
|
4800 |
|
|
multiple of 2 between 0 and 30. Validation of immediate operands
|
4801 |
|
|
is deferred to md_apply_fix. */
|
4802 |
|
|
|
4803 |
|
|
static int
|
4804 |
|
|
parse_shifter_operand (char **str, int i)
|
4805 |
|
|
{
|
4806 |
|
|
int value;
|
4807 |
|
|
expressionS exp;
|
4808 |
|
|
|
4809 |
|
|
if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
|
4810 |
|
|
{
|
4811 |
|
|
inst.operands[i].reg = value;
|
4812 |
|
|
inst.operands[i].isreg = 1;
|
4813 |
|
|
|
4814 |
|
|
/* parse_shift will override this if appropriate */
|
4815 |
|
|
inst.reloc.exp.X_op = O_constant;
|
4816 |
|
|
inst.reloc.exp.X_add_number = 0;
|
4817 |
|
|
|
4818 |
|
|
if (skip_past_comma (str) == FAIL)
|
4819 |
|
|
return SUCCESS;
|
4820 |
|
|
|
4821 |
|
|
/* Shift operation on register. */
|
4822 |
|
|
return parse_shift (str, i, NO_SHIFT_RESTRICT);
|
4823 |
|
|
}
|
4824 |
|
|
|
4825 |
|
|
if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
|
4826 |
|
|
return FAIL;
|
4827 |
|
|
|
4828 |
|
|
if (skip_past_comma (str) == SUCCESS)
|
4829 |
|
|
{
|
4830 |
|
|
/* #x, y -- ie explicit rotation by Y. */
|
4831 |
|
|
if (my_get_expression (&exp, str, GE_NO_PREFIX))
|
4832 |
|
|
return FAIL;
|
4833 |
|
|
|
4834 |
|
|
if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
|
4835 |
|
|
{
|
4836 |
|
|
inst.error = _("constant expression expected");
|
4837 |
|
|
return FAIL;
|
4838 |
|
|
}
|
4839 |
|
|
|
4840 |
|
|
value = exp.X_add_number;
|
4841 |
|
|
if (value < 0 || value > 30 || value % 2 != 0)
|
4842 |
|
|
{
|
4843 |
|
|
inst.error = _("invalid rotation");
|
4844 |
|
|
return FAIL;
|
4845 |
|
|
}
|
4846 |
|
|
if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
|
4847 |
|
|
{
|
4848 |
|
|
inst.error = _("invalid constant");
|
4849 |
|
|
return FAIL;
|
4850 |
|
|
}
|
4851 |
|
|
|
4852 |
|
|
/* Convert to decoded value. md_apply_fix will put it back. */
|
4853 |
|
|
inst.reloc.exp.X_add_number
|
4854 |
|
|
= (((inst.reloc.exp.X_add_number << (32 - value))
|
4855 |
|
|
| (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
|
4856 |
|
|
}
|
4857 |
|
|
|
4858 |
|
|
inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
|
4859 |
|
|
inst.reloc.pc_rel = 0;
|
4860 |
|
|
return SUCCESS;
|
4861 |
|
|
}
|
4862 |
|
|
|
4863 |
|
|
/* Group relocation information. Each entry in the table contains the
|
4864 |
|
|
textual name of the relocation as may appear in assembler source
|
4865 |
|
|
and must end with a colon.
|
4866 |
|
|
Along with this textual name are the relocation codes to be used if
|
4867 |
|
|
the corresponding instruction is an ALU instruction (ADD or SUB only),
|
4868 |
|
|
an LDR, an LDRS, or an LDC. */
|
4869 |
|
|
|
4870 |
|
|
struct group_reloc_table_entry
|
4871 |
|
|
{
|
4872 |
|
|
const char *name;
|
4873 |
|
|
int alu_code;
|
4874 |
|
|
int ldr_code;
|
4875 |
|
|
int ldrs_code;
|
4876 |
|
|
int ldc_code;
|
4877 |
|
|
};
|
4878 |
|
|
|
4879 |
|
|
typedef enum
|
4880 |
|
|
{
|
4881 |
|
|
/* Varieties of non-ALU group relocation. */
|
4882 |
|
|
|
4883 |
|
|
GROUP_LDR,
|
4884 |
|
|
GROUP_LDRS,
|
4885 |
|
|
GROUP_LDC
|
4886 |
|
|
} group_reloc_type;
|
4887 |
|
|
|
4888 |
|
|
static struct group_reloc_table_entry group_reloc_table[] =
|
4889 |
|
|
{ /* Program counter relative: */
|
4890 |
|
|
{ "pc_g0_nc",
|
4891 |
|
|
BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
|
4892 |
|
|
0, /* LDR */
|
4893 |
|
|
0, /* LDRS */
|
4894 |
|
|
|
4895 |
|
|
{ "pc_g0",
|
4896 |
|
|
BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
|
4897 |
|
|
BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
|
4898 |
|
|
BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
|
4899 |
|
|
BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
|
4900 |
|
|
{ "pc_g1_nc",
|
4901 |
|
|
BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
|
4902 |
|
|
0, /* LDR */
|
4903 |
|
|
0, /* LDRS */
|
4904 |
|
|
|
4905 |
|
|
{ "pc_g1",
|
4906 |
|
|
BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
|
4907 |
|
|
BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
|
4908 |
|
|
BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
|
4909 |
|
|
BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
|
4910 |
|
|
{ "pc_g2",
|
4911 |
|
|
BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
|
4912 |
|
|
BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
|
4913 |
|
|
BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
|
4914 |
|
|
BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
|
4915 |
|
|
/* Section base relative */
|
4916 |
|
|
{ "sb_g0_nc",
|
4917 |
|
|
BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
|
4918 |
|
|
0, /* LDR */
|
4919 |
|
|
0, /* LDRS */
|
4920 |
|
|
|
4921 |
|
|
{ "sb_g0",
|
4922 |
|
|
BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
|
4923 |
|
|
BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
|
4924 |
|
|
BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
|
4925 |
|
|
BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
|
4926 |
|
|
{ "sb_g1_nc",
|
4927 |
|
|
BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
|
4928 |
|
|
0, /* LDR */
|
4929 |
|
|
0, /* LDRS */
|
4930 |
|
|
|
4931 |
|
|
{ "sb_g1",
|
4932 |
|
|
BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
|
4933 |
|
|
BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
|
4934 |
|
|
BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
|
4935 |
|
|
BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
|
4936 |
|
|
{ "sb_g2",
|
4937 |
|
|
BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
|
4938 |
|
|
BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
|
4939 |
|
|
BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
|
4940 |
|
|
BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
|
4941 |
|
|
|
4942 |
|
|
/* Given the address of a pointer pointing to the textual name of a group
|
4943 |
|
|
relocation as may appear in assembler source, attempt to find its details
|
4944 |
|
|
in group_reloc_table. The pointer will be updated to the character after
|
4945 |
|
|
the trailing colon. On failure, FAIL will be returned; SUCCESS
|
4946 |
|
|
otherwise. On success, *entry will be updated to point at the relevant
|
4947 |
|
|
group_reloc_table entry. */
|
4948 |
|
|
|
4949 |
|
|
static int
|
4950 |
|
|
find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
|
4951 |
|
|
{
|
4952 |
|
|
unsigned int i;
|
4953 |
|
|
for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
|
4954 |
|
|
{
|
4955 |
|
|
int length = strlen (group_reloc_table[i].name);
|
4956 |
|
|
|
4957 |
|
|
if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
|
4958 |
|
|
&& (*str)[length] == ':')
|
4959 |
|
|
{
|
4960 |
|
|
*out = &group_reloc_table[i];
|
4961 |
|
|
*str += (length + 1);
|
4962 |
|
|
return SUCCESS;
|
4963 |
|
|
}
|
4964 |
|
|
}
|
4965 |
|
|
|
4966 |
|
|
return FAIL;
|
4967 |
|
|
}
|
4968 |
|
|
|
4969 |
|
|
/* Parse a <shifter_operand> for an ARM data processing instruction
|
4970 |
|
|
(as for parse_shifter_operand) where group relocations are allowed:
|
4971 |
|
|
|
4972 |
|
|
#<immediate>
|
4973 |
|
|
#<immediate>, <rotate>
|
4974 |
|
|
#:<group_reloc>:<expression>
|
4975 |
|
|
<Rm>
|
4976 |
|
|
<Rm>, <shift>
|
4977 |
|
|
|
4978 |
|
|
where <group_reloc> is one of the strings defined in group_reloc_table.
|
4979 |
|
|
The hashes are optional.
|
4980 |
|
|
|
4981 |
|
|
Everything else is as for parse_shifter_operand. */
|
4982 |
|
|
|
4983 |
|
|
static parse_operand_result
|
4984 |
|
|
parse_shifter_operand_group_reloc (char **str, int i)
|
4985 |
|
|
{
|
4986 |
|
|
/* Determine if we have the sequence of characters #: or just :
|
4987 |
|
|
coming next. If we do, then we check for a group relocation.
|
4988 |
|
|
If we don't, punt the whole lot to parse_shifter_operand. */
|
4989 |
|
|
|
4990 |
|
|
if (((*str)[0] == '#' && (*str)[1] == ':')
|
4991 |
|
|
|| (*str)[0] == ':')
|
4992 |
|
|
{
|
4993 |
|
|
struct group_reloc_table_entry *entry;
|
4994 |
|
|
|
4995 |
|
|
if ((*str)[0] == '#')
|
4996 |
|
|
(*str) += 2;
|
4997 |
|
|
else
|
4998 |
|
|
(*str)++;
|
4999 |
|
|
|
5000 |
|
|
/* Try to parse a group relocation. Anything else is an error. */
|
5001 |
|
|
if (find_group_reloc_table_entry (str, &entry) == FAIL)
|
5002 |
|
|
{
|
5003 |
|
|
inst.error = _("unknown group relocation");
|
5004 |
|
|
return PARSE_OPERAND_FAIL_NO_BACKTRACK;
|
5005 |
|
|
}
|
5006 |
|
|
|
5007 |
|
|
/* We now have the group relocation table entry corresponding to
|
5008 |
|
|
the name in the assembler source. Next, we parse the expression. */
|
5009 |
|
|
if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
|
5010 |
|
|
return PARSE_OPERAND_FAIL_NO_BACKTRACK;
|
5011 |
|
|
|
5012 |
|
|
/* Record the relocation type (always the ALU variant here). */
|
5013 |
|
|
inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
|
5014 |
|
|
gas_assert (inst.reloc.type != 0);
|
5015 |
|
|
|
5016 |
|
|
return PARSE_OPERAND_SUCCESS;
|
5017 |
|
|
}
|
5018 |
|
|
else
|
5019 |
|
|
return parse_shifter_operand (str, i) == SUCCESS
|
5020 |
|
|
? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
|
5021 |
|
|
|
5022 |
|
|
/* Never reached. */
|
5023 |
|
|
}
|
5024 |
|
|
|
5025 |
|
|
/* Parse a Neon alignment expression. Information is written to
|
5026 |
|
|
inst.operands[i]. We assume the initial ':' has been skipped.
|
5027 |
|
|
|
5028 |
|
|
align .imm = align << 8, .immisalign=1, .preind=0 */
|
5029 |
|
|
static parse_operand_result
|
5030 |
|
|
parse_neon_alignment (char **str, int i)
|
5031 |
|
|
{
|
5032 |
|
|
char *p = *str;
|
5033 |
|
|
expressionS exp;
|
5034 |
|
|
|
5035 |
|
|
my_get_expression (&exp, &p, GE_NO_PREFIX);
|
5036 |
|
|
|
5037 |
|
|
if (exp.X_op != O_constant)
|
5038 |
|
|
{
|
5039 |
|
|
inst.error = _("alignment must be constant");
|
5040 |
|
|
return PARSE_OPERAND_FAIL;
|
5041 |
|
|
}
|
5042 |
|
|
|
5043 |
|
|
inst.operands[i].imm = exp.X_add_number << 8;
|
5044 |
|
|
inst.operands[i].immisalign = 1;
|
5045 |
|
|
/* Alignments are not pre-indexes. */
|
5046 |
|
|
inst.operands[i].preind = 0;
|
5047 |
|
|
|
5048 |
|
|
*str = p;
|
5049 |
|
|
return PARSE_OPERAND_SUCCESS;
|
5050 |
|
|
}
|
5051 |
|
|
|
5052 |
|
|
/* Parse all forms of an ARM address expression. Information is written
|
5053 |
|
|
to inst.operands[i] and/or inst.reloc.
|
5054 |
|
|
|
5055 |
|
|
Preindexed addressing (.preind=1):
|
5056 |
|
|
|
5057 |
|
|
[Rn, #offset] .reg=Rn .reloc.exp=offset
|
5058 |
|
|
[Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
|
5059 |
|
|
[Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
|
5060 |
|
|
.shift_kind=shift .reloc.exp=shift_imm
|
5061 |
|
|
|
5062 |
|
|
These three may have a trailing ! which causes .writeback to be set also.
|
5063 |
|
|
|
5064 |
|
|
Postindexed addressing (.postind=1, .writeback=1):
|
5065 |
|
|
|
5066 |
|
|
[Rn], #offset .reg=Rn .reloc.exp=offset
|
5067 |
|
|
[Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
|
5068 |
|
|
[Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
|
5069 |
|
|
.shift_kind=shift .reloc.exp=shift_imm
|
5070 |
|
|
|
5071 |
|
|
Unindexed addressing (.preind=0, .postind=0):
|
5072 |
|
|
|
5073 |
|
|
[Rn], {option} .reg=Rn .imm=option .immisreg=0
|
5074 |
|
|
|
5075 |
|
|
Other:
|
5076 |
|
|
|
5077 |
|
|
[Rn]{!} shorthand for [Rn,#0]{!}
|
5078 |
|
|
=immediate .isreg=0 .reloc.exp=immediate
|
5079 |
|
|
label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
|
5080 |
|
|
|
5081 |
|
|
It is the caller's responsibility to check for addressing modes not
|
5082 |
|
|
supported by the instruction, and to set inst.reloc.type. */
|
5083 |
|
|
|
5084 |
|
|
static parse_operand_result
|
5085 |
|
|
parse_address_main (char **str, int i, int group_relocations,
|
5086 |
|
|
group_reloc_type group_type)
|
5087 |
|
|
{
|
5088 |
|
|
char *p = *str;
|
5089 |
|
|
int reg;
|
5090 |
|
|
|
5091 |
|
|
if (skip_past_char (&p, '[') == FAIL)
|
5092 |
|
|
{
|
5093 |
|
|
if (skip_past_char (&p, '=') == FAIL)
|
5094 |
|
|
{
|
5095 |
|
|
/* Bare address - translate to PC-relative offset. */
|
5096 |
|
|
inst.reloc.pc_rel = 1;
|
5097 |
|
|
inst.operands[i].reg = REG_PC;
|
5098 |
|
|
inst.operands[i].isreg = 1;
|
5099 |
|
|
inst.operands[i].preind = 1;
|
5100 |
|
|
}
|
5101 |
|
|
/* Otherwise a load-constant pseudo op, no special treatment needed here. */
|
5102 |
|
|
|
5103 |
|
|
if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
|
5104 |
|
|
return PARSE_OPERAND_FAIL;
|
5105 |
|
|
|
5106 |
|
|
*str = p;
|
5107 |
|
|
return PARSE_OPERAND_SUCCESS;
|
5108 |
|
|
}
|
5109 |
|
|
|
5110 |
|
|
if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
|
5111 |
|
|
{
|
5112 |
|
|
inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
|
5113 |
|
|
return PARSE_OPERAND_FAIL;
|
5114 |
|
|
}
|
5115 |
|
|
inst.operands[i].reg = reg;
|
5116 |
|
|
inst.operands[i].isreg = 1;
|
5117 |
|
|
|
5118 |
|
|
if (skip_past_comma (&p) == SUCCESS)
|
5119 |
|
|
{
|
5120 |
|
|
inst.operands[i].preind = 1;
|
5121 |
|
|
|
5122 |
|
|
if (*p == '+') p++;
|
5123 |
|
|
else if (*p == '-') p++, inst.operands[i].negative = 1;
|
5124 |
|
|
|
5125 |
|
|
if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
|
5126 |
|
|
{
|
5127 |
|
|
inst.operands[i].imm = reg;
|
5128 |
|
|
inst.operands[i].immisreg = 1;
|
5129 |
|
|
|
5130 |
|
|
if (skip_past_comma (&p) == SUCCESS)
|
5131 |
|
|
if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
|
5132 |
|
|
return PARSE_OPERAND_FAIL;
|
5133 |
|
|
}
|
5134 |
|
|
else if (skip_past_char (&p, ':') == SUCCESS)
|
5135 |
|
|
{
|
5136 |
|
|
/* FIXME: '@' should be used here, but it's filtered out by generic
|
5137 |
|
|
code before we get to see it here. This may be subject to
|
5138 |
|
|
change. */
|
5139 |
|
|
parse_operand_result result = parse_neon_alignment (&p, i);
|
5140 |
|
|
|
5141 |
|
|
if (result != PARSE_OPERAND_SUCCESS)
|
5142 |
|
|
return result;
|
5143 |
|
|
}
|
5144 |
|
|
else
|
5145 |
|
|
{
|
5146 |
|
|
if (inst.operands[i].negative)
|
5147 |
|
|
{
|
5148 |
|
|
inst.operands[i].negative = 0;
|
5149 |
|
|
p--;
|
5150 |
|
|
}
|
5151 |
|
|
|
5152 |
|
|
if (group_relocations
|
5153 |
|
|
&& ((*p == '#' && *(p + 1) == ':') || *p == ':'))
|
5154 |
|
|
{
|
5155 |
|
|
struct group_reloc_table_entry *entry;
|
5156 |
|
|
|
5157 |
|
|
/* Skip over the #: or : sequence. */
|
5158 |
|
|
if (*p == '#')
|
5159 |
|
|
p += 2;
|
5160 |
|
|
else
|
5161 |
|
|
p++;
|
5162 |
|
|
|
5163 |
|
|
/* Try to parse a group relocation. Anything else is an
|
5164 |
|
|
error. */
|
5165 |
|
|
if (find_group_reloc_table_entry (&p, &entry) == FAIL)
|
5166 |
|
|
{
|
5167 |
|
|
inst.error = _("unknown group relocation");
|
5168 |
|
|
return PARSE_OPERAND_FAIL_NO_BACKTRACK;
|
5169 |
|
|
}
|
5170 |
|
|
|
5171 |
|
|
/* We now have the group relocation table entry corresponding to
|
5172 |
|
|
the name in the assembler source. Next, we parse the
|
5173 |
|
|
expression. */
|
5174 |
|
|
if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
|
5175 |
|
|
return PARSE_OPERAND_FAIL_NO_BACKTRACK;
|
5176 |
|
|
|
5177 |
|
|
/* Record the relocation type. */
|
5178 |
|
|
switch (group_type)
|
5179 |
|
|
{
|
5180 |
|
|
case GROUP_LDR:
|
5181 |
|
|
inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
|
5182 |
|
|
break;
|
5183 |
|
|
|
5184 |
|
|
case GROUP_LDRS:
|
5185 |
|
|
inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
|
5186 |
|
|
break;
|
5187 |
|
|
|
5188 |
|
|
case GROUP_LDC:
|
5189 |
|
|
inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
|
5190 |
|
|
break;
|
5191 |
|
|
|
5192 |
|
|
default:
|
5193 |
|
|
gas_assert (0);
|
5194 |
|
|
}
|
5195 |
|
|
|
5196 |
|
|
if (inst.reloc.type == 0)
|
5197 |
|
|
{
|
5198 |
|
|
inst.error = _("this group relocation is not allowed on this instruction");
|
5199 |
|
|
return PARSE_OPERAND_FAIL_NO_BACKTRACK;
|
5200 |
|
|
}
|
5201 |
|
|
}
|
5202 |
|
|
else
|
5203 |
|
|
{
|
5204 |
|
|
char *q = p;
|
5205 |
|
|
if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
|
5206 |
|
|
return PARSE_OPERAND_FAIL;
|
5207 |
|
|
/* If the offset is 0, find out if it's a +0 or -0. */
|
5208 |
|
|
if (inst.reloc.exp.X_op == O_constant
|
5209 |
|
|
&& inst.reloc.exp.X_add_number == 0)
|
5210 |
|
|
{
|
5211 |
|
|
skip_whitespace (q);
|
5212 |
|
|
if (*q == '#')
|
5213 |
|
|
{
|
5214 |
|
|
q++;
|
5215 |
|
|
skip_whitespace (q);
|
5216 |
|
|
}
|
5217 |
|
|
if (*q == '-')
|
5218 |
|
|
inst.operands[i].negative = 1;
|
5219 |
|
|
}
|
5220 |
|
|
}
|
5221 |
|
|
}
|
5222 |
|
|
}
|
5223 |
|
|
else if (skip_past_char (&p, ':') == SUCCESS)
|
5224 |
|
|
{
|
5225 |
|
|
/* FIXME: '@' should be used here, but it's filtered out by generic code
|
5226 |
|
|
before we get to see it here. This may be subject to change. */
|
5227 |
|
|
parse_operand_result result = parse_neon_alignment (&p, i);
|
5228 |
|
|
|
5229 |
|
|
if (result != PARSE_OPERAND_SUCCESS)
|
5230 |
|
|
return result;
|
5231 |
|
|
}
|
5232 |
|
|
|
5233 |
|
|
if (skip_past_char (&p, ']') == FAIL)
|
5234 |
|
|
{
|
5235 |
|
|
inst.error = _("']' expected");
|
5236 |
|
|
return PARSE_OPERAND_FAIL;
|
5237 |
|
|
}
|
5238 |
|
|
|
5239 |
|
|
if (skip_past_char (&p, '!') == SUCCESS)
|
5240 |
|
|
inst.operands[i].writeback = 1;
|
5241 |
|
|
|
5242 |
|
|
else if (skip_past_comma (&p) == SUCCESS)
|
5243 |
|
|
{
|
5244 |
|
|
if (skip_past_char (&p, '{') == SUCCESS)
|
5245 |
|
|
{
|
5246 |
|
|
/* [Rn], {expr} - unindexed, with option */
|
5247 |
|
|
if (parse_immediate (&p, &inst.operands[i].imm,
|
5248 |
|
|
0, 255, TRUE) == FAIL)
|
5249 |
|
|
return PARSE_OPERAND_FAIL;
|
5250 |
|
|
|
5251 |
|
|
if (skip_past_char (&p, '}') == FAIL)
|
5252 |
|
|
{
|
5253 |
|
|
inst.error = _("'}' expected at end of 'option' field");
|
5254 |
|
|
return PARSE_OPERAND_FAIL;
|
5255 |
|
|
}
|
5256 |
|
|
if (inst.operands[i].preind)
|
5257 |
|
|
{
|
5258 |
|
|
inst.error = _("cannot combine index with option");
|
5259 |
|
|
return PARSE_OPERAND_FAIL;
|
5260 |
|
|
}
|
5261 |
|
|
*str = p;
|
5262 |
|
|
return PARSE_OPERAND_SUCCESS;
|
5263 |
|
|
}
|
5264 |
|
|
else
|
5265 |
|
|
{
|
5266 |
|
|
inst.operands[i].postind = 1;
|
5267 |
|
|
inst.operands[i].writeback = 1;
|
5268 |
|
|
|
5269 |
|
|
if (inst.operands[i].preind)
|
5270 |
|
|
{
|
5271 |
|
|
inst.error = _("cannot combine pre- and post-indexing");
|
5272 |
|
|
return PARSE_OPERAND_FAIL;
|
5273 |
|
|
}
|
5274 |
|
|
|
5275 |
|
|
if (*p == '+') p++;
|
5276 |
|
|
else if (*p == '-') p++, inst.operands[i].negative = 1;
|
5277 |
|
|
|
5278 |
|
|
if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
|
5279 |
|
|
{
|
5280 |
|
|
/* We might be using the immediate for alignment already. If we
|
5281 |
|
|
are, OR the register number into the low-order bits. */
|
5282 |
|
|
if (inst.operands[i].immisalign)
|
5283 |
|
|
inst.operands[i].imm |= reg;
|
5284 |
|
|
else
|
5285 |
|
|
inst.operands[i].imm = reg;
|
5286 |
|
|
inst.operands[i].immisreg = 1;
|
5287 |
|
|
|
5288 |
|
|
if (skip_past_comma (&p) == SUCCESS)
|
5289 |
|
|
if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
|
5290 |
|
|
return PARSE_OPERAND_FAIL;
|
5291 |
|
|
}
|
5292 |
|
|
else
|
5293 |
|
|
{
|
5294 |
|
|
char *q = p;
|
5295 |
|
|
if (inst.operands[i].negative)
|
5296 |
|
|
{
|
5297 |
|
|
inst.operands[i].negative = 0;
|
5298 |
|
|
p--;
|
5299 |
|
|
}
|
5300 |
|
|
if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
|
5301 |
|
|
return PARSE_OPERAND_FAIL;
|
5302 |
|
|
/* If the offset is 0, find out if it's a +0 or -0. */
|
5303 |
|
|
if (inst.reloc.exp.X_op == O_constant
|
5304 |
|
|
&& inst.reloc.exp.X_add_number == 0)
|
5305 |
|
|
{
|
5306 |
|
|
skip_whitespace (q);
|
5307 |
|
|
if (*q == '#')
|
5308 |
|
|
{
|
5309 |
|
|
q++;
|
5310 |
|
|
skip_whitespace (q);
|
5311 |
|
|
}
|
5312 |
|
|
if (*q == '-')
|
5313 |
|
|
inst.operands[i].negative = 1;
|
5314 |
|
|
}
|
5315 |
|
|
}
|
5316 |
|
|
}
|
5317 |
|
|
}
|
5318 |
|
|
|
5319 |
|
|
/* If at this point neither .preind nor .postind is set, we have a
|
5320 |
|
|
bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
|
5321 |
|
|
if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
|
5322 |
|
|
{
|
5323 |
|
|
inst.operands[i].preind = 1;
|
5324 |
|
|
inst.reloc.exp.X_op = O_constant;
|
5325 |
|
|
inst.reloc.exp.X_add_number = 0;
|
5326 |
|
|
}
|
5327 |
|
|
*str = p;
|
5328 |
|
|
return PARSE_OPERAND_SUCCESS;
|
5329 |
|
|
}
|
5330 |
|
|
|
5331 |
|
|
static int
|
5332 |
|
|
parse_address (char **str, int i)
|
5333 |
|
|
{
|
5334 |
|
|
return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
|
5335 |
|
|
? SUCCESS : FAIL;
|
5336 |
|
|
}
|
5337 |
|
|
|
5338 |
|
|
static parse_operand_result
|
5339 |
|
|
parse_address_group_reloc (char **str, int i, group_reloc_type type)
|
5340 |
|
|
{
|
5341 |
|
|
return parse_address_main (str, i, 1, type);
|
5342 |
|
|
}
|
5343 |
|
|
|
5344 |
|
|
/* Parse an operand for a MOVW or MOVT instruction. */
|
5345 |
|
|
static int
|
5346 |
|
|
parse_half (char **str)
|
5347 |
|
|
{
|
5348 |
|
|
char * p;
|
5349 |
|
|
|
5350 |
|
|
p = *str;
|
5351 |
|
|
skip_past_char (&p, '#');
|
5352 |
|
|
if (strncasecmp (p, ":lower16:", 9) == 0)
|
5353 |
|
|
inst.reloc.type = BFD_RELOC_ARM_MOVW;
|
5354 |
|
|
else if (strncasecmp (p, ":upper16:", 9) == 0)
|
5355 |
|
|
inst.reloc.type = BFD_RELOC_ARM_MOVT;
|
5356 |
|
|
|
5357 |
|
|
if (inst.reloc.type != BFD_RELOC_UNUSED)
|
5358 |
|
|
{
|
5359 |
|
|
p += 9;
|
5360 |
|
|
skip_whitespace (p);
|
5361 |
|
|
}
|
5362 |
|
|
|
5363 |
|
|
if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
|
5364 |
|
|
return FAIL;
|
5365 |
|
|
|
5366 |
|
|
if (inst.reloc.type == BFD_RELOC_UNUSED)
|
5367 |
|
|
{
|
5368 |
|
|
if (inst.reloc.exp.X_op != O_constant)
|
5369 |
|
|
{
|
5370 |
|
|
inst.error = _("constant expression expected");
|
5371 |
|
|
return FAIL;
|
5372 |
|
|
}
|
5373 |
|
|
if (inst.reloc.exp.X_add_number < 0
|
5374 |
|
|
|| inst.reloc.exp.X_add_number > 0xffff)
|
5375 |
|
|
{
|
5376 |
|
|
inst.error = _("immediate value out of range");
|
5377 |
|
|
return FAIL;
|
5378 |
|
|
}
|
5379 |
|
|
}
|
5380 |
|
|
*str = p;
|
5381 |
|
|
return SUCCESS;
|
5382 |
|
|
}
|
5383 |
|
|
|
5384 |
|
|
/* Miscellaneous. */
|
5385 |
|
|
|
5386 |
|
|
/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
|
5387 |
|
|
or a bitmask suitable to be or-ed into the ARM msr instruction. */
|
5388 |
|
|
static int
|
5389 |
|
|
parse_psr (char **str, bfd_boolean lhs)
|
5390 |
|
|
{
|
5391 |
|
|
char *p;
|
5392 |
|
|
unsigned long psr_field;
|
5393 |
|
|
const struct asm_psr *psr;
|
5394 |
|
|
char *start;
|
5395 |
|
|
bfd_boolean is_apsr = FALSE;
|
5396 |
|
|
bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
|
5397 |
|
|
|
5398 |
|
|
/* PR gas/12698: If the user has specified -march=all then m_profile will
|
5399 |
|
|
be TRUE, but we want to ignore it in this case as we are building for any
|
5400 |
|
|
CPU type, including non-m variants. */
|
5401 |
|
|
if (selected_cpu.core == arm_arch_any.core)
|
5402 |
|
|
m_profile = FALSE;
|
5403 |
|
|
|
5404 |
|
|
/* CPSR's and SPSR's can now be lowercase. This is just a convenience
|
5405 |
|
|
feature for ease of use and backwards compatibility. */
|
5406 |
|
|
p = *str;
|
5407 |
|
|
if (strncasecmp (p, "SPSR", 4) == 0)
|
5408 |
|
|
{
|
5409 |
|
|
if (m_profile)
|
5410 |
|
|
goto unsupported_psr;
|
5411 |
|
|
|
5412 |
|
|
psr_field = SPSR_BIT;
|
5413 |
|
|
}
|
5414 |
|
|
else if (strncasecmp (p, "CPSR", 4) == 0)
|
5415 |
|
|
{
|
5416 |
|
|
if (m_profile)
|
5417 |
|
|
goto unsupported_psr;
|
5418 |
|
|
|
5419 |
|
|
psr_field = 0;
|
5420 |
|
|
}
|
5421 |
|
|
else if (strncasecmp (p, "APSR", 4) == 0)
|
5422 |
|
|
{
|
5423 |
|
|
/* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
|
5424 |
|
|
and ARMv7-R architecture CPUs. */
|
5425 |
|
|
is_apsr = TRUE;
|
5426 |
|
|
psr_field = 0;
|
5427 |
|
|
}
|
5428 |
|
|
else if (m_profile)
|
5429 |
|
|
{
|
5430 |
|
|
start = p;
|
5431 |
|
|
do
|
5432 |
|
|
p++;
|
5433 |
|
|
while (ISALNUM (*p) || *p == '_');
|
5434 |
|
|
|
5435 |
|
|
if (strncasecmp (start, "iapsr", 5) == 0
|
5436 |
|
|
|| strncasecmp (start, "eapsr", 5) == 0
|
5437 |
|
|
|| strncasecmp (start, "xpsr", 4) == 0
|
5438 |
|
|
|| strncasecmp (start, "psr", 3) == 0)
|
5439 |
|
|
p = start + strcspn (start, "rR") + 1;
|
5440 |
|
|
|
5441 |
|
|
psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
|
5442 |
|
|
p - start);
|
5443 |
|
|
|
5444 |
|
|
if (!psr)
|
5445 |
|
|
return FAIL;
|
5446 |
|
|
|
5447 |
|
|
/* If APSR is being written, a bitfield may be specified. Note that
|
5448 |
|
|
APSR itself is handled above. */
|
5449 |
|
|
if (psr->field <= 3)
|
5450 |
|
|
{
|
5451 |
|
|
psr_field = psr->field;
|
5452 |
|
|
is_apsr = TRUE;
|
5453 |
|
|
goto check_suffix;
|
5454 |
|
|
}
|
5455 |
|
|
|
5456 |
|
|
*str = p;
|
5457 |
|
|
/* M-profile MSR instructions have the mask field set to "10", except
|
5458 |
|
|
*PSR variants which modify APSR, which may use a different mask (and
|
5459 |
|
|
have been handled already). Do that by setting the PSR_f field
|
5460 |
|
|
here. */
|
5461 |
|
|
return psr->field | (lhs ? PSR_f : 0);
|
5462 |
|
|
}
|
5463 |
|
|
else
|
5464 |
|
|
goto unsupported_psr;
|
5465 |
|
|
|
5466 |
|
|
p += 4;
|
5467 |
|
|
check_suffix:
|
5468 |
|
|
if (*p == '_')
|
5469 |
|
|
{
|
5470 |
|
|
/* A suffix follows. */
|
5471 |
|
|
p++;
|
5472 |
|
|
start = p;
|
5473 |
|
|
|
5474 |
|
|
do
|
5475 |
|
|
p++;
|
5476 |
|
|
while (ISALNUM (*p) || *p == '_');
|
5477 |
|
|
|
5478 |
|
|
if (is_apsr)
|
5479 |
|
|
{
|
5480 |
|
|
/* APSR uses a notation for bits, rather than fields. */
|
5481 |
|
|
unsigned int nzcvq_bits = 0;
|
5482 |
|
|
unsigned int g_bit = 0;
|
5483 |
|
|
char *bit;
|
5484 |
|
|
|
5485 |
|
|
for (bit = start; bit != p; bit++)
|
5486 |
|
|
{
|
5487 |
|
|
switch (TOLOWER (*bit))
|
5488 |
|
|
{
|
5489 |
|
|
case 'n':
|
5490 |
|
|
nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
|
5491 |
|
|
break;
|
5492 |
|
|
|
5493 |
|
|
case 'z':
|
5494 |
|
|
nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
|
5495 |
|
|
break;
|
5496 |
|
|
|
5497 |
|
|
case 'c':
|
5498 |
|
|
nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
|
5499 |
|
|
break;
|
5500 |
|
|
|
5501 |
|
|
case 'v':
|
5502 |
|
|
nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
|
5503 |
|
|
break;
|
5504 |
|
|
|
5505 |
|
|
case 'q':
|
5506 |
|
|
nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
|
5507 |
|
|
break;
|
5508 |
|
|
|
5509 |
|
|
case 'g':
|
5510 |
|
|
g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
|
5511 |
|
|
break;
|
5512 |
|
|
|
5513 |
|
|
default:
|
5514 |
|
|
inst.error = _("unexpected bit specified after APSR");
|
5515 |
|
|
return FAIL;
|
5516 |
|
|
}
|
5517 |
|
|
}
|
5518 |
|
|
|
5519 |
|
|
if (nzcvq_bits == 0x1f)
|
5520 |
|
|
psr_field |= PSR_f;
|
5521 |
|
|
|
5522 |
|
|
if (g_bit == 0x1)
|
5523 |
|
|
{
|
5524 |
|
|
if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
|
5525 |
|
|
{
|
5526 |
|
|
inst.error = _("selected processor does not "
|
5527 |
|
|
"support DSP extension");
|
5528 |
|
|
return FAIL;
|
5529 |
|
|
}
|
5530 |
|
|
|
5531 |
|
|
psr_field |= PSR_s;
|
5532 |
|
|
}
|
5533 |
|
|
|
5534 |
|
|
if ((nzcvq_bits & 0x20) != 0
|
5535 |
|
|
|| (nzcvq_bits != 0x1f && nzcvq_bits != 0)
|
5536 |
|
|
|| (g_bit & 0x2) != 0)
|
5537 |
|
|
{
|
5538 |
|
|
inst.error = _("bad bitmask specified after APSR");
|
5539 |
|
|
return FAIL;
|
5540 |
|
|
}
|
5541 |
|
|
}
|
5542 |
|
|
else
|
5543 |
|
|
{
|
5544 |
|
|
psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
|
5545 |
|
|
p - start);
|
5546 |
|
|
if (!psr)
|
5547 |
|
|
goto error;
|
5548 |
|
|
|
5549 |
|
|
psr_field |= psr->field;
|
5550 |
|
|
}
|
5551 |
|
|
}
|
5552 |
|
|
else
|
5553 |
|
|
{
|
5554 |
|
|
if (ISALNUM (*p))
|
5555 |
|
|
goto error; /* Garbage after "[CS]PSR". */
|
5556 |
|
|
|
5557 |
|
|
/* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
|
5558 |
|
|
is deprecated, but allow it anyway. */
|
5559 |
|
|
if (is_apsr && lhs)
|
5560 |
|
|
{
|
5561 |
|
|
psr_field |= PSR_f;
|
5562 |
|
|
as_tsktsk (_("writing to APSR without specifying a bitmask is "
|
5563 |
|
|
"deprecated"));
|
5564 |
|
|
}
|
5565 |
|
|
else if (!m_profile)
|
5566 |
|
|
/* These bits are never right for M-profile devices: don't set them
|
5567 |
|
|
(only code paths which read/write APSR reach here). */
|
5568 |
|
|
psr_field |= (PSR_c | PSR_f);
|
5569 |
|
|
}
|
5570 |
|
|
*str = p;
|
5571 |
|
|
return psr_field;
|
5572 |
|
|
|
5573 |
|
|
unsupported_psr:
|
5574 |
|
|
inst.error = _("selected processor does not support requested special "
|
5575 |
|
|
"purpose register");
|
5576 |
|
|
return FAIL;
|
5577 |
|
|
|
5578 |
|
|
error:
|
5579 |
|
|
inst.error = _("flag for {c}psr instruction expected");
|
5580 |
|
|
return FAIL;
|
5581 |
|
|
}
|
5582 |
|
|
|
5583 |
|
|
/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
|
5584 |
|
|
value suitable for splatting into the AIF field of the instruction. */
|
5585 |
|
|
|
5586 |
|
|
static int
|
5587 |
|
|
parse_cps_flags (char **str)
|
5588 |
|
|
{
|
5589 |
|
|
int val = 0;
|
5590 |
|
|
int saw_a_flag = 0;
|
5591 |
|
|
char *s = *str;
|
5592 |
|
|
|
5593 |
|
|
for (;;)
|
5594 |
|
|
switch (*s++)
|
5595 |
|
|
{
|
5596 |
|
|
case '\0': case ',':
|
5597 |
|
|
goto done;
|
5598 |
|
|
|
5599 |
|
|
case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
|
5600 |
|
|
case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
|
5601 |
|
|
case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
|
5602 |
|
|
|
5603 |
|
|
default:
|
5604 |
|
|
inst.error = _("unrecognized CPS flag");
|
5605 |
|
|
return FAIL;
|
5606 |
|
|
}
|
5607 |
|
|
|
5608 |
|
|
done:
|
5609 |
|
|
if (saw_a_flag == 0)
|
5610 |
|
|
{
|
5611 |
|
|
inst.error = _("missing CPS flags");
|
5612 |
|
|
return FAIL;
|
5613 |
|
|
}
|
5614 |
|
|
|
5615 |
|
|
*str = s - 1;
|
5616 |
|
|
return val;
|
5617 |
|
|
}
|
5618 |
|
|
|
5619 |
|
|
/* Parse an endian specifier ("BE" or "LE", case insensitive);
|
5620 |
|
|
returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
|
5621 |
|
|
|
5622 |
|
|
static int
|
5623 |
|
|
parse_endian_specifier (char **str)
|
5624 |
|
|
{
|
5625 |
|
|
int little_endian;
|
5626 |
|
|
char *s = *str;
|
5627 |
|
|
|
5628 |
|
|
if (strncasecmp (s, "BE", 2))
|
5629 |
|
|
little_endian = 0;
|
5630 |
|
|
else if (strncasecmp (s, "LE", 2))
|
5631 |
|
|
little_endian = 1;
|
5632 |
|
|
else
|
5633 |
|
|
{
|
5634 |
|
|
inst.error = _("valid endian specifiers are be or le");
|
5635 |
|
|
return FAIL;
|
5636 |
|
|
}
|
5637 |
|
|
|
5638 |
|
|
if (ISALNUM (s[2]) || s[2] == '_')
|
5639 |
|
|
{
|
5640 |
|
|
inst.error = _("valid endian specifiers are be or le");
|
5641 |
|
|
return FAIL;
|
5642 |
|
|
}
|
5643 |
|
|
|
5644 |
|
|
*str = s + 2;
|
5645 |
|
|
return little_endian;
|
5646 |
|
|
}
|
5647 |
|
|
|
5648 |
|
|
/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
|
5649 |
|
|
value suitable for poking into the rotate field of an sxt or sxta
|
5650 |
|
|
instruction, or FAIL on error. */
|
5651 |
|
|
|
5652 |
|
|
static int
|
5653 |
|
|
parse_ror (char **str)
|
5654 |
|
|
{
|
5655 |
|
|
int rot;
|
5656 |
|
|
char *s = *str;
|
5657 |
|
|
|
5658 |
|
|
if (strncasecmp (s, "ROR", 3) == 0)
|
5659 |
|
|
s += 3;
|
5660 |
|
|
else
|
5661 |
|
|
{
|
5662 |
|
|
inst.error = _("missing rotation field after comma");
|
5663 |
|
|
return FAIL;
|
5664 |
|
|
}
|
5665 |
|
|
|
5666 |
|
|
if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
|
5667 |
|
|
return FAIL;
|
5668 |
|
|
|
5669 |
|
|
switch (rot)
|
5670 |
|
|
{
|
5671 |
|
|
case 0: *str = s; return 0x0;
|
5672 |
|
|
case 8: *str = s; return 0x1;
|
5673 |
|
|
case 16: *str = s; return 0x2;
|
5674 |
|
|
case 24: *str = s; return 0x3;
|
5675 |
|
|
|
5676 |
|
|
default:
|
5677 |
|
|
inst.error = _("rotation can only be 0, 8, 16, or 24");
|
5678 |
|
|
return FAIL;
|
5679 |
|
|
}
|
5680 |
|
|
}
|
5681 |
|
|
|
5682 |
|
|
/* Parse a conditional code (from conds[] below). The value returned is in the
|
5683 |
|
|
range 0 .. 14, or FAIL. */
|
5684 |
|
|
static int
|
5685 |
|
|
parse_cond (char **str)
|
5686 |
|
|
{
|
5687 |
|
|
char *q;
|
5688 |
|
|
const struct asm_cond *c;
|
5689 |
|
|
int n;
|
5690 |
|
|
/* Condition codes are always 2 characters, so matching up to
|
5691 |
|
|
3 characters is sufficient. */
|
5692 |
|
|
char cond[3];
|
5693 |
|
|
|
5694 |
|
|
q = *str;
|
5695 |
|
|
n = 0;
|
5696 |
|
|
while (ISALPHA (*q) && n < 3)
|
5697 |
|
|
{
|
5698 |
|
|
cond[n] = TOLOWER (*q);
|
5699 |
|
|
q++;
|
5700 |
|
|
n++;
|
5701 |
|
|
}
|
5702 |
|
|
|
5703 |
|
|
c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
|
5704 |
|
|
if (!c)
|
5705 |
|
|
{
|
5706 |
|
|
inst.error = _("condition required");
|
5707 |
|
|
return FAIL;
|
5708 |
|
|
}
|
5709 |
|
|
|
5710 |
|
|
*str = q;
|
5711 |
|
|
return c->value;
|
5712 |
|
|
}
|
5713 |
|
|
|
5714 |
|
|
/* Parse an option for a barrier instruction. Returns the encoding for the
|
5715 |
|
|
option, or FAIL. */
|
5716 |
|
|
static int
|
5717 |
|
|
parse_barrier (char **str)
|
5718 |
|
|
{
|
5719 |
|
|
char *p, *q;
|
5720 |
|
|
const struct asm_barrier_opt *o;
|
5721 |
|
|
|
5722 |
|
|
p = q = *str;
|
5723 |
|
|
while (ISALPHA (*q))
|
5724 |
|
|
q++;
|
5725 |
|
|
|
5726 |
|
|
o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
|
5727 |
|
|
q - p);
|
5728 |
|
|
if (!o)
|
5729 |
|
|
return FAIL;
|
5730 |
|
|
|
5731 |
|
|
*str = q;
|
5732 |
|
|
return o->value;
|
5733 |
|
|
}
|
5734 |
|
|
|
5735 |
|
|
/* Parse the operands of a table branch instruction. Similar to a memory
|
5736 |
|
|
operand. */
|
5737 |
|
|
static int
|
5738 |
|
|
parse_tb (char **str)
|
5739 |
|
|
{
|
5740 |
|
|
char * p = *str;
|
5741 |
|
|
int reg;
|
5742 |
|
|
|
5743 |
|
|
if (skip_past_char (&p, '[') == FAIL)
|
5744 |
|
|
{
|
5745 |
|
|
inst.error = _("'[' expected");
|
5746 |
|
|
return FAIL;
|
5747 |
|
|
}
|
5748 |
|
|
|
5749 |
|
|
if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
|
5750 |
|
|
{
|
5751 |
|
|
inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
|
5752 |
|
|
return FAIL;
|
5753 |
|
|
}
|
5754 |
|
|
inst.operands[0].reg = reg;
|
5755 |
|
|
|
5756 |
|
|
if (skip_past_comma (&p) == FAIL)
|
5757 |
|
|
{
|
5758 |
|
|
inst.error = _("',' expected");
|
5759 |
|
|
return FAIL;
|
5760 |
|
|
}
|
5761 |
|
|
|
5762 |
|
|
if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
|
5763 |
|
|
{
|
5764 |
|
|
inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
|
5765 |
|
|
return FAIL;
|
5766 |
|
|
}
|
5767 |
|
|
inst.operands[0].imm = reg;
|
5768 |
|
|
|
5769 |
|
|
if (skip_past_comma (&p) == SUCCESS)
|
5770 |
|
|
{
|
5771 |
|
|
if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
|
5772 |
|
|
return FAIL;
|
5773 |
|
|
if (inst.reloc.exp.X_add_number != 1)
|
5774 |
|
|
{
|
5775 |
|
|
inst.error = _("invalid shift");
|
5776 |
|
|
return FAIL;
|
5777 |
|
|
}
|
5778 |
|
|
inst.operands[0].shifted = 1;
|
5779 |
|
|
}
|
5780 |
|
|
|
5781 |
|
|
if (skip_past_char (&p, ']') == FAIL)
|
5782 |
|
|
{
|
5783 |
|
|
inst.error = _("']' expected");
|
5784 |
|
|
return FAIL;
|
5785 |
|
|
}
|
5786 |
|
|
*str = p;
|
5787 |
|
|
return SUCCESS;
|
5788 |
|
|
}
|
5789 |
|
|
|
5790 |
|
|
/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
|
5791 |
|
|
information on the types the operands can take and how they are encoded.
|
5792 |
|
|
Up to four operands may be read; this function handles setting the
|
5793 |
|
|
".present" field for each read operand itself.
|
5794 |
|
|
Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
|
5795 |
|
|
else returns FAIL. */
|
5796 |
|
|
|
5797 |
|
|
static int
|
5798 |
|
|
parse_neon_mov (char **str, int *which_operand)
|
5799 |
|
|
{
|
5800 |
|
|
int i = *which_operand, val;
|
5801 |
|
|
enum arm_reg_type rtype;
|
5802 |
|
|
char *ptr = *str;
|
5803 |
|
|
struct neon_type_el optype;
|
5804 |
|
|
|
5805 |
|
|
if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
|
5806 |
|
|
{
|
5807 |
|
|
/* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
|
5808 |
|
|
inst.operands[i].reg = val;
|
5809 |
|
|
inst.operands[i].isscalar = 1;
|
5810 |
|
|
inst.operands[i].vectype = optype;
|
5811 |
|
|
inst.operands[i++].present = 1;
|
5812 |
|
|
|
5813 |
|
|
if (skip_past_comma (&ptr) == FAIL)
|
5814 |
|
|
goto wanted_comma;
|
5815 |
|
|
|
5816 |
|
|
if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
|
5817 |
|
|
goto wanted_arm;
|
5818 |
|
|
|
5819 |
|
|
inst.operands[i].reg = val;
|
5820 |
|
|
inst.operands[i].isreg = 1;
|
5821 |
|
|
inst.operands[i].present = 1;
|
5822 |
|
|
}
|
5823 |
|
|
else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
|
5824 |
|
|
!= FAIL)
|
5825 |
|
|
{
|
5826 |
|
|
/* Cases 0, 1, 2, 3, 5 (D only). */
|
5827 |
|
|
if (skip_past_comma (&ptr) == FAIL)
|
5828 |
|
|
goto wanted_comma;
|
5829 |
|
|
|
5830 |
|
|
inst.operands[i].reg = val;
|
5831 |
|
|
inst.operands[i].isreg = 1;
|
5832 |
|
|
inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
|
5833 |
|
|
inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
|
5834 |
|
|
inst.operands[i].isvec = 1;
|
5835 |
|
|
inst.operands[i].vectype = optype;
|
5836 |
|
|
inst.operands[i++].present = 1;
|
5837 |
|
|
|
5838 |
|
|
if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
|
5839 |
|
|
{
|
5840 |
|
|
/* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
|
5841 |
|
|
Case 13: VMOV <Sd>, <Rm> */
|
5842 |
|
|
inst.operands[i].reg = val;
|
5843 |
|
|
inst.operands[i].isreg = 1;
|
5844 |
|
|
inst.operands[i].present = 1;
|
5845 |
|
|
|
5846 |
|
|
if (rtype == REG_TYPE_NQ)
|
5847 |
|
|
{
|
5848 |
|
|
first_error (_("can't use Neon quad register here"));
|
5849 |
|
|
return FAIL;
|
5850 |
|
|
}
|
5851 |
|
|
else if (rtype != REG_TYPE_VFS)
|
5852 |
|
|
{
|
5853 |
|
|
i++;
|
5854 |
|
|
if (skip_past_comma (&ptr) == FAIL)
|
5855 |
|
|
goto wanted_comma;
|
5856 |
|
|
if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
|
5857 |
|
|
goto wanted_arm;
|
5858 |
|
|
inst.operands[i].reg = val;
|
5859 |
|
|
inst.operands[i].isreg = 1;
|
5860 |
|
|
inst.operands[i].present = 1;
|
5861 |
|
|
}
|
5862 |
|
|
}
|
5863 |
|
|
else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
|
5864 |
|
|
&optype)) != FAIL)
|
5865 |
|
|
{
|
5866 |
|
|
/* Case 0: VMOV<c><q> <Qd>, <Qm>
|
5867 |
|
|
Case 1: VMOV<c><q> <Dd>, <Dm>
|
5868 |
|
|
Case 8: VMOV.F32 <Sd>, <Sm>
|
5869 |
|
|
Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
|
5870 |
|
|
|
5871 |
|
|
inst.operands[i].reg = val;
|
5872 |
|
|
inst.operands[i].isreg = 1;
|
5873 |
|
|
inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
|
5874 |
|
|
inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
|
5875 |
|
|
inst.operands[i].isvec = 1;
|
5876 |
|
|
inst.operands[i].vectype = optype;
|
5877 |
|
|
inst.operands[i].present = 1;
|
5878 |
|
|
|
5879 |
|
|
if (skip_past_comma (&ptr) == SUCCESS)
|
5880 |
|
|
{
|
5881 |
|
|
/* Case 15. */
|
5882 |
|
|
i++;
|
5883 |
|
|
|
5884 |
|
|
if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
|
5885 |
|
|
goto wanted_arm;
|
5886 |
|
|
|
5887 |
|
|
inst.operands[i].reg = val;
|
5888 |
|
|
inst.operands[i].isreg = 1;
|
5889 |
|
|
inst.operands[i++].present = 1;
|
5890 |
|
|
|
5891 |
|
|
if (skip_past_comma (&ptr) == FAIL)
|
5892 |
|
|
goto wanted_comma;
|
5893 |
|
|
|
5894 |
|
|
if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
|
5895 |
|
|
goto wanted_arm;
|
5896 |
|
|
|
5897 |
|
|
inst.operands[i].reg = val;
|
5898 |
|
|
inst.operands[i].isreg = 1;
|
5899 |
|
|
inst.operands[i++].present = 1;
|
5900 |
|
|
}
|
5901 |
|
|
}
|
5902 |
|
|
else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
|
5903 |
|
|
/* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
|
5904 |
|
|
Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
|
5905 |
|
|
Case 10: VMOV.F32 <Sd>, #<imm>
|
5906 |
|
|
Case 11: VMOV.F64 <Dd>, #<imm> */
|
5907 |
|
|
inst.operands[i].immisfloat = 1;
|
5908 |
|
|
else if (parse_big_immediate (&ptr, i) == SUCCESS)
|
5909 |
|
|
/* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
|
5910 |
|
|
Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
|
5911 |
|
|
;
|
5912 |
|
|
else
|
5913 |
|
|
{
|
5914 |
|
|
first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
|
5915 |
|
|
return FAIL;
|
5916 |
|
|
}
|
5917 |
|
|
}
|
5918 |
|
|
else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
|
5919 |
|
|
{
|
5920 |
|
|
/* Cases 6, 7. */
|
5921 |
|
|
inst.operands[i].reg = val;
|
5922 |
|
|
inst.operands[i].isreg = 1;
|
5923 |
|
|
inst.operands[i++].present = 1;
|
5924 |
|
|
|
5925 |
|
|
if (skip_past_comma (&ptr) == FAIL)
|
5926 |
|
|
goto wanted_comma;
|
5927 |
|
|
|
5928 |
|
|
if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
|
5929 |
|
|
{
|
5930 |
|
|
/* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
|
5931 |
|
|
inst.operands[i].reg = val;
|
5932 |
|
|
inst.operands[i].isscalar = 1;
|
5933 |
|
|
inst.operands[i].present = 1;
|
5934 |
|
|
inst.operands[i].vectype = optype;
|
5935 |
|
|
}
|
5936 |
|
|
else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
|
5937 |
|
|
{
|
5938 |
|
|
/* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
|
5939 |
|
|
inst.operands[i].reg = val;
|
5940 |
|
|
inst.operands[i].isreg = 1;
|
5941 |
|
|
inst.operands[i++].present = 1;
|
5942 |
|
|
|
5943 |
|
|
if (skip_past_comma (&ptr) == FAIL)
|
5944 |
|
|
goto wanted_comma;
|
5945 |
|
|
|
5946 |
|
|
if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
|
5947 |
|
|
== FAIL)
|
5948 |
|
|
{
|
5949 |
|
|
first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
|
5950 |
|
|
return FAIL;
|
5951 |
|
|
}
|
5952 |
|
|
|
5953 |
|
|
inst.operands[i].reg = val;
|
5954 |
|
|
inst.operands[i].isreg = 1;
|
5955 |
|
|
inst.operands[i].isvec = 1;
|
5956 |
|
|
inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
|
5957 |
|
|
inst.operands[i].vectype = optype;
|
5958 |
|
|
inst.operands[i].present = 1;
|
5959 |
|
|
|
5960 |
|
|
if (rtype == REG_TYPE_VFS)
|
5961 |
|
|
{
|
5962 |
|
|
/* Case 14. */
|
5963 |
|
|
i++;
|
5964 |
|
|
if (skip_past_comma (&ptr) == FAIL)
|
5965 |
|
|
goto wanted_comma;
|
5966 |
|
|
if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
|
5967 |
|
|
&optype)) == FAIL)
|
5968 |
|
|
{
|
5969 |
|
|
first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
|
5970 |
|
|
return FAIL;
|
5971 |
|
|
}
|
5972 |
|
|
inst.operands[i].reg = val;
|
5973 |
|
|
inst.operands[i].isreg = 1;
|
5974 |
|
|
inst.operands[i].isvec = 1;
|
5975 |
|
|
inst.operands[i].issingle = 1;
|
5976 |
|
|
inst.operands[i].vectype = optype;
|
5977 |
|
|
inst.operands[i].present = 1;
|
5978 |
|
|
}
|
5979 |
|
|
}
|
5980 |
|
|
else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
|
5981 |
|
|
!= FAIL)
|
5982 |
|
|
{
|
5983 |
|
|
/* Case 13. */
|
5984 |
|
|
inst.operands[i].reg = val;
|
5985 |
|
|
inst.operands[i].isreg = 1;
|
5986 |
|
|
inst.operands[i].isvec = 1;
|
5987 |
|
|
inst.operands[i].issingle = 1;
|
5988 |
|
|
inst.operands[i].vectype = optype;
|
5989 |
|
|
inst.operands[i++].present = 1;
|
5990 |
|
|
}
|
5991 |
|
|
}
|
5992 |
|
|
else
|
5993 |
|
|
{
|
5994 |
|
|
first_error (_("parse error"));
|
5995 |
|
|
return FAIL;
|
5996 |
|
|
}
|
5997 |
|
|
|
5998 |
|
|
/* Successfully parsed the operands. Update args. */
|
5999 |
|
|
*which_operand = i;
|
6000 |
|
|
*str = ptr;
|
6001 |
|
|
return SUCCESS;
|
6002 |
|
|
|
6003 |
|
|
wanted_comma:
|
6004 |
|
|
first_error (_("expected comma"));
|
6005 |
|
|
return FAIL;
|
6006 |
|
|
|
6007 |
|
|
wanted_arm:
|
6008 |
|
|
first_error (_(reg_expected_msgs[REG_TYPE_RN]));
|
6009 |
|
|
return FAIL;
|
6010 |
|
|
}
|
6011 |
|
|
|
6012 |
|
|
/* Use this macro when the operand constraints are different
|
6013 |
|
|
for ARM and THUMB (e.g. ldrd). */
|
6014 |
|
|
#define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
|
6015 |
|
|
((arm_operand) | ((thumb_operand) << 16))
|
6016 |
|
|
|
6017 |
|
|
/* Matcher codes for parse_operands. */
|
6018 |
|
|
enum operand_parse_code
|
6019 |
|
|
{
|
6020 |
|
|
OP_stop, /* end of line */
|
6021 |
|
|
|
6022 |
|
|
OP_RR, /* ARM register */
|
6023 |
|
|
OP_RRnpc, /* ARM register, not r15 */
|
6024 |
|
|
OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
|
6025 |
|
|
OP_RRnpcb, /* ARM register, not r15, in square brackets */
|
6026 |
|
|
OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
|
6027 |
|
|
optional trailing ! */
|
6028 |
|
|
OP_RRw, /* ARM register, not r15, optional trailing ! */
|
6029 |
|
|
OP_RCP, /* Coprocessor number */
|
6030 |
|
|
OP_RCN, /* Coprocessor register */
|
6031 |
|
|
OP_RF, /* FPA register */
|
6032 |
|
|
OP_RVS, /* VFP single precision register */
|
6033 |
|
|
OP_RVD, /* VFP double precision register (0..15) */
|
6034 |
|
|
OP_RND, /* Neon double precision register (0..31) */
|
6035 |
|
|
OP_RNQ, /* Neon quad precision register */
|
6036 |
|
|
OP_RVSD, /* VFP single or double precision register */
|
6037 |
|
|
OP_RNDQ, /* Neon double or quad precision register */
|
6038 |
|
|
OP_RNSDQ, /* Neon single, double or quad precision register */
|
6039 |
|
|
OP_RNSC, /* Neon scalar D[X] */
|
6040 |
|
|
OP_RVC, /* VFP control register */
|
6041 |
|
|
OP_RMF, /* Maverick F register */
|
6042 |
|
|
OP_RMD, /* Maverick D register */
|
6043 |
|
|
OP_RMFX, /* Maverick FX register */
|
6044 |
|
|
OP_RMDX, /* Maverick DX register */
|
6045 |
|
|
OP_RMAX, /* Maverick AX register */
|
6046 |
|
|
OP_RMDS, /* Maverick DSPSC register */
|
6047 |
|
|
OP_RIWR, /* iWMMXt wR register */
|
6048 |
|
|
OP_RIWC, /* iWMMXt wC register */
|
6049 |
|
|
OP_RIWG, /* iWMMXt wCG register */
|
6050 |
|
|
OP_RXA, /* XScale accumulator register */
|
6051 |
|
|
|
6052 |
|
|
OP_REGLST, /* ARM register list */
|
6053 |
|
|
OP_VRSLST, /* VFP single-precision register list */
|
6054 |
|
|
OP_VRDLST, /* VFP double-precision register list */
|
6055 |
|
|
OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
|
6056 |
|
|
OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
|
6057 |
|
|
OP_NSTRLST, /* Neon element/structure list */
|
6058 |
|
|
|
6059 |
|
|
OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
|
6060 |
|
|
OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
|
6061 |
|
|
OP_RR_RNSC, /* ARM reg or Neon scalar. */
|
6062 |
|
|
OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
|
6063 |
|
|
OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
|
6064 |
|
|
OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
|
6065 |
|
|
OP_VMOV, /* Neon VMOV operands. */
|
6066 |
|
|
OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
|
6067 |
|
|
OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
|
6068 |
|
|
OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
|
6069 |
|
|
|
6070 |
|
|
OP_I0, /* immediate zero */
|
6071 |
|
|
OP_I7, /* immediate value 0 .. 7 */
|
6072 |
|
|
OP_I15, /* 0 .. 15 */
|
6073 |
|
|
OP_I16, /* 1 .. 16 */
|
6074 |
|
|
OP_I16z, /* 0 .. 16 */
|
6075 |
|
|
OP_I31, /* 0 .. 31 */
|
6076 |
|
|
OP_I31w, /* 0 .. 31, optional trailing ! */
|
6077 |
|
|
OP_I32, /* 1 .. 32 */
|
6078 |
|
|
OP_I32z, /* 0 .. 32 */
|
6079 |
|
|
OP_I63, /* 0 .. 63 */
|
6080 |
|
|
OP_I63s, /* -64 .. 63 */
|
6081 |
|
|
OP_I64, /* 1 .. 64 */
|
6082 |
|
|
OP_I64z, /* 0 .. 64 */
|
6083 |
|
|
OP_I255, /* 0 .. 255 */
|
6084 |
|
|
|
6085 |
|
|
OP_I4b, /* immediate, prefix optional, 1 .. 4 */
|
6086 |
|
|
OP_I7b, /* 0 .. 7 */
|
6087 |
|
|
OP_I15b, /* 0 .. 15 */
|
6088 |
|
|
OP_I31b, /* 0 .. 31 */
|
6089 |
|
|
|
6090 |
|
|
OP_SH, /* shifter operand */
|
6091 |
|
|
OP_SHG, /* shifter operand with possible group relocation */
|
6092 |
|
|
OP_ADDR, /* Memory address expression (any mode) */
|
6093 |
|
|
OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
|
6094 |
|
|
OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
|
6095 |
|
|
OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
|
6096 |
|
|
OP_EXP, /* arbitrary expression */
|
6097 |
|
|
OP_EXPi, /* same, with optional immediate prefix */
|
6098 |
|
|
OP_EXPr, /* same, with optional relocation suffix */
|
6099 |
|
|
OP_HALF, /* 0 .. 65535 or low/high reloc. */
|
6100 |
|
|
|
6101 |
|
|
OP_CPSF, /* CPS flags */
|
6102 |
|
|
OP_ENDI, /* Endianness specifier */
|
6103 |
|
|
OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
|
6104 |
|
|
OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
|
6105 |
|
|
OP_COND, /* conditional code */
|
6106 |
|
|
OP_TB, /* Table branch. */
|
6107 |
|
|
|
6108 |
|
|
OP_APSR_RR, /* ARM register or "APSR_nzcv". */
|
6109 |
|
|
|
6110 |
|
|
OP_RRnpc_I0, /* ARM register or literal 0 */
|
6111 |
|
|
OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
|
6112 |
|
|
OP_RR_EXi, /* ARM register or expression with imm prefix */
|
6113 |
|
|
OP_RF_IF, /* FPA register or immediate */
|
6114 |
|
|
OP_RIWR_RIWC, /* iWMMXt R or C reg */
|
6115 |
|
|
OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
|
6116 |
|
|
|
6117 |
|
|
/* Optional operands. */
|
6118 |
|
|
OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
|
6119 |
|
|
OP_oI31b, /* 0 .. 31 */
|
6120 |
|
|
OP_oI32b, /* 1 .. 32 */
|
6121 |
|
|
OP_oIffffb, /* 0 .. 65535 */
|
6122 |
|
|
OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
|
6123 |
|
|
|
6124 |
|
|
OP_oRR, /* ARM register */
|
6125 |
|
|
OP_oRRnpc, /* ARM register, not the PC */
|
6126 |
|
|
OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
|
6127 |
|
|
OP_oRRw, /* ARM register, not r15, optional trailing ! */
|
6128 |
|
|
OP_oRND, /* Optional Neon double precision register */
|
6129 |
|
|
OP_oRNQ, /* Optional Neon quad precision register */
|
6130 |
|
|
OP_oRNDQ, /* Optional Neon double or quad precision register */
|
6131 |
|
|
OP_oRNSDQ, /* Optional single, double or quad precision vector register */
|
6132 |
|
|
OP_oSHll, /* LSL immediate */
|
6133 |
|
|
OP_oSHar, /* ASR immediate */
|
6134 |
|
|
OP_oSHllar, /* LSL or ASR immediate */
|
6135 |
|
|
OP_oROR, /* ROR 0/8/16/24 */
|
6136 |
|
|
OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
|
6137 |
|
|
|
6138 |
|
|
/* Some pre-defined mixed (ARM/THUMB) operands. */
|
6139 |
|
|
OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
|
6140 |
|
|
OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
|
6141 |
|
|
OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
|
6142 |
|
|
|
6143 |
|
|
OP_FIRST_OPTIONAL = OP_oI7b
|
6144 |
|
|
};
|
6145 |
|
|
|
6146 |
|
|
/* Generic instruction operand parser. This does no encoding and no
|
6147 |
|
|
semantic validation; it merely squirrels values away in the inst
|
6148 |
|
|
structure. Returns SUCCESS or FAIL depending on whether the
|
6149 |
|
|
specified grammar matched. */
|
6150 |
|
|
static int
|
6151 |
|
|
parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
|
6152 |
|
|
{
|
6153 |
|
|
unsigned const int *upat = pattern;
|
6154 |
|
|
char *backtrack_pos = 0;
|
6155 |
|
|
const char *backtrack_error = 0;
|
6156 |
|
|
int i, val, backtrack_index = 0;
|
6157 |
|
|
enum arm_reg_type rtype;
|
6158 |
|
|
parse_operand_result result;
|
6159 |
|
|
unsigned int op_parse_code;
|
6160 |
|
|
|
6161 |
|
|
#define po_char_or_fail(chr) \
|
6162 |
|
|
do \
|
6163 |
|
|
{ \
|
6164 |
|
|
if (skip_past_char (&str, chr) == FAIL) \
|
6165 |
|
|
goto bad_args; \
|
6166 |
|
|
} \
|
6167 |
|
|
while (0)
|
6168 |
|
|
|
6169 |
|
|
#define po_reg_or_fail(regtype) \
|
6170 |
|
|
do \
|
6171 |
|
|
{ \
|
6172 |
|
|
val = arm_typed_reg_parse (& str, regtype, & rtype, \
|
6173 |
|
|
& inst.operands[i].vectype); \
|
6174 |
|
|
if (val == FAIL) \
|
6175 |
|
|
{ \
|
6176 |
|
|
first_error (_(reg_expected_msgs[regtype])); \
|
6177 |
|
|
goto failure; \
|
6178 |
|
|
} \
|
6179 |
|
|
inst.operands[i].reg = val; \
|
6180 |
|
|
inst.operands[i].isreg = 1; \
|
6181 |
|
|
inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
|
6182 |
|
|
inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
|
6183 |
|
|
inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
|
6184 |
|
|
|| rtype == REG_TYPE_VFD \
|
6185 |
|
|
|| rtype == REG_TYPE_NQ); \
|
6186 |
|
|
} \
|
6187 |
|
|
while (0)
|
6188 |
|
|
|
6189 |
|
|
#define po_reg_or_goto(regtype, label) \
|
6190 |
|
|
do \
|
6191 |
|
|
{ \
|
6192 |
|
|
val = arm_typed_reg_parse (& str, regtype, & rtype, \
|
6193 |
|
|
& inst.operands[i].vectype); \
|
6194 |
|
|
if (val == FAIL) \
|
6195 |
|
|
goto label; \
|
6196 |
|
|
\
|
6197 |
|
|
inst.operands[i].reg = val; \
|
6198 |
|
|
inst.operands[i].isreg = 1; \
|
6199 |
|
|
inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
|
6200 |
|
|
inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
|
6201 |
|
|
inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
|
6202 |
|
|
|| rtype == REG_TYPE_VFD \
|
6203 |
|
|
|| rtype == REG_TYPE_NQ); \
|
6204 |
|
|
} \
|
6205 |
|
|
while (0)
|
6206 |
|
|
|
6207 |
|
|
#define po_imm_or_fail(min, max, popt) \
|
6208 |
|
|
do \
|
6209 |
|
|
{ \
|
6210 |
|
|
if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
|
6211 |
|
|
goto failure; \
|
6212 |
|
|
inst.operands[i].imm = val; \
|
6213 |
|
|
} \
|
6214 |
|
|
while (0)
|
6215 |
|
|
|
6216 |
|
|
#define po_scalar_or_goto(elsz, label) \
|
6217 |
|
|
do \
|
6218 |
|
|
{ \
|
6219 |
|
|
val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
|
6220 |
|
|
if (val == FAIL) \
|
6221 |
|
|
goto label; \
|
6222 |
|
|
inst.operands[i].reg = val; \
|
6223 |
|
|
inst.operands[i].isscalar = 1; \
|
6224 |
|
|
} \
|
6225 |
|
|
while (0)
|
6226 |
|
|
|
6227 |
|
|
#define po_misc_or_fail(expr) \
|
6228 |
|
|
do \
|
6229 |
|
|
{ \
|
6230 |
|
|
if (expr) \
|
6231 |
|
|
goto failure; \
|
6232 |
|
|
} \
|
6233 |
|
|
while (0)
|
6234 |
|
|
|
6235 |
|
|
#define po_misc_or_fail_no_backtrack(expr) \
|
6236 |
|
|
do \
|
6237 |
|
|
{ \
|
6238 |
|
|
result = expr; \
|
6239 |
|
|
if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
|
6240 |
|
|
backtrack_pos = 0; \
|
6241 |
|
|
if (result != PARSE_OPERAND_SUCCESS) \
|
6242 |
|
|
goto failure; \
|
6243 |
|
|
} \
|
6244 |
|
|
while (0)
|
6245 |
|
|
|
6246 |
|
|
#define po_barrier_or_imm(str) \
|
6247 |
|
|
do \
|
6248 |
|
|
{ \
|
6249 |
|
|
val = parse_barrier (&str); \
|
6250 |
|
|
if (val == FAIL) \
|
6251 |
|
|
{ \
|
6252 |
|
|
if (ISALPHA (*str)) \
|
6253 |
|
|
goto failure; \
|
6254 |
|
|
else \
|
6255 |
|
|
goto immediate; \
|
6256 |
|
|
} \
|
6257 |
|
|
else \
|
6258 |
|
|
{ \
|
6259 |
|
|
if ((inst.instruction & 0xf0) == 0x60 \
|
6260 |
|
|
&& val != 0xf) \
|
6261 |
|
|
{ \
|
6262 |
|
|
/* ISB can only take SY as an option. */ \
|
6263 |
|
|
inst.error = _("invalid barrier type"); \
|
6264 |
|
|
goto failure; \
|
6265 |
|
|
} \
|
6266 |
|
|
} \
|
6267 |
|
|
} \
|
6268 |
|
|
while (0)
|
6269 |
|
|
|
6270 |
|
|
skip_whitespace (str);
|
6271 |
|
|
|
6272 |
|
|
for (i = 0; upat[i] != OP_stop; i++)
|
6273 |
|
|
{
|
6274 |
|
|
op_parse_code = upat[i];
|
6275 |
|
|
if (op_parse_code >= 1<<16)
|
6276 |
|
|
op_parse_code = thumb ? (op_parse_code >> 16)
|
6277 |
|
|
: (op_parse_code & ((1<<16)-1));
|
6278 |
|
|
|
6279 |
|
|
if (op_parse_code >= OP_FIRST_OPTIONAL)
|
6280 |
|
|
{
|
6281 |
|
|
/* Remember where we are in case we need to backtrack. */
|
6282 |
|
|
gas_assert (!backtrack_pos);
|
6283 |
|
|
backtrack_pos = str;
|
6284 |
|
|
backtrack_error = inst.error;
|
6285 |
|
|
backtrack_index = i;
|
6286 |
|
|
}
|
6287 |
|
|
|
6288 |
|
|
if (i > 0 && (i > 1 || inst.operands[0].present))
|
6289 |
|
|
po_char_or_fail (',');
|
6290 |
|
|
|
6291 |
|
|
switch (op_parse_code)
|
6292 |
|
|
{
|
6293 |
|
|
/* Registers */
|
6294 |
|
|
case OP_oRRnpc:
|
6295 |
|
|
case OP_oRRnpcsp:
|
6296 |
|
|
case OP_RRnpc:
|
6297 |
|
|
case OP_RRnpcsp:
|
6298 |
|
|
case OP_oRR:
|
6299 |
|
|
case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
|
6300 |
|
|
case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
|
6301 |
|
|
case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
|
6302 |
|
|
case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
|
6303 |
|
|
case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
|
6304 |
|
|
case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
|
6305 |
|
|
case OP_oRND:
|
6306 |
|
|
case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
|
6307 |
|
|
case OP_RVC:
|
6308 |
|
|
po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
|
6309 |
|
|
break;
|
6310 |
|
|
/* Also accept generic coprocessor regs for unknown registers. */
|
6311 |
|
|
coproc_reg:
|
6312 |
|
|
po_reg_or_fail (REG_TYPE_CN);
|
6313 |
|
|
break;
|
6314 |
|
|
case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
|
6315 |
|
|
case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
|
6316 |
|
|
case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
|
6317 |
|
|
case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
|
6318 |
|
|
case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
|
6319 |
|
|
case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
|
6320 |
|
|
case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
|
6321 |
|
|
case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
|
6322 |
|
|
case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
|
6323 |
|
|
case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
|
6324 |
|
|
case OP_oRNQ:
|
6325 |
|
|
case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
|
6326 |
|
|
case OP_oRNDQ:
|
6327 |
|
|
case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
|
6328 |
|
|
case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
|
6329 |
|
|
case OP_oRNSDQ:
|
6330 |
|
|
case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
|
6331 |
|
|
|
6332 |
|
|
/* Neon scalar. Using an element size of 8 means that some invalid
|
6333 |
|
|
scalars are accepted here, so deal with those in later code. */
|
6334 |
|
|
case OP_RNSC: po_scalar_or_goto (8, failure); break;
|
6335 |
|
|
|
6336 |
|
|
case OP_RNDQ_I0:
|
6337 |
|
|
{
|
6338 |
|
|
po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
|
6339 |
|
|
break;
|
6340 |
|
|
try_imm0:
|
6341 |
|
|
po_imm_or_fail (0, 0, TRUE);
|
6342 |
|
|
}
|
6343 |
|
|
break;
|
6344 |
|
|
|
6345 |
|
|
case OP_RVSD_I0:
|
6346 |
|
|
po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
|
6347 |
|
|
break;
|
6348 |
|
|
|
6349 |
|
|
case OP_RR_RNSC:
|
6350 |
|
|
{
|
6351 |
|
|
po_scalar_or_goto (8, try_rr);
|
6352 |
|
|
break;
|
6353 |
|
|
try_rr:
|
6354 |
|
|
po_reg_or_fail (REG_TYPE_RN);
|
6355 |
|
|
}
|
6356 |
|
|
break;
|
6357 |
|
|
|
6358 |
|
|
case OP_RNSDQ_RNSC:
|
6359 |
|
|
{
|
6360 |
|
|
po_scalar_or_goto (8, try_nsdq);
|
6361 |
|
|
break;
|
6362 |
|
|
try_nsdq:
|
6363 |
|
|
po_reg_or_fail (REG_TYPE_NSDQ);
|
6364 |
|
|
}
|
6365 |
|
|
break;
|
6366 |
|
|
|
6367 |
|
|
case OP_RNDQ_RNSC:
|
6368 |
|
|
{
|
6369 |
|
|
po_scalar_or_goto (8, try_ndq);
|
6370 |
|
|
break;
|
6371 |
|
|
try_ndq:
|
6372 |
|
|
po_reg_or_fail (REG_TYPE_NDQ);
|
6373 |
|
|
}
|
6374 |
|
|
break;
|
6375 |
|
|
|
6376 |
|
|
case OP_RND_RNSC:
|
6377 |
|
|
{
|
6378 |
|
|
po_scalar_or_goto (8, try_vfd);
|
6379 |
|
|
break;
|
6380 |
|
|
try_vfd:
|
6381 |
|
|
po_reg_or_fail (REG_TYPE_VFD);
|
6382 |
|
|
}
|
6383 |
|
|
break;
|
6384 |
|
|
|
6385 |
|
|
case OP_VMOV:
|
6386 |
|
|
/* WARNING: parse_neon_mov can move the operand counter, i. If we're
|
6387 |
|
|
not careful then bad things might happen. */
|
6388 |
|
|
po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
|
6389 |
|
|
break;
|
6390 |
|
|
|
6391 |
|
|
case OP_RNDQ_Ibig:
|
6392 |
|
|
{
|
6393 |
|
|
po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
|
6394 |
|
|
break;
|
6395 |
|
|
try_immbig:
|
6396 |
|
|
/* There's a possibility of getting a 64-bit immediate here, so
|
6397 |
|
|
we need special handling. */
|
6398 |
|
|
if (parse_big_immediate (&str, i) == FAIL)
|
6399 |
|
|
{
|
6400 |
|
|
inst.error = _("immediate value is out of range");
|
6401 |
|
|
goto failure;
|
6402 |
|
|
}
|
6403 |
|
|
}
|
6404 |
|
|
break;
|
6405 |
|
|
|
6406 |
|
|
case OP_RNDQ_I63b:
|
6407 |
|
|
{
|
6408 |
|
|
po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
|
6409 |
|
|
break;
|
6410 |
|
|
try_shimm:
|
6411 |
|
|
po_imm_or_fail (0, 63, TRUE);
|
6412 |
|
|
}
|
6413 |
|
|
break;
|
6414 |
|
|
|
6415 |
|
|
case OP_RRnpcb:
|
6416 |
|
|
po_char_or_fail ('[');
|
6417 |
|
|
po_reg_or_fail (REG_TYPE_RN);
|
6418 |
|
|
po_char_or_fail (']');
|
6419 |
|
|
break;
|
6420 |
|
|
|
6421 |
|
|
case OP_RRnpctw:
|
6422 |
|
|
case OP_RRw:
|
6423 |
|
|
case OP_oRRw:
|
6424 |
|
|
po_reg_or_fail (REG_TYPE_RN);
|
6425 |
|
|
if (skip_past_char (&str, '!') == SUCCESS)
|
6426 |
|
|
inst.operands[i].writeback = 1;
|
6427 |
|
|
break;
|
6428 |
|
|
|
6429 |
|
|
/* Immediates */
|
6430 |
|
|
case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
|
6431 |
|
|
case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
|
6432 |
|
|
case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
|
6433 |
|
|
case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
|
6434 |
|
|
case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
|
6435 |
|
|
case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
|
6436 |
|
|
case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
|
6437 |
|
|
case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
|
6438 |
|
|
case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
|
6439 |
|
|
case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
|
6440 |
|
|
case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
|
6441 |
|
|
case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
|
6442 |
|
|
|
6443 |
|
|
case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
|
6444 |
|
|
case OP_oI7b:
|
6445 |
|
|
case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
|
6446 |
|
|
case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
|
6447 |
|
|
case OP_oI31b:
|
6448 |
|
|
case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
|
6449 |
|
|
case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
|
6450 |
|
|
case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
|
6451 |
|
|
|
6452 |
|
|
/* Immediate variants */
|
6453 |
|
|
case OP_oI255c:
|
6454 |
|
|
po_char_or_fail ('{');
|
6455 |
|
|
po_imm_or_fail (0, 255, TRUE);
|
6456 |
|
|
po_char_or_fail ('}');
|
6457 |
|
|
break;
|
6458 |
|
|
|
6459 |
|
|
case OP_I31w:
|
6460 |
|
|
/* The expression parser chokes on a trailing !, so we have
|
6461 |
|
|
to find it first and zap it. */
|
6462 |
|
|
{
|
6463 |
|
|
char *s = str;
|
6464 |
|
|
while (*s && *s != ',')
|
6465 |
|
|
s++;
|
6466 |
|
|
if (s[-1] == '!')
|
6467 |
|
|
{
|
6468 |
|
|
s[-1] = '\0';
|
6469 |
|
|
inst.operands[i].writeback = 1;
|
6470 |
|
|
}
|
6471 |
|
|
po_imm_or_fail (0, 31, TRUE);
|
6472 |
|
|
if (str == s - 1)
|
6473 |
|
|
str = s;
|
6474 |
|
|
}
|
6475 |
|
|
break;
|
6476 |
|
|
|
6477 |
|
|
/* Expressions */
|
6478 |
|
|
case OP_EXPi: EXPi:
|
6479 |
|
|
po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
|
6480 |
|
|
GE_OPT_PREFIX));
|
6481 |
|
|
break;
|
6482 |
|
|
|
6483 |
|
|
case OP_EXP:
|
6484 |
|
|
po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
|
6485 |
|
|
GE_NO_PREFIX));
|
6486 |
|
|
break;
|
6487 |
|
|
|
6488 |
|
|
case OP_EXPr: EXPr:
|
6489 |
|
|
po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
|
6490 |
|
|
GE_NO_PREFIX));
|
6491 |
|
|
if (inst.reloc.exp.X_op == O_symbol)
|
6492 |
|
|
{
|
6493 |
|
|
val = parse_reloc (&str);
|
6494 |
|
|
if (val == -1)
|
6495 |
|
|
{
|
6496 |
|
|
inst.error = _("unrecognized relocation suffix");
|
6497 |
|
|
goto failure;
|
6498 |
|
|
}
|
6499 |
|
|
else if (val != BFD_RELOC_UNUSED)
|
6500 |
|
|
{
|
6501 |
|
|
inst.operands[i].imm = val;
|
6502 |
|
|
inst.operands[i].hasreloc = 1;
|
6503 |
|
|
}
|
6504 |
|
|
}
|
6505 |
|
|
break;
|
6506 |
|
|
|
6507 |
|
|
/* Operand for MOVW or MOVT. */
|
6508 |
|
|
case OP_HALF:
|
6509 |
|
|
po_misc_or_fail (parse_half (&str));
|
6510 |
|
|
break;
|
6511 |
|
|
|
6512 |
|
|
/* Register or expression. */
|
6513 |
|
|
case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
|
6514 |
|
|
case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
|
6515 |
|
|
|
6516 |
|
|
/* Register or immediate. */
|
6517 |
|
|
case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
|
6518 |
|
|
I0: po_imm_or_fail (0, 0, FALSE); break;
|
6519 |
|
|
|
6520 |
|
|
case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
|
6521 |
|
|
IF:
|
6522 |
|
|
if (!is_immediate_prefix (*str))
|
6523 |
|
|
goto bad_args;
|
6524 |
|
|
str++;
|
6525 |
|
|
val = parse_fpa_immediate (&str);
|
6526 |
|
|
if (val == FAIL)
|
6527 |
|
|
goto failure;
|
6528 |
|
|
/* FPA immediates are encoded as registers 8-15.
|
6529 |
|
|
parse_fpa_immediate has already applied the offset. */
|
6530 |
|
|
inst.operands[i].reg = val;
|
6531 |
|
|
inst.operands[i].isreg = 1;
|
6532 |
|
|
break;
|
6533 |
|
|
|
6534 |
|
|
case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
|
6535 |
|
|
I32z: po_imm_or_fail (0, 32, FALSE); break;
|
6536 |
|
|
|
6537 |
|
|
/* Two kinds of register. */
|
6538 |
|
|
case OP_RIWR_RIWC:
|
6539 |
|
|
{
|
6540 |
|
|
struct reg_entry *rege = arm_reg_parse_multi (&str);
|
6541 |
|
|
if (!rege
|
6542 |
|
|
|| (rege->type != REG_TYPE_MMXWR
|
6543 |
|
|
&& rege->type != REG_TYPE_MMXWC
|
6544 |
|
|
&& rege->type != REG_TYPE_MMXWCG))
|
6545 |
|
|
{
|
6546 |
|
|
inst.error = _("iWMMXt data or control register expected");
|
6547 |
|
|
goto failure;
|
6548 |
|
|
}
|
6549 |
|
|
inst.operands[i].reg = rege->number;
|
6550 |
|
|
inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
|
6551 |
|
|
}
|
6552 |
|
|
break;
|
6553 |
|
|
|
6554 |
|
|
case OP_RIWC_RIWG:
|
6555 |
|
|
{
|
6556 |
|
|
struct reg_entry *rege = arm_reg_parse_multi (&str);
|
6557 |
|
|
if (!rege
|
6558 |
|
|
|| (rege->type != REG_TYPE_MMXWC
|
6559 |
|
|
&& rege->type != REG_TYPE_MMXWCG))
|
6560 |
|
|
{
|
6561 |
|
|
inst.error = _("iWMMXt control register expected");
|
6562 |
|
|
goto failure;
|
6563 |
|
|
}
|
6564 |
|
|
inst.operands[i].reg = rege->number;
|
6565 |
|
|
inst.operands[i].isreg = 1;
|
6566 |
|
|
}
|
6567 |
|
|
break;
|
6568 |
|
|
|
6569 |
|
|
/* Misc */
|
6570 |
|
|
case OP_CPSF: val = parse_cps_flags (&str); break;
|
6571 |
|
|
case OP_ENDI: val = parse_endian_specifier (&str); break;
|
6572 |
|
|
case OP_oROR: val = parse_ror (&str); break;
|
6573 |
|
|
case OP_COND: val = parse_cond (&str); break;
|
6574 |
|
|
case OP_oBARRIER_I15:
|
6575 |
|
|
po_barrier_or_imm (str); break;
|
6576 |
|
|
immediate:
|
6577 |
|
|
if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
|
6578 |
|
|
goto failure;
|
6579 |
|
|
break;
|
6580 |
|
|
|
6581 |
|
|
case OP_wPSR:
|
6582 |
|
|
case OP_rPSR:
|
6583 |
|
|
po_reg_or_goto (REG_TYPE_RNB, try_psr);
|
6584 |
|
|
if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
|
6585 |
|
|
{
|
6586 |
|
|
inst.error = _("Banked registers are not available with this "
|
6587 |
|
|
"architecture.");
|
6588 |
|
|
goto failure;
|
6589 |
|
|
}
|
6590 |
|
|
break;
|
6591 |
|
|
try_psr:
|
6592 |
|
|
val = parse_psr (&str, op_parse_code == OP_wPSR);
|
6593 |
|
|
break;
|
6594 |
|
|
|
6595 |
|
|
case OP_APSR_RR:
|
6596 |
|
|
po_reg_or_goto (REG_TYPE_RN, try_apsr);
|
6597 |
|
|
break;
|
6598 |
|
|
try_apsr:
|
6599 |
|
|
/* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
|
6600 |
|
|
instruction). */
|
6601 |
|
|
if (strncasecmp (str, "APSR_", 5) == 0)
|
6602 |
|
|
{
|
6603 |
|
|
unsigned found = 0;
|
6604 |
|
|
str += 5;
|
6605 |
|
|
while (found < 15)
|
6606 |
|
|
switch (*str++)
|
6607 |
|
|
{
|
6608 |
|
|
case 'c': found = (found & 1) ? 16 : found | 1; break;
|
6609 |
|
|
case 'n': found = (found & 2) ? 16 : found | 2; break;
|
6610 |
|
|
case 'z': found = (found & 4) ? 16 : found | 4; break;
|
6611 |
|
|
case 'v': found = (found & 8) ? 16 : found | 8; break;
|
6612 |
|
|
default: found = 16;
|
6613 |
|
|
}
|
6614 |
|
|
if (found != 15)
|
6615 |
|
|
goto failure;
|
6616 |
|
|
inst.operands[i].isvec = 1;
|
6617 |
|
|
/* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
|
6618 |
|
|
inst.operands[i].reg = REG_PC;
|
6619 |
|
|
}
|
6620 |
|
|
else
|
6621 |
|
|
goto failure;
|
6622 |
|
|
break;
|
6623 |
|
|
|
6624 |
|
|
case OP_TB:
|
6625 |
|
|
po_misc_or_fail (parse_tb (&str));
|
6626 |
|
|
break;
|
6627 |
|
|
|
6628 |
|
|
/* Register lists. */
|
6629 |
|
|
case OP_REGLST:
|
6630 |
|
|
val = parse_reg_list (&str);
|
6631 |
|
|
if (*str == '^')
|
6632 |
|
|
{
|
6633 |
|
|
inst.operands[1].writeback = 1;
|
6634 |
|
|
str++;
|
6635 |
|
|
}
|
6636 |
|
|
break;
|
6637 |
|
|
|
6638 |
|
|
case OP_VRSLST:
|
6639 |
|
|
val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
|
6640 |
|
|
break;
|
6641 |
|
|
|
6642 |
|
|
case OP_VRDLST:
|
6643 |
|
|
val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
|
6644 |
|
|
break;
|
6645 |
|
|
|
6646 |
|
|
case OP_VRSDLST:
|
6647 |
|
|
/* Allow Q registers too. */
|
6648 |
|
|
val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
|
6649 |
|
|
REGLIST_NEON_D);
|
6650 |
|
|
if (val == FAIL)
|
6651 |
|
|
{
|
6652 |
|
|
inst.error = NULL;
|
6653 |
|
|
val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
|
6654 |
|
|
REGLIST_VFP_S);
|
6655 |
|
|
inst.operands[i].issingle = 1;
|
6656 |
|
|
}
|
6657 |
|
|
break;
|
6658 |
|
|
|
6659 |
|
|
case OP_NRDLST:
|
6660 |
|
|
val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
|
6661 |
|
|
REGLIST_NEON_D);
|
6662 |
|
|
break;
|
6663 |
|
|
|
6664 |
|
|
case OP_NSTRLST:
|
6665 |
|
|
val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
|
6666 |
|
|
&inst.operands[i].vectype);
|
6667 |
|
|
break;
|
6668 |
|
|
|
6669 |
|
|
/* Addressing modes */
|
6670 |
|
|
case OP_ADDR:
|
6671 |
|
|
po_misc_or_fail (parse_address (&str, i));
|
6672 |
|
|
break;
|
6673 |
|
|
|
6674 |
|
|
case OP_ADDRGLDR:
|
6675 |
|
|
po_misc_or_fail_no_backtrack (
|
6676 |
|
|
parse_address_group_reloc (&str, i, GROUP_LDR));
|
6677 |
|
|
break;
|
6678 |
|
|
|
6679 |
|
|
case OP_ADDRGLDRS:
|
6680 |
|
|
po_misc_or_fail_no_backtrack (
|
6681 |
|
|
parse_address_group_reloc (&str, i, GROUP_LDRS));
|
6682 |
|
|
break;
|
6683 |
|
|
|
6684 |
|
|
case OP_ADDRGLDC:
|
6685 |
|
|
po_misc_or_fail_no_backtrack (
|
6686 |
|
|
parse_address_group_reloc (&str, i, GROUP_LDC));
|
6687 |
|
|
break;
|
6688 |
|
|
|
6689 |
|
|
case OP_SH:
|
6690 |
|
|
po_misc_or_fail (parse_shifter_operand (&str, i));
|
6691 |
|
|
break;
|
6692 |
|
|
|
6693 |
|
|
case OP_SHG:
|
6694 |
|
|
po_misc_or_fail_no_backtrack (
|
6695 |
|
|
parse_shifter_operand_group_reloc (&str, i));
|
6696 |
|
|
break;
|
6697 |
|
|
|
6698 |
|
|
case OP_oSHll:
|
6699 |
|
|
po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
|
6700 |
|
|
break;
|
6701 |
|
|
|
6702 |
|
|
case OP_oSHar:
|
6703 |
|
|
po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
|
6704 |
|
|
break;
|
6705 |
|
|
|
6706 |
|
|
case OP_oSHllar:
|
6707 |
|
|
po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
|
6708 |
|
|
break;
|
6709 |
|
|
|
6710 |
|
|
default:
|
6711 |
|
|
as_fatal (_("unhandled operand code %d"), op_parse_code);
|
6712 |
|
|
}
|
6713 |
|
|
|
6714 |
|
|
/* Various value-based sanity checks and shared operations. We
|
6715 |
|
|
do not signal immediate failures for the register constraints;
|
6716 |
|
|
this allows a syntax error to take precedence. */
|
6717 |
|
|
switch (op_parse_code)
|
6718 |
|
|
{
|
6719 |
|
|
case OP_oRRnpc:
|
6720 |
|
|
case OP_RRnpc:
|
6721 |
|
|
case OP_RRnpcb:
|
6722 |
|
|
case OP_RRw:
|
6723 |
|
|
case OP_oRRw:
|
6724 |
|
|
case OP_RRnpc_I0:
|
6725 |
|
|
if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
|
6726 |
|
|
inst.error = BAD_PC;
|
6727 |
|
|
break;
|
6728 |
|
|
|
6729 |
|
|
case OP_oRRnpcsp:
|
6730 |
|
|
case OP_RRnpcsp:
|
6731 |
|
|
if (inst.operands[i].isreg)
|
6732 |
|
|
{
|
6733 |
|
|
if (inst.operands[i].reg == REG_PC)
|
6734 |
|
|
inst.error = BAD_PC;
|
6735 |
|
|
else if (inst.operands[i].reg == REG_SP)
|
6736 |
|
|
inst.error = BAD_SP;
|
6737 |
|
|
}
|
6738 |
|
|
break;
|
6739 |
|
|
|
6740 |
|
|
case OP_RRnpctw:
|
6741 |
|
|
if (inst.operands[i].isreg
|
6742 |
|
|
&& inst.operands[i].reg == REG_PC
|
6743 |
|
|
&& (inst.operands[i].writeback || thumb))
|
6744 |
|
|
inst.error = BAD_PC;
|
6745 |
|
|
break;
|
6746 |
|
|
|
6747 |
|
|
case OP_CPSF:
|
6748 |
|
|
case OP_ENDI:
|
6749 |
|
|
case OP_oROR:
|
6750 |
|
|
case OP_wPSR:
|
6751 |
|
|
case OP_rPSR:
|
6752 |
|
|
case OP_COND:
|
6753 |
|
|
case OP_oBARRIER_I15:
|
6754 |
|
|
case OP_REGLST:
|
6755 |
|
|
case OP_VRSLST:
|
6756 |
|
|
case OP_VRDLST:
|
6757 |
|
|
case OP_VRSDLST:
|
6758 |
|
|
case OP_NRDLST:
|
6759 |
|
|
case OP_NSTRLST:
|
6760 |
|
|
if (val == FAIL)
|
6761 |
|
|
goto failure;
|
6762 |
|
|
inst.operands[i].imm = val;
|
6763 |
|
|
break;
|
6764 |
|
|
|
6765 |
|
|
default:
|
6766 |
|
|
break;
|
6767 |
|
|
}
|
6768 |
|
|
|
6769 |
|
|
/* If we get here, this operand was successfully parsed. */
|
6770 |
|
|
inst.operands[i].present = 1;
|
6771 |
|
|
continue;
|
6772 |
|
|
|
6773 |
|
|
bad_args:
|
6774 |
|
|
inst.error = BAD_ARGS;
|
6775 |
|
|
|
6776 |
|
|
failure:
|
6777 |
|
|
if (!backtrack_pos)
|
6778 |
|
|
{
|
6779 |
|
|
/* The parse routine should already have set inst.error, but set a
|
6780 |
|
|
default here just in case. */
|
6781 |
|
|
if (!inst.error)
|
6782 |
|
|
inst.error = _("syntax error");
|
6783 |
|
|
return FAIL;
|
6784 |
|
|
}
|
6785 |
|
|
|
6786 |
|
|
/* Do not backtrack over a trailing optional argument that
|
6787 |
|
|
absorbed some text. We will only fail again, with the
|
6788 |
|
|
'garbage following instruction' error message, which is
|
6789 |
|
|
probably less helpful than the current one. */
|
6790 |
|
|
if (backtrack_index == i && backtrack_pos != str
|
6791 |
|
|
&& upat[i+1] == OP_stop)
|
6792 |
|
|
{
|
6793 |
|
|
if (!inst.error)
|
6794 |
|
|
inst.error = _("syntax error");
|
6795 |
|
|
return FAIL;
|
6796 |
|
|
}
|
6797 |
|
|
|
6798 |
|
|
/* Try again, skipping the optional argument at backtrack_pos. */
|
6799 |
|
|
str = backtrack_pos;
|
6800 |
|
|
inst.error = backtrack_error;
|
6801 |
|
|
inst.operands[backtrack_index].present = 0;
|
6802 |
|
|
i = backtrack_index;
|
6803 |
|
|
backtrack_pos = 0;
|
6804 |
|
|
}
|
6805 |
|
|
|
6806 |
|
|
/* Check that we have parsed all the arguments. */
|
6807 |
|
|
if (*str != '\0' && !inst.error)
|
6808 |
|
|
inst.error = _("garbage following instruction");
|
6809 |
|
|
|
6810 |
|
|
return inst.error ? FAIL : SUCCESS;
|
6811 |
|
|
}
|
6812 |
|
|
|
6813 |
|
|
#undef po_char_or_fail
|
6814 |
|
|
#undef po_reg_or_fail
|
6815 |
|
|
#undef po_reg_or_goto
|
6816 |
|
|
#undef po_imm_or_fail
|
6817 |
|
|
#undef po_scalar_or_fail
|
6818 |
|
|
#undef po_barrier_or_imm
|
6819 |
|
|
|
6820 |
|
|
/* Shorthand macro for instruction encoding functions issuing errors. */
|
6821 |
|
|
#define constraint(expr, err) \
|
6822 |
|
|
do \
|
6823 |
|
|
{ \
|
6824 |
|
|
if (expr) \
|
6825 |
|
|
{ \
|
6826 |
|
|
inst.error = err; \
|
6827 |
|
|
return; \
|
6828 |
|
|
} \
|
6829 |
|
|
} \
|
6830 |
|
|
while (0)
|
6831 |
|
|
|
6832 |
|
|
/* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
|
6833 |
|
|
instructions are unpredictable if these registers are used. This
|
6834 |
|
|
is the BadReg predicate in ARM's Thumb-2 documentation. */
|
6835 |
|
|
#define reject_bad_reg(reg) \
|
6836 |
|
|
do \
|
6837 |
|
|
if (reg == REG_SP || reg == REG_PC) \
|
6838 |
|
|
{ \
|
6839 |
|
|
inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
|
6840 |
|
|
return; \
|
6841 |
|
|
} \
|
6842 |
|
|
while (0)
|
6843 |
|
|
|
6844 |
|
|
/* If REG is R13 (the stack pointer), warn that its use is
|
6845 |
|
|
deprecated. */
|
6846 |
|
|
#define warn_deprecated_sp(reg) \
|
6847 |
|
|
do \
|
6848 |
|
|
if (warn_on_deprecated && reg == REG_SP) \
|
6849 |
|
|
as_warn (_("use of r13 is deprecated")); \
|
6850 |
|
|
while (0)
|
6851 |
|
|
|
6852 |
|
|
/* Functions for operand encoding. ARM, then Thumb. */
|
6853 |
|
|
|
6854 |
|
|
#define rotate_left(v, n) (v << n | v >> (32 - n))
|
6855 |
|
|
|
6856 |
|
|
/* If VAL can be encoded in the immediate field of an ARM instruction,
|
6857 |
|
|
return the encoded form. Otherwise, return FAIL. */
|
6858 |
|
|
|
6859 |
|
|
static unsigned int
|
6860 |
|
|
encode_arm_immediate (unsigned int val)
|
6861 |
|
|
{
|
6862 |
|
|
unsigned int a, i;
|
6863 |
|
|
|
6864 |
|
|
for (i = 0; i < 32; i += 2)
|
6865 |
|
|
if ((a = rotate_left (val, i)) <= 0xff)
|
6866 |
|
|
return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
|
6867 |
|
|
|
6868 |
|
|
return FAIL;
|
6869 |
|
|
}
|
6870 |
|
|
|
6871 |
|
|
/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
|
6872 |
|
|
return the encoded form. Otherwise, return FAIL. */
|
6873 |
|
|
static unsigned int
|
6874 |
|
|
encode_thumb32_immediate (unsigned int val)
|
6875 |
|
|
{
|
6876 |
|
|
unsigned int a, i;
|
6877 |
|
|
|
6878 |
|
|
if (val <= 0xff)
|
6879 |
|
|
return val;
|
6880 |
|
|
|
6881 |
|
|
for (i = 1; i <= 24; i++)
|
6882 |
|
|
{
|
6883 |
|
|
a = val >> i;
|
6884 |
|
|
if ((val & ~(0xff << i)) == 0)
|
6885 |
|
|
return ((val >> i) & 0x7f) | ((32 - i) << 7);
|
6886 |
|
|
}
|
6887 |
|
|
|
6888 |
|
|
a = val & 0xff;
|
6889 |
|
|
if (val == ((a << 16) | a))
|
6890 |
|
|
return 0x100 | a;
|
6891 |
|
|
if (val == ((a << 24) | (a << 16) | (a << 8) | a))
|
6892 |
|
|
return 0x300 | a;
|
6893 |
|
|
|
6894 |
|
|
a = val & 0xff00;
|
6895 |
|
|
if (val == ((a << 16) | a))
|
6896 |
|
|
return 0x200 | (a >> 8);
|
6897 |
|
|
|
6898 |
|
|
return FAIL;
|
6899 |
|
|
}
|
6900 |
|
|
/* Encode a VFP SP or DP register number into inst.instruction. */
|
6901 |
|
|
|
6902 |
|
|
static void
|
6903 |
|
|
encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
|
6904 |
|
|
{
|
6905 |
|
|
if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
|
6906 |
|
|
&& reg > 15)
|
6907 |
|
|
{
|
6908 |
|
|
if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
|
6909 |
|
|
{
|
6910 |
|
|
if (thumb_mode)
|
6911 |
|
|
ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
|
6912 |
|
|
fpu_vfp_ext_d32);
|
6913 |
|
|
else
|
6914 |
|
|
ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
|
6915 |
|
|
fpu_vfp_ext_d32);
|
6916 |
|
|
}
|
6917 |
|
|
else
|
6918 |
|
|
{
|
6919 |
|
|
first_error (_("D register out of range for selected VFP version"));
|
6920 |
|
|
return;
|
6921 |
|
|
}
|
6922 |
|
|
}
|
6923 |
|
|
|
6924 |
|
|
switch (pos)
|
6925 |
|
|
{
|
6926 |
|
|
case VFP_REG_Sd:
|
6927 |
|
|
inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
|
6928 |
|
|
break;
|
6929 |
|
|
|
6930 |
|
|
case VFP_REG_Sn:
|
6931 |
|
|
inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
|
6932 |
|
|
break;
|
6933 |
|
|
|
6934 |
|
|
case VFP_REG_Sm:
|
6935 |
|
|
inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
|
6936 |
|
|
break;
|
6937 |
|
|
|
6938 |
|
|
case VFP_REG_Dd:
|
6939 |
|
|
inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
|
6940 |
|
|
break;
|
6941 |
|
|
|
6942 |
|
|
case VFP_REG_Dn:
|
6943 |
|
|
inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
|
6944 |
|
|
break;
|
6945 |
|
|
|
6946 |
|
|
case VFP_REG_Dm:
|
6947 |
|
|
inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
|
6948 |
|
|
break;
|
6949 |
|
|
|
6950 |
|
|
default:
|
6951 |
|
|
abort ();
|
6952 |
|
|
}
|
6953 |
|
|
}
|
6954 |
|
|
|
6955 |
|
|
/* Encode a <shift> in an ARM-format instruction. The immediate,
|
6956 |
|
|
if any, is handled by md_apply_fix. */
|
6957 |
|
|
static void
|
6958 |
|
|
encode_arm_shift (int i)
|
6959 |
|
|
{
|
6960 |
|
|
if (inst.operands[i].shift_kind == SHIFT_RRX)
|
6961 |
|
|
inst.instruction |= SHIFT_ROR << 5;
|
6962 |
|
|
else
|
6963 |
|
|
{
|
6964 |
|
|
inst.instruction |= inst.operands[i].shift_kind << 5;
|
6965 |
|
|
if (inst.operands[i].immisreg)
|
6966 |
|
|
{
|
6967 |
|
|
inst.instruction |= SHIFT_BY_REG;
|
6968 |
|
|
inst.instruction |= inst.operands[i].imm << 8;
|
6969 |
|
|
}
|
6970 |
|
|
else
|
6971 |
|
|
inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
|
6972 |
|
|
}
|
6973 |
|
|
}
|
6974 |
|
|
|
6975 |
|
|
static void
|
6976 |
|
|
encode_arm_shifter_operand (int i)
|
6977 |
|
|
{
|
6978 |
|
|
if (inst.operands[i].isreg)
|
6979 |
|
|
{
|
6980 |
|
|
inst.instruction |= inst.operands[i].reg;
|
6981 |
|
|
encode_arm_shift (i);
|
6982 |
|
|
}
|
6983 |
|
|
else
|
6984 |
|
|
inst.instruction |= INST_IMMEDIATE;
|
6985 |
|
|
}
|
6986 |
|
|
|
6987 |
|
|
/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
|
6988 |
|
|
static void
|
6989 |
|
|
encode_arm_addr_mode_common (int i, bfd_boolean is_t)
|
6990 |
|
|
{
|
6991 |
|
|
gas_assert (inst.operands[i].isreg);
|
6992 |
|
|
inst.instruction |= inst.operands[i].reg << 16;
|
6993 |
|
|
|
6994 |
|
|
if (inst.operands[i].preind)
|
6995 |
|
|
{
|
6996 |
|
|
if (is_t)
|
6997 |
|
|
{
|
6998 |
|
|
inst.error = _("instruction does not accept preindexed addressing");
|
6999 |
|
|
return;
|
7000 |
|
|
}
|
7001 |
|
|
inst.instruction |= PRE_INDEX;
|
7002 |
|
|
if (inst.operands[i].writeback)
|
7003 |
|
|
inst.instruction |= WRITE_BACK;
|
7004 |
|
|
|
7005 |
|
|
}
|
7006 |
|
|
else if (inst.operands[i].postind)
|
7007 |
|
|
{
|
7008 |
|
|
gas_assert (inst.operands[i].writeback);
|
7009 |
|
|
if (is_t)
|
7010 |
|
|
inst.instruction |= WRITE_BACK;
|
7011 |
|
|
}
|
7012 |
|
|
else /* unindexed - only for coprocessor */
|
7013 |
|
|
{
|
7014 |
|
|
inst.error = _("instruction does not accept unindexed addressing");
|
7015 |
|
|
return;
|
7016 |
|
|
}
|
7017 |
|
|
|
7018 |
|
|
if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
|
7019 |
|
|
&& (((inst.instruction & 0x000f0000) >> 16)
|
7020 |
|
|
== ((inst.instruction & 0x0000f000) >> 12)))
|
7021 |
|
|
as_warn ((inst.instruction & LOAD_BIT)
|
7022 |
|
|
? _("destination register same as write-back base")
|
7023 |
|
|
: _("source register same as write-back base"));
|
7024 |
|
|
}
|
7025 |
|
|
|
7026 |
|
|
/* inst.operands[i] was set up by parse_address. Encode it into an
|
7027 |
|
|
ARM-format mode 2 load or store instruction. If is_t is true,
|
7028 |
|
|
reject forms that cannot be used with a T instruction (i.e. not
|
7029 |
|
|
post-indexed). */
|
7030 |
|
|
static void
|
7031 |
|
|
encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
|
7032 |
|
|
{
|
7033 |
|
|
const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
|
7034 |
|
|
|
7035 |
|
|
encode_arm_addr_mode_common (i, is_t);
|
7036 |
|
|
|
7037 |
|
|
if (inst.operands[i].immisreg)
|
7038 |
|
|
{
|
7039 |
|
|
constraint ((inst.operands[i].imm == REG_PC
|
7040 |
|
|
|| (is_pc && inst.operands[i].writeback)),
|
7041 |
|
|
BAD_PC_ADDRESSING);
|
7042 |
|
|
inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
|
7043 |
|
|
inst.instruction |= inst.operands[i].imm;
|
7044 |
|
|
if (!inst.operands[i].negative)
|
7045 |
|
|
inst.instruction |= INDEX_UP;
|
7046 |
|
|
if (inst.operands[i].shifted)
|
7047 |
|
|
{
|
7048 |
|
|
if (inst.operands[i].shift_kind == SHIFT_RRX)
|
7049 |
|
|
inst.instruction |= SHIFT_ROR << 5;
|
7050 |
|
|
else
|
7051 |
|
|
{
|
7052 |
|
|
inst.instruction |= inst.operands[i].shift_kind << 5;
|
7053 |
|
|
inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
|
7054 |
|
|
}
|
7055 |
|
|
}
|
7056 |
|
|
}
|
7057 |
|
|
else /* immediate offset in inst.reloc */
|
7058 |
|
|
{
|
7059 |
|
|
if (is_pc && !inst.reloc.pc_rel)
|
7060 |
|
|
{
|
7061 |
|
|
const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
|
7062 |
|
|
|
7063 |
|
|
/* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
|
7064 |
|
|
cannot use PC in addressing.
|
7065 |
|
|
PC cannot be used in writeback addressing, either. */
|
7066 |
|
|
constraint ((is_t || inst.operands[i].writeback),
|
7067 |
|
|
BAD_PC_ADDRESSING);
|
7068 |
|
|
|
7069 |
|
|
/* Use of PC in str is deprecated for ARMv7. */
|
7070 |
|
|
if (warn_on_deprecated
|
7071 |
|
|
&& !is_load
|
7072 |
|
|
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
|
7073 |
|
|
as_warn (_("use of PC in this instruction is deprecated"));
|
7074 |
|
|
}
|
7075 |
|
|
|
7076 |
|
|
if (inst.reloc.type == BFD_RELOC_UNUSED)
|
7077 |
|
|
{
|
7078 |
|
|
/* Prefer + for zero encoded value. */
|
7079 |
|
|
if (!inst.operands[i].negative)
|
7080 |
|
|
inst.instruction |= INDEX_UP;
|
7081 |
|
|
inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
|
7082 |
|
|
}
|
7083 |
|
|
}
|
7084 |
|
|
}
|
7085 |
|
|
|
7086 |
|
|
/* inst.operands[i] was set up by parse_address. Encode it into an
|
7087 |
|
|
ARM-format mode 3 load or store instruction. Reject forms that
|
7088 |
|
|
cannot be used with such instructions. If is_t is true, reject
|
7089 |
|
|
forms that cannot be used with a T instruction (i.e. not
|
7090 |
|
|
post-indexed). */
|
7091 |
|
|
static void
|
7092 |
|
|
encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
|
7093 |
|
|
{
|
7094 |
|
|
if (inst.operands[i].immisreg && inst.operands[i].shifted)
|
7095 |
|
|
{
|
7096 |
|
|
inst.error = _("instruction does not accept scaled register index");
|
7097 |
|
|
return;
|
7098 |
|
|
}
|
7099 |
|
|
|
7100 |
|
|
encode_arm_addr_mode_common (i, is_t);
|
7101 |
|
|
|
7102 |
|
|
if (inst.operands[i].immisreg)
|
7103 |
|
|
{
|
7104 |
|
|
constraint ((inst.operands[i].imm == REG_PC
|
7105 |
|
|
|| inst.operands[i].reg == REG_PC),
|
7106 |
|
|
BAD_PC_ADDRESSING);
|
7107 |
|
|
inst.instruction |= inst.operands[i].imm;
|
7108 |
|
|
if (!inst.operands[i].negative)
|
7109 |
|
|
inst.instruction |= INDEX_UP;
|
7110 |
|
|
}
|
7111 |
|
|
else /* immediate offset in inst.reloc */
|
7112 |
|
|
{
|
7113 |
|
|
constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
|
7114 |
|
|
&& inst.operands[i].writeback),
|
7115 |
|
|
BAD_PC_WRITEBACK);
|
7116 |
|
|
inst.instruction |= HWOFFSET_IMM;
|
7117 |
|
|
if (inst.reloc.type == BFD_RELOC_UNUSED)
|
7118 |
|
|
{
|
7119 |
|
|
/* Prefer + for zero encoded value. */
|
7120 |
|
|
if (!inst.operands[i].negative)
|
7121 |
|
|
inst.instruction |= INDEX_UP;
|
7122 |
|
|
|
7123 |
|
|
inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
|
7124 |
|
|
}
|
7125 |
|
|
}
|
7126 |
|
|
}
|
7127 |
|
|
|
7128 |
|
|
/* inst.operands[i] was set up by parse_address. Encode it into an
|
7129 |
|
|
ARM-format instruction. Reject all forms which cannot be encoded
|
7130 |
|
|
into a coprocessor load/store instruction. If wb_ok is false,
|
7131 |
|
|
reject use of writeback; if unind_ok is false, reject use of
|
7132 |
|
|
unindexed addressing. If reloc_override is not 0, use it instead
|
7133 |
|
|
of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
|
7134 |
|
|
(in which case it is preserved). */
|
7135 |
|
|
|
7136 |
|
|
static int
|
7137 |
|
|
encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
|
7138 |
|
|
{
|
7139 |
|
|
inst.instruction |= inst.operands[i].reg << 16;
|
7140 |
|
|
|
7141 |
|
|
gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
|
7142 |
|
|
|
7143 |
|
|
if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
|
7144 |
|
|
{
|
7145 |
|
|
gas_assert (!inst.operands[i].writeback);
|
7146 |
|
|
if (!unind_ok)
|
7147 |
|
|
{
|
7148 |
|
|
inst.error = _("instruction does not support unindexed addressing");
|
7149 |
|
|
return FAIL;
|
7150 |
|
|
}
|
7151 |
|
|
inst.instruction |= inst.operands[i].imm;
|
7152 |
|
|
inst.instruction |= INDEX_UP;
|
7153 |
|
|
return SUCCESS;
|
7154 |
|
|
}
|
7155 |
|
|
|
7156 |
|
|
if (inst.operands[i].preind)
|
7157 |
|
|
inst.instruction |= PRE_INDEX;
|
7158 |
|
|
|
7159 |
|
|
if (inst.operands[i].writeback)
|
7160 |
|
|
{
|
7161 |
|
|
if (inst.operands[i].reg == REG_PC)
|
7162 |
|
|
{
|
7163 |
|
|
inst.error = _("pc may not be used with write-back");
|
7164 |
|
|
return FAIL;
|
7165 |
|
|
}
|
7166 |
|
|
if (!wb_ok)
|
7167 |
|
|
{
|
7168 |
|
|
inst.error = _("instruction does not support writeback");
|
7169 |
|
|
return FAIL;
|
7170 |
|
|
}
|
7171 |
|
|
inst.instruction |= WRITE_BACK;
|
7172 |
|
|
}
|
7173 |
|
|
|
7174 |
|
|
if (reloc_override)
|
7175 |
|
|
inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
|
7176 |
|
|
else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
|
7177 |
|
|
|| inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
|
7178 |
|
|
&& inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
|
7179 |
|
|
{
|
7180 |
|
|
if (thumb_mode)
|
7181 |
|
|
inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
|
7182 |
|
|
else
|
7183 |
|
|
inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
|
7184 |
|
|
}
|
7185 |
|
|
|
7186 |
|
|
/* Prefer + for zero encoded value. */
|
7187 |
|
|
if (!inst.operands[i].negative)
|
7188 |
|
|
inst.instruction |= INDEX_UP;
|
7189 |
|
|
|
7190 |
|
|
return SUCCESS;
|
7191 |
|
|
}
|
7192 |
|
|
|
7193 |
|
|
/* inst.reloc.exp describes an "=expr" load pseudo-operation.
|
7194 |
|
|
Determine whether it can be performed with a move instruction; if
|
7195 |
|
|
it can, convert inst.instruction to that move instruction and
|
7196 |
|
|
return TRUE; if it can't, convert inst.instruction to a literal-pool
|
7197 |
|
|
load and return FALSE. If this is not a valid thing to do in the
|
7198 |
|
|
current context, set inst.error and return TRUE.
|
7199 |
|
|
|
7200 |
|
|
inst.operands[i] describes the destination register. */
|
7201 |
|
|
|
7202 |
|
|
static bfd_boolean
|
7203 |
|
|
move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
|
7204 |
|
|
{
|
7205 |
|
|
unsigned long tbit;
|
7206 |
|
|
|
7207 |
|
|
if (thumb_p)
|
7208 |
|
|
tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
|
7209 |
|
|
else
|
7210 |
|
|
tbit = LOAD_BIT;
|
7211 |
|
|
|
7212 |
|
|
if ((inst.instruction & tbit) == 0)
|
7213 |
|
|
{
|
7214 |
|
|
inst.error = _("invalid pseudo operation");
|
7215 |
|
|
return TRUE;
|
7216 |
|
|
}
|
7217 |
|
|
if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
|
7218 |
|
|
{
|
7219 |
|
|
inst.error = _("constant expression expected");
|
7220 |
|
|
return TRUE;
|
7221 |
|
|
}
|
7222 |
|
|
if (inst.reloc.exp.X_op == O_constant)
|
7223 |
|
|
{
|
7224 |
|
|
if (thumb_p)
|
7225 |
|
|
{
|
7226 |
|
|
if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
|
7227 |
|
|
{
|
7228 |
|
|
/* This can be done with a mov(1) instruction. */
|
7229 |
|
|
inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
|
7230 |
|
|
inst.instruction |= inst.reloc.exp.X_add_number;
|
7231 |
|
|
return TRUE;
|
7232 |
|
|
}
|
7233 |
|
|
}
|
7234 |
|
|
else
|
7235 |
|
|
{
|
7236 |
|
|
int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
|
7237 |
|
|
if (value != FAIL)
|
7238 |
|
|
{
|
7239 |
|
|
/* This can be done with a mov instruction. */
|
7240 |
|
|
inst.instruction &= LITERAL_MASK;
|
7241 |
|
|
inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
|
7242 |
|
|
inst.instruction |= value & 0xfff;
|
7243 |
|
|
return TRUE;
|
7244 |
|
|
}
|
7245 |
|
|
|
7246 |
|
|
value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
|
7247 |
|
|
if (value != FAIL)
|
7248 |
|
|
{
|
7249 |
|
|
/* This can be done with a mvn instruction. */
|
7250 |
|
|
inst.instruction &= LITERAL_MASK;
|
7251 |
|
|
inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
|
7252 |
|
|
inst.instruction |= value & 0xfff;
|
7253 |
|
|
return TRUE;
|
7254 |
|
|
}
|
7255 |
|
|
}
|
7256 |
|
|
}
|
7257 |
|
|
|
7258 |
|
|
if (add_to_lit_pool () == FAIL)
|
7259 |
|
|
{
|
7260 |
|
|
inst.error = _("literal pool insertion failed");
|
7261 |
|
|
return TRUE;
|
7262 |
|
|
}
|
7263 |
|
|
inst.operands[1].reg = REG_PC;
|
7264 |
|
|
inst.operands[1].isreg = 1;
|
7265 |
|
|
inst.operands[1].preind = 1;
|
7266 |
|
|
inst.reloc.pc_rel = 1;
|
7267 |
|
|
inst.reloc.type = (thumb_p
|
7268 |
|
|
? BFD_RELOC_ARM_THUMB_OFFSET
|
7269 |
|
|
: (mode_3
|
7270 |
|
|
? BFD_RELOC_ARM_HWLITERAL
|
7271 |
|
|
: BFD_RELOC_ARM_LITERAL));
|
7272 |
|
|
return FALSE;
|
7273 |
|
|
}
|
7274 |
|
|
|
7275 |
|
|
/* Functions for instruction encoding, sorted by sub-architecture.
|
7276 |
|
|
First some generics; their names are taken from the conventional
|
7277 |
|
|
bit positions for register arguments in ARM format instructions. */
|
7278 |
|
|
|
7279 |
|
|
static void
|
7280 |
|
|
do_noargs (void)
|
7281 |
|
|
{
|
7282 |
|
|
}
|
7283 |
|
|
|
7284 |
|
|
static void
|
7285 |
|
|
do_rd (void)
|
7286 |
|
|
{
|
7287 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7288 |
|
|
}
|
7289 |
|
|
|
7290 |
|
|
static void
|
7291 |
|
|
do_rd_rm (void)
|
7292 |
|
|
{
|
7293 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7294 |
|
|
inst.instruction |= inst.operands[1].reg;
|
7295 |
|
|
}
|
7296 |
|
|
|
7297 |
|
|
static void
|
7298 |
|
|
do_rd_rn (void)
|
7299 |
|
|
{
|
7300 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7301 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
7302 |
|
|
}
|
7303 |
|
|
|
7304 |
|
|
static void
|
7305 |
|
|
do_rn_rd (void)
|
7306 |
|
|
{
|
7307 |
|
|
inst.instruction |= inst.operands[0].reg << 16;
|
7308 |
|
|
inst.instruction |= inst.operands[1].reg << 12;
|
7309 |
|
|
}
|
7310 |
|
|
|
7311 |
|
|
static void
|
7312 |
|
|
do_rd_rm_rn (void)
|
7313 |
|
|
{
|
7314 |
|
|
unsigned Rn = inst.operands[2].reg;
|
7315 |
|
|
/* Enforce restrictions on SWP instruction. */
|
7316 |
|
|
if ((inst.instruction & 0x0fbfffff) == 0x01000090)
|
7317 |
|
|
{
|
7318 |
|
|
constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
|
7319 |
|
|
_("Rn must not overlap other operands"));
|
7320 |
|
|
|
7321 |
|
|
/* SWP{b} is deprecated for ARMv6* and ARMv7. */
|
7322 |
|
|
if (warn_on_deprecated
|
7323 |
|
|
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
|
7324 |
|
|
as_warn (_("swp{b} use is deprecated for this architecture"));
|
7325 |
|
|
|
7326 |
|
|
}
|
7327 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7328 |
|
|
inst.instruction |= inst.operands[1].reg;
|
7329 |
|
|
inst.instruction |= Rn << 16;
|
7330 |
|
|
}
|
7331 |
|
|
|
7332 |
|
|
static void
|
7333 |
|
|
do_rd_rn_rm (void)
|
7334 |
|
|
{
|
7335 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7336 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
7337 |
|
|
inst.instruction |= inst.operands[2].reg;
|
7338 |
|
|
}
|
7339 |
|
|
|
7340 |
|
|
static void
|
7341 |
|
|
do_rm_rd_rn (void)
|
7342 |
|
|
{
|
7343 |
|
|
constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
|
7344 |
|
|
constraint (((inst.reloc.exp.X_op != O_constant
|
7345 |
|
|
&& inst.reloc.exp.X_op != O_illegal)
|
7346 |
|
|
|| inst.reloc.exp.X_add_number != 0),
|
7347 |
|
|
BAD_ADDR_MODE);
|
7348 |
|
|
inst.instruction |= inst.operands[0].reg;
|
7349 |
|
|
inst.instruction |= inst.operands[1].reg << 12;
|
7350 |
|
|
inst.instruction |= inst.operands[2].reg << 16;
|
7351 |
|
|
}
|
7352 |
|
|
|
7353 |
|
|
static void
|
7354 |
|
|
do_imm0 (void)
|
7355 |
|
|
{
|
7356 |
|
|
inst.instruction |= inst.operands[0].imm;
|
7357 |
|
|
}
|
7358 |
|
|
|
7359 |
|
|
static void
|
7360 |
|
|
do_rd_cpaddr (void)
|
7361 |
|
|
{
|
7362 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7363 |
|
|
encode_arm_cp_address (1, TRUE, TRUE, 0);
|
7364 |
|
|
}
|
7365 |
|
|
|
7366 |
|
|
/* ARM instructions, in alphabetical order by function name (except
|
7367 |
|
|
that wrapper functions appear immediately after the function they
|
7368 |
|
|
wrap). */
|
7369 |
|
|
|
7370 |
|
|
/* This is a pseudo-op of the form "adr rd, label" to be converted
|
7371 |
|
|
into a relative address of the form "add rd, pc, #label-.-8". */
|
7372 |
|
|
|
7373 |
|
|
static void
|
7374 |
|
|
do_adr (void)
|
7375 |
|
|
{
|
7376 |
|
|
inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
|
7377 |
|
|
|
7378 |
|
|
/* Frag hacking will turn this into a sub instruction if the offset turns
|
7379 |
|
|
out to be negative. */
|
7380 |
|
|
inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
|
7381 |
|
|
inst.reloc.pc_rel = 1;
|
7382 |
|
|
inst.reloc.exp.X_add_number -= 8;
|
7383 |
|
|
}
|
7384 |
|
|
|
7385 |
|
|
/* This is a pseudo-op of the form "adrl rd, label" to be converted
|
7386 |
|
|
into a relative address of the form:
|
7387 |
|
|
add rd, pc, #low(label-.-8)"
|
7388 |
|
|
add rd, rd, #high(label-.-8)" */
|
7389 |
|
|
|
7390 |
|
|
static void
|
7391 |
|
|
do_adrl (void)
|
7392 |
|
|
{
|
7393 |
|
|
inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
|
7394 |
|
|
|
7395 |
|
|
/* Frag hacking will turn this into a sub instruction if the offset turns
|
7396 |
|
|
out to be negative. */
|
7397 |
|
|
inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
|
7398 |
|
|
inst.reloc.pc_rel = 1;
|
7399 |
|
|
inst.size = INSN_SIZE * 2;
|
7400 |
|
|
inst.reloc.exp.X_add_number -= 8;
|
7401 |
|
|
}
|
7402 |
|
|
|
7403 |
|
|
static void
|
7404 |
|
|
do_arit (void)
|
7405 |
|
|
{
|
7406 |
|
|
if (!inst.operands[1].present)
|
7407 |
|
|
inst.operands[1].reg = inst.operands[0].reg;
|
7408 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7409 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
7410 |
|
|
encode_arm_shifter_operand (2);
|
7411 |
|
|
}
|
7412 |
|
|
|
7413 |
|
|
static void
|
7414 |
|
|
do_barrier (void)
|
7415 |
|
|
{
|
7416 |
|
|
if (inst.operands[0].present)
|
7417 |
|
|
{
|
7418 |
|
|
constraint ((inst.instruction & 0xf0) != 0x40
|
7419 |
|
|
&& inst.operands[0].imm > 0xf
|
7420 |
|
|
&& inst.operands[0].imm < 0x0,
|
7421 |
|
|
_("bad barrier type"));
|
7422 |
|
|
inst.instruction |= inst.operands[0].imm;
|
7423 |
|
|
}
|
7424 |
|
|
else
|
7425 |
|
|
inst.instruction |= 0xf;
|
7426 |
|
|
}
|
7427 |
|
|
|
7428 |
|
|
static void
|
7429 |
|
|
do_bfc (void)
|
7430 |
|
|
{
|
7431 |
|
|
unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
|
7432 |
|
|
constraint (msb > 32, _("bit-field extends past end of register"));
|
7433 |
|
|
/* The instruction encoding stores the LSB and MSB,
|
7434 |
|
|
not the LSB and width. */
|
7435 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7436 |
|
|
inst.instruction |= inst.operands[1].imm << 7;
|
7437 |
|
|
inst.instruction |= (msb - 1) << 16;
|
7438 |
|
|
}
|
7439 |
|
|
|
7440 |
|
|
static void
|
7441 |
|
|
do_bfi (void)
|
7442 |
|
|
{
|
7443 |
|
|
unsigned int msb;
|
7444 |
|
|
|
7445 |
|
|
/* #0 in second position is alternative syntax for bfc, which is
|
7446 |
|
|
the same instruction but with REG_PC in the Rm field. */
|
7447 |
|
|
if (!inst.operands[1].isreg)
|
7448 |
|
|
inst.operands[1].reg = REG_PC;
|
7449 |
|
|
|
7450 |
|
|
msb = inst.operands[2].imm + inst.operands[3].imm;
|
7451 |
|
|
constraint (msb > 32, _("bit-field extends past end of register"));
|
7452 |
|
|
/* The instruction encoding stores the LSB and MSB,
|
7453 |
|
|
not the LSB and width. */
|
7454 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7455 |
|
|
inst.instruction |= inst.operands[1].reg;
|
7456 |
|
|
inst.instruction |= inst.operands[2].imm << 7;
|
7457 |
|
|
inst.instruction |= (msb - 1) << 16;
|
7458 |
|
|
}
|
7459 |
|
|
|
7460 |
|
|
static void
|
7461 |
|
|
do_bfx (void)
|
7462 |
|
|
{
|
7463 |
|
|
constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
|
7464 |
|
|
_("bit-field extends past end of register"));
|
7465 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7466 |
|
|
inst.instruction |= inst.operands[1].reg;
|
7467 |
|
|
inst.instruction |= inst.operands[2].imm << 7;
|
7468 |
|
|
inst.instruction |= (inst.operands[3].imm - 1) << 16;
|
7469 |
|
|
}
|
7470 |
|
|
|
7471 |
|
|
/* ARM V5 breakpoint instruction (argument parse)
|
7472 |
|
|
BKPT <16 bit unsigned immediate>
|
7473 |
|
|
Instruction is not conditional.
|
7474 |
|
|
The bit pattern given in insns[] has the COND_ALWAYS condition,
|
7475 |
|
|
and it is an error if the caller tried to override that. */
|
7476 |
|
|
|
7477 |
|
|
static void
|
7478 |
|
|
do_bkpt (void)
|
7479 |
|
|
{
|
7480 |
|
|
/* Top 12 of 16 bits to bits 19:8. */
|
7481 |
|
|
inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
|
7482 |
|
|
|
7483 |
|
|
/* Bottom 4 of 16 bits to bits 3:0. */
|
7484 |
|
|
inst.instruction |= inst.operands[0].imm & 0xf;
|
7485 |
|
|
}
|
7486 |
|
|
|
7487 |
|
|
static void
|
7488 |
|
|
encode_branch (int default_reloc)
|
7489 |
|
|
{
|
7490 |
|
|
if (inst.operands[0].hasreloc)
|
7491 |
|
|
{
|
7492 |
|
|
constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
|
7493 |
|
|
&& inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
|
7494 |
|
|
_("the only valid suffixes here are '(plt)' and '(tlscall)'"));
|
7495 |
|
|
inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
|
7496 |
|
|
? BFD_RELOC_ARM_PLT32
|
7497 |
|
|
: thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
|
7498 |
|
|
}
|
7499 |
|
|
else
|
7500 |
|
|
inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
|
7501 |
|
|
inst.reloc.pc_rel = 1;
|
7502 |
|
|
}
|
7503 |
|
|
|
7504 |
|
|
static void
|
7505 |
|
|
do_branch (void)
|
7506 |
|
|
{
|
7507 |
|
|
#ifdef OBJ_ELF
|
7508 |
|
|
if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
|
7509 |
|
|
encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
|
7510 |
|
|
else
|
7511 |
|
|
#endif
|
7512 |
|
|
encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
|
7513 |
|
|
}
|
7514 |
|
|
|
7515 |
|
|
static void
|
7516 |
|
|
do_bl (void)
|
7517 |
|
|
{
|
7518 |
|
|
#ifdef OBJ_ELF
|
7519 |
|
|
if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
|
7520 |
|
|
{
|
7521 |
|
|
if (inst.cond == COND_ALWAYS)
|
7522 |
|
|
encode_branch (BFD_RELOC_ARM_PCREL_CALL);
|
7523 |
|
|
else
|
7524 |
|
|
encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
|
7525 |
|
|
}
|
7526 |
|
|
else
|
7527 |
|
|
#endif
|
7528 |
|
|
encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
|
7529 |
|
|
}
|
7530 |
|
|
|
7531 |
|
|
/* ARM V5 branch-link-exchange instruction (argument parse)
|
7532 |
|
|
BLX <target_addr> ie BLX(1)
|
7533 |
|
|
BLX{<condition>} <Rm> ie BLX(2)
|
7534 |
|
|
Unfortunately, there are two different opcodes for this mnemonic.
|
7535 |
|
|
So, the insns[].value is not used, and the code here zaps values
|
7536 |
|
|
into inst.instruction.
|
7537 |
|
|
Also, the <target_addr> can be 25 bits, hence has its own reloc. */
|
7538 |
|
|
|
7539 |
|
|
static void
|
7540 |
|
|
do_blx (void)
|
7541 |
|
|
{
|
7542 |
|
|
if (inst.operands[0].isreg)
|
7543 |
|
|
{
|
7544 |
|
|
/* Arg is a register; the opcode provided by insns[] is correct.
|
7545 |
|
|
It is not illegal to do "blx pc", just useless. */
|
7546 |
|
|
if (inst.operands[0].reg == REG_PC)
|
7547 |
|
|
as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
|
7548 |
|
|
|
7549 |
|
|
inst.instruction |= inst.operands[0].reg;
|
7550 |
|
|
}
|
7551 |
|
|
else
|
7552 |
|
|
{
|
7553 |
|
|
/* Arg is an address; this instruction cannot be executed
|
7554 |
|
|
conditionally, and the opcode must be adjusted.
|
7555 |
|
|
We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
|
7556 |
|
|
where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
|
7557 |
|
|
constraint (inst.cond != COND_ALWAYS, BAD_COND);
|
7558 |
|
|
inst.instruction = 0xfa000000;
|
7559 |
|
|
encode_branch (BFD_RELOC_ARM_PCREL_BLX);
|
7560 |
|
|
}
|
7561 |
|
|
}
|
7562 |
|
|
|
7563 |
|
|
static void
|
7564 |
|
|
do_bx (void)
|
7565 |
|
|
{
|
7566 |
|
|
bfd_boolean want_reloc;
|
7567 |
|
|
|
7568 |
|
|
if (inst.operands[0].reg == REG_PC)
|
7569 |
|
|
as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
|
7570 |
|
|
|
7571 |
|
|
inst.instruction |= inst.operands[0].reg;
|
7572 |
|
|
/* Output R_ARM_V4BX relocations if is an EABI object that looks like
|
7573 |
|
|
it is for ARMv4t or earlier. */
|
7574 |
|
|
want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
|
7575 |
|
|
if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
|
7576 |
|
|
want_reloc = TRUE;
|
7577 |
|
|
|
7578 |
|
|
#ifdef OBJ_ELF
|
7579 |
|
|
if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
|
7580 |
|
|
#endif
|
7581 |
|
|
want_reloc = FALSE;
|
7582 |
|
|
|
7583 |
|
|
if (want_reloc)
|
7584 |
|
|
inst.reloc.type = BFD_RELOC_ARM_V4BX;
|
7585 |
|
|
}
|
7586 |
|
|
|
7587 |
|
|
|
7588 |
|
|
/* ARM v5TEJ. Jump to Jazelle code. */
|
7589 |
|
|
|
7590 |
|
|
static void
|
7591 |
|
|
do_bxj (void)
|
7592 |
|
|
{
|
7593 |
|
|
if (inst.operands[0].reg == REG_PC)
|
7594 |
|
|
as_tsktsk (_("use of r15 in bxj is not really useful"));
|
7595 |
|
|
|
7596 |
|
|
inst.instruction |= inst.operands[0].reg;
|
7597 |
|
|
}
|
7598 |
|
|
|
7599 |
|
|
/* Co-processor data operation:
|
7600 |
|
|
CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
|
7601 |
|
|
CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
|
7602 |
|
|
static void
|
7603 |
|
|
do_cdp (void)
|
7604 |
|
|
{
|
7605 |
|
|
inst.instruction |= inst.operands[0].reg << 8;
|
7606 |
|
|
inst.instruction |= inst.operands[1].imm << 20;
|
7607 |
|
|
inst.instruction |= inst.operands[2].reg << 12;
|
7608 |
|
|
inst.instruction |= inst.operands[3].reg << 16;
|
7609 |
|
|
inst.instruction |= inst.operands[4].reg;
|
7610 |
|
|
inst.instruction |= inst.operands[5].imm << 5;
|
7611 |
|
|
}
|
7612 |
|
|
|
7613 |
|
|
static void
|
7614 |
|
|
do_cmp (void)
|
7615 |
|
|
{
|
7616 |
|
|
inst.instruction |= inst.operands[0].reg << 16;
|
7617 |
|
|
encode_arm_shifter_operand (1);
|
7618 |
|
|
}
|
7619 |
|
|
|
7620 |
|
|
/* Transfer between coprocessor and ARM registers.
|
7621 |
|
|
MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
|
7622 |
|
|
MRC2
|
7623 |
|
|
MCR{cond}
|
7624 |
|
|
MCR2
|
7625 |
|
|
|
7626 |
|
|
No special properties. */
|
7627 |
|
|
|
7628 |
|
|
static void
|
7629 |
|
|
do_co_reg (void)
|
7630 |
|
|
{
|
7631 |
|
|
unsigned Rd;
|
7632 |
|
|
|
7633 |
|
|
Rd = inst.operands[2].reg;
|
7634 |
|
|
if (thumb_mode)
|
7635 |
|
|
{
|
7636 |
|
|
if (inst.instruction == 0xee000010
|
7637 |
|
|
|| inst.instruction == 0xfe000010)
|
7638 |
|
|
/* MCR, MCR2 */
|
7639 |
|
|
reject_bad_reg (Rd);
|
7640 |
|
|
else
|
7641 |
|
|
/* MRC, MRC2 */
|
7642 |
|
|
constraint (Rd == REG_SP, BAD_SP);
|
7643 |
|
|
}
|
7644 |
|
|
else
|
7645 |
|
|
{
|
7646 |
|
|
/* MCR */
|
7647 |
|
|
if (inst.instruction == 0xe000010)
|
7648 |
|
|
constraint (Rd == REG_PC, BAD_PC);
|
7649 |
|
|
}
|
7650 |
|
|
|
7651 |
|
|
|
7652 |
|
|
inst.instruction |= inst.operands[0].reg << 8;
|
7653 |
|
|
inst.instruction |= inst.operands[1].imm << 21;
|
7654 |
|
|
inst.instruction |= Rd << 12;
|
7655 |
|
|
inst.instruction |= inst.operands[3].reg << 16;
|
7656 |
|
|
inst.instruction |= inst.operands[4].reg;
|
7657 |
|
|
inst.instruction |= inst.operands[5].imm << 5;
|
7658 |
|
|
}
|
7659 |
|
|
|
7660 |
|
|
/* Transfer between coprocessor register and pair of ARM registers.
|
7661 |
|
|
MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
|
7662 |
|
|
MCRR2
|
7663 |
|
|
MRRC{cond}
|
7664 |
|
|
MRRC2
|
7665 |
|
|
|
7666 |
|
|
Two XScale instructions are special cases of these:
|
7667 |
|
|
|
7668 |
|
|
MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
|
7669 |
|
|
MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
|
7670 |
|
|
|
7671 |
|
|
Result unpredictable if Rd or Rn is R15. */
|
7672 |
|
|
|
7673 |
|
|
static void
|
7674 |
|
|
do_co_reg2c (void)
|
7675 |
|
|
{
|
7676 |
|
|
unsigned Rd, Rn;
|
7677 |
|
|
|
7678 |
|
|
Rd = inst.operands[2].reg;
|
7679 |
|
|
Rn = inst.operands[3].reg;
|
7680 |
|
|
|
7681 |
|
|
if (thumb_mode)
|
7682 |
|
|
{
|
7683 |
|
|
reject_bad_reg (Rd);
|
7684 |
|
|
reject_bad_reg (Rn);
|
7685 |
|
|
}
|
7686 |
|
|
else
|
7687 |
|
|
{
|
7688 |
|
|
constraint (Rd == REG_PC, BAD_PC);
|
7689 |
|
|
constraint (Rn == REG_PC, BAD_PC);
|
7690 |
|
|
}
|
7691 |
|
|
|
7692 |
|
|
inst.instruction |= inst.operands[0].reg << 8;
|
7693 |
|
|
inst.instruction |= inst.operands[1].imm << 4;
|
7694 |
|
|
inst.instruction |= Rd << 12;
|
7695 |
|
|
inst.instruction |= Rn << 16;
|
7696 |
|
|
inst.instruction |= inst.operands[4].reg;
|
7697 |
|
|
}
|
7698 |
|
|
|
7699 |
|
|
static void
|
7700 |
|
|
do_cpsi (void)
|
7701 |
|
|
{
|
7702 |
|
|
inst.instruction |= inst.operands[0].imm << 6;
|
7703 |
|
|
if (inst.operands[1].present)
|
7704 |
|
|
{
|
7705 |
|
|
inst.instruction |= CPSI_MMOD;
|
7706 |
|
|
inst.instruction |= inst.operands[1].imm;
|
7707 |
|
|
}
|
7708 |
|
|
}
|
7709 |
|
|
|
7710 |
|
|
static void
|
7711 |
|
|
do_dbg (void)
|
7712 |
|
|
{
|
7713 |
|
|
inst.instruction |= inst.operands[0].imm;
|
7714 |
|
|
}
|
7715 |
|
|
|
7716 |
|
|
static void
|
7717 |
|
|
do_div (void)
|
7718 |
|
|
{
|
7719 |
|
|
unsigned Rd, Rn, Rm;
|
7720 |
|
|
|
7721 |
|
|
Rd = inst.operands[0].reg;
|
7722 |
|
|
Rn = (inst.operands[1].present
|
7723 |
|
|
? inst.operands[1].reg : Rd);
|
7724 |
|
|
Rm = inst.operands[2].reg;
|
7725 |
|
|
|
7726 |
|
|
constraint ((Rd == REG_PC), BAD_PC);
|
7727 |
|
|
constraint ((Rn == REG_PC), BAD_PC);
|
7728 |
|
|
constraint ((Rm == REG_PC), BAD_PC);
|
7729 |
|
|
|
7730 |
|
|
inst.instruction |= Rd << 16;
|
7731 |
|
|
inst.instruction |= Rn << 0;
|
7732 |
|
|
inst.instruction |= Rm << 8;
|
7733 |
|
|
}
|
7734 |
|
|
|
7735 |
|
|
static void
|
7736 |
|
|
do_it (void)
|
7737 |
|
|
{
|
7738 |
|
|
/* There is no IT instruction in ARM mode. We
|
7739 |
|
|
process it to do the validation as if in
|
7740 |
|
|
thumb mode, just in case the code gets
|
7741 |
|
|
assembled for thumb using the unified syntax. */
|
7742 |
|
|
|
7743 |
|
|
inst.size = 0;
|
7744 |
|
|
if (unified_syntax)
|
7745 |
|
|
{
|
7746 |
|
|
set_it_insn_type (IT_INSN);
|
7747 |
|
|
now_it.mask = (inst.instruction & 0xf) | 0x10;
|
7748 |
|
|
now_it.cc = inst.operands[0].imm;
|
7749 |
|
|
}
|
7750 |
|
|
}
|
7751 |
|
|
|
7752 |
|
|
static void
|
7753 |
|
|
do_ldmstm (void)
|
7754 |
|
|
{
|
7755 |
|
|
int base_reg = inst.operands[0].reg;
|
7756 |
|
|
int range = inst.operands[1].imm;
|
7757 |
|
|
|
7758 |
|
|
inst.instruction |= base_reg << 16;
|
7759 |
|
|
inst.instruction |= range;
|
7760 |
|
|
|
7761 |
|
|
if (inst.operands[1].writeback)
|
7762 |
|
|
inst.instruction |= LDM_TYPE_2_OR_3;
|
7763 |
|
|
|
7764 |
|
|
if (inst.operands[0].writeback)
|
7765 |
|
|
{
|
7766 |
|
|
inst.instruction |= WRITE_BACK;
|
7767 |
|
|
/* Check for unpredictable uses of writeback. */
|
7768 |
|
|
if (inst.instruction & LOAD_BIT)
|
7769 |
|
|
{
|
7770 |
|
|
/* Not allowed in LDM type 2. */
|
7771 |
|
|
if ((inst.instruction & LDM_TYPE_2_OR_3)
|
7772 |
|
|
&& ((range & (1 << REG_PC)) == 0))
|
7773 |
|
|
as_warn (_("writeback of base register is UNPREDICTABLE"));
|
7774 |
|
|
/* Only allowed if base reg not in list for other types. */
|
7775 |
|
|
else if (range & (1 << base_reg))
|
7776 |
|
|
as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
|
7777 |
|
|
}
|
7778 |
|
|
else /* STM. */
|
7779 |
|
|
{
|
7780 |
|
|
/* Not allowed for type 2. */
|
7781 |
|
|
if (inst.instruction & LDM_TYPE_2_OR_3)
|
7782 |
|
|
as_warn (_("writeback of base register is UNPREDICTABLE"));
|
7783 |
|
|
/* Only allowed if base reg not in list, or first in list. */
|
7784 |
|
|
else if ((range & (1 << base_reg))
|
7785 |
|
|
&& (range & ((1 << base_reg) - 1)))
|
7786 |
|
|
as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
|
7787 |
|
|
}
|
7788 |
|
|
}
|
7789 |
|
|
}
|
7790 |
|
|
|
7791 |
|
|
/* ARMv5TE load-consecutive (argument parse)
|
7792 |
|
|
Mode is like LDRH.
|
7793 |
|
|
|
7794 |
|
|
LDRccD R, mode
|
7795 |
|
|
STRccD R, mode. */
|
7796 |
|
|
|
7797 |
|
|
static void
|
7798 |
|
|
do_ldrd (void)
|
7799 |
|
|
{
|
7800 |
|
|
constraint (inst.operands[0].reg % 2 != 0,
|
7801 |
148 |
khays |
_("first transfer register must be even"));
|
7802 |
16 |
khays |
constraint (inst.operands[1].present
|
7803 |
|
|
&& inst.operands[1].reg != inst.operands[0].reg + 1,
|
7804 |
148 |
khays |
_("can only transfer two consecutive registers"));
|
7805 |
16 |
khays |
constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
|
7806 |
|
|
constraint (!inst.operands[2].isreg, _("'[' expected"));
|
7807 |
|
|
|
7808 |
|
|
if (!inst.operands[1].present)
|
7809 |
|
|
inst.operands[1].reg = inst.operands[0].reg + 1;
|
7810 |
|
|
|
7811 |
148 |
khays |
/* encode_arm_addr_mode_3 will diagnose overlap between the base
|
7812 |
|
|
register and the first register written; we have to diagnose
|
7813 |
|
|
overlap between the base and the second register written here. */
|
7814 |
16 |
khays |
|
7815 |
148 |
khays |
if (inst.operands[2].reg == inst.operands[1].reg
|
7816 |
|
|
&& (inst.operands[2].writeback || inst.operands[2].postind))
|
7817 |
|
|
as_warn (_("base register written back, and overlaps "
|
7818 |
|
|
"second transfer register"));
|
7819 |
16 |
khays |
|
7820 |
148 |
khays |
if (!(inst.instruction & V4_STR_BIT))
|
7821 |
|
|
{
|
7822 |
16 |
khays |
/* For an index-register load, the index register must not overlap the
|
7823 |
148 |
khays |
destination (even if not write-back). */
|
7824 |
|
|
if (inst.operands[2].immisreg
|
7825 |
|
|
&& ((unsigned) inst.operands[2].imm == inst.operands[0].reg
|
7826 |
|
|
|| (unsigned) inst.operands[2].imm == inst.operands[1].reg))
|
7827 |
|
|
as_warn (_("index register overlaps transfer register"));
|
7828 |
16 |
khays |
}
|
7829 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7830 |
|
|
encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
|
7831 |
|
|
}
|
7832 |
|
|
|
7833 |
|
|
static void
|
7834 |
|
|
do_ldrex (void)
|
7835 |
|
|
{
|
7836 |
|
|
constraint (!inst.operands[1].isreg || !inst.operands[1].preind
|
7837 |
|
|
|| inst.operands[1].postind || inst.operands[1].writeback
|
7838 |
|
|
|| inst.operands[1].immisreg || inst.operands[1].shifted
|
7839 |
|
|
|| inst.operands[1].negative
|
7840 |
|
|
/* This can arise if the programmer has written
|
7841 |
|
|
strex rN, rM, foo
|
7842 |
|
|
or if they have mistakenly used a register name as the last
|
7843 |
|
|
operand, eg:
|
7844 |
|
|
strex rN, rM, rX
|
7845 |
|
|
It is very difficult to distinguish between these two cases
|
7846 |
|
|
because "rX" might actually be a label. ie the register
|
7847 |
|
|
name has been occluded by a symbol of the same name. So we
|
7848 |
|
|
just generate a general 'bad addressing mode' type error
|
7849 |
|
|
message and leave it up to the programmer to discover the
|
7850 |
|
|
true cause and fix their mistake. */
|
7851 |
|
|
|| (inst.operands[1].reg == REG_PC),
|
7852 |
|
|
BAD_ADDR_MODE);
|
7853 |
|
|
|
7854 |
|
|
constraint (inst.reloc.exp.X_op != O_constant
|
7855 |
|
|
|| inst.reloc.exp.X_add_number != 0,
|
7856 |
|
|
_("offset must be zero in ARM encoding"));
|
7857 |
|
|
|
7858 |
|
|
constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
|
7859 |
|
|
|
7860 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7861 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
7862 |
|
|
inst.reloc.type = BFD_RELOC_UNUSED;
|
7863 |
|
|
}
|
7864 |
|
|
|
7865 |
|
|
static void
|
7866 |
|
|
do_ldrexd (void)
|
7867 |
|
|
{
|
7868 |
|
|
constraint (inst.operands[0].reg % 2 != 0,
|
7869 |
|
|
_("even register required"));
|
7870 |
|
|
constraint (inst.operands[1].present
|
7871 |
|
|
&& inst.operands[1].reg != inst.operands[0].reg + 1,
|
7872 |
|
|
_("can only load two consecutive registers"));
|
7873 |
|
|
/* If op 1 were present and equal to PC, this function wouldn't
|
7874 |
|
|
have been called in the first place. */
|
7875 |
|
|
constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
|
7876 |
|
|
|
7877 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7878 |
|
|
inst.instruction |= inst.operands[2].reg << 16;
|
7879 |
|
|
}
|
7880 |
|
|
|
7881 |
|
|
static void
|
7882 |
|
|
do_ldst (void)
|
7883 |
|
|
{
|
7884 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7885 |
|
|
if (!inst.operands[1].isreg)
|
7886 |
|
|
if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
|
7887 |
|
|
return;
|
7888 |
|
|
encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
|
7889 |
|
|
}
|
7890 |
|
|
|
7891 |
|
|
static void
|
7892 |
|
|
do_ldstt (void)
|
7893 |
|
|
{
|
7894 |
|
|
/* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
|
7895 |
|
|
reject [Rn,...]. */
|
7896 |
|
|
if (inst.operands[1].preind)
|
7897 |
|
|
{
|
7898 |
|
|
constraint (inst.reloc.exp.X_op != O_constant
|
7899 |
|
|
|| inst.reloc.exp.X_add_number != 0,
|
7900 |
|
|
_("this instruction requires a post-indexed address"));
|
7901 |
|
|
|
7902 |
|
|
inst.operands[1].preind = 0;
|
7903 |
|
|
inst.operands[1].postind = 1;
|
7904 |
|
|
inst.operands[1].writeback = 1;
|
7905 |
|
|
}
|
7906 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7907 |
|
|
encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
|
7908 |
|
|
}
|
7909 |
|
|
|
7910 |
|
|
/* Halfword and signed-byte load/store operations. */
|
7911 |
|
|
|
7912 |
|
|
static void
|
7913 |
|
|
do_ldstv4 (void)
|
7914 |
|
|
{
|
7915 |
|
|
constraint (inst.operands[0].reg == REG_PC, BAD_PC);
|
7916 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7917 |
|
|
if (!inst.operands[1].isreg)
|
7918 |
|
|
if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
|
7919 |
|
|
return;
|
7920 |
|
|
encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
|
7921 |
|
|
}
|
7922 |
|
|
|
7923 |
|
|
static void
|
7924 |
|
|
do_ldsttv4 (void)
|
7925 |
|
|
{
|
7926 |
|
|
/* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
|
7927 |
|
|
reject [Rn,...]. */
|
7928 |
|
|
if (inst.operands[1].preind)
|
7929 |
|
|
{
|
7930 |
|
|
constraint (inst.reloc.exp.X_op != O_constant
|
7931 |
|
|
|| inst.reloc.exp.X_add_number != 0,
|
7932 |
|
|
_("this instruction requires a post-indexed address"));
|
7933 |
|
|
|
7934 |
|
|
inst.operands[1].preind = 0;
|
7935 |
|
|
inst.operands[1].postind = 1;
|
7936 |
|
|
inst.operands[1].writeback = 1;
|
7937 |
|
|
}
|
7938 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7939 |
|
|
encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
|
7940 |
|
|
}
|
7941 |
|
|
|
7942 |
|
|
/* Co-processor register load/store.
|
7943 |
|
|
Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
|
7944 |
|
|
static void
|
7945 |
|
|
do_lstc (void)
|
7946 |
|
|
{
|
7947 |
|
|
inst.instruction |= inst.operands[0].reg << 8;
|
7948 |
|
|
inst.instruction |= inst.operands[1].reg << 12;
|
7949 |
|
|
encode_arm_cp_address (2, TRUE, TRUE, 0);
|
7950 |
|
|
}
|
7951 |
|
|
|
7952 |
|
|
static void
|
7953 |
|
|
do_mlas (void)
|
7954 |
|
|
{
|
7955 |
|
|
/* This restriction does not apply to mls (nor to mla in v6 or later). */
|
7956 |
|
|
if (inst.operands[0].reg == inst.operands[1].reg
|
7957 |
|
|
&& !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
|
7958 |
|
|
&& !(inst.instruction & 0x00400000))
|
7959 |
|
|
as_tsktsk (_("Rd and Rm should be different in mla"));
|
7960 |
|
|
|
7961 |
|
|
inst.instruction |= inst.operands[0].reg << 16;
|
7962 |
|
|
inst.instruction |= inst.operands[1].reg;
|
7963 |
|
|
inst.instruction |= inst.operands[2].reg << 8;
|
7964 |
|
|
inst.instruction |= inst.operands[3].reg << 12;
|
7965 |
|
|
}
|
7966 |
|
|
|
7967 |
|
|
static void
|
7968 |
|
|
do_mov (void)
|
7969 |
|
|
{
|
7970 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7971 |
|
|
encode_arm_shifter_operand (1);
|
7972 |
|
|
}
|
7973 |
|
|
|
7974 |
|
|
/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
|
7975 |
|
|
static void
|
7976 |
|
|
do_mov16 (void)
|
7977 |
|
|
{
|
7978 |
|
|
bfd_vma imm;
|
7979 |
|
|
bfd_boolean top;
|
7980 |
|
|
|
7981 |
|
|
top = (inst.instruction & 0x00400000) != 0;
|
7982 |
|
|
constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
|
7983 |
|
|
_(":lower16: not allowed this instruction"));
|
7984 |
|
|
constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
|
7985 |
|
|
_(":upper16: not allowed instruction"));
|
7986 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
7987 |
|
|
if (inst.reloc.type == BFD_RELOC_UNUSED)
|
7988 |
|
|
{
|
7989 |
|
|
imm = inst.reloc.exp.X_add_number;
|
7990 |
|
|
/* The value is in two pieces: 0:11, 16:19. */
|
7991 |
|
|
inst.instruction |= (imm & 0x00000fff);
|
7992 |
|
|
inst.instruction |= (imm & 0x0000f000) << 4;
|
7993 |
|
|
}
|
7994 |
|
|
}
|
7995 |
|
|
|
7996 |
|
|
static void do_vfp_nsyn_opcode (const char *);
|
7997 |
|
|
|
7998 |
|
|
static int
|
7999 |
|
|
do_vfp_nsyn_mrs (void)
|
8000 |
|
|
{
|
8001 |
|
|
if (inst.operands[0].isvec)
|
8002 |
|
|
{
|
8003 |
|
|
if (inst.operands[1].reg != 1)
|
8004 |
|
|
first_error (_("operand 1 must be FPSCR"));
|
8005 |
|
|
memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
|
8006 |
|
|
memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
|
8007 |
|
|
do_vfp_nsyn_opcode ("fmstat");
|
8008 |
|
|
}
|
8009 |
|
|
else if (inst.operands[1].isvec)
|
8010 |
|
|
do_vfp_nsyn_opcode ("fmrx");
|
8011 |
|
|
else
|
8012 |
|
|
return FAIL;
|
8013 |
|
|
|
8014 |
|
|
return SUCCESS;
|
8015 |
|
|
}
|
8016 |
|
|
|
8017 |
|
|
static int
|
8018 |
|
|
do_vfp_nsyn_msr (void)
|
8019 |
|
|
{
|
8020 |
|
|
if (inst.operands[0].isvec)
|
8021 |
|
|
do_vfp_nsyn_opcode ("fmxr");
|
8022 |
|
|
else
|
8023 |
|
|
return FAIL;
|
8024 |
|
|
|
8025 |
|
|
return SUCCESS;
|
8026 |
|
|
}
|
8027 |
|
|
|
8028 |
|
|
static void
|
8029 |
|
|
do_vmrs (void)
|
8030 |
|
|
{
|
8031 |
|
|
unsigned Rt = inst.operands[0].reg;
|
8032 |
|
|
|
8033 |
|
|
if (thumb_mode && inst.operands[0].reg == REG_SP)
|
8034 |
|
|
{
|
8035 |
|
|
inst.error = BAD_SP;
|
8036 |
|
|
return;
|
8037 |
|
|
}
|
8038 |
|
|
|
8039 |
|
|
/* APSR_ sets isvec. All other refs to PC are illegal. */
|
8040 |
|
|
if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
|
8041 |
|
|
{
|
8042 |
|
|
inst.error = BAD_PC;
|
8043 |
|
|
return;
|
8044 |
|
|
}
|
8045 |
|
|
|
8046 |
|
|
if (inst.operands[1].reg != 1)
|
8047 |
|
|
first_error (_("operand 1 must be FPSCR"));
|
8048 |
|
|
|
8049 |
|
|
inst.instruction |= (Rt << 12);
|
8050 |
|
|
}
|
8051 |
|
|
|
8052 |
|
|
static void
|
8053 |
|
|
do_vmsr (void)
|
8054 |
|
|
{
|
8055 |
|
|
unsigned Rt = inst.operands[1].reg;
|
8056 |
|
|
|
8057 |
|
|
if (thumb_mode)
|
8058 |
|
|
reject_bad_reg (Rt);
|
8059 |
|
|
else if (Rt == REG_PC)
|
8060 |
|
|
{
|
8061 |
|
|
inst.error = BAD_PC;
|
8062 |
|
|
return;
|
8063 |
|
|
}
|
8064 |
|
|
|
8065 |
|
|
if (inst.operands[0].reg != 1)
|
8066 |
|
|
first_error (_("operand 0 must be FPSCR"));
|
8067 |
|
|
|
8068 |
|
|
inst.instruction |= (Rt << 12);
|
8069 |
|
|
}
|
8070 |
|
|
|
8071 |
|
|
static void
|
8072 |
|
|
do_mrs (void)
|
8073 |
|
|
{
|
8074 |
|
|
unsigned br;
|
8075 |
|
|
|
8076 |
|
|
if (do_vfp_nsyn_mrs () == SUCCESS)
|
8077 |
|
|
return;
|
8078 |
|
|
|
8079 |
|
|
constraint (inst.operands[0].reg == REG_PC, BAD_PC);
|
8080 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8081 |
|
|
|
8082 |
|
|
if (inst.operands[1].isreg)
|
8083 |
|
|
{
|
8084 |
|
|
br = inst.operands[1].reg;
|
8085 |
|
|
if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
|
8086 |
|
|
as_bad (_("bad register for mrs"));
|
8087 |
|
|
}
|
8088 |
|
|
else
|
8089 |
|
|
{
|
8090 |
|
|
/* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
|
8091 |
|
|
constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
|
8092 |
|
|
!= (PSR_c|PSR_f),
|
8093 |
|
|
_("'APSR', 'CPSR' or 'SPSR' expected"));
|
8094 |
|
|
br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
|
8095 |
|
|
}
|
8096 |
|
|
|
8097 |
|
|
inst.instruction |= br;
|
8098 |
|
|
}
|
8099 |
|
|
|
8100 |
|
|
/* Two possible forms:
|
8101 |
|
|
"{C|S}PSR_<field>, Rm",
|
8102 |
|
|
"{C|S}PSR_f, #expression". */
|
8103 |
|
|
|
8104 |
|
|
static void
|
8105 |
|
|
do_msr (void)
|
8106 |
|
|
{
|
8107 |
|
|
if (do_vfp_nsyn_msr () == SUCCESS)
|
8108 |
|
|
return;
|
8109 |
|
|
|
8110 |
|
|
inst.instruction |= inst.operands[0].imm;
|
8111 |
|
|
if (inst.operands[1].isreg)
|
8112 |
|
|
inst.instruction |= inst.operands[1].reg;
|
8113 |
|
|
else
|
8114 |
|
|
{
|
8115 |
|
|
inst.instruction |= INST_IMMEDIATE;
|
8116 |
|
|
inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
|
8117 |
|
|
inst.reloc.pc_rel = 0;
|
8118 |
|
|
}
|
8119 |
|
|
}
|
8120 |
|
|
|
8121 |
|
|
static void
|
8122 |
|
|
do_mul (void)
|
8123 |
|
|
{
|
8124 |
|
|
constraint (inst.operands[2].reg == REG_PC, BAD_PC);
|
8125 |
|
|
|
8126 |
|
|
if (!inst.operands[2].present)
|
8127 |
|
|
inst.operands[2].reg = inst.operands[0].reg;
|
8128 |
|
|
inst.instruction |= inst.operands[0].reg << 16;
|
8129 |
|
|
inst.instruction |= inst.operands[1].reg;
|
8130 |
|
|
inst.instruction |= inst.operands[2].reg << 8;
|
8131 |
|
|
|
8132 |
|
|
if (inst.operands[0].reg == inst.operands[1].reg
|
8133 |
|
|
&& !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
|
8134 |
|
|
as_tsktsk (_("Rd and Rm should be different in mul"));
|
8135 |
|
|
}
|
8136 |
|
|
|
8137 |
|
|
/* Long Multiply Parser
|
8138 |
|
|
UMULL RdLo, RdHi, Rm, Rs
|
8139 |
|
|
SMULL RdLo, RdHi, Rm, Rs
|
8140 |
|
|
UMLAL RdLo, RdHi, Rm, Rs
|
8141 |
|
|
SMLAL RdLo, RdHi, Rm, Rs. */
|
8142 |
|
|
|
8143 |
|
|
static void
|
8144 |
|
|
do_mull (void)
|
8145 |
|
|
{
|
8146 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8147 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
8148 |
|
|
inst.instruction |= inst.operands[2].reg;
|
8149 |
|
|
inst.instruction |= inst.operands[3].reg << 8;
|
8150 |
|
|
|
8151 |
|
|
/* rdhi and rdlo must be different. */
|
8152 |
|
|
if (inst.operands[0].reg == inst.operands[1].reg)
|
8153 |
|
|
as_tsktsk (_("rdhi and rdlo must be different"));
|
8154 |
|
|
|
8155 |
|
|
/* rdhi, rdlo and rm must all be different before armv6. */
|
8156 |
|
|
if ((inst.operands[0].reg == inst.operands[2].reg
|
8157 |
|
|
|| inst.operands[1].reg == inst.operands[2].reg)
|
8158 |
|
|
&& !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
|
8159 |
|
|
as_tsktsk (_("rdhi, rdlo and rm must all be different"));
|
8160 |
|
|
}
|
8161 |
|
|
|
8162 |
|
|
static void
|
8163 |
|
|
do_nop (void)
|
8164 |
|
|
{
|
8165 |
|
|
if (inst.operands[0].present
|
8166 |
|
|
|| ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
|
8167 |
|
|
{
|
8168 |
|
|
/* Architectural NOP hints are CPSR sets with no bits selected. */
|
8169 |
|
|
inst.instruction &= 0xf0000000;
|
8170 |
|
|
inst.instruction |= 0x0320f000;
|
8171 |
|
|
if (inst.operands[0].present)
|
8172 |
|
|
inst.instruction |= inst.operands[0].imm;
|
8173 |
|
|
}
|
8174 |
|
|
}
|
8175 |
|
|
|
8176 |
|
|
/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
|
8177 |
|
|
PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
|
8178 |
|
|
Condition defaults to COND_ALWAYS.
|
8179 |
|
|
Error if Rd, Rn or Rm are R15. */
|
8180 |
|
|
|
8181 |
|
|
static void
|
8182 |
|
|
do_pkhbt (void)
|
8183 |
|
|
{
|
8184 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8185 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
8186 |
|
|
inst.instruction |= inst.operands[2].reg;
|
8187 |
|
|
if (inst.operands[3].present)
|
8188 |
|
|
encode_arm_shift (3);
|
8189 |
|
|
}
|
8190 |
|
|
|
8191 |
|
|
/* ARM V6 PKHTB (Argument Parse). */
|
8192 |
|
|
|
8193 |
|
|
static void
|
8194 |
|
|
do_pkhtb (void)
|
8195 |
|
|
{
|
8196 |
|
|
if (!inst.operands[3].present)
|
8197 |
|
|
{
|
8198 |
|
|
/* If the shift specifier is omitted, turn the instruction
|
8199 |
|
|
into pkhbt rd, rm, rn. */
|
8200 |
|
|
inst.instruction &= 0xfff00010;
|
8201 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8202 |
|
|
inst.instruction |= inst.operands[1].reg;
|
8203 |
|
|
inst.instruction |= inst.operands[2].reg << 16;
|
8204 |
|
|
}
|
8205 |
|
|
else
|
8206 |
|
|
{
|
8207 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8208 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
8209 |
|
|
inst.instruction |= inst.operands[2].reg;
|
8210 |
|
|
encode_arm_shift (3);
|
8211 |
|
|
}
|
8212 |
|
|
}
|
8213 |
|
|
|
8214 |
|
|
/* ARMv5TE: Preload-Cache
|
8215 |
|
|
MP Extensions: Preload for write
|
8216 |
|
|
|
8217 |
|
|
PLD(W) <addr_mode>
|
8218 |
|
|
|
8219 |
|
|
Syntactically, like LDR with B=1, W=0, L=1. */
|
8220 |
|
|
|
8221 |
|
|
static void
|
8222 |
|
|
do_pld (void)
|
8223 |
|
|
{
|
8224 |
|
|
constraint (!inst.operands[0].isreg,
|
8225 |
|
|
_("'[' expected after PLD mnemonic"));
|
8226 |
|
|
constraint (inst.operands[0].postind,
|
8227 |
|
|
_("post-indexed expression used in preload instruction"));
|
8228 |
|
|
constraint (inst.operands[0].writeback,
|
8229 |
|
|
_("writeback used in preload instruction"));
|
8230 |
|
|
constraint (!inst.operands[0].preind,
|
8231 |
|
|
_("unindexed addressing used in preload instruction"));
|
8232 |
|
|
encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
|
8233 |
|
|
}
|
8234 |
|
|
|
8235 |
|
|
/* ARMv7: PLI <addr_mode> */
|
8236 |
|
|
static void
|
8237 |
|
|
do_pli (void)
|
8238 |
|
|
{
|
8239 |
|
|
constraint (!inst.operands[0].isreg,
|
8240 |
|
|
_("'[' expected after PLI mnemonic"));
|
8241 |
|
|
constraint (inst.operands[0].postind,
|
8242 |
|
|
_("post-indexed expression used in preload instruction"));
|
8243 |
|
|
constraint (inst.operands[0].writeback,
|
8244 |
|
|
_("writeback used in preload instruction"));
|
8245 |
|
|
constraint (!inst.operands[0].preind,
|
8246 |
|
|
_("unindexed addressing used in preload instruction"));
|
8247 |
|
|
encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
|
8248 |
|
|
inst.instruction &= ~PRE_INDEX;
|
8249 |
|
|
}
|
8250 |
|
|
|
8251 |
|
|
static void
|
8252 |
|
|
do_push_pop (void)
|
8253 |
|
|
{
|
8254 |
|
|
inst.operands[1] = inst.operands[0];
|
8255 |
|
|
memset (&inst.operands[0], 0, sizeof inst.operands[0]);
|
8256 |
|
|
inst.operands[0].isreg = 1;
|
8257 |
|
|
inst.operands[0].writeback = 1;
|
8258 |
|
|
inst.operands[0].reg = REG_SP;
|
8259 |
|
|
do_ldmstm ();
|
8260 |
|
|
}
|
8261 |
|
|
|
8262 |
|
|
/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
|
8263 |
|
|
word at the specified address and the following word
|
8264 |
|
|
respectively.
|
8265 |
|
|
Unconditionally executed.
|
8266 |
|
|
Error if Rn is R15. */
|
8267 |
|
|
|
8268 |
|
|
static void
|
8269 |
|
|
do_rfe (void)
|
8270 |
|
|
{
|
8271 |
|
|
inst.instruction |= inst.operands[0].reg << 16;
|
8272 |
|
|
if (inst.operands[0].writeback)
|
8273 |
|
|
inst.instruction |= WRITE_BACK;
|
8274 |
|
|
}
|
8275 |
|
|
|
8276 |
|
|
/* ARM V6 ssat (argument parse). */
|
8277 |
|
|
|
8278 |
|
|
static void
|
8279 |
|
|
do_ssat (void)
|
8280 |
|
|
{
|
8281 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8282 |
|
|
inst.instruction |= (inst.operands[1].imm - 1) << 16;
|
8283 |
|
|
inst.instruction |= inst.operands[2].reg;
|
8284 |
|
|
|
8285 |
|
|
if (inst.operands[3].present)
|
8286 |
|
|
encode_arm_shift (3);
|
8287 |
|
|
}
|
8288 |
|
|
|
8289 |
|
|
/* ARM V6 usat (argument parse). */
|
8290 |
|
|
|
8291 |
|
|
static void
|
8292 |
|
|
do_usat (void)
|
8293 |
|
|
{
|
8294 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8295 |
|
|
inst.instruction |= inst.operands[1].imm << 16;
|
8296 |
|
|
inst.instruction |= inst.operands[2].reg;
|
8297 |
|
|
|
8298 |
|
|
if (inst.operands[3].present)
|
8299 |
|
|
encode_arm_shift (3);
|
8300 |
|
|
}
|
8301 |
|
|
|
8302 |
|
|
/* ARM V6 ssat16 (argument parse). */
|
8303 |
|
|
|
8304 |
|
|
static void
|
8305 |
|
|
do_ssat16 (void)
|
8306 |
|
|
{
|
8307 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8308 |
|
|
inst.instruction |= ((inst.operands[1].imm - 1) << 16);
|
8309 |
|
|
inst.instruction |= inst.operands[2].reg;
|
8310 |
|
|
}
|
8311 |
|
|
|
8312 |
|
|
static void
|
8313 |
|
|
do_usat16 (void)
|
8314 |
|
|
{
|
8315 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8316 |
|
|
inst.instruction |= inst.operands[1].imm << 16;
|
8317 |
|
|
inst.instruction |= inst.operands[2].reg;
|
8318 |
|
|
}
|
8319 |
|
|
|
8320 |
|
|
/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
|
8321 |
|
|
preserving the other bits.
|
8322 |
|
|
|
8323 |
|
|
setend <endian_specifier>, where <endian_specifier> is either
|
8324 |
|
|
BE or LE. */
|
8325 |
|
|
|
8326 |
|
|
static void
|
8327 |
|
|
do_setend (void)
|
8328 |
|
|
{
|
8329 |
|
|
if (inst.operands[0].imm)
|
8330 |
|
|
inst.instruction |= 0x200;
|
8331 |
|
|
}
|
8332 |
|
|
|
8333 |
|
|
static void
|
8334 |
|
|
do_shift (void)
|
8335 |
|
|
{
|
8336 |
|
|
unsigned int Rm = (inst.operands[1].present
|
8337 |
|
|
? inst.operands[1].reg
|
8338 |
|
|
: inst.operands[0].reg);
|
8339 |
|
|
|
8340 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8341 |
|
|
inst.instruction |= Rm;
|
8342 |
|
|
if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
|
8343 |
|
|
{
|
8344 |
|
|
inst.instruction |= inst.operands[2].reg << 8;
|
8345 |
|
|
inst.instruction |= SHIFT_BY_REG;
|
8346 |
148 |
khays |
/* PR 12854: Error on extraneous shifts. */
|
8347 |
|
|
constraint (inst.operands[2].shifted,
|
8348 |
|
|
_("extraneous shift as part of operand to shift insn"));
|
8349 |
16 |
khays |
}
|
8350 |
|
|
else
|
8351 |
|
|
inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
|
8352 |
|
|
}
|
8353 |
|
|
|
8354 |
|
|
static void
|
8355 |
|
|
do_smc (void)
|
8356 |
|
|
{
|
8357 |
|
|
inst.reloc.type = BFD_RELOC_ARM_SMC;
|
8358 |
|
|
inst.reloc.pc_rel = 0;
|
8359 |
|
|
}
|
8360 |
|
|
|
8361 |
|
|
static void
|
8362 |
|
|
do_hvc (void)
|
8363 |
|
|
{
|
8364 |
|
|
inst.reloc.type = BFD_RELOC_ARM_HVC;
|
8365 |
|
|
inst.reloc.pc_rel = 0;
|
8366 |
|
|
}
|
8367 |
|
|
|
8368 |
|
|
static void
|
8369 |
|
|
do_swi (void)
|
8370 |
|
|
{
|
8371 |
|
|
inst.reloc.type = BFD_RELOC_ARM_SWI;
|
8372 |
|
|
inst.reloc.pc_rel = 0;
|
8373 |
|
|
}
|
8374 |
|
|
|
8375 |
|
|
/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
|
8376 |
|
|
SMLAxy{cond} Rd,Rm,Rs,Rn
|
8377 |
|
|
SMLAWy{cond} Rd,Rm,Rs,Rn
|
8378 |
|
|
Error if any register is R15. */
|
8379 |
|
|
|
8380 |
|
|
static void
|
8381 |
|
|
do_smla (void)
|
8382 |
|
|
{
|
8383 |
|
|
inst.instruction |= inst.operands[0].reg << 16;
|
8384 |
|
|
inst.instruction |= inst.operands[1].reg;
|
8385 |
|
|
inst.instruction |= inst.operands[2].reg << 8;
|
8386 |
|
|
inst.instruction |= inst.operands[3].reg << 12;
|
8387 |
|
|
}
|
8388 |
|
|
|
8389 |
|
|
/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
|
8390 |
|
|
SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
|
8391 |
|
|
Error if any register is R15.
|
8392 |
|
|
Warning if Rdlo == Rdhi. */
|
8393 |
|
|
|
8394 |
|
|
static void
|
8395 |
|
|
do_smlal (void)
|
8396 |
|
|
{
|
8397 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8398 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
8399 |
|
|
inst.instruction |= inst.operands[2].reg;
|
8400 |
|
|
inst.instruction |= inst.operands[3].reg << 8;
|
8401 |
|
|
|
8402 |
|
|
if (inst.operands[0].reg == inst.operands[1].reg)
|
8403 |
|
|
as_tsktsk (_("rdhi and rdlo must be different"));
|
8404 |
|
|
}
|
8405 |
|
|
|
8406 |
|
|
/* ARM V5E (El Segundo) signed-multiply (argument parse)
|
8407 |
|
|
SMULxy{cond} Rd,Rm,Rs
|
8408 |
|
|
Error if any register is R15. */
|
8409 |
|
|
|
8410 |
|
|
static void
|
8411 |
|
|
do_smul (void)
|
8412 |
|
|
{
|
8413 |
|
|
inst.instruction |= inst.operands[0].reg << 16;
|
8414 |
|
|
inst.instruction |= inst.operands[1].reg;
|
8415 |
|
|
inst.instruction |= inst.operands[2].reg << 8;
|
8416 |
|
|
}
|
8417 |
|
|
|
8418 |
|
|
/* ARM V6 srs (argument parse). The variable fields in the encoding are
|
8419 |
|
|
the same for both ARM and Thumb-2. */
|
8420 |
|
|
|
8421 |
|
|
static void
|
8422 |
|
|
do_srs (void)
|
8423 |
|
|
{
|
8424 |
|
|
int reg;
|
8425 |
|
|
|
8426 |
|
|
if (inst.operands[0].present)
|
8427 |
|
|
{
|
8428 |
|
|
reg = inst.operands[0].reg;
|
8429 |
|
|
constraint (reg != REG_SP, _("SRS base register must be r13"));
|
8430 |
|
|
}
|
8431 |
|
|
else
|
8432 |
|
|
reg = REG_SP;
|
8433 |
|
|
|
8434 |
|
|
inst.instruction |= reg << 16;
|
8435 |
|
|
inst.instruction |= inst.operands[1].imm;
|
8436 |
|
|
if (inst.operands[0].writeback || inst.operands[1].writeback)
|
8437 |
|
|
inst.instruction |= WRITE_BACK;
|
8438 |
|
|
}
|
8439 |
|
|
|
8440 |
|
|
/* ARM V6 strex (argument parse). */
|
8441 |
|
|
|
8442 |
|
|
static void
|
8443 |
|
|
do_strex (void)
|
8444 |
|
|
{
|
8445 |
|
|
constraint (!inst.operands[2].isreg || !inst.operands[2].preind
|
8446 |
|
|
|| inst.operands[2].postind || inst.operands[2].writeback
|
8447 |
|
|
|| inst.operands[2].immisreg || inst.operands[2].shifted
|
8448 |
|
|
|| inst.operands[2].negative
|
8449 |
|
|
/* See comment in do_ldrex(). */
|
8450 |
|
|
|| (inst.operands[2].reg == REG_PC),
|
8451 |
|
|
BAD_ADDR_MODE);
|
8452 |
|
|
|
8453 |
|
|
constraint (inst.operands[0].reg == inst.operands[1].reg
|
8454 |
|
|
|| inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
|
8455 |
|
|
|
8456 |
|
|
constraint (inst.reloc.exp.X_op != O_constant
|
8457 |
|
|
|| inst.reloc.exp.X_add_number != 0,
|
8458 |
|
|
_("offset must be zero in ARM encoding"));
|
8459 |
|
|
|
8460 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8461 |
|
|
inst.instruction |= inst.operands[1].reg;
|
8462 |
|
|
inst.instruction |= inst.operands[2].reg << 16;
|
8463 |
|
|
inst.reloc.type = BFD_RELOC_UNUSED;
|
8464 |
|
|
}
|
8465 |
|
|
|
8466 |
|
|
static void
|
8467 |
|
|
do_strexd (void)
|
8468 |
|
|
{
|
8469 |
|
|
constraint (inst.operands[1].reg % 2 != 0,
|
8470 |
|
|
_("even register required"));
|
8471 |
|
|
constraint (inst.operands[2].present
|
8472 |
|
|
&& inst.operands[2].reg != inst.operands[1].reg + 1,
|
8473 |
|
|
_("can only store two consecutive registers"));
|
8474 |
|
|
/* If op 2 were present and equal to PC, this function wouldn't
|
8475 |
|
|
have been called in the first place. */
|
8476 |
|
|
constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
|
8477 |
|
|
|
8478 |
|
|
constraint (inst.operands[0].reg == inst.operands[1].reg
|
8479 |
|
|
|| inst.operands[0].reg == inst.operands[1].reg + 1
|
8480 |
|
|
|| inst.operands[0].reg == inst.operands[3].reg,
|
8481 |
|
|
BAD_OVERLAP);
|
8482 |
|
|
|
8483 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8484 |
|
|
inst.instruction |= inst.operands[1].reg;
|
8485 |
|
|
inst.instruction |= inst.operands[3].reg << 16;
|
8486 |
|
|
}
|
8487 |
|
|
|
8488 |
|
|
/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
|
8489 |
|
|
extends it to 32-bits, and adds the result to a value in another
|
8490 |
|
|
register. You can specify a rotation by 0, 8, 16, or 24 bits
|
8491 |
|
|
before extracting the 16-bit value.
|
8492 |
|
|
SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
|
8493 |
|
|
Condition defaults to COND_ALWAYS.
|
8494 |
|
|
Error if any register uses R15. */
|
8495 |
|
|
|
8496 |
|
|
static void
|
8497 |
|
|
do_sxtah (void)
|
8498 |
|
|
{
|
8499 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8500 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
8501 |
|
|
inst.instruction |= inst.operands[2].reg;
|
8502 |
|
|
inst.instruction |= inst.operands[3].imm << 10;
|
8503 |
|
|
}
|
8504 |
|
|
|
8505 |
|
|
/* ARM V6 SXTH.
|
8506 |
|
|
|
8507 |
|
|
SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
|
8508 |
|
|
Condition defaults to COND_ALWAYS.
|
8509 |
|
|
Error if any register uses R15. */
|
8510 |
|
|
|
8511 |
|
|
static void
|
8512 |
|
|
do_sxth (void)
|
8513 |
|
|
{
|
8514 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8515 |
|
|
inst.instruction |= inst.operands[1].reg;
|
8516 |
|
|
inst.instruction |= inst.operands[2].imm << 10;
|
8517 |
|
|
}
|
8518 |
|
|
|
8519 |
|
|
/* VFP instructions. In a logical order: SP variant first, monad
|
8520 |
|
|
before dyad, arithmetic then move then load/store. */
|
8521 |
|
|
|
8522 |
|
|
static void
|
8523 |
|
|
do_vfp_sp_monadic (void)
|
8524 |
|
|
{
|
8525 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
|
8526 |
|
|
encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
|
8527 |
|
|
}
|
8528 |
|
|
|
8529 |
|
|
static void
|
8530 |
|
|
do_vfp_sp_dyadic (void)
|
8531 |
|
|
{
|
8532 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
|
8533 |
|
|
encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
|
8534 |
|
|
encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
|
8535 |
|
|
}
|
8536 |
|
|
|
8537 |
|
|
static void
|
8538 |
|
|
do_vfp_sp_compare_z (void)
|
8539 |
|
|
{
|
8540 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
|
8541 |
|
|
}
|
8542 |
|
|
|
8543 |
|
|
static void
|
8544 |
|
|
do_vfp_dp_sp_cvt (void)
|
8545 |
|
|
{
|
8546 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
|
8547 |
|
|
encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
|
8548 |
|
|
}
|
8549 |
|
|
|
8550 |
|
|
static void
|
8551 |
|
|
do_vfp_sp_dp_cvt (void)
|
8552 |
|
|
{
|
8553 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
|
8554 |
|
|
encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
|
8555 |
|
|
}
|
8556 |
|
|
|
8557 |
|
|
static void
|
8558 |
|
|
do_vfp_reg_from_sp (void)
|
8559 |
|
|
{
|
8560 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8561 |
|
|
encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
|
8562 |
|
|
}
|
8563 |
|
|
|
8564 |
|
|
static void
|
8565 |
|
|
do_vfp_reg2_from_sp2 (void)
|
8566 |
|
|
{
|
8567 |
|
|
constraint (inst.operands[2].imm != 2,
|
8568 |
|
|
_("only two consecutive VFP SP registers allowed here"));
|
8569 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8570 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
8571 |
|
|
encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
|
8572 |
|
|
}
|
8573 |
|
|
|
8574 |
|
|
static void
|
8575 |
|
|
do_vfp_sp_from_reg (void)
|
8576 |
|
|
{
|
8577 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
|
8578 |
|
|
inst.instruction |= inst.operands[1].reg << 12;
|
8579 |
|
|
}
|
8580 |
|
|
|
8581 |
|
|
static void
|
8582 |
|
|
do_vfp_sp2_from_reg2 (void)
|
8583 |
|
|
{
|
8584 |
|
|
constraint (inst.operands[0].imm != 2,
|
8585 |
|
|
_("only two consecutive VFP SP registers allowed here"));
|
8586 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
|
8587 |
|
|
inst.instruction |= inst.operands[1].reg << 12;
|
8588 |
|
|
inst.instruction |= inst.operands[2].reg << 16;
|
8589 |
|
|
}
|
8590 |
|
|
|
8591 |
|
|
static void
|
8592 |
|
|
do_vfp_sp_ldst (void)
|
8593 |
|
|
{
|
8594 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
|
8595 |
|
|
encode_arm_cp_address (1, FALSE, TRUE, 0);
|
8596 |
|
|
}
|
8597 |
|
|
|
8598 |
|
|
static void
|
8599 |
|
|
do_vfp_dp_ldst (void)
|
8600 |
|
|
{
|
8601 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
|
8602 |
|
|
encode_arm_cp_address (1, FALSE, TRUE, 0);
|
8603 |
|
|
}
|
8604 |
|
|
|
8605 |
|
|
|
8606 |
|
|
static void
|
8607 |
|
|
vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
|
8608 |
|
|
{
|
8609 |
|
|
if (inst.operands[0].writeback)
|
8610 |
|
|
inst.instruction |= WRITE_BACK;
|
8611 |
|
|
else
|
8612 |
|
|
constraint (ldstm_type != VFP_LDSTMIA,
|
8613 |
|
|
_("this addressing mode requires base-register writeback"));
|
8614 |
|
|
inst.instruction |= inst.operands[0].reg << 16;
|
8615 |
|
|
encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
|
8616 |
|
|
inst.instruction |= inst.operands[1].imm;
|
8617 |
|
|
}
|
8618 |
|
|
|
8619 |
|
|
static void
|
8620 |
|
|
vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
|
8621 |
|
|
{
|
8622 |
|
|
int count;
|
8623 |
|
|
|
8624 |
|
|
if (inst.operands[0].writeback)
|
8625 |
|
|
inst.instruction |= WRITE_BACK;
|
8626 |
|
|
else
|
8627 |
|
|
constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
|
8628 |
|
|
_("this addressing mode requires base-register writeback"));
|
8629 |
|
|
|
8630 |
|
|
inst.instruction |= inst.operands[0].reg << 16;
|
8631 |
|
|
encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
|
8632 |
|
|
|
8633 |
|
|
count = inst.operands[1].imm << 1;
|
8634 |
|
|
if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
|
8635 |
|
|
count += 1;
|
8636 |
|
|
|
8637 |
|
|
inst.instruction |= count;
|
8638 |
|
|
}
|
8639 |
|
|
|
8640 |
|
|
static void
|
8641 |
|
|
do_vfp_sp_ldstmia (void)
|
8642 |
|
|
{
|
8643 |
|
|
vfp_sp_ldstm (VFP_LDSTMIA);
|
8644 |
|
|
}
|
8645 |
|
|
|
8646 |
|
|
static void
|
8647 |
|
|
do_vfp_sp_ldstmdb (void)
|
8648 |
|
|
{
|
8649 |
|
|
vfp_sp_ldstm (VFP_LDSTMDB);
|
8650 |
|
|
}
|
8651 |
|
|
|
8652 |
|
|
static void
|
8653 |
|
|
do_vfp_dp_ldstmia (void)
|
8654 |
|
|
{
|
8655 |
|
|
vfp_dp_ldstm (VFP_LDSTMIA);
|
8656 |
|
|
}
|
8657 |
|
|
|
8658 |
|
|
static void
|
8659 |
|
|
do_vfp_dp_ldstmdb (void)
|
8660 |
|
|
{
|
8661 |
|
|
vfp_dp_ldstm (VFP_LDSTMDB);
|
8662 |
|
|
}
|
8663 |
|
|
|
8664 |
|
|
static void
|
8665 |
|
|
do_vfp_xp_ldstmia (void)
|
8666 |
|
|
{
|
8667 |
|
|
vfp_dp_ldstm (VFP_LDSTMIAX);
|
8668 |
|
|
}
|
8669 |
|
|
|
8670 |
|
|
static void
|
8671 |
|
|
do_vfp_xp_ldstmdb (void)
|
8672 |
|
|
{
|
8673 |
|
|
vfp_dp_ldstm (VFP_LDSTMDBX);
|
8674 |
|
|
}
|
8675 |
|
|
|
8676 |
|
|
static void
|
8677 |
|
|
do_vfp_dp_rd_rm (void)
|
8678 |
|
|
{
|
8679 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
|
8680 |
|
|
encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
|
8681 |
|
|
}
|
8682 |
|
|
|
8683 |
|
|
static void
|
8684 |
|
|
do_vfp_dp_rn_rd (void)
|
8685 |
|
|
{
|
8686 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
|
8687 |
|
|
encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
|
8688 |
|
|
}
|
8689 |
|
|
|
8690 |
|
|
static void
|
8691 |
|
|
do_vfp_dp_rd_rn (void)
|
8692 |
|
|
{
|
8693 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
|
8694 |
|
|
encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
|
8695 |
|
|
}
|
8696 |
|
|
|
8697 |
|
|
static void
|
8698 |
|
|
do_vfp_dp_rd_rn_rm (void)
|
8699 |
|
|
{
|
8700 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
|
8701 |
|
|
encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
|
8702 |
|
|
encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
|
8703 |
|
|
}
|
8704 |
|
|
|
8705 |
|
|
static void
|
8706 |
|
|
do_vfp_dp_rd (void)
|
8707 |
|
|
{
|
8708 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
|
8709 |
|
|
}
|
8710 |
|
|
|
8711 |
|
|
static void
|
8712 |
|
|
do_vfp_dp_rm_rd_rn (void)
|
8713 |
|
|
{
|
8714 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
|
8715 |
|
|
encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
|
8716 |
|
|
encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
|
8717 |
|
|
}
|
8718 |
|
|
|
8719 |
|
|
/* VFPv3 instructions. */
|
8720 |
|
|
static void
|
8721 |
|
|
do_vfp_sp_const (void)
|
8722 |
|
|
{
|
8723 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
|
8724 |
|
|
inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
|
8725 |
|
|
inst.instruction |= (inst.operands[1].imm & 0x0f);
|
8726 |
|
|
}
|
8727 |
|
|
|
8728 |
|
|
static void
|
8729 |
|
|
do_vfp_dp_const (void)
|
8730 |
|
|
{
|
8731 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
|
8732 |
|
|
inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
|
8733 |
|
|
inst.instruction |= (inst.operands[1].imm & 0x0f);
|
8734 |
|
|
}
|
8735 |
|
|
|
8736 |
|
|
static void
|
8737 |
|
|
vfp_conv (int srcsize)
|
8738 |
|
|
{
|
8739 |
|
|
unsigned immbits = srcsize - inst.operands[1].imm;
|
8740 |
|
|
inst.instruction |= (immbits & 1) << 5;
|
8741 |
|
|
inst.instruction |= (immbits >> 1);
|
8742 |
|
|
}
|
8743 |
|
|
|
8744 |
|
|
static void
|
8745 |
|
|
do_vfp_sp_conv_16 (void)
|
8746 |
|
|
{
|
8747 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
|
8748 |
|
|
vfp_conv (16);
|
8749 |
|
|
}
|
8750 |
|
|
|
8751 |
|
|
static void
|
8752 |
|
|
do_vfp_dp_conv_16 (void)
|
8753 |
|
|
{
|
8754 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
|
8755 |
|
|
vfp_conv (16);
|
8756 |
|
|
}
|
8757 |
|
|
|
8758 |
|
|
static void
|
8759 |
|
|
do_vfp_sp_conv_32 (void)
|
8760 |
|
|
{
|
8761 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
|
8762 |
|
|
vfp_conv (32);
|
8763 |
|
|
}
|
8764 |
|
|
|
8765 |
|
|
static void
|
8766 |
|
|
do_vfp_dp_conv_32 (void)
|
8767 |
|
|
{
|
8768 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
|
8769 |
|
|
vfp_conv (32);
|
8770 |
|
|
}
|
8771 |
|
|
|
8772 |
|
|
/* FPA instructions. Also in a logical order. */
|
8773 |
|
|
|
8774 |
|
|
static void
|
8775 |
|
|
do_fpa_cmp (void)
|
8776 |
|
|
{
|
8777 |
|
|
inst.instruction |= inst.operands[0].reg << 16;
|
8778 |
|
|
inst.instruction |= inst.operands[1].reg;
|
8779 |
|
|
}
|
8780 |
|
|
|
8781 |
|
|
static void
|
8782 |
|
|
do_fpa_ldmstm (void)
|
8783 |
|
|
{
|
8784 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8785 |
|
|
switch (inst.operands[1].imm)
|
8786 |
|
|
{
|
8787 |
|
|
case 1: inst.instruction |= CP_T_X; break;
|
8788 |
|
|
case 2: inst.instruction |= CP_T_Y; break;
|
8789 |
|
|
case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
|
8790 |
|
|
case 4: break;
|
8791 |
|
|
default: abort ();
|
8792 |
|
|
}
|
8793 |
|
|
|
8794 |
|
|
if (inst.instruction & (PRE_INDEX | INDEX_UP))
|
8795 |
|
|
{
|
8796 |
|
|
/* The instruction specified "ea" or "fd", so we can only accept
|
8797 |
|
|
[Rn]{!}. The instruction does not really support stacking or
|
8798 |
|
|
unstacking, so we have to emulate these by setting appropriate
|
8799 |
|
|
bits and offsets. */
|
8800 |
|
|
constraint (inst.reloc.exp.X_op != O_constant
|
8801 |
|
|
|| inst.reloc.exp.X_add_number != 0,
|
8802 |
|
|
_("this instruction does not support indexing"));
|
8803 |
|
|
|
8804 |
|
|
if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
|
8805 |
|
|
inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
|
8806 |
|
|
|
8807 |
|
|
if (!(inst.instruction & INDEX_UP))
|
8808 |
|
|
inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
|
8809 |
|
|
|
8810 |
|
|
if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
|
8811 |
|
|
{
|
8812 |
|
|
inst.operands[2].preind = 0;
|
8813 |
|
|
inst.operands[2].postind = 1;
|
8814 |
|
|
}
|
8815 |
|
|
}
|
8816 |
|
|
|
8817 |
|
|
encode_arm_cp_address (2, TRUE, TRUE, 0);
|
8818 |
|
|
}
|
8819 |
|
|
|
8820 |
|
|
/* iWMMXt instructions: strictly in alphabetical order. */
|
8821 |
|
|
|
8822 |
|
|
static void
|
8823 |
|
|
do_iwmmxt_tandorc (void)
|
8824 |
|
|
{
|
8825 |
|
|
constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
|
8826 |
|
|
}
|
8827 |
|
|
|
8828 |
|
|
static void
|
8829 |
|
|
do_iwmmxt_textrc (void)
|
8830 |
|
|
{
|
8831 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8832 |
|
|
inst.instruction |= inst.operands[1].imm;
|
8833 |
|
|
}
|
8834 |
|
|
|
8835 |
|
|
static void
|
8836 |
|
|
do_iwmmxt_textrm (void)
|
8837 |
|
|
{
|
8838 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8839 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
8840 |
|
|
inst.instruction |= inst.operands[2].imm;
|
8841 |
|
|
}
|
8842 |
|
|
|
8843 |
|
|
static void
|
8844 |
|
|
do_iwmmxt_tinsr (void)
|
8845 |
|
|
{
|
8846 |
|
|
inst.instruction |= inst.operands[0].reg << 16;
|
8847 |
|
|
inst.instruction |= inst.operands[1].reg << 12;
|
8848 |
|
|
inst.instruction |= inst.operands[2].imm;
|
8849 |
|
|
}
|
8850 |
|
|
|
8851 |
|
|
static void
|
8852 |
|
|
do_iwmmxt_tmia (void)
|
8853 |
|
|
{
|
8854 |
|
|
inst.instruction |= inst.operands[0].reg << 5;
|
8855 |
|
|
inst.instruction |= inst.operands[1].reg;
|
8856 |
|
|
inst.instruction |= inst.operands[2].reg << 12;
|
8857 |
|
|
}
|
8858 |
|
|
|
8859 |
|
|
static void
|
8860 |
|
|
do_iwmmxt_waligni (void)
|
8861 |
|
|
{
|
8862 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8863 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
8864 |
|
|
inst.instruction |= inst.operands[2].reg;
|
8865 |
|
|
inst.instruction |= inst.operands[3].imm << 20;
|
8866 |
|
|
}
|
8867 |
|
|
|
8868 |
|
|
static void
|
8869 |
|
|
do_iwmmxt_wmerge (void)
|
8870 |
|
|
{
|
8871 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8872 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
8873 |
|
|
inst.instruction |= inst.operands[2].reg;
|
8874 |
|
|
inst.instruction |= inst.operands[3].imm << 21;
|
8875 |
|
|
}
|
8876 |
|
|
|
8877 |
|
|
static void
|
8878 |
|
|
do_iwmmxt_wmov (void)
|
8879 |
|
|
{
|
8880 |
|
|
/* WMOV rD, rN is an alias for WOR rD, rN, rN. */
|
8881 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8882 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
8883 |
|
|
inst.instruction |= inst.operands[1].reg;
|
8884 |
|
|
}
|
8885 |
|
|
|
8886 |
|
|
static void
|
8887 |
|
|
do_iwmmxt_wldstbh (void)
|
8888 |
|
|
{
|
8889 |
|
|
int reloc;
|
8890 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8891 |
|
|
if (thumb_mode)
|
8892 |
|
|
reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
|
8893 |
|
|
else
|
8894 |
|
|
reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
|
8895 |
|
|
encode_arm_cp_address (1, TRUE, FALSE, reloc);
|
8896 |
|
|
}
|
8897 |
|
|
|
8898 |
|
|
static void
|
8899 |
|
|
do_iwmmxt_wldstw (void)
|
8900 |
|
|
{
|
8901 |
|
|
/* RIWR_RIWC clears .isreg for a control register. */
|
8902 |
|
|
if (!inst.operands[0].isreg)
|
8903 |
|
|
{
|
8904 |
|
|
constraint (inst.cond != COND_ALWAYS, BAD_COND);
|
8905 |
|
|
inst.instruction |= 0xf0000000;
|
8906 |
|
|
}
|
8907 |
|
|
|
8908 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8909 |
|
|
encode_arm_cp_address (1, TRUE, TRUE, 0);
|
8910 |
|
|
}
|
8911 |
|
|
|
8912 |
|
|
static void
|
8913 |
|
|
do_iwmmxt_wldstd (void)
|
8914 |
|
|
{
|
8915 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8916 |
|
|
if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
|
8917 |
|
|
&& inst.operands[1].immisreg)
|
8918 |
|
|
{
|
8919 |
|
|
inst.instruction &= ~0x1a000ff;
|
8920 |
|
|
inst.instruction |= (0xf << 28);
|
8921 |
|
|
if (inst.operands[1].preind)
|
8922 |
|
|
inst.instruction |= PRE_INDEX;
|
8923 |
|
|
if (!inst.operands[1].negative)
|
8924 |
|
|
inst.instruction |= INDEX_UP;
|
8925 |
|
|
if (inst.operands[1].writeback)
|
8926 |
|
|
inst.instruction |= WRITE_BACK;
|
8927 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
8928 |
|
|
inst.instruction |= inst.reloc.exp.X_add_number << 4;
|
8929 |
|
|
inst.instruction |= inst.operands[1].imm;
|
8930 |
|
|
}
|
8931 |
|
|
else
|
8932 |
|
|
encode_arm_cp_address (1, TRUE, FALSE, 0);
|
8933 |
|
|
}
|
8934 |
|
|
|
8935 |
|
|
static void
|
8936 |
|
|
do_iwmmxt_wshufh (void)
|
8937 |
|
|
{
|
8938 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8939 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
8940 |
|
|
inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
|
8941 |
|
|
inst.instruction |= (inst.operands[2].imm & 0x0f);
|
8942 |
|
|
}
|
8943 |
|
|
|
8944 |
|
|
static void
|
8945 |
|
|
do_iwmmxt_wzero (void)
|
8946 |
|
|
{
|
8947 |
|
|
/* WZERO reg is an alias for WANDN reg, reg, reg. */
|
8948 |
|
|
inst.instruction |= inst.operands[0].reg;
|
8949 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
8950 |
|
|
inst.instruction |= inst.operands[0].reg << 16;
|
8951 |
|
|
}
|
8952 |
|
|
|
8953 |
|
|
static void
|
8954 |
|
|
do_iwmmxt_wrwrwr_or_imm5 (void)
|
8955 |
|
|
{
|
8956 |
|
|
if (inst.operands[2].isreg)
|
8957 |
|
|
do_rd_rn_rm ();
|
8958 |
|
|
else {
|
8959 |
|
|
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
|
8960 |
|
|
_("immediate operand requires iWMMXt2"));
|
8961 |
|
|
do_rd_rn ();
|
8962 |
|
|
if (inst.operands[2].imm == 0)
|
8963 |
|
|
{
|
8964 |
|
|
switch ((inst.instruction >> 20) & 0xf)
|
8965 |
|
|
{
|
8966 |
|
|
case 4:
|
8967 |
|
|
case 5:
|
8968 |
|
|
case 6:
|
8969 |
|
|
case 7:
|
8970 |
|
|
/* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
|
8971 |
|
|
inst.operands[2].imm = 16;
|
8972 |
|
|
inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
|
8973 |
|
|
break;
|
8974 |
|
|
case 8:
|
8975 |
|
|
case 9:
|
8976 |
|
|
case 10:
|
8977 |
|
|
case 11:
|
8978 |
|
|
/* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
|
8979 |
|
|
inst.operands[2].imm = 32;
|
8980 |
|
|
inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
|
8981 |
|
|
break;
|
8982 |
|
|
case 12:
|
8983 |
|
|
case 13:
|
8984 |
|
|
case 14:
|
8985 |
|
|
case 15:
|
8986 |
|
|
{
|
8987 |
|
|
/* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
|
8988 |
|
|
unsigned long wrn;
|
8989 |
|
|
wrn = (inst.instruction >> 16) & 0xf;
|
8990 |
|
|
inst.instruction &= 0xff0fff0f;
|
8991 |
|
|
inst.instruction |= wrn;
|
8992 |
|
|
/* Bail out here; the instruction is now assembled. */
|
8993 |
|
|
return;
|
8994 |
|
|
}
|
8995 |
|
|
}
|
8996 |
|
|
}
|
8997 |
|
|
/* Map 32 -> 0, etc. */
|
8998 |
|
|
inst.operands[2].imm &= 0x1f;
|
8999 |
|
|
inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
|
9000 |
|
|
}
|
9001 |
|
|
}
|
9002 |
|
|
|
9003 |
|
|
/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
|
9004 |
|
|
operations first, then control, shift, and load/store. */
|
9005 |
|
|
|
9006 |
|
|
/* Insns like "foo X,Y,Z". */
|
9007 |
|
|
|
9008 |
|
|
static void
|
9009 |
|
|
do_mav_triple (void)
|
9010 |
|
|
{
|
9011 |
|
|
inst.instruction |= inst.operands[0].reg << 16;
|
9012 |
|
|
inst.instruction |= inst.operands[1].reg;
|
9013 |
|
|
inst.instruction |= inst.operands[2].reg << 12;
|
9014 |
|
|
}
|
9015 |
|
|
|
9016 |
|
|
/* Insns like "foo W,X,Y,Z".
|
9017 |
|
|
where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
|
9018 |
|
|
|
9019 |
|
|
static void
|
9020 |
|
|
do_mav_quad (void)
|
9021 |
|
|
{
|
9022 |
|
|
inst.instruction |= inst.operands[0].reg << 5;
|
9023 |
|
|
inst.instruction |= inst.operands[1].reg << 12;
|
9024 |
|
|
inst.instruction |= inst.operands[2].reg << 16;
|
9025 |
|
|
inst.instruction |= inst.operands[3].reg;
|
9026 |
|
|
}
|
9027 |
|
|
|
9028 |
|
|
/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
|
9029 |
|
|
static void
|
9030 |
|
|
do_mav_dspsc (void)
|
9031 |
|
|
{
|
9032 |
|
|
inst.instruction |= inst.operands[1].reg << 12;
|
9033 |
|
|
}
|
9034 |
|
|
|
9035 |
|
|
/* Maverick shift immediate instructions.
|
9036 |
|
|
cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
|
9037 |
|
|
cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
|
9038 |
|
|
|
9039 |
|
|
static void
|
9040 |
|
|
do_mav_shift (void)
|
9041 |
|
|
{
|
9042 |
|
|
int imm = inst.operands[2].imm;
|
9043 |
|
|
|
9044 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
9045 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
9046 |
|
|
|
9047 |
|
|
/* Bits 0-3 of the insn should have bits 0-3 of the immediate.
|
9048 |
|
|
Bits 5-7 of the insn should have bits 4-6 of the immediate.
|
9049 |
|
|
Bit 4 should be 0. */
|
9050 |
|
|
imm = (imm & 0xf) | ((imm & 0x70) << 1);
|
9051 |
|
|
|
9052 |
|
|
inst.instruction |= imm;
|
9053 |
|
|
}
|
9054 |
|
|
|
9055 |
|
|
/* XScale instructions. Also sorted arithmetic before move. */
|
9056 |
|
|
|
9057 |
|
|
/* Xscale multiply-accumulate (argument parse)
|
9058 |
|
|
MIAcc acc0,Rm,Rs
|
9059 |
|
|
MIAPHcc acc0,Rm,Rs
|
9060 |
|
|
MIAxycc acc0,Rm,Rs. */
|
9061 |
|
|
|
9062 |
|
|
static void
|
9063 |
|
|
do_xsc_mia (void)
|
9064 |
|
|
{
|
9065 |
|
|
inst.instruction |= inst.operands[1].reg;
|
9066 |
|
|
inst.instruction |= inst.operands[2].reg << 12;
|
9067 |
|
|
}
|
9068 |
|
|
|
9069 |
|
|
/* Xscale move-accumulator-register (argument parse)
|
9070 |
|
|
|
9071 |
|
|
MARcc acc0,RdLo,RdHi. */
|
9072 |
|
|
|
9073 |
|
|
static void
|
9074 |
|
|
do_xsc_mar (void)
|
9075 |
|
|
{
|
9076 |
|
|
inst.instruction |= inst.operands[1].reg << 12;
|
9077 |
|
|
inst.instruction |= inst.operands[2].reg << 16;
|
9078 |
|
|
}
|
9079 |
|
|
|
9080 |
|
|
/* Xscale move-register-accumulator (argument parse)
|
9081 |
|
|
|
9082 |
|
|
MRAcc RdLo,RdHi,acc0. */
|
9083 |
|
|
|
9084 |
|
|
static void
|
9085 |
|
|
do_xsc_mra (void)
|
9086 |
|
|
{
|
9087 |
|
|
constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
|
9088 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
9089 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
9090 |
|
|
}
|
9091 |
|
|
|
9092 |
|
|
/* Encoding functions relevant only to Thumb. */
|
9093 |
|
|
|
9094 |
|
|
/* inst.operands[i] is a shifted-register operand; encode
|
9095 |
|
|
it into inst.instruction in the format used by Thumb32. */
|
9096 |
|
|
|
9097 |
|
|
static void
|
9098 |
|
|
encode_thumb32_shifted_operand (int i)
|
9099 |
|
|
{
|
9100 |
|
|
unsigned int value = inst.reloc.exp.X_add_number;
|
9101 |
|
|
unsigned int shift = inst.operands[i].shift_kind;
|
9102 |
|
|
|
9103 |
|
|
constraint (inst.operands[i].immisreg,
|
9104 |
|
|
_("shift by register not allowed in thumb mode"));
|
9105 |
|
|
inst.instruction |= inst.operands[i].reg;
|
9106 |
|
|
if (shift == SHIFT_RRX)
|
9107 |
|
|
inst.instruction |= SHIFT_ROR << 4;
|
9108 |
|
|
else
|
9109 |
|
|
{
|
9110 |
|
|
constraint (inst.reloc.exp.X_op != O_constant,
|
9111 |
|
|
_("expression too complex"));
|
9112 |
|
|
|
9113 |
|
|
constraint (value > 32
|
9114 |
|
|
|| (value == 32 && (shift == SHIFT_LSL
|
9115 |
|
|
|| shift == SHIFT_ROR)),
|
9116 |
|
|
_("shift expression is too large"));
|
9117 |
|
|
|
9118 |
|
|
if (value == 0)
|
9119 |
|
|
shift = SHIFT_LSL;
|
9120 |
|
|
else if (value == 32)
|
9121 |
|
|
value = 0;
|
9122 |
|
|
|
9123 |
|
|
inst.instruction |= shift << 4;
|
9124 |
|
|
inst.instruction |= (value & 0x1c) << 10;
|
9125 |
|
|
inst.instruction |= (value & 0x03) << 6;
|
9126 |
|
|
}
|
9127 |
|
|
}
|
9128 |
|
|
|
9129 |
|
|
|
9130 |
|
|
/* inst.operands[i] was set up by parse_address. Encode it into a
|
9131 |
|
|
Thumb32 format load or store instruction. Reject forms that cannot
|
9132 |
|
|
be used with such instructions. If is_t is true, reject forms that
|
9133 |
|
|
cannot be used with a T instruction; if is_d is true, reject forms
|
9134 |
|
|
that cannot be used with a D instruction. If it is a store insn,
|
9135 |
|
|
reject PC in Rn. */
|
9136 |
|
|
|
9137 |
|
|
static void
|
9138 |
|
|
encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
|
9139 |
|
|
{
|
9140 |
|
|
const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
|
9141 |
|
|
|
9142 |
|
|
constraint (!inst.operands[i].isreg,
|
9143 |
|
|
_("Instruction does not support =N addresses"));
|
9144 |
|
|
|
9145 |
|
|
inst.instruction |= inst.operands[i].reg << 16;
|
9146 |
|
|
if (inst.operands[i].immisreg)
|
9147 |
|
|
{
|
9148 |
|
|
constraint (is_pc, BAD_PC_ADDRESSING);
|
9149 |
|
|
constraint (is_t || is_d, _("cannot use register index with this instruction"));
|
9150 |
|
|
constraint (inst.operands[i].negative,
|
9151 |
|
|
_("Thumb does not support negative register indexing"));
|
9152 |
|
|
constraint (inst.operands[i].postind,
|
9153 |
|
|
_("Thumb does not support register post-indexing"));
|
9154 |
|
|
constraint (inst.operands[i].writeback,
|
9155 |
|
|
_("Thumb does not support register indexing with writeback"));
|
9156 |
|
|
constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
|
9157 |
|
|
_("Thumb supports only LSL in shifted register indexing"));
|
9158 |
|
|
|
9159 |
|
|
inst.instruction |= inst.operands[i].imm;
|
9160 |
|
|
if (inst.operands[i].shifted)
|
9161 |
|
|
{
|
9162 |
|
|
constraint (inst.reloc.exp.X_op != O_constant,
|
9163 |
|
|
_("expression too complex"));
|
9164 |
|
|
constraint (inst.reloc.exp.X_add_number < 0
|
9165 |
|
|
|| inst.reloc.exp.X_add_number > 3,
|
9166 |
|
|
_("shift out of range"));
|
9167 |
|
|
inst.instruction |= inst.reloc.exp.X_add_number << 4;
|
9168 |
|
|
}
|
9169 |
|
|
inst.reloc.type = BFD_RELOC_UNUSED;
|
9170 |
|
|
}
|
9171 |
|
|
else if (inst.operands[i].preind)
|
9172 |
|
|
{
|
9173 |
|
|
constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
|
9174 |
|
|
constraint (is_t && inst.operands[i].writeback,
|
9175 |
|
|
_("cannot use writeback with this instruction"));
|
9176 |
|
|
constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
|
9177 |
|
|
&& !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
|
9178 |
|
|
|
9179 |
|
|
if (is_d)
|
9180 |
|
|
{
|
9181 |
|
|
inst.instruction |= 0x01000000;
|
9182 |
|
|
if (inst.operands[i].writeback)
|
9183 |
|
|
inst.instruction |= 0x00200000;
|
9184 |
|
|
}
|
9185 |
|
|
else
|
9186 |
|
|
{
|
9187 |
|
|
inst.instruction |= 0x00000c00;
|
9188 |
|
|
if (inst.operands[i].writeback)
|
9189 |
|
|
inst.instruction |= 0x00000100;
|
9190 |
|
|
}
|
9191 |
|
|
inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
|
9192 |
|
|
}
|
9193 |
|
|
else if (inst.operands[i].postind)
|
9194 |
|
|
{
|
9195 |
|
|
gas_assert (inst.operands[i].writeback);
|
9196 |
|
|
constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
|
9197 |
|
|
constraint (is_t, _("cannot use post-indexing with this instruction"));
|
9198 |
|
|
|
9199 |
|
|
if (is_d)
|
9200 |
|
|
inst.instruction |= 0x00200000;
|
9201 |
|
|
else
|
9202 |
|
|
inst.instruction |= 0x00000900;
|
9203 |
|
|
inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
|
9204 |
|
|
}
|
9205 |
|
|
else /* unindexed - only for coprocessor */
|
9206 |
|
|
inst.error = _("instruction does not accept unindexed addressing");
|
9207 |
|
|
}
|
9208 |
|
|
|
9209 |
|
|
/* Table of Thumb instructions which exist in both 16- and 32-bit
|
9210 |
|
|
encodings (the latter only in post-V6T2 cores). The index is the
|
9211 |
|
|
value used in the insns table below. When there is more than one
|
9212 |
|
|
possible 16-bit encoding for the instruction, this table always
|
9213 |
|
|
holds variant (1).
|
9214 |
|
|
Also contains several pseudo-instructions used during relaxation. */
|
9215 |
|
|
#define T16_32_TAB \
|
9216 |
|
|
X(_adc, 4140, eb400000), \
|
9217 |
|
|
X(_adcs, 4140, eb500000), \
|
9218 |
|
|
X(_add, 1c00, eb000000), \
|
9219 |
|
|
X(_adds, 1c00, eb100000), \
|
9220 |
|
|
X(_addi, 0000, f1000000), \
|
9221 |
|
|
X(_addis, 0000, f1100000), \
|
9222 |
|
|
X(_add_pc,000f, f20f0000), \
|
9223 |
|
|
X(_add_sp,000d, f10d0000), \
|
9224 |
|
|
X(_adr, 000f, f20f0000), \
|
9225 |
|
|
X(_and, 4000, ea000000), \
|
9226 |
|
|
X(_ands, 4000, ea100000), \
|
9227 |
|
|
X(_asr, 1000, fa40f000), \
|
9228 |
|
|
X(_asrs, 1000, fa50f000), \
|
9229 |
|
|
X(_b, e000, f000b000), \
|
9230 |
|
|
X(_bcond, d000, f0008000), \
|
9231 |
|
|
X(_bic, 4380, ea200000), \
|
9232 |
|
|
X(_bics, 4380, ea300000), \
|
9233 |
|
|
X(_cmn, 42c0, eb100f00), \
|
9234 |
|
|
X(_cmp, 2800, ebb00f00), \
|
9235 |
|
|
X(_cpsie, b660, f3af8400), \
|
9236 |
|
|
X(_cpsid, b670, f3af8600), \
|
9237 |
|
|
X(_cpy, 4600, ea4f0000), \
|
9238 |
|
|
X(_dec_sp,80dd, f1ad0d00), \
|
9239 |
|
|
X(_eor, 4040, ea800000), \
|
9240 |
|
|
X(_eors, 4040, ea900000), \
|
9241 |
|
|
X(_inc_sp,00dd, f10d0d00), \
|
9242 |
|
|
X(_ldmia, c800, e8900000), \
|
9243 |
|
|
X(_ldr, 6800, f8500000), \
|
9244 |
|
|
X(_ldrb, 7800, f8100000), \
|
9245 |
|
|
X(_ldrh, 8800, f8300000), \
|
9246 |
|
|
X(_ldrsb, 5600, f9100000), \
|
9247 |
|
|
X(_ldrsh, 5e00, f9300000), \
|
9248 |
|
|
X(_ldr_pc,4800, f85f0000), \
|
9249 |
|
|
X(_ldr_pc2,4800, f85f0000), \
|
9250 |
|
|
X(_ldr_sp,9800, f85d0000), \
|
9251 |
|
|
X(_lsl, 0000, fa00f000), \
|
9252 |
|
|
X(_lsls, 0000, fa10f000), \
|
9253 |
|
|
X(_lsr, 0800, fa20f000), \
|
9254 |
|
|
X(_lsrs, 0800, fa30f000), \
|
9255 |
|
|
X(_mov, 2000, ea4f0000), \
|
9256 |
|
|
X(_movs, 2000, ea5f0000), \
|
9257 |
|
|
X(_mul, 4340, fb00f000), \
|
9258 |
|
|
X(_muls, 4340, ffffffff), /* no 32b muls */ \
|
9259 |
|
|
X(_mvn, 43c0, ea6f0000), \
|
9260 |
|
|
X(_mvns, 43c0, ea7f0000), \
|
9261 |
|
|
X(_neg, 4240, f1c00000), /* rsb #0 */ \
|
9262 |
|
|
X(_negs, 4240, f1d00000), /* rsbs #0 */ \
|
9263 |
|
|
X(_orr, 4300, ea400000), \
|
9264 |
|
|
X(_orrs, 4300, ea500000), \
|
9265 |
|
|
X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
|
9266 |
|
|
X(_push, b400, e92d0000), /* stmdb sp!,... */ \
|
9267 |
|
|
X(_rev, ba00, fa90f080), \
|
9268 |
|
|
X(_rev16, ba40, fa90f090), \
|
9269 |
|
|
X(_revsh, bac0, fa90f0b0), \
|
9270 |
|
|
X(_ror, 41c0, fa60f000), \
|
9271 |
|
|
X(_rors, 41c0, fa70f000), \
|
9272 |
|
|
X(_sbc, 4180, eb600000), \
|
9273 |
|
|
X(_sbcs, 4180, eb700000), \
|
9274 |
|
|
X(_stmia, c000, e8800000), \
|
9275 |
|
|
X(_str, 6000, f8400000), \
|
9276 |
|
|
X(_strb, 7000, f8000000), \
|
9277 |
|
|
X(_strh, 8000, f8200000), \
|
9278 |
|
|
X(_str_sp,9000, f84d0000), \
|
9279 |
|
|
X(_sub, 1e00, eba00000), \
|
9280 |
|
|
X(_subs, 1e00, ebb00000), \
|
9281 |
|
|
X(_subi, 8000, f1a00000), \
|
9282 |
|
|
X(_subis, 8000, f1b00000), \
|
9283 |
|
|
X(_sxtb, b240, fa4ff080), \
|
9284 |
|
|
X(_sxth, b200, fa0ff080), \
|
9285 |
|
|
X(_tst, 4200, ea100f00), \
|
9286 |
|
|
X(_uxtb, b2c0, fa5ff080), \
|
9287 |
|
|
X(_uxth, b280, fa1ff080), \
|
9288 |
|
|
X(_nop, bf00, f3af8000), \
|
9289 |
|
|
X(_yield, bf10, f3af8001), \
|
9290 |
|
|
X(_wfe, bf20, f3af8002), \
|
9291 |
|
|
X(_wfi, bf30, f3af8003), \
|
9292 |
|
|
X(_sev, bf40, f3af8004),
|
9293 |
|
|
|
9294 |
|
|
/* To catch errors in encoding functions, the codes are all offset by
|
9295 |
|
|
0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
|
9296 |
|
|
as 16-bit instructions. */
|
9297 |
|
|
#define X(a,b,c) T_MNEM##a
|
9298 |
|
|
enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
|
9299 |
|
|
#undef X
|
9300 |
|
|
|
9301 |
|
|
#define X(a,b,c) 0x##b
|
9302 |
|
|
static const unsigned short thumb_op16[] = { T16_32_TAB };
|
9303 |
|
|
#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
|
9304 |
|
|
#undef X
|
9305 |
|
|
|
9306 |
|
|
#define X(a,b,c) 0x##c
|
9307 |
|
|
static const unsigned int thumb_op32[] = { T16_32_TAB };
|
9308 |
|
|
#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
|
9309 |
|
|
#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
|
9310 |
|
|
#undef X
|
9311 |
|
|
#undef T16_32_TAB
|
9312 |
|
|
|
9313 |
|
|
/* Thumb instruction encoders, in alphabetical order. */
|
9314 |
|
|
|
9315 |
|
|
/* ADDW or SUBW. */
|
9316 |
|
|
|
9317 |
|
|
static void
|
9318 |
|
|
do_t_add_sub_w (void)
|
9319 |
|
|
{
|
9320 |
|
|
int Rd, Rn;
|
9321 |
|
|
|
9322 |
|
|
Rd = inst.operands[0].reg;
|
9323 |
|
|
Rn = inst.operands[1].reg;
|
9324 |
|
|
|
9325 |
|
|
/* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
|
9326 |
|
|
is the SP-{plus,minus}-immediate form of the instruction. */
|
9327 |
|
|
if (Rn == REG_SP)
|
9328 |
|
|
constraint (Rd == REG_PC, BAD_PC);
|
9329 |
|
|
else
|
9330 |
|
|
reject_bad_reg (Rd);
|
9331 |
|
|
|
9332 |
|
|
inst.instruction |= (Rn << 16) | (Rd << 8);
|
9333 |
|
|
inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
|
9334 |
|
|
}
|
9335 |
|
|
|
9336 |
|
|
/* Parse an add or subtract instruction. We get here with inst.instruction
|
9337 |
|
|
equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
|
9338 |
|
|
|
9339 |
|
|
static void
|
9340 |
|
|
do_t_add_sub (void)
|
9341 |
|
|
{
|
9342 |
|
|
int Rd, Rs, Rn;
|
9343 |
|
|
|
9344 |
|
|
Rd = inst.operands[0].reg;
|
9345 |
|
|
Rs = (inst.operands[1].present
|
9346 |
|
|
? inst.operands[1].reg /* Rd, Rs, foo */
|
9347 |
|
|
: inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
|
9348 |
|
|
|
9349 |
|
|
if (Rd == REG_PC)
|
9350 |
|
|
set_it_insn_type_last ();
|
9351 |
|
|
|
9352 |
|
|
if (unified_syntax)
|
9353 |
|
|
{
|
9354 |
|
|
bfd_boolean flags;
|
9355 |
|
|
bfd_boolean narrow;
|
9356 |
|
|
int opcode;
|
9357 |
|
|
|
9358 |
|
|
flags = (inst.instruction == T_MNEM_adds
|
9359 |
|
|
|| inst.instruction == T_MNEM_subs);
|
9360 |
|
|
if (flags)
|
9361 |
|
|
narrow = !in_it_block ();
|
9362 |
|
|
else
|
9363 |
|
|
narrow = in_it_block ();
|
9364 |
|
|
if (!inst.operands[2].isreg)
|
9365 |
|
|
{
|
9366 |
|
|
int add;
|
9367 |
|
|
|
9368 |
|
|
constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
|
9369 |
|
|
|
9370 |
|
|
add = (inst.instruction == T_MNEM_add
|
9371 |
|
|
|| inst.instruction == T_MNEM_adds);
|
9372 |
|
|
opcode = 0;
|
9373 |
|
|
if (inst.size_req != 4)
|
9374 |
|
|
{
|
9375 |
|
|
/* Attempt to use a narrow opcode, with relaxation if
|
9376 |
|
|
appropriate. */
|
9377 |
|
|
if (Rd == REG_SP && Rs == REG_SP && !flags)
|
9378 |
|
|
opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
|
9379 |
|
|
else if (Rd <= 7 && Rs == REG_SP && add && !flags)
|
9380 |
|
|
opcode = T_MNEM_add_sp;
|
9381 |
|
|
else if (Rd <= 7 && Rs == REG_PC && add && !flags)
|
9382 |
|
|
opcode = T_MNEM_add_pc;
|
9383 |
|
|
else if (Rd <= 7 && Rs <= 7 && narrow)
|
9384 |
|
|
{
|
9385 |
|
|
if (flags)
|
9386 |
|
|
opcode = add ? T_MNEM_addis : T_MNEM_subis;
|
9387 |
|
|
else
|
9388 |
|
|
opcode = add ? T_MNEM_addi : T_MNEM_subi;
|
9389 |
|
|
}
|
9390 |
|
|
if (opcode)
|
9391 |
|
|
{
|
9392 |
|
|
inst.instruction = THUMB_OP16(opcode);
|
9393 |
|
|
inst.instruction |= (Rd << 4) | Rs;
|
9394 |
|
|
inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
|
9395 |
|
|
if (inst.size_req != 2)
|
9396 |
|
|
inst.relax = opcode;
|
9397 |
|
|
}
|
9398 |
|
|
else
|
9399 |
|
|
constraint (inst.size_req == 2, BAD_HIREG);
|
9400 |
|
|
}
|
9401 |
|
|
if (inst.size_req == 4
|
9402 |
|
|
|| (inst.size_req != 2 && !opcode))
|
9403 |
|
|
{
|
9404 |
|
|
if (Rd == REG_PC)
|
9405 |
|
|
{
|
9406 |
|
|
constraint (add, BAD_PC);
|
9407 |
|
|
constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
|
9408 |
|
|
_("only SUBS PC, LR, #const allowed"));
|
9409 |
|
|
constraint (inst.reloc.exp.X_op != O_constant,
|
9410 |
|
|
_("expression too complex"));
|
9411 |
|
|
constraint (inst.reloc.exp.X_add_number < 0
|
9412 |
|
|
|| inst.reloc.exp.X_add_number > 0xff,
|
9413 |
|
|
_("immediate value out of range"));
|
9414 |
|
|
inst.instruction = T2_SUBS_PC_LR
|
9415 |
|
|
| inst.reloc.exp.X_add_number;
|
9416 |
|
|
inst.reloc.type = BFD_RELOC_UNUSED;
|
9417 |
|
|
return;
|
9418 |
|
|
}
|
9419 |
|
|
else if (Rs == REG_PC)
|
9420 |
|
|
{
|
9421 |
|
|
/* Always use addw/subw. */
|
9422 |
|
|
inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
|
9423 |
|
|
inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
|
9424 |
|
|
}
|
9425 |
|
|
else
|
9426 |
|
|
{
|
9427 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
9428 |
|
|
inst.instruction = (inst.instruction & 0xe1ffffff)
|
9429 |
|
|
| 0x10000000;
|
9430 |
|
|
if (flags)
|
9431 |
|
|
inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
|
9432 |
|
|
else
|
9433 |
|
|
inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
|
9434 |
|
|
}
|
9435 |
|
|
inst.instruction |= Rd << 8;
|
9436 |
|
|
inst.instruction |= Rs << 16;
|
9437 |
|
|
}
|
9438 |
|
|
}
|
9439 |
|
|
else
|
9440 |
|
|
{
|
9441 |
|
|
Rn = inst.operands[2].reg;
|
9442 |
|
|
/* See if we can do this with a 16-bit instruction. */
|
9443 |
|
|
if (!inst.operands[2].shifted && inst.size_req != 4)
|
9444 |
|
|
{
|
9445 |
|
|
if (Rd > 7 || Rs > 7 || Rn > 7)
|
9446 |
|
|
narrow = FALSE;
|
9447 |
|
|
|
9448 |
|
|
if (narrow)
|
9449 |
|
|
{
|
9450 |
|
|
inst.instruction = ((inst.instruction == T_MNEM_adds
|
9451 |
|
|
|| inst.instruction == T_MNEM_add)
|
9452 |
|
|
? T_OPCODE_ADD_R3
|
9453 |
|
|
: T_OPCODE_SUB_R3);
|
9454 |
|
|
inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
|
9455 |
|
|
return;
|
9456 |
|
|
}
|
9457 |
|
|
|
9458 |
|
|
if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
|
9459 |
|
|
{
|
9460 |
|
|
/* Thumb-1 cores (except v6-M) require at least one high
|
9461 |
|
|
register in a narrow non flag setting add. */
|
9462 |
|
|
if (Rd > 7 || Rn > 7
|
9463 |
|
|
|| ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
|
9464 |
|
|
|| ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
|
9465 |
|
|
{
|
9466 |
|
|
if (Rd == Rn)
|
9467 |
|
|
{
|
9468 |
|
|
Rn = Rs;
|
9469 |
|
|
Rs = Rd;
|
9470 |
|
|
}
|
9471 |
|
|
inst.instruction = T_OPCODE_ADD_HI;
|
9472 |
|
|
inst.instruction |= (Rd & 8) << 4;
|
9473 |
|
|
inst.instruction |= (Rd & 7);
|
9474 |
|
|
inst.instruction |= Rn << 3;
|
9475 |
|
|
return;
|
9476 |
|
|
}
|
9477 |
|
|
}
|
9478 |
|
|
}
|
9479 |
|
|
|
9480 |
|
|
constraint (Rd == REG_PC, BAD_PC);
|
9481 |
|
|
constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
|
9482 |
|
|
constraint (Rs == REG_PC, BAD_PC);
|
9483 |
|
|
reject_bad_reg (Rn);
|
9484 |
|
|
|
9485 |
|
|
/* If we get here, it can't be done in 16 bits. */
|
9486 |
|
|
constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
|
9487 |
|
|
_("shift must be constant"));
|
9488 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
9489 |
|
|
inst.instruction |= Rd << 8;
|
9490 |
|
|
inst.instruction |= Rs << 16;
|
9491 |
|
|
encode_thumb32_shifted_operand (2);
|
9492 |
|
|
}
|
9493 |
|
|
}
|
9494 |
|
|
else
|
9495 |
|
|
{
|
9496 |
|
|
constraint (inst.instruction == T_MNEM_adds
|
9497 |
|
|
|| inst.instruction == T_MNEM_subs,
|
9498 |
|
|
BAD_THUMB32);
|
9499 |
|
|
|
9500 |
|
|
if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
|
9501 |
|
|
{
|
9502 |
|
|
constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
|
9503 |
|
|
|| (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
|
9504 |
|
|
BAD_HIREG);
|
9505 |
|
|
|
9506 |
|
|
inst.instruction = (inst.instruction == T_MNEM_add
|
9507 |
|
|
? 0x0000 : 0x8000);
|
9508 |
|
|
inst.instruction |= (Rd << 4) | Rs;
|
9509 |
|
|
inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
|
9510 |
|
|
return;
|
9511 |
|
|
}
|
9512 |
|
|
|
9513 |
|
|
Rn = inst.operands[2].reg;
|
9514 |
|
|
constraint (inst.operands[2].shifted, _("unshifted register required"));
|
9515 |
|
|
|
9516 |
|
|
/* We now have Rd, Rs, and Rn set to registers. */
|
9517 |
|
|
if (Rd > 7 || Rs > 7 || Rn > 7)
|
9518 |
|
|
{
|
9519 |
|
|
/* Can't do this for SUB. */
|
9520 |
|
|
constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
|
9521 |
|
|
inst.instruction = T_OPCODE_ADD_HI;
|
9522 |
|
|
inst.instruction |= (Rd & 8) << 4;
|
9523 |
|
|
inst.instruction |= (Rd & 7);
|
9524 |
|
|
if (Rs == Rd)
|
9525 |
|
|
inst.instruction |= Rn << 3;
|
9526 |
|
|
else if (Rn == Rd)
|
9527 |
|
|
inst.instruction |= Rs << 3;
|
9528 |
|
|
else
|
9529 |
|
|
constraint (1, _("dest must overlap one source register"));
|
9530 |
|
|
}
|
9531 |
|
|
else
|
9532 |
|
|
{
|
9533 |
|
|
inst.instruction = (inst.instruction == T_MNEM_add
|
9534 |
|
|
? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
|
9535 |
|
|
inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
|
9536 |
|
|
}
|
9537 |
|
|
}
|
9538 |
|
|
}
|
9539 |
|
|
|
9540 |
|
|
static void
|
9541 |
|
|
do_t_adr (void)
|
9542 |
|
|
{
|
9543 |
|
|
unsigned Rd;
|
9544 |
|
|
|
9545 |
|
|
Rd = inst.operands[0].reg;
|
9546 |
|
|
reject_bad_reg (Rd);
|
9547 |
|
|
|
9548 |
|
|
if (unified_syntax && inst.size_req == 0 && Rd <= 7)
|
9549 |
|
|
{
|
9550 |
|
|
/* Defer to section relaxation. */
|
9551 |
|
|
inst.relax = inst.instruction;
|
9552 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
9553 |
|
|
inst.instruction |= Rd << 4;
|
9554 |
|
|
}
|
9555 |
|
|
else if (unified_syntax && inst.size_req != 2)
|
9556 |
|
|
{
|
9557 |
|
|
/* Generate a 32-bit opcode. */
|
9558 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
9559 |
|
|
inst.instruction |= Rd << 8;
|
9560 |
|
|
inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
|
9561 |
|
|
inst.reloc.pc_rel = 1;
|
9562 |
|
|
}
|
9563 |
|
|
else
|
9564 |
|
|
{
|
9565 |
|
|
/* Generate a 16-bit opcode. */
|
9566 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
9567 |
|
|
inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
|
9568 |
|
|
inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
|
9569 |
|
|
inst.reloc.pc_rel = 1;
|
9570 |
|
|
|
9571 |
|
|
inst.instruction |= Rd << 4;
|
9572 |
|
|
}
|
9573 |
|
|
}
|
9574 |
|
|
|
9575 |
|
|
/* Arithmetic instructions for which there is just one 16-bit
|
9576 |
|
|
instruction encoding, and it allows only two low registers.
|
9577 |
|
|
For maximal compatibility with ARM syntax, we allow three register
|
9578 |
|
|
operands even when Thumb-32 instructions are not available, as long
|
9579 |
|
|
as the first two are identical. For instance, both "sbc r0,r1" and
|
9580 |
|
|
"sbc r0,r0,r1" are allowed. */
|
9581 |
|
|
static void
|
9582 |
|
|
do_t_arit3 (void)
|
9583 |
|
|
{
|
9584 |
|
|
int Rd, Rs, Rn;
|
9585 |
|
|
|
9586 |
|
|
Rd = inst.operands[0].reg;
|
9587 |
|
|
Rs = (inst.operands[1].present
|
9588 |
|
|
? inst.operands[1].reg /* Rd, Rs, foo */
|
9589 |
|
|
: inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
|
9590 |
|
|
Rn = inst.operands[2].reg;
|
9591 |
|
|
|
9592 |
|
|
reject_bad_reg (Rd);
|
9593 |
|
|
reject_bad_reg (Rs);
|
9594 |
|
|
if (inst.operands[2].isreg)
|
9595 |
|
|
reject_bad_reg (Rn);
|
9596 |
|
|
|
9597 |
|
|
if (unified_syntax)
|
9598 |
|
|
{
|
9599 |
|
|
if (!inst.operands[2].isreg)
|
9600 |
|
|
{
|
9601 |
|
|
/* For an immediate, we always generate a 32-bit opcode;
|
9602 |
|
|
section relaxation will shrink it later if possible. */
|
9603 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
9604 |
|
|
inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
|
9605 |
|
|
inst.instruction |= Rd << 8;
|
9606 |
|
|
inst.instruction |= Rs << 16;
|
9607 |
|
|
inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
|
9608 |
|
|
}
|
9609 |
|
|
else
|
9610 |
|
|
{
|
9611 |
|
|
bfd_boolean narrow;
|
9612 |
|
|
|
9613 |
|
|
/* See if we can do this with a 16-bit instruction. */
|
9614 |
|
|
if (THUMB_SETS_FLAGS (inst.instruction))
|
9615 |
|
|
narrow = !in_it_block ();
|
9616 |
|
|
else
|
9617 |
|
|
narrow = in_it_block ();
|
9618 |
|
|
|
9619 |
|
|
if (Rd > 7 || Rn > 7 || Rs > 7)
|
9620 |
|
|
narrow = FALSE;
|
9621 |
|
|
if (inst.operands[2].shifted)
|
9622 |
|
|
narrow = FALSE;
|
9623 |
|
|
if (inst.size_req == 4)
|
9624 |
|
|
narrow = FALSE;
|
9625 |
|
|
|
9626 |
|
|
if (narrow
|
9627 |
|
|
&& Rd == Rs)
|
9628 |
|
|
{
|
9629 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
9630 |
|
|
inst.instruction |= Rd;
|
9631 |
|
|
inst.instruction |= Rn << 3;
|
9632 |
|
|
return;
|
9633 |
|
|
}
|
9634 |
|
|
|
9635 |
|
|
/* If we get here, it can't be done in 16 bits. */
|
9636 |
|
|
constraint (inst.operands[2].shifted
|
9637 |
|
|
&& inst.operands[2].immisreg,
|
9638 |
|
|
_("shift must be constant"));
|
9639 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
9640 |
|
|
inst.instruction |= Rd << 8;
|
9641 |
|
|
inst.instruction |= Rs << 16;
|
9642 |
|
|
encode_thumb32_shifted_operand (2);
|
9643 |
|
|
}
|
9644 |
|
|
}
|
9645 |
|
|
else
|
9646 |
|
|
{
|
9647 |
|
|
/* On its face this is a lie - the instruction does set the
|
9648 |
|
|
flags. However, the only supported mnemonic in this mode
|
9649 |
|
|
says it doesn't. */
|
9650 |
|
|
constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
|
9651 |
|
|
|
9652 |
|
|
constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
|
9653 |
|
|
_("unshifted register required"));
|
9654 |
|
|
constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
|
9655 |
|
|
constraint (Rd != Rs,
|
9656 |
|
|
_("dest and source1 must be the same register"));
|
9657 |
|
|
|
9658 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
9659 |
|
|
inst.instruction |= Rd;
|
9660 |
|
|
inst.instruction |= Rn << 3;
|
9661 |
|
|
}
|
9662 |
|
|
}
|
9663 |
|
|
|
9664 |
|
|
/* Similarly, but for instructions where the arithmetic operation is
|
9665 |
|
|
commutative, so we can allow either of them to be different from
|
9666 |
|
|
the destination operand in a 16-bit instruction. For instance, all
|
9667 |
|
|
three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
|
9668 |
|
|
accepted. */
|
9669 |
|
|
static void
|
9670 |
|
|
do_t_arit3c (void)
|
9671 |
|
|
{
|
9672 |
|
|
int Rd, Rs, Rn;
|
9673 |
|
|
|
9674 |
|
|
Rd = inst.operands[0].reg;
|
9675 |
|
|
Rs = (inst.operands[1].present
|
9676 |
|
|
? inst.operands[1].reg /* Rd, Rs, foo */
|
9677 |
|
|
: inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
|
9678 |
|
|
Rn = inst.operands[2].reg;
|
9679 |
|
|
|
9680 |
|
|
reject_bad_reg (Rd);
|
9681 |
|
|
reject_bad_reg (Rs);
|
9682 |
|
|
if (inst.operands[2].isreg)
|
9683 |
|
|
reject_bad_reg (Rn);
|
9684 |
|
|
|
9685 |
|
|
if (unified_syntax)
|
9686 |
|
|
{
|
9687 |
|
|
if (!inst.operands[2].isreg)
|
9688 |
|
|
{
|
9689 |
|
|
/* For an immediate, we always generate a 32-bit opcode;
|
9690 |
|
|
section relaxation will shrink it later if possible. */
|
9691 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
9692 |
|
|
inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
|
9693 |
|
|
inst.instruction |= Rd << 8;
|
9694 |
|
|
inst.instruction |= Rs << 16;
|
9695 |
|
|
inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
|
9696 |
|
|
}
|
9697 |
|
|
else
|
9698 |
|
|
{
|
9699 |
|
|
bfd_boolean narrow;
|
9700 |
|
|
|
9701 |
|
|
/* See if we can do this with a 16-bit instruction. */
|
9702 |
|
|
if (THUMB_SETS_FLAGS (inst.instruction))
|
9703 |
|
|
narrow = !in_it_block ();
|
9704 |
|
|
else
|
9705 |
|
|
narrow = in_it_block ();
|
9706 |
|
|
|
9707 |
|
|
if (Rd > 7 || Rn > 7 || Rs > 7)
|
9708 |
|
|
narrow = FALSE;
|
9709 |
|
|
if (inst.operands[2].shifted)
|
9710 |
|
|
narrow = FALSE;
|
9711 |
|
|
if (inst.size_req == 4)
|
9712 |
|
|
narrow = FALSE;
|
9713 |
|
|
|
9714 |
|
|
if (narrow)
|
9715 |
|
|
{
|
9716 |
|
|
if (Rd == Rs)
|
9717 |
|
|
{
|
9718 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
9719 |
|
|
inst.instruction |= Rd;
|
9720 |
|
|
inst.instruction |= Rn << 3;
|
9721 |
|
|
return;
|
9722 |
|
|
}
|
9723 |
|
|
if (Rd == Rn)
|
9724 |
|
|
{
|
9725 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
9726 |
|
|
inst.instruction |= Rd;
|
9727 |
|
|
inst.instruction |= Rs << 3;
|
9728 |
|
|
return;
|
9729 |
|
|
}
|
9730 |
|
|
}
|
9731 |
|
|
|
9732 |
|
|
/* If we get here, it can't be done in 16 bits. */
|
9733 |
|
|
constraint (inst.operands[2].shifted
|
9734 |
|
|
&& inst.operands[2].immisreg,
|
9735 |
|
|
_("shift must be constant"));
|
9736 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
9737 |
|
|
inst.instruction |= Rd << 8;
|
9738 |
|
|
inst.instruction |= Rs << 16;
|
9739 |
|
|
encode_thumb32_shifted_operand (2);
|
9740 |
|
|
}
|
9741 |
|
|
}
|
9742 |
|
|
else
|
9743 |
|
|
{
|
9744 |
|
|
/* On its face this is a lie - the instruction does set the
|
9745 |
|
|
flags. However, the only supported mnemonic in this mode
|
9746 |
|
|
says it doesn't. */
|
9747 |
|
|
constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
|
9748 |
|
|
|
9749 |
|
|
constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
|
9750 |
|
|
_("unshifted register required"));
|
9751 |
|
|
constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
|
9752 |
|
|
|
9753 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
9754 |
|
|
inst.instruction |= Rd;
|
9755 |
|
|
|
9756 |
|
|
if (Rd == Rs)
|
9757 |
|
|
inst.instruction |= Rn << 3;
|
9758 |
|
|
else if (Rd == Rn)
|
9759 |
|
|
inst.instruction |= Rs << 3;
|
9760 |
|
|
else
|
9761 |
|
|
constraint (1, _("dest must overlap one source register"));
|
9762 |
|
|
}
|
9763 |
|
|
}
|
9764 |
|
|
|
9765 |
|
|
static void
|
9766 |
|
|
do_t_barrier (void)
|
9767 |
|
|
{
|
9768 |
|
|
if (inst.operands[0].present)
|
9769 |
|
|
{
|
9770 |
|
|
constraint ((inst.instruction & 0xf0) != 0x40
|
9771 |
|
|
&& inst.operands[0].imm > 0xf
|
9772 |
|
|
&& inst.operands[0].imm < 0x0,
|
9773 |
|
|
_("bad barrier type"));
|
9774 |
|
|
inst.instruction |= inst.operands[0].imm;
|
9775 |
|
|
}
|
9776 |
|
|
else
|
9777 |
|
|
inst.instruction |= 0xf;
|
9778 |
|
|
}
|
9779 |
|
|
|
9780 |
|
|
static void
|
9781 |
|
|
do_t_bfc (void)
|
9782 |
|
|
{
|
9783 |
|
|
unsigned Rd;
|
9784 |
|
|
unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
|
9785 |
|
|
constraint (msb > 32, _("bit-field extends past end of register"));
|
9786 |
|
|
/* The instruction encoding stores the LSB and MSB,
|
9787 |
|
|
not the LSB and width. */
|
9788 |
|
|
Rd = inst.operands[0].reg;
|
9789 |
|
|
reject_bad_reg (Rd);
|
9790 |
|
|
inst.instruction |= Rd << 8;
|
9791 |
|
|
inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
|
9792 |
|
|
inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
|
9793 |
|
|
inst.instruction |= msb - 1;
|
9794 |
|
|
}
|
9795 |
|
|
|
9796 |
|
|
static void
|
9797 |
|
|
do_t_bfi (void)
|
9798 |
|
|
{
|
9799 |
|
|
int Rd, Rn;
|
9800 |
|
|
unsigned int msb;
|
9801 |
|
|
|
9802 |
|
|
Rd = inst.operands[0].reg;
|
9803 |
|
|
reject_bad_reg (Rd);
|
9804 |
|
|
|
9805 |
|
|
/* #0 in second position is alternative syntax for bfc, which is
|
9806 |
|
|
the same instruction but with REG_PC in the Rm field. */
|
9807 |
|
|
if (!inst.operands[1].isreg)
|
9808 |
|
|
Rn = REG_PC;
|
9809 |
|
|
else
|
9810 |
|
|
{
|
9811 |
|
|
Rn = inst.operands[1].reg;
|
9812 |
|
|
reject_bad_reg (Rn);
|
9813 |
|
|
}
|
9814 |
|
|
|
9815 |
|
|
msb = inst.operands[2].imm + inst.operands[3].imm;
|
9816 |
|
|
constraint (msb > 32, _("bit-field extends past end of register"));
|
9817 |
|
|
/* The instruction encoding stores the LSB and MSB,
|
9818 |
|
|
not the LSB and width. */
|
9819 |
|
|
inst.instruction |= Rd << 8;
|
9820 |
|
|
inst.instruction |= Rn << 16;
|
9821 |
|
|
inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
|
9822 |
|
|
inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
|
9823 |
|
|
inst.instruction |= msb - 1;
|
9824 |
|
|
}
|
9825 |
|
|
|
9826 |
|
|
static void
|
9827 |
|
|
do_t_bfx (void)
|
9828 |
|
|
{
|
9829 |
|
|
unsigned Rd, Rn;
|
9830 |
|
|
|
9831 |
|
|
Rd = inst.operands[0].reg;
|
9832 |
|
|
Rn = inst.operands[1].reg;
|
9833 |
|
|
|
9834 |
|
|
reject_bad_reg (Rd);
|
9835 |
|
|
reject_bad_reg (Rn);
|
9836 |
|
|
|
9837 |
|
|
constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
|
9838 |
|
|
_("bit-field extends past end of register"));
|
9839 |
|
|
inst.instruction |= Rd << 8;
|
9840 |
|
|
inst.instruction |= Rn << 16;
|
9841 |
|
|
inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
|
9842 |
|
|
inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
|
9843 |
|
|
inst.instruction |= inst.operands[3].imm - 1;
|
9844 |
|
|
}
|
9845 |
|
|
|
9846 |
|
|
/* ARM V5 Thumb BLX (argument parse)
|
9847 |
|
|
BLX <target_addr> which is BLX(1)
|
9848 |
|
|
BLX <Rm> which is BLX(2)
|
9849 |
|
|
Unfortunately, there are two different opcodes for this mnemonic.
|
9850 |
|
|
So, the insns[].value is not used, and the code here zaps values
|
9851 |
|
|
into inst.instruction.
|
9852 |
|
|
|
9853 |
|
|
??? How to take advantage of the additional two bits of displacement
|
9854 |
|
|
available in Thumb32 mode? Need new relocation? */
|
9855 |
|
|
|
9856 |
|
|
static void
|
9857 |
|
|
do_t_blx (void)
|
9858 |
|
|
{
|
9859 |
|
|
set_it_insn_type_last ();
|
9860 |
|
|
|
9861 |
|
|
if (inst.operands[0].isreg)
|
9862 |
|
|
{
|
9863 |
|
|
constraint (inst.operands[0].reg == REG_PC, BAD_PC);
|
9864 |
|
|
/* We have a register, so this is BLX(2). */
|
9865 |
|
|
inst.instruction |= inst.operands[0].reg << 3;
|
9866 |
|
|
}
|
9867 |
|
|
else
|
9868 |
|
|
{
|
9869 |
|
|
/* No register. This must be BLX(1). */
|
9870 |
|
|
inst.instruction = 0xf000e800;
|
9871 |
|
|
encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
|
9872 |
|
|
}
|
9873 |
|
|
}
|
9874 |
|
|
|
9875 |
|
|
static void
|
9876 |
|
|
do_t_branch (void)
|
9877 |
|
|
{
|
9878 |
|
|
int opcode;
|
9879 |
|
|
int cond;
|
9880 |
|
|
int reloc;
|
9881 |
|
|
|
9882 |
|
|
cond = inst.cond;
|
9883 |
|
|
set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
|
9884 |
|
|
|
9885 |
|
|
if (in_it_block ())
|
9886 |
|
|
{
|
9887 |
|
|
/* Conditional branches inside IT blocks are encoded as unconditional
|
9888 |
|
|
branches. */
|
9889 |
|
|
cond = COND_ALWAYS;
|
9890 |
|
|
}
|
9891 |
|
|
else
|
9892 |
|
|
cond = inst.cond;
|
9893 |
|
|
|
9894 |
|
|
if (cond != COND_ALWAYS)
|
9895 |
|
|
opcode = T_MNEM_bcond;
|
9896 |
|
|
else
|
9897 |
|
|
opcode = inst.instruction;
|
9898 |
|
|
|
9899 |
|
|
if (unified_syntax
|
9900 |
|
|
&& (inst.size_req == 4
|
9901 |
|
|
|| (inst.size_req != 2
|
9902 |
|
|
&& (inst.operands[0].hasreloc
|
9903 |
|
|
|| inst.reloc.exp.X_op == O_constant))))
|
9904 |
|
|
{
|
9905 |
|
|
inst.instruction = THUMB_OP32(opcode);
|
9906 |
|
|
if (cond == COND_ALWAYS)
|
9907 |
|
|
reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
|
9908 |
|
|
else
|
9909 |
|
|
{
|
9910 |
|
|
gas_assert (cond != 0xF);
|
9911 |
|
|
inst.instruction |= cond << 22;
|
9912 |
|
|
reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
|
9913 |
|
|
}
|
9914 |
|
|
}
|
9915 |
|
|
else
|
9916 |
|
|
{
|
9917 |
|
|
inst.instruction = THUMB_OP16(opcode);
|
9918 |
|
|
if (cond == COND_ALWAYS)
|
9919 |
|
|
reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
|
9920 |
|
|
else
|
9921 |
|
|
{
|
9922 |
|
|
inst.instruction |= cond << 8;
|
9923 |
|
|
reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
|
9924 |
|
|
}
|
9925 |
|
|
/* Allow section relaxation. */
|
9926 |
|
|
if (unified_syntax && inst.size_req != 2)
|
9927 |
|
|
inst.relax = opcode;
|
9928 |
|
|
}
|
9929 |
|
|
inst.reloc.type = reloc;
|
9930 |
|
|
inst.reloc.pc_rel = 1;
|
9931 |
|
|
}
|
9932 |
|
|
|
9933 |
|
|
static void
|
9934 |
|
|
do_t_bkpt (void)
|
9935 |
|
|
{
|
9936 |
|
|
constraint (inst.cond != COND_ALWAYS,
|
9937 |
|
|
_("instruction is always unconditional"));
|
9938 |
|
|
if (inst.operands[0].present)
|
9939 |
|
|
{
|
9940 |
|
|
constraint (inst.operands[0].imm > 255,
|
9941 |
|
|
_("immediate value out of range"));
|
9942 |
|
|
inst.instruction |= inst.operands[0].imm;
|
9943 |
|
|
set_it_insn_type (NEUTRAL_IT_INSN);
|
9944 |
|
|
}
|
9945 |
|
|
}
|
9946 |
|
|
|
9947 |
|
|
static void
|
9948 |
|
|
do_t_branch23 (void)
|
9949 |
|
|
{
|
9950 |
|
|
set_it_insn_type_last ();
|
9951 |
|
|
encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
|
9952 |
|
|
|
9953 |
|
|
/* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
|
9954 |
|
|
this file. We used to simply ignore the PLT reloc type here --
|
9955 |
|
|
the branch encoding is now needed to deal with TLSCALL relocs.
|
9956 |
|
|
So if we see a PLT reloc now, put it back to how it used to be to
|
9957 |
|
|
keep the preexisting behaviour. */
|
9958 |
|
|
if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
|
9959 |
|
|
inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
|
9960 |
|
|
|
9961 |
|
|
#if defined(OBJ_COFF)
|
9962 |
|
|
/* If the destination of the branch is a defined symbol which does not have
|
9963 |
|
|
the THUMB_FUNC attribute, then we must be calling a function which has
|
9964 |
|
|
the (interfacearm) attribute. We look for the Thumb entry point to that
|
9965 |
|
|
function and change the branch to refer to that function instead. */
|
9966 |
|
|
if ( inst.reloc.exp.X_op == O_symbol
|
9967 |
|
|
&& inst.reloc.exp.X_add_symbol != NULL
|
9968 |
|
|
&& S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
|
9969 |
|
|
&& ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
|
9970 |
|
|
inst.reloc.exp.X_add_symbol =
|
9971 |
|
|
find_real_start (inst.reloc.exp.X_add_symbol);
|
9972 |
|
|
#endif
|
9973 |
|
|
}
|
9974 |
|
|
|
9975 |
|
|
static void
|
9976 |
|
|
do_t_bx (void)
|
9977 |
|
|
{
|
9978 |
|
|
set_it_insn_type_last ();
|
9979 |
|
|
inst.instruction |= inst.operands[0].reg << 3;
|
9980 |
|
|
/* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
|
9981 |
|
|
should cause the alignment to be checked once it is known. This is
|
9982 |
|
|
because BX PC only works if the instruction is word aligned. */
|
9983 |
|
|
}
|
9984 |
|
|
|
9985 |
|
|
static void
|
9986 |
|
|
do_t_bxj (void)
|
9987 |
|
|
{
|
9988 |
|
|
int Rm;
|
9989 |
|
|
|
9990 |
|
|
set_it_insn_type_last ();
|
9991 |
|
|
Rm = inst.operands[0].reg;
|
9992 |
|
|
reject_bad_reg (Rm);
|
9993 |
|
|
inst.instruction |= Rm << 16;
|
9994 |
|
|
}
|
9995 |
|
|
|
9996 |
|
|
static void
|
9997 |
|
|
do_t_clz (void)
|
9998 |
|
|
{
|
9999 |
|
|
unsigned Rd;
|
10000 |
|
|
unsigned Rm;
|
10001 |
|
|
|
10002 |
|
|
Rd = inst.operands[0].reg;
|
10003 |
|
|
Rm = inst.operands[1].reg;
|
10004 |
|
|
|
10005 |
|
|
reject_bad_reg (Rd);
|
10006 |
|
|
reject_bad_reg (Rm);
|
10007 |
|
|
|
10008 |
|
|
inst.instruction |= Rd << 8;
|
10009 |
|
|
inst.instruction |= Rm << 16;
|
10010 |
|
|
inst.instruction |= Rm;
|
10011 |
|
|
}
|
10012 |
|
|
|
10013 |
|
|
static void
|
10014 |
|
|
do_t_cps (void)
|
10015 |
|
|
{
|
10016 |
|
|
set_it_insn_type (OUTSIDE_IT_INSN);
|
10017 |
|
|
inst.instruction |= inst.operands[0].imm;
|
10018 |
|
|
}
|
10019 |
|
|
|
10020 |
|
|
static void
|
10021 |
|
|
do_t_cpsi (void)
|
10022 |
|
|
{
|
10023 |
|
|
set_it_insn_type (OUTSIDE_IT_INSN);
|
10024 |
|
|
if (unified_syntax
|
10025 |
|
|
&& (inst.operands[1].present || inst.size_req == 4)
|
10026 |
|
|
&& ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
|
10027 |
|
|
{
|
10028 |
|
|
unsigned int imod = (inst.instruction & 0x0030) >> 4;
|
10029 |
|
|
inst.instruction = 0xf3af8000;
|
10030 |
|
|
inst.instruction |= imod << 9;
|
10031 |
|
|
inst.instruction |= inst.operands[0].imm << 5;
|
10032 |
|
|
if (inst.operands[1].present)
|
10033 |
|
|
inst.instruction |= 0x100 | inst.operands[1].imm;
|
10034 |
|
|
}
|
10035 |
|
|
else
|
10036 |
|
|
{
|
10037 |
|
|
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
|
10038 |
|
|
&& (inst.operands[0].imm & 4),
|
10039 |
|
|
_("selected processor does not support 'A' form "
|
10040 |
|
|
"of this instruction"));
|
10041 |
|
|
constraint (inst.operands[1].present || inst.size_req == 4,
|
10042 |
|
|
_("Thumb does not support the 2-argument "
|
10043 |
|
|
"form of this instruction"));
|
10044 |
|
|
inst.instruction |= inst.operands[0].imm;
|
10045 |
|
|
}
|
10046 |
|
|
}
|
10047 |
|
|
|
10048 |
|
|
/* THUMB CPY instruction (argument parse). */
|
10049 |
|
|
|
10050 |
|
|
static void
|
10051 |
|
|
do_t_cpy (void)
|
10052 |
|
|
{
|
10053 |
|
|
if (inst.size_req == 4)
|
10054 |
|
|
{
|
10055 |
|
|
inst.instruction = THUMB_OP32 (T_MNEM_mov);
|
10056 |
|
|
inst.instruction |= inst.operands[0].reg << 8;
|
10057 |
|
|
inst.instruction |= inst.operands[1].reg;
|
10058 |
|
|
}
|
10059 |
|
|
else
|
10060 |
|
|
{
|
10061 |
|
|
inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
|
10062 |
|
|
inst.instruction |= (inst.operands[0].reg & 0x7);
|
10063 |
|
|
inst.instruction |= inst.operands[1].reg << 3;
|
10064 |
|
|
}
|
10065 |
|
|
}
|
10066 |
|
|
|
10067 |
|
|
static void
|
10068 |
|
|
do_t_cbz (void)
|
10069 |
|
|
{
|
10070 |
|
|
set_it_insn_type (OUTSIDE_IT_INSN);
|
10071 |
|
|
constraint (inst.operands[0].reg > 7, BAD_HIREG);
|
10072 |
|
|
inst.instruction |= inst.operands[0].reg;
|
10073 |
|
|
inst.reloc.pc_rel = 1;
|
10074 |
|
|
inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
|
10075 |
|
|
}
|
10076 |
|
|
|
10077 |
|
|
static void
|
10078 |
|
|
do_t_dbg (void)
|
10079 |
|
|
{
|
10080 |
|
|
inst.instruction |= inst.operands[0].imm;
|
10081 |
|
|
}
|
10082 |
|
|
|
10083 |
|
|
static void
|
10084 |
|
|
do_t_div (void)
|
10085 |
|
|
{
|
10086 |
|
|
unsigned Rd, Rn, Rm;
|
10087 |
|
|
|
10088 |
|
|
Rd = inst.operands[0].reg;
|
10089 |
|
|
Rn = (inst.operands[1].present
|
10090 |
|
|
? inst.operands[1].reg : Rd);
|
10091 |
|
|
Rm = inst.operands[2].reg;
|
10092 |
|
|
|
10093 |
|
|
reject_bad_reg (Rd);
|
10094 |
|
|
reject_bad_reg (Rn);
|
10095 |
|
|
reject_bad_reg (Rm);
|
10096 |
|
|
|
10097 |
|
|
inst.instruction |= Rd << 8;
|
10098 |
|
|
inst.instruction |= Rn << 16;
|
10099 |
|
|
inst.instruction |= Rm;
|
10100 |
|
|
}
|
10101 |
|
|
|
10102 |
|
|
static void
|
10103 |
|
|
do_t_hint (void)
|
10104 |
|
|
{
|
10105 |
|
|
if (unified_syntax && inst.size_req == 4)
|
10106 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
10107 |
|
|
else
|
10108 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
10109 |
|
|
}
|
10110 |
|
|
|
10111 |
|
|
static void
|
10112 |
|
|
do_t_it (void)
|
10113 |
|
|
{
|
10114 |
|
|
unsigned int cond = inst.operands[0].imm;
|
10115 |
|
|
|
10116 |
|
|
set_it_insn_type (IT_INSN);
|
10117 |
|
|
now_it.mask = (inst.instruction & 0xf) | 0x10;
|
10118 |
|
|
now_it.cc = cond;
|
10119 |
|
|
|
10120 |
|
|
/* If the condition is a negative condition, invert the mask. */
|
10121 |
|
|
if ((cond & 0x1) == 0x0)
|
10122 |
|
|
{
|
10123 |
|
|
unsigned int mask = inst.instruction & 0x000f;
|
10124 |
|
|
|
10125 |
|
|
if ((mask & 0x7) == 0)
|
10126 |
|
|
/* no conversion needed */;
|
10127 |
|
|
else if ((mask & 0x3) == 0)
|
10128 |
|
|
mask ^= 0x8;
|
10129 |
|
|
else if ((mask & 0x1) == 0)
|
10130 |
|
|
mask ^= 0xC;
|
10131 |
|
|
else
|
10132 |
|
|
mask ^= 0xE;
|
10133 |
|
|
|
10134 |
|
|
inst.instruction &= 0xfff0;
|
10135 |
|
|
inst.instruction |= mask;
|
10136 |
|
|
}
|
10137 |
|
|
|
10138 |
|
|
inst.instruction |= cond << 4;
|
10139 |
|
|
}
|
10140 |
|
|
|
10141 |
|
|
/* Helper function used for both push/pop and ldm/stm. */
|
10142 |
|
|
static void
|
10143 |
|
|
encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
|
10144 |
|
|
{
|
10145 |
|
|
bfd_boolean load;
|
10146 |
|
|
|
10147 |
|
|
load = (inst.instruction & (1 << 20)) != 0;
|
10148 |
|
|
|
10149 |
|
|
if (mask & (1 << 13))
|
10150 |
|
|
inst.error = _("SP not allowed in register list");
|
10151 |
|
|
|
10152 |
|
|
if ((mask & (1 << base)) != 0
|
10153 |
|
|
&& writeback)
|
10154 |
|
|
inst.error = _("having the base register in the register list when "
|
10155 |
|
|
"using write back is UNPREDICTABLE");
|
10156 |
|
|
|
10157 |
|
|
if (load)
|
10158 |
|
|
{
|
10159 |
|
|
if (mask & (1 << 15))
|
10160 |
|
|
{
|
10161 |
|
|
if (mask & (1 << 14))
|
10162 |
|
|
inst.error = _("LR and PC should not both be in register list");
|
10163 |
|
|
else
|
10164 |
|
|
set_it_insn_type_last ();
|
10165 |
|
|
}
|
10166 |
|
|
}
|
10167 |
|
|
else
|
10168 |
|
|
{
|
10169 |
|
|
if (mask & (1 << 15))
|
10170 |
|
|
inst.error = _("PC not allowed in register list");
|
10171 |
|
|
}
|
10172 |
|
|
|
10173 |
|
|
if ((mask & (mask - 1)) == 0)
|
10174 |
|
|
{
|
10175 |
|
|
/* Single register transfers implemented as str/ldr. */
|
10176 |
|
|
if (writeback)
|
10177 |
|
|
{
|
10178 |
|
|
if (inst.instruction & (1 << 23))
|
10179 |
|
|
inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
|
10180 |
|
|
else
|
10181 |
|
|
inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
|
10182 |
|
|
}
|
10183 |
|
|
else
|
10184 |
|
|
{
|
10185 |
|
|
if (inst.instruction & (1 << 23))
|
10186 |
|
|
inst.instruction = 0x00800000; /* ia -> [base] */
|
10187 |
|
|
else
|
10188 |
|
|
inst.instruction = 0x00000c04; /* db -> [base, #-4] */
|
10189 |
|
|
}
|
10190 |
|
|
|
10191 |
|
|
inst.instruction |= 0xf8400000;
|
10192 |
|
|
if (load)
|
10193 |
|
|
inst.instruction |= 0x00100000;
|
10194 |
|
|
|
10195 |
|
|
mask = ffs (mask) - 1;
|
10196 |
|
|
mask <<= 12;
|
10197 |
|
|
}
|
10198 |
|
|
else if (writeback)
|
10199 |
|
|
inst.instruction |= WRITE_BACK;
|
10200 |
|
|
|
10201 |
|
|
inst.instruction |= mask;
|
10202 |
|
|
inst.instruction |= base << 16;
|
10203 |
|
|
}
|
10204 |
|
|
|
10205 |
|
|
static void
|
10206 |
|
|
do_t_ldmstm (void)
|
10207 |
|
|
{
|
10208 |
|
|
/* This really doesn't seem worth it. */
|
10209 |
|
|
constraint (inst.reloc.type != BFD_RELOC_UNUSED,
|
10210 |
|
|
_("expression too complex"));
|
10211 |
|
|
constraint (inst.operands[1].writeback,
|
10212 |
|
|
_("Thumb load/store multiple does not support {reglist}^"));
|
10213 |
|
|
|
10214 |
|
|
if (unified_syntax)
|
10215 |
|
|
{
|
10216 |
|
|
bfd_boolean narrow;
|
10217 |
|
|
unsigned mask;
|
10218 |
|
|
|
10219 |
|
|
narrow = FALSE;
|
10220 |
|
|
/* See if we can use a 16-bit instruction. */
|
10221 |
|
|
if (inst.instruction < 0xffff /* not ldmdb/stmdb */
|
10222 |
|
|
&& inst.size_req != 4
|
10223 |
|
|
&& !(inst.operands[1].imm & ~0xff))
|
10224 |
|
|
{
|
10225 |
|
|
mask = 1 << inst.operands[0].reg;
|
10226 |
|
|
|
10227 |
|
|
if (inst.operands[0].reg <= 7)
|
10228 |
|
|
{
|
10229 |
|
|
if (inst.instruction == T_MNEM_stmia
|
10230 |
|
|
? inst.operands[0].writeback
|
10231 |
|
|
: (inst.operands[0].writeback
|
10232 |
|
|
== !(inst.operands[1].imm & mask)))
|
10233 |
|
|
{
|
10234 |
|
|
if (inst.instruction == T_MNEM_stmia
|
10235 |
|
|
&& (inst.operands[1].imm & mask)
|
10236 |
|
|
&& (inst.operands[1].imm & (mask - 1)))
|
10237 |
|
|
as_warn (_("value stored for r%d is UNKNOWN"),
|
10238 |
|
|
inst.operands[0].reg);
|
10239 |
|
|
|
10240 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
10241 |
|
|
inst.instruction |= inst.operands[0].reg << 8;
|
10242 |
|
|
inst.instruction |= inst.operands[1].imm;
|
10243 |
|
|
narrow = TRUE;
|
10244 |
|
|
}
|
10245 |
|
|
else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
|
10246 |
|
|
{
|
10247 |
|
|
/* This means 1 register in reg list one of 3 situations:
|
10248 |
|
|
1. Instruction is stmia, but without writeback.
|
10249 |
|
|
2. lmdia without writeback, but with Rn not in
|
10250 |
|
|
reglist.
|
10251 |
|
|
3. ldmia with writeback, but with Rn in reglist.
|
10252 |
|
|
Case 3 is UNPREDICTABLE behaviour, so we handle
|
10253 |
|
|
case 1 and 2 which can be converted into a 16-bit
|
10254 |
|
|
str or ldr. The SP cases are handled below. */
|
10255 |
|
|
unsigned long opcode;
|
10256 |
|
|
/* First, record an error for Case 3. */
|
10257 |
|
|
if (inst.operands[1].imm & mask
|
10258 |
|
|
&& inst.operands[0].writeback)
|
10259 |
|
|
inst.error =
|
10260 |
|
|
_("having the base register in the register list when "
|
10261 |
|
|
"using write back is UNPREDICTABLE");
|
10262 |
|
|
|
10263 |
|
|
opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
|
10264 |
|
|
: T_MNEM_ldr);
|
10265 |
|
|
inst.instruction = THUMB_OP16 (opcode);
|
10266 |
|
|
inst.instruction |= inst.operands[0].reg << 3;
|
10267 |
|
|
inst.instruction |= (ffs (inst.operands[1].imm)-1);
|
10268 |
|
|
narrow = TRUE;
|
10269 |
|
|
}
|
10270 |
|
|
}
|
10271 |
|
|
else if (inst.operands[0] .reg == REG_SP)
|
10272 |
|
|
{
|
10273 |
|
|
if (inst.operands[0].writeback)
|
10274 |
|
|
{
|
10275 |
|
|
inst.instruction =
|
10276 |
|
|
THUMB_OP16 (inst.instruction == T_MNEM_stmia
|
10277 |
|
|
? T_MNEM_push : T_MNEM_pop);
|
10278 |
|
|
inst.instruction |= inst.operands[1].imm;
|
10279 |
|
|
narrow = TRUE;
|
10280 |
|
|
}
|
10281 |
|
|
else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
|
10282 |
|
|
{
|
10283 |
|
|
inst.instruction =
|
10284 |
|
|
THUMB_OP16 (inst.instruction == T_MNEM_stmia
|
10285 |
|
|
? T_MNEM_str_sp : T_MNEM_ldr_sp);
|
10286 |
|
|
inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
|
10287 |
|
|
narrow = TRUE;
|
10288 |
|
|
}
|
10289 |
|
|
}
|
10290 |
|
|
}
|
10291 |
|
|
|
10292 |
|
|
if (!narrow)
|
10293 |
|
|
{
|
10294 |
|
|
if (inst.instruction < 0xffff)
|
10295 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
10296 |
|
|
|
10297 |
|
|
encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
|
10298 |
|
|
inst.operands[0].writeback);
|
10299 |
|
|
}
|
10300 |
|
|
}
|
10301 |
|
|
else
|
10302 |
|
|
{
|
10303 |
|
|
constraint (inst.operands[0].reg > 7
|
10304 |
|
|
|| (inst.operands[1].imm & ~0xff), BAD_HIREG);
|
10305 |
|
|
constraint (inst.instruction != T_MNEM_ldmia
|
10306 |
|
|
&& inst.instruction != T_MNEM_stmia,
|
10307 |
|
|
_("Thumb-2 instruction only valid in unified syntax"));
|
10308 |
|
|
if (inst.instruction == T_MNEM_stmia)
|
10309 |
|
|
{
|
10310 |
|
|
if (!inst.operands[0].writeback)
|
10311 |
|
|
as_warn (_("this instruction will write back the base register"));
|
10312 |
|
|
if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
|
10313 |
|
|
&& (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
|
10314 |
|
|
as_warn (_("value stored for r%d is UNKNOWN"),
|
10315 |
|
|
inst.operands[0].reg);
|
10316 |
|
|
}
|
10317 |
|
|
else
|
10318 |
|
|
{
|
10319 |
|
|
if (!inst.operands[0].writeback
|
10320 |
|
|
&& !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
|
10321 |
|
|
as_warn (_("this instruction will write back the base register"));
|
10322 |
|
|
else if (inst.operands[0].writeback
|
10323 |
|
|
&& (inst.operands[1].imm & (1 << inst.operands[0].reg)))
|
10324 |
|
|
as_warn (_("this instruction will not write back the base register"));
|
10325 |
|
|
}
|
10326 |
|
|
|
10327 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
10328 |
|
|
inst.instruction |= inst.operands[0].reg << 8;
|
10329 |
|
|
inst.instruction |= inst.operands[1].imm;
|
10330 |
|
|
}
|
10331 |
|
|
}
|
10332 |
|
|
|
10333 |
|
|
static void
|
10334 |
|
|
do_t_ldrex (void)
|
10335 |
|
|
{
|
10336 |
|
|
constraint (!inst.operands[1].isreg || !inst.operands[1].preind
|
10337 |
|
|
|| inst.operands[1].postind || inst.operands[1].writeback
|
10338 |
|
|
|| inst.operands[1].immisreg || inst.operands[1].shifted
|
10339 |
|
|
|| inst.operands[1].negative,
|
10340 |
|
|
BAD_ADDR_MODE);
|
10341 |
|
|
|
10342 |
|
|
constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
|
10343 |
|
|
|
10344 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
10345 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
10346 |
|
|
inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
|
10347 |
|
|
}
|
10348 |
|
|
|
10349 |
|
|
static void
|
10350 |
|
|
do_t_ldrexd (void)
|
10351 |
|
|
{
|
10352 |
|
|
if (!inst.operands[1].present)
|
10353 |
|
|
{
|
10354 |
|
|
constraint (inst.operands[0].reg == REG_LR,
|
10355 |
|
|
_("r14 not allowed as first register "
|
10356 |
|
|
"when second register is omitted"));
|
10357 |
|
|
inst.operands[1].reg = inst.operands[0].reg + 1;
|
10358 |
|
|
}
|
10359 |
|
|
constraint (inst.operands[0].reg == inst.operands[1].reg,
|
10360 |
|
|
BAD_OVERLAP);
|
10361 |
|
|
|
10362 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
10363 |
|
|
inst.instruction |= inst.operands[1].reg << 8;
|
10364 |
|
|
inst.instruction |= inst.operands[2].reg << 16;
|
10365 |
|
|
}
|
10366 |
|
|
|
10367 |
|
|
static void
|
10368 |
|
|
do_t_ldst (void)
|
10369 |
|
|
{
|
10370 |
|
|
unsigned long opcode;
|
10371 |
|
|
int Rn;
|
10372 |
|
|
|
10373 |
|
|
if (inst.operands[0].isreg
|
10374 |
|
|
&& !inst.operands[0].preind
|
10375 |
|
|
&& inst.operands[0].reg == REG_PC)
|
10376 |
|
|
set_it_insn_type_last ();
|
10377 |
|
|
|
10378 |
|
|
opcode = inst.instruction;
|
10379 |
|
|
if (unified_syntax)
|
10380 |
|
|
{
|
10381 |
|
|
if (!inst.operands[1].isreg)
|
10382 |
|
|
{
|
10383 |
|
|
if (opcode <= 0xffff)
|
10384 |
|
|
inst.instruction = THUMB_OP32 (opcode);
|
10385 |
|
|
if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
|
10386 |
|
|
return;
|
10387 |
|
|
}
|
10388 |
|
|
if (inst.operands[1].isreg
|
10389 |
|
|
&& !inst.operands[1].writeback
|
10390 |
|
|
&& !inst.operands[1].shifted && !inst.operands[1].postind
|
10391 |
|
|
&& !inst.operands[1].negative && inst.operands[0].reg <= 7
|
10392 |
|
|
&& opcode <= 0xffff
|
10393 |
|
|
&& inst.size_req != 4)
|
10394 |
|
|
{
|
10395 |
|
|
/* Insn may have a 16-bit form. */
|
10396 |
|
|
Rn = inst.operands[1].reg;
|
10397 |
|
|
if (inst.operands[1].immisreg)
|
10398 |
|
|
{
|
10399 |
|
|
inst.instruction = THUMB_OP16 (opcode);
|
10400 |
|
|
/* [Rn, Rik] */
|
10401 |
|
|
if (Rn <= 7 && inst.operands[1].imm <= 7)
|
10402 |
|
|
goto op16;
|
10403 |
|
|
else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
|
10404 |
|
|
reject_bad_reg (inst.operands[1].imm);
|
10405 |
|
|
}
|
10406 |
|
|
else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
|
10407 |
|
|
&& opcode != T_MNEM_ldrsb)
|
10408 |
|
|
|| ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
|
10409 |
|
|
|| (Rn == REG_SP && opcode == T_MNEM_str))
|
10410 |
|
|
{
|
10411 |
|
|
/* [Rn, #const] */
|
10412 |
|
|
if (Rn > 7)
|
10413 |
|
|
{
|
10414 |
|
|
if (Rn == REG_PC)
|
10415 |
|
|
{
|
10416 |
|
|
if (inst.reloc.pc_rel)
|
10417 |
|
|
opcode = T_MNEM_ldr_pc2;
|
10418 |
|
|
else
|
10419 |
|
|
opcode = T_MNEM_ldr_pc;
|
10420 |
|
|
}
|
10421 |
|
|
else
|
10422 |
|
|
{
|
10423 |
|
|
if (opcode == T_MNEM_ldr)
|
10424 |
|
|
opcode = T_MNEM_ldr_sp;
|
10425 |
|
|
else
|
10426 |
|
|
opcode = T_MNEM_str_sp;
|
10427 |
|
|
}
|
10428 |
|
|
inst.instruction = inst.operands[0].reg << 8;
|
10429 |
|
|
}
|
10430 |
|
|
else
|
10431 |
|
|
{
|
10432 |
|
|
inst.instruction = inst.operands[0].reg;
|
10433 |
|
|
inst.instruction |= inst.operands[1].reg << 3;
|
10434 |
|
|
}
|
10435 |
|
|
inst.instruction |= THUMB_OP16 (opcode);
|
10436 |
|
|
if (inst.size_req == 2)
|
10437 |
|
|
inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
|
10438 |
|
|
else
|
10439 |
|
|
inst.relax = opcode;
|
10440 |
|
|
return;
|
10441 |
|
|
}
|
10442 |
|
|
}
|
10443 |
|
|
/* Definitely a 32-bit variant. */
|
10444 |
|
|
|
10445 |
|
|
/* Warning for Erratum 752419. */
|
10446 |
|
|
if (opcode == T_MNEM_ldr
|
10447 |
|
|
&& inst.operands[0].reg == REG_SP
|
10448 |
|
|
&& inst.operands[1].writeback == 1
|
10449 |
|
|
&& !inst.operands[1].immisreg)
|
10450 |
|
|
{
|
10451 |
|
|
if (no_cpu_selected ()
|
10452 |
|
|
|| (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
|
10453 |
|
|
&& !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
|
10454 |
|
|
&& !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
|
10455 |
|
|
as_warn (_("This instruction may be unpredictable "
|
10456 |
|
|
"if executed on M-profile cores "
|
10457 |
|
|
"with interrupts enabled."));
|
10458 |
|
|
}
|
10459 |
|
|
|
10460 |
|
|
/* Do some validations regarding addressing modes. */
|
10461 |
|
|
if (inst.operands[1].immisreg && opcode != T_MNEM_ldr
|
10462 |
|
|
&& opcode != T_MNEM_str)
|
10463 |
|
|
reject_bad_reg (inst.operands[1].imm);
|
10464 |
|
|
|
10465 |
|
|
inst.instruction = THUMB_OP32 (opcode);
|
10466 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
10467 |
|
|
encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
|
10468 |
|
|
return;
|
10469 |
|
|
}
|
10470 |
|
|
|
10471 |
|
|
constraint (inst.operands[0].reg > 7, BAD_HIREG);
|
10472 |
|
|
|
10473 |
|
|
if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
|
10474 |
|
|
{
|
10475 |
|
|
/* Only [Rn,Rm] is acceptable. */
|
10476 |
|
|
constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
|
10477 |
|
|
constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
|
10478 |
|
|
|| inst.operands[1].postind || inst.operands[1].shifted
|
10479 |
|
|
|| inst.operands[1].negative,
|
10480 |
|
|
_("Thumb does not support this addressing mode"));
|
10481 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
10482 |
|
|
goto op16;
|
10483 |
|
|
}
|
10484 |
|
|
|
10485 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
10486 |
|
|
if (!inst.operands[1].isreg)
|
10487 |
|
|
if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
|
10488 |
|
|
return;
|
10489 |
|
|
|
10490 |
|
|
constraint (!inst.operands[1].preind
|
10491 |
|
|
|| inst.operands[1].shifted
|
10492 |
|
|
|| inst.operands[1].writeback,
|
10493 |
|
|
_("Thumb does not support this addressing mode"));
|
10494 |
|
|
if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
|
10495 |
|
|
{
|
10496 |
|
|
constraint (inst.instruction & 0x0600,
|
10497 |
|
|
_("byte or halfword not valid for base register"));
|
10498 |
|
|
constraint (inst.operands[1].reg == REG_PC
|
10499 |
|
|
&& !(inst.instruction & THUMB_LOAD_BIT),
|
10500 |
|
|
_("r15 based store not allowed"));
|
10501 |
|
|
constraint (inst.operands[1].immisreg,
|
10502 |
|
|
_("invalid base register for register offset"));
|
10503 |
|
|
|
10504 |
|
|
if (inst.operands[1].reg == REG_PC)
|
10505 |
|
|
inst.instruction = T_OPCODE_LDR_PC;
|
10506 |
|
|
else if (inst.instruction & THUMB_LOAD_BIT)
|
10507 |
|
|
inst.instruction = T_OPCODE_LDR_SP;
|
10508 |
|
|
else
|
10509 |
|
|
inst.instruction = T_OPCODE_STR_SP;
|
10510 |
|
|
|
10511 |
|
|
inst.instruction |= inst.operands[0].reg << 8;
|
10512 |
|
|
inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
|
10513 |
|
|
return;
|
10514 |
|
|
}
|
10515 |
|
|
|
10516 |
|
|
constraint (inst.operands[1].reg > 7, BAD_HIREG);
|
10517 |
|
|
if (!inst.operands[1].immisreg)
|
10518 |
|
|
{
|
10519 |
|
|
/* Immediate offset. */
|
10520 |
|
|
inst.instruction |= inst.operands[0].reg;
|
10521 |
|
|
inst.instruction |= inst.operands[1].reg << 3;
|
10522 |
|
|
inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
|
10523 |
|
|
return;
|
10524 |
|
|
}
|
10525 |
|
|
|
10526 |
|
|
/* Register offset. */
|
10527 |
|
|
constraint (inst.operands[1].imm > 7, BAD_HIREG);
|
10528 |
|
|
constraint (inst.operands[1].negative,
|
10529 |
|
|
_("Thumb does not support this addressing mode"));
|
10530 |
|
|
|
10531 |
|
|
op16:
|
10532 |
|
|
switch (inst.instruction)
|
10533 |
|
|
{
|
10534 |
|
|
case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
|
10535 |
|
|
case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
|
10536 |
|
|
case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
|
10537 |
|
|
case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
|
10538 |
|
|
case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
|
10539 |
|
|
case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
|
10540 |
|
|
case 0x5600 /* ldrsb */:
|
10541 |
|
|
case 0x5e00 /* ldrsh */: break;
|
10542 |
|
|
default: abort ();
|
10543 |
|
|
}
|
10544 |
|
|
|
10545 |
|
|
inst.instruction |= inst.operands[0].reg;
|
10546 |
|
|
inst.instruction |= inst.operands[1].reg << 3;
|
10547 |
|
|
inst.instruction |= inst.operands[1].imm << 6;
|
10548 |
|
|
}
|
10549 |
|
|
|
10550 |
|
|
static void
|
10551 |
|
|
do_t_ldstd (void)
|
10552 |
|
|
{
|
10553 |
|
|
if (!inst.operands[1].present)
|
10554 |
|
|
{
|
10555 |
|
|
inst.operands[1].reg = inst.operands[0].reg + 1;
|
10556 |
|
|
constraint (inst.operands[0].reg == REG_LR,
|
10557 |
|
|
_("r14 not allowed here"));
|
10558 |
|
|
}
|
10559 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
10560 |
|
|
inst.instruction |= inst.operands[1].reg << 8;
|
10561 |
|
|
encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
|
10562 |
|
|
}
|
10563 |
|
|
|
10564 |
|
|
static void
|
10565 |
|
|
do_t_ldstt (void)
|
10566 |
|
|
{
|
10567 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
10568 |
|
|
encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
|
10569 |
|
|
}
|
10570 |
|
|
|
10571 |
|
|
static void
|
10572 |
|
|
do_t_mla (void)
|
10573 |
|
|
{
|
10574 |
|
|
unsigned Rd, Rn, Rm, Ra;
|
10575 |
|
|
|
10576 |
|
|
Rd = inst.operands[0].reg;
|
10577 |
|
|
Rn = inst.operands[1].reg;
|
10578 |
|
|
Rm = inst.operands[2].reg;
|
10579 |
|
|
Ra = inst.operands[3].reg;
|
10580 |
|
|
|
10581 |
|
|
reject_bad_reg (Rd);
|
10582 |
|
|
reject_bad_reg (Rn);
|
10583 |
|
|
reject_bad_reg (Rm);
|
10584 |
|
|
reject_bad_reg (Ra);
|
10585 |
|
|
|
10586 |
|
|
inst.instruction |= Rd << 8;
|
10587 |
|
|
inst.instruction |= Rn << 16;
|
10588 |
|
|
inst.instruction |= Rm;
|
10589 |
|
|
inst.instruction |= Ra << 12;
|
10590 |
|
|
}
|
10591 |
|
|
|
10592 |
|
|
static void
|
10593 |
|
|
do_t_mlal (void)
|
10594 |
|
|
{
|
10595 |
|
|
unsigned RdLo, RdHi, Rn, Rm;
|
10596 |
|
|
|
10597 |
|
|
RdLo = inst.operands[0].reg;
|
10598 |
|
|
RdHi = inst.operands[1].reg;
|
10599 |
|
|
Rn = inst.operands[2].reg;
|
10600 |
|
|
Rm = inst.operands[3].reg;
|
10601 |
|
|
|
10602 |
|
|
reject_bad_reg (RdLo);
|
10603 |
|
|
reject_bad_reg (RdHi);
|
10604 |
|
|
reject_bad_reg (Rn);
|
10605 |
|
|
reject_bad_reg (Rm);
|
10606 |
|
|
|
10607 |
|
|
inst.instruction |= RdLo << 12;
|
10608 |
|
|
inst.instruction |= RdHi << 8;
|
10609 |
|
|
inst.instruction |= Rn << 16;
|
10610 |
|
|
inst.instruction |= Rm;
|
10611 |
|
|
}
|
10612 |
|
|
|
10613 |
|
|
static void
|
10614 |
|
|
do_t_mov_cmp (void)
|
10615 |
|
|
{
|
10616 |
|
|
unsigned Rn, Rm;
|
10617 |
|
|
|
10618 |
|
|
Rn = inst.operands[0].reg;
|
10619 |
|
|
Rm = inst.operands[1].reg;
|
10620 |
|
|
|
10621 |
|
|
if (Rn == REG_PC)
|
10622 |
|
|
set_it_insn_type_last ();
|
10623 |
|
|
|
10624 |
|
|
if (unified_syntax)
|
10625 |
|
|
{
|
10626 |
|
|
int r0off = (inst.instruction == T_MNEM_mov
|
10627 |
|
|
|| inst.instruction == T_MNEM_movs) ? 8 : 16;
|
10628 |
|
|
unsigned long opcode;
|
10629 |
|
|
bfd_boolean narrow;
|
10630 |
|
|
bfd_boolean low_regs;
|
10631 |
|
|
|
10632 |
|
|
low_regs = (Rn <= 7 && Rm <= 7);
|
10633 |
|
|
opcode = inst.instruction;
|
10634 |
|
|
if (in_it_block ())
|
10635 |
|
|
narrow = opcode != T_MNEM_movs;
|
10636 |
|
|
else
|
10637 |
|
|
narrow = opcode != T_MNEM_movs || low_regs;
|
10638 |
|
|
if (inst.size_req == 4
|
10639 |
|
|
|| inst.operands[1].shifted)
|
10640 |
|
|
narrow = FALSE;
|
10641 |
|
|
|
10642 |
|
|
/* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
|
10643 |
|
|
if (opcode == T_MNEM_movs && inst.operands[1].isreg
|
10644 |
|
|
&& !inst.operands[1].shifted
|
10645 |
|
|
&& Rn == REG_PC
|
10646 |
|
|
&& Rm == REG_LR)
|
10647 |
|
|
{
|
10648 |
|
|
inst.instruction = T2_SUBS_PC_LR;
|
10649 |
|
|
return;
|
10650 |
|
|
}
|
10651 |
|
|
|
10652 |
|
|
if (opcode == T_MNEM_cmp)
|
10653 |
|
|
{
|
10654 |
|
|
constraint (Rn == REG_PC, BAD_PC);
|
10655 |
|
|
if (narrow)
|
10656 |
|
|
{
|
10657 |
|
|
/* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
|
10658 |
|
|
but valid. */
|
10659 |
|
|
warn_deprecated_sp (Rm);
|
10660 |
|
|
/* R15 was documented as a valid choice for Rm in ARMv6,
|
10661 |
|
|
but as UNPREDICTABLE in ARMv7. ARM's proprietary
|
10662 |
|
|
tools reject R15, so we do too. */
|
10663 |
|
|
constraint (Rm == REG_PC, BAD_PC);
|
10664 |
|
|
}
|
10665 |
|
|
else
|
10666 |
|
|
reject_bad_reg (Rm);
|
10667 |
|
|
}
|
10668 |
|
|
else if (opcode == T_MNEM_mov
|
10669 |
|
|
|| opcode == T_MNEM_movs)
|
10670 |
|
|
{
|
10671 |
|
|
if (inst.operands[1].isreg)
|
10672 |
|
|
{
|
10673 |
|
|
if (opcode == T_MNEM_movs)
|
10674 |
|
|
{
|
10675 |
|
|
reject_bad_reg (Rn);
|
10676 |
|
|
reject_bad_reg (Rm);
|
10677 |
|
|
}
|
10678 |
|
|
else if (narrow)
|
10679 |
|
|
{
|
10680 |
|
|
/* This is mov.n. */
|
10681 |
|
|
if ((Rn == REG_SP || Rn == REG_PC)
|
10682 |
|
|
&& (Rm == REG_SP || Rm == REG_PC))
|
10683 |
|
|
{
|
10684 |
|
|
as_warn (_("Use of r%u as a source register is "
|
10685 |
|
|
"deprecated when r%u is the destination "
|
10686 |
|
|
"register."), Rm, Rn);
|
10687 |
|
|
}
|
10688 |
|
|
}
|
10689 |
|
|
else
|
10690 |
|
|
{
|
10691 |
|
|
/* This is mov.w. */
|
10692 |
|
|
constraint (Rn == REG_PC, BAD_PC);
|
10693 |
|
|
constraint (Rm == REG_PC, BAD_PC);
|
10694 |
|
|
constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
|
10695 |
|
|
}
|
10696 |
|
|
}
|
10697 |
|
|
else
|
10698 |
|
|
reject_bad_reg (Rn);
|
10699 |
|
|
}
|
10700 |
|
|
|
10701 |
|
|
if (!inst.operands[1].isreg)
|
10702 |
|
|
{
|
10703 |
|
|
/* Immediate operand. */
|
10704 |
|
|
if (!in_it_block () && opcode == T_MNEM_mov)
|
10705 |
|
|
narrow = 0;
|
10706 |
|
|
if (low_regs && narrow)
|
10707 |
|
|
{
|
10708 |
|
|
inst.instruction = THUMB_OP16 (opcode);
|
10709 |
|
|
inst.instruction |= Rn << 8;
|
10710 |
|
|
if (inst.size_req == 2)
|
10711 |
|
|
inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
|
10712 |
|
|
else
|
10713 |
|
|
inst.relax = opcode;
|
10714 |
|
|
}
|
10715 |
|
|
else
|
10716 |
|
|
{
|
10717 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
10718 |
|
|
inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
|
10719 |
|
|
inst.instruction |= Rn << r0off;
|
10720 |
|
|
inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
|
10721 |
|
|
}
|
10722 |
|
|
}
|
10723 |
|
|
else if (inst.operands[1].shifted && inst.operands[1].immisreg
|
10724 |
|
|
&& (inst.instruction == T_MNEM_mov
|
10725 |
|
|
|| inst.instruction == T_MNEM_movs))
|
10726 |
|
|
{
|
10727 |
|
|
/* Register shifts are encoded as separate shift instructions. */
|
10728 |
|
|
bfd_boolean flags = (inst.instruction == T_MNEM_movs);
|
10729 |
|
|
|
10730 |
|
|
if (in_it_block ())
|
10731 |
|
|
narrow = !flags;
|
10732 |
|
|
else
|
10733 |
|
|
narrow = flags;
|
10734 |
|
|
|
10735 |
|
|
if (inst.size_req == 4)
|
10736 |
|
|
narrow = FALSE;
|
10737 |
|
|
|
10738 |
|
|
if (!low_regs || inst.operands[1].imm > 7)
|
10739 |
|
|
narrow = FALSE;
|
10740 |
|
|
|
10741 |
|
|
if (Rn != Rm)
|
10742 |
|
|
narrow = FALSE;
|
10743 |
|
|
|
10744 |
|
|
switch (inst.operands[1].shift_kind)
|
10745 |
|
|
{
|
10746 |
|
|
case SHIFT_LSL:
|
10747 |
|
|
opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
|
10748 |
|
|
break;
|
10749 |
|
|
case SHIFT_ASR:
|
10750 |
|
|
opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
|
10751 |
|
|
break;
|
10752 |
|
|
case SHIFT_LSR:
|
10753 |
|
|
opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
|
10754 |
|
|
break;
|
10755 |
|
|
case SHIFT_ROR:
|
10756 |
|
|
opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
|
10757 |
|
|
break;
|
10758 |
|
|
default:
|
10759 |
|
|
abort ();
|
10760 |
|
|
}
|
10761 |
|
|
|
10762 |
|
|
inst.instruction = opcode;
|
10763 |
|
|
if (narrow)
|
10764 |
|
|
{
|
10765 |
|
|
inst.instruction |= Rn;
|
10766 |
|
|
inst.instruction |= inst.operands[1].imm << 3;
|
10767 |
|
|
}
|
10768 |
|
|
else
|
10769 |
|
|
{
|
10770 |
|
|
if (flags)
|
10771 |
|
|
inst.instruction |= CONDS_BIT;
|
10772 |
|
|
|
10773 |
|
|
inst.instruction |= Rn << 8;
|
10774 |
|
|
inst.instruction |= Rm << 16;
|
10775 |
|
|
inst.instruction |= inst.operands[1].imm;
|
10776 |
|
|
}
|
10777 |
|
|
}
|
10778 |
|
|
else if (!narrow)
|
10779 |
|
|
{
|
10780 |
|
|
/* Some mov with immediate shift have narrow variants.
|
10781 |
|
|
Register shifts are handled above. */
|
10782 |
|
|
if (low_regs && inst.operands[1].shifted
|
10783 |
|
|
&& (inst.instruction == T_MNEM_mov
|
10784 |
|
|
|| inst.instruction == T_MNEM_movs))
|
10785 |
|
|
{
|
10786 |
|
|
if (in_it_block ())
|
10787 |
|
|
narrow = (inst.instruction == T_MNEM_mov);
|
10788 |
|
|
else
|
10789 |
|
|
narrow = (inst.instruction == T_MNEM_movs);
|
10790 |
|
|
}
|
10791 |
|
|
|
10792 |
|
|
if (narrow)
|
10793 |
|
|
{
|
10794 |
|
|
switch (inst.operands[1].shift_kind)
|
10795 |
|
|
{
|
10796 |
|
|
case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
|
10797 |
|
|
case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
|
10798 |
|
|
case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
|
10799 |
|
|
default: narrow = FALSE; break;
|
10800 |
|
|
}
|
10801 |
|
|
}
|
10802 |
|
|
|
10803 |
|
|
if (narrow)
|
10804 |
|
|
{
|
10805 |
|
|
inst.instruction |= Rn;
|
10806 |
|
|
inst.instruction |= Rm << 3;
|
10807 |
|
|
inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
|
10808 |
|
|
}
|
10809 |
|
|
else
|
10810 |
|
|
{
|
10811 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
10812 |
|
|
inst.instruction |= Rn << r0off;
|
10813 |
|
|
encode_thumb32_shifted_operand (1);
|
10814 |
|
|
}
|
10815 |
|
|
}
|
10816 |
|
|
else
|
10817 |
|
|
switch (inst.instruction)
|
10818 |
|
|
{
|
10819 |
|
|
case T_MNEM_mov:
|
10820 |
|
|
inst.instruction = T_OPCODE_MOV_HR;
|
10821 |
|
|
inst.instruction |= (Rn & 0x8) << 4;
|
10822 |
|
|
inst.instruction |= (Rn & 0x7);
|
10823 |
|
|
inst.instruction |= Rm << 3;
|
10824 |
|
|
break;
|
10825 |
|
|
|
10826 |
|
|
case T_MNEM_movs:
|
10827 |
|
|
/* We know we have low registers at this point.
|
10828 |
|
|
Generate LSLS Rd, Rs, #0. */
|
10829 |
|
|
inst.instruction = T_OPCODE_LSL_I;
|
10830 |
|
|
inst.instruction |= Rn;
|
10831 |
|
|
inst.instruction |= Rm << 3;
|
10832 |
|
|
break;
|
10833 |
|
|
|
10834 |
|
|
case T_MNEM_cmp:
|
10835 |
|
|
if (low_regs)
|
10836 |
|
|
{
|
10837 |
|
|
inst.instruction = T_OPCODE_CMP_LR;
|
10838 |
|
|
inst.instruction |= Rn;
|
10839 |
|
|
inst.instruction |= Rm << 3;
|
10840 |
|
|
}
|
10841 |
|
|
else
|
10842 |
|
|
{
|
10843 |
|
|
inst.instruction = T_OPCODE_CMP_HR;
|
10844 |
|
|
inst.instruction |= (Rn & 0x8) << 4;
|
10845 |
|
|
inst.instruction |= (Rn & 0x7);
|
10846 |
|
|
inst.instruction |= Rm << 3;
|
10847 |
|
|
}
|
10848 |
|
|
break;
|
10849 |
|
|
}
|
10850 |
|
|
return;
|
10851 |
|
|
}
|
10852 |
|
|
|
10853 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
10854 |
|
|
|
10855 |
|
|
/* PR 10443: Do not silently ignore shifted operands. */
|
10856 |
|
|
constraint (inst.operands[1].shifted,
|
10857 |
|
|
_("shifts in CMP/MOV instructions are only supported in unified syntax"));
|
10858 |
|
|
|
10859 |
|
|
if (inst.operands[1].isreg)
|
10860 |
|
|
{
|
10861 |
|
|
if (Rn < 8 && Rm < 8)
|
10862 |
|
|
{
|
10863 |
|
|
/* A move of two lowregs is encoded as ADD Rd, Rs, #0
|
10864 |
|
|
since a MOV instruction produces unpredictable results. */
|
10865 |
|
|
if (inst.instruction == T_OPCODE_MOV_I8)
|
10866 |
|
|
inst.instruction = T_OPCODE_ADD_I3;
|
10867 |
|
|
else
|
10868 |
|
|
inst.instruction = T_OPCODE_CMP_LR;
|
10869 |
|
|
|
10870 |
|
|
inst.instruction |= Rn;
|
10871 |
|
|
inst.instruction |= Rm << 3;
|
10872 |
|
|
}
|
10873 |
|
|
else
|
10874 |
|
|
{
|
10875 |
|
|
if (inst.instruction == T_OPCODE_MOV_I8)
|
10876 |
|
|
inst.instruction = T_OPCODE_MOV_HR;
|
10877 |
|
|
else
|
10878 |
|
|
inst.instruction = T_OPCODE_CMP_HR;
|
10879 |
|
|
do_t_cpy ();
|
10880 |
|
|
}
|
10881 |
|
|
}
|
10882 |
|
|
else
|
10883 |
|
|
{
|
10884 |
|
|
constraint (Rn > 7,
|
10885 |
|
|
_("only lo regs allowed with immediate"));
|
10886 |
|
|
inst.instruction |= Rn << 8;
|
10887 |
|
|
inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
|
10888 |
|
|
}
|
10889 |
|
|
}
|
10890 |
|
|
|
10891 |
|
|
static void
|
10892 |
|
|
do_t_mov16 (void)
|
10893 |
|
|
{
|
10894 |
|
|
unsigned Rd;
|
10895 |
|
|
bfd_vma imm;
|
10896 |
|
|
bfd_boolean top;
|
10897 |
|
|
|
10898 |
|
|
top = (inst.instruction & 0x00800000) != 0;
|
10899 |
|
|
if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
|
10900 |
|
|
{
|
10901 |
|
|
constraint (top, _(":lower16: not allowed this instruction"));
|
10902 |
|
|
inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
|
10903 |
|
|
}
|
10904 |
|
|
else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
|
10905 |
|
|
{
|
10906 |
|
|
constraint (!top, _(":upper16: not allowed this instruction"));
|
10907 |
|
|
inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
|
10908 |
|
|
}
|
10909 |
|
|
|
10910 |
|
|
Rd = inst.operands[0].reg;
|
10911 |
|
|
reject_bad_reg (Rd);
|
10912 |
|
|
|
10913 |
|
|
inst.instruction |= Rd << 8;
|
10914 |
|
|
if (inst.reloc.type == BFD_RELOC_UNUSED)
|
10915 |
|
|
{
|
10916 |
|
|
imm = inst.reloc.exp.X_add_number;
|
10917 |
|
|
inst.instruction |= (imm & 0xf000) << 4;
|
10918 |
|
|
inst.instruction |= (imm & 0x0800) << 15;
|
10919 |
|
|
inst.instruction |= (imm & 0x0700) << 4;
|
10920 |
|
|
inst.instruction |= (imm & 0x00ff);
|
10921 |
|
|
}
|
10922 |
|
|
}
|
10923 |
|
|
|
10924 |
|
|
static void
|
10925 |
|
|
do_t_mvn_tst (void)
|
10926 |
|
|
{
|
10927 |
|
|
unsigned Rn, Rm;
|
10928 |
|
|
|
10929 |
|
|
Rn = inst.operands[0].reg;
|
10930 |
|
|
Rm = inst.operands[1].reg;
|
10931 |
|
|
|
10932 |
|
|
if (inst.instruction == T_MNEM_cmp
|
10933 |
|
|
|| inst.instruction == T_MNEM_cmn)
|
10934 |
|
|
constraint (Rn == REG_PC, BAD_PC);
|
10935 |
|
|
else
|
10936 |
|
|
reject_bad_reg (Rn);
|
10937 |
|
|
reject_bad_reg (Rm);
|
10938 |
|
|
|
10939 |
|
|
if (unified_syntax)
|
10940 |
|
|
{
|
10941 |
|
|
int r0off = (inst.instruction == T_MNEM_mvn
|
10942 |
|
|
|| inst.instruction == T_MNEM_mvns) ? 8 : 16;
|
10943 |
|
|
bfd_boolean narrow;
|
10944 |
|
|
|
10945 |
|
|
if (inst.size_req == 4
|
10946 |
|
|
|| inst.instruction > 0xffff
|
10947 |
|
|
|| inst.operands[1].shifted
|
10948 |
|
|
|| Rn > 7 || Rm > 7)
|
10949 |
|
|
narrow = FALSE;
|
10950 |
|
|
else if (inst.instruction == T_MNEM_cmn)
|
10951 |
|
|
narrow = TRUE;
|
10952 |
|
|
else if (THUMB_SETS_FLAGS (inst.instruction))
|
10953 |
|
|
narrow = !in_it_block ();
|
10954 |
|
|
else
|
10955 |
|
|
narrow = in_it_block ();
|
10956 |
|
|
|
10957 |
|
|
if (!inst.operands[1].isreg)
|
10958 |
|
|
{
|
10959 |
|
|
/* For an immediate, we always generate a 32-bit opcode;
|
10960 |
|
|
section relaxation will shrink it later if possible. */
|
10961 |
|
|
if (inst.instruction < 0xffff)
|
10962 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
10963 |
|
|
inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
|
10964 |
|
|
inst.instruction |= Rn << r0off;
|
10965 |
|
|
inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
|
10966 |
|
|
}
|
10967 |
|
|
else
|
10968 |
|
|
{
|
10969 |
|
|
/* See if we can do this with a 16-bit instruction. */
|
10970 |
|
|
if (narrow)
|
10971 |
|
|
{
|
10972 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
10973 |
|
|
inst.instruction |= Rn;
|
10974 |
|
|
inst.instruction |= Rm << 3;
|
10975 |
|
|
}
|
10976 |
|
|
else
|
10977 |
|
|
{
|
10978 |
|
|
constraint (inst.operands[1].shifted
|
10979 |
|
|
&& inst.operands[1].immisreg,
|
10980 |
|
|
_("shift must be constant"));
|
10981 |
|
|
if (inst.instruction < 0xffff)
|
10982 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
10983 |
|
|
inst.instruction |= Rn << r0off;
|
10984 |
|
|
encode_thumb32_shifted_operand (1);
|
10985 |
|
|
}
|
10986 |
|
|
}
|
10987 |
|
|
}
|
10988 |
|
|
else
|
10989 |
|
|
{
|
10990 |
|
|
constraint (inst.instruction > 0xffff
|
10991 |
|
|
|| inst.instruction == T_MNEM_mvns, BAD_THUMB32);
|
10992 |
|
|
constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
|
10993 |
|
|
_("unshifted register required"));
|
10994 |
|
|
constraint (Rn > 7 || Rm > 7,
|
10995 |
|
|
BAD_HIREG);
|
10996 |
|
|
|
10997 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
10998 |
|
|
inst.instruction |= Rn;
|
10999 |
|
|
inst.instruction |= Rm << 3;
|
11000 |
|
|
}
|
11001 |
|
|
}
|
11002 |
|
|
|
11003 |
|
|
static void
|
11004 |
|
|
do_t_mrs (void)
|
11005 |
|
|
{
|
11006 |
|
|
unsigned Rd;
|
11007 |
|
|
|
11008 |
|
|
if (do_vfp_nsyn_mrs () == SUCCESS)
|
11009 |
|
|
return;
|
11010 |
|
|
|
11011 |
|
|
Rd = inst.operands[0].reg;
|
11012 |
|
|
reject_bad_reg (Rd);
|
11013 |
|
|
inst.instruction |= Rd << 8;
|
11014 |
|
|
|
11015 |
|
|
if (inst.operands[1].isreg)
|
11016 |
|
|
{
|
11017 |
|
|
unsigned br = inst.operands[1].reg;
|
11018 |
|
|
if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
|
11019 |
|
|
as_bad (_("bad register for mrs"));
|
11020 |
|
|
|
11021 |
|
|
inst.instruction |= br & (0xf << 16);
|
11022 |
|
|
inst.instruction |= (br & 0x300) >> 4;
|
11023 |
|
|
inst.instruction |= (br & SPSR_BIT) >> 2;
|
11024 |
|
|
}
|
11025 |
|
|
else
|
11026 |
|
|
{
|
11027 |
|
|
int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
|
11028 |
|
|
|
11029 |
|
|
if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
|
11030 |
|
|
constraint (flags != 0, _("selected processor does not support "
|
11031 |
|
|
"requested special purpose register"));
|
11032 |
|
|
else
|
11033 |
|
|
/* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
|
11034 |
|
|
devices). */
|
11035 |
|
|
constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
|
11036 |
|
|
_("'APSR', 'CPSR' or 'SPSR' expected"));
|
11037 |
|
|
|
11038 |
|
|
inst.instruction |= (flags & SPSR_BIT) >> 2;
|
11039 |
|
|
inst.instruction |= inst.operands[1].imm & 0xff;
|
11040 |
|
|
inst.instruction |= 0xf0000;
|
11041 |
|
|
}
|
11042 |
|
|
}
|
11043 |
|
|
|
11044 |
|
|
static void
|
11045 |
|
|
do_t_msr (void)
|
11046 |
|
|
{
|
11047 |
|
|
int flags;
|
11048 |
|
|
unsigned Rn;
|
11049 |
|
|
|
11050 |
|
|
if (do_vfp_nsyn_msr () == SUCCESS)
|
11051 |
|
|
return;
|
11052 |
|
|
|
11053 |
|
|
constraint (!inst.operands[1].isreg,
|
11054 |
|
|
_("Thumb encoding does not support an immediate here"));
|
11055 |
|
|
|
11056 |
|
|
if (inst.operands[0].isreg)
|
11057 |
|
|
flags = (int)(inst.operands[0].reg);
|
11058 |
|
|
else
|
11059 |
|
|
flags = inst.operands[0].imm;
|
11060 |
|
|
|
11061 |
|
|
if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
|
11062 |
|
|
{
|
11063 |
|
|
int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
|
11064 |
|
|
|
11065 |
|
|
constraint ((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
|
11066 |
|
|
&& (bits & ~(PSR_s | PSR_f)) != 0)
|
11067 |
|
|
|| (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
|
11068 |
|
|
&& bits != PSR_f),
|
11069 |
|
|
_("selected processor does not support requested special "
|
11070 |
|
|
"purpose register"));
|
11071 |
|
|
}
|
11072 |
|
|
else
|
11073 |
|
|
constraint ((flags & 0xff) != 0, _("selected processor does not support "
|
11074 |
|
|
"requested special purpose register"));
|
11075 |
|
|
|
11076 |
|
|
Rn = inst.operands[1].reg;
|
11077 |
|
|
reject_bad_reg (Rn);
|
11078 |
|
|
|
11079 |
|
|
inst.instruction |= (flags & SPSR_BIT) >> 2;
|
11080 |
|
|
inst.instruction |= (flags & 0xf0000) >> 8;
|
11081 |
|
|
inst.instruction |= (flags & 0x300) >> 4;
|
11082 |
|
|
inst.instruction |= (flags & 0xff);
|
11083 |
|
|
inst.instruction |= Rn << 16;
|
11084 |
|
|
}
|
11085 |
|
|
|
11086 |
|
|
static void
|
11087 |
|
|
do_t_mul (void)
|
11088 |
|
|
{
|
11089 |
|
|
bfd_boolean narrow;
|
11090 |
|
|
unsigned Rd, Rn, Rm;
|
11091 |
|
|
|
11092 |
|
|
if (!inst.operands[2].present)
|
11093 |
|
|
inst.operands[2].reg = inst.operands[0].reg;
|
11094 |
|
|
|
11095 |
|
|
Rd = inst.operands[0].reg;
|
11096 |
|
|
Rn = inst.operands[1].reg;
|
11097 |
|
|
Rm = inst.operands[2].reg;
|
11098 |
|
|
|
11099 |
|
|
if (unified_syntax)
|
11100 |
|
|
{
|
11101 |
|
|
if (inst.size_req == 4
|
11102 |
|
|
|| (Rd != Rn
|
11103 |
|
|
&& Rd != Rm)
|
11104 |
|
|
|| Rn > 7
|
11105 |
|
|
|| Rm > 7)
|
11106 |
|
|
narrow = FALSE;
|
11107 |
|
|
else if (inst.instruction == T_MNEM_muls)
|
11108 |
|
|
narrow = !in_it_block ();
|
11109 |
|
|
else
|
11110 |
|
|
narrow = in_it_block ();
|
11111 |
|
|
}
|
11112 |
|
|
else
|
11113 |
|
|
{
|
11114 |
|
|
constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
|
11115 |
|
|
constraint (Rn > 7 || Rm > 7,
|
11116 |
|
|
BAD_HIREG);
|
11117 |
|
|
narrow = TRUE;
|
11118 |
|
|
}
|
11119 |
|
|
|
11120 |
|
|
if (narrow)
|
11121 |
|
|
{
|
11122 |
|
|
/* 16-bit MULS/Conditional MUL. */
|
11123 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
11124 |
|
|
inst.instruction |= Rd;
|
11125 |
|
|
|
11126 |
|
|
if (Rd == Rn)
|
11127 |
|
|
inst.instruction |= Rm << 3;
|
11128 |
|
|
else if (Rd == Rm)
|
11129 |
|
|
inst.instruction |= Rn << 3;
|
11130 |
|
|
else
|
11131 |
|
|
constraint (1, _("dest must overlap one source register"));
|
11132 |
|
|
}
|
11133 |
|
|
else
|
11134 |
|
|
{
|
11135 |
|
|
constraint (inst.instruction != T_MNEM_mul,
|
11136 |
|
|
_("Thumb-2 MUL must not set flags"));
|
11137 |
|
|
/* 32-bit MUL. */
|
11138 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
11139 |
|
|
inst.instruction |= Rd << 8;
|
11140 |
|
|
inst.instruction |= Rn << 16;
|
11141 |
|
|
inst.instruction |= Rm << 0;
|
11142 |
|
|
|
11143 |
|
|
reject_bad_reg (Rd);
|
11144 |
|
|
reject_bad_reg (Rn);
|
11145 |
|
|
reject_bad_reg (Rm);
|
11146 |
|
|
}
|
11147 |
|
|
}
|
11148 |
|
|
|
11149 |
|
|
static void
|
11150 |
|
|
do_t_mull (void)
|
11151 |
|
|
{
|
11152 |
|
|
unsigned RdLo, RdHi, Rn, Rm;
|
11153 |
|
|
|
11154 |
|
|
RdLo = inst.operands[0].reg;
|
11155 |
|
|
RdHi = inst.operands[1].reg;
|
11156 |
|
|
Rn = inst.operands[2].reg;
|
11157 |
|
|
Rm = inst.operands[3].reg;
|
11158 |
|
|
|
11159 |
|
|
reject_bad_reg (RdLo);
|
11160 |
|
|
reject_bad_reg (RdHi);
|
11161 |
|
|
reject_bad_reg (Rn);
|
11162 |
|
|
reject_bad_reg (Rm);
|
11163 |
|
|
|
11164 |
|
|
inst.instruction |= RdLo << 12;
|
11165 |
|
|
inst.instruction |= RdHi << 8;
|
11166 |
|
|
inst.instruction |= Rn << 16;
|
11167 |
|
|
inst.instruction |= Rm;
|
11168 |
|
|
|
11169 |
|
|
if (RdLo == RdHi)
|
11170 |
|
|
as_tsktsk (_("rdhi and rdlo must be different"));
|
11171 |
|
|
}
|
11172 |
|
|
|
11173 |
|
|
static void
|
11174 |
|
|
do_t_nop (void)
|
11175 |
|
|
{
|
11176 |
|
|
set_it_insn_type (NEUTRAL_IT_INSN);
|
11177 |
|
|
|
11178 |
|
|
if (unified_syntax)
|
11179 |
|
|
{
|
11180 |
|
|
if (inst.size_req == 4 || inst.operands[0].imm > 15)
|
11181 |
|
|
{
|
11182 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
11183 |
|
|
inst.instruction |= inst.operands[0].imm;
|
11184 |
|
|
}
|
11185 |
|
|
else
|
11186 |
|
|
{
|
11187 |
|
|
/* PR9722: Check for Thumb2 availability before
|
11188 |
|
|
generating a thumb2 nop instruction. */
|
11189 |
|
|
if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
|
11190 |
|
|
{
|
11191 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
11192 |
|
|
inst.instruction |= inst.operands[0].imm << 4;
|
11193 |
|
|
}
|
11194 |
|
|
else
|
11195 |
|
|
inst.instruction = 0x46c0;
|
11196 |
|
|
}
|
11197 |
|
|
}
|
11198 |
|
|
else
|
11199 |
|
|
{
|
11200 |
|
|
constraint (inst.operands[0].present,
|
11201 |
|
|
_("Thumb does not support NOP with hints"));
|
11202 |
|
|
inst.instruction = 0x46c0;
|
11203 |
|
|
}
|
11204 |
|
|
}
|
11205 |
|
|
|
11206 |
|
|
static void
|
11207 |
|
|
do_t_neg (void)
|
11208 |
|
|
{
|
11209 |
|
|
if (unified_syntax)
|
11210 |
|
|
{
|
11211 |
|
|
bfd_boolean narrow;
|
11212 |
|
|
|
11213 |
|
|
if (THUMB_SETS_FLAGS (inst.instruction))
|
11214 |
|
|
narrow = !in_it_block ();
|
11215 |
|
|
else
|
11216 |
|
|
narrow = in_it_block ();
|
11217 |
|
|
if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
|
11218 |
|
|
narrow = FALSE;
|
11219 |
|
|
if (inst.size_req == 4)
|
11220 |
|
|
narrow = FALSE;
|
11221 |
|
|
|
11222 |
|
|
if (!narrow)
|
11223 |
|
|
{
|
11224 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
11225 |
|
|
inst.instruction |= inst.operands[0].reg << 8;
|
11226 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
11227 |
|
|
}
|
11228 |
|
|
else
|
11229 |
|
|
{
|
11230 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
11231 |
|
|
inst.instruction |= inst.operands[0].reg;
|
11232 |
|
|
inst.instruction |= inst.operands[1].reg << 3;
|
11233 |
|
|
}
|
11234 |
|
|
}
|
11235 |
|
|
else
|
11236 |
|
|
{
|
11237 |
|
|
constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
|
11238 |
|
|
BAD_HIREG);
|
11239 |
|
|
constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
|
11240 |
|
|
|
11241 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
11242 |
|
|
inst.instruction |= inst.operands[0].reg;
|
11243 |
|
|
inst.instruction |= inst.operands[1].reg << 3;
|
11244 |
|
|
}
|
11245 |
|
|
}
|
11246 |
|
|
|
11247 |
|
|
static void
|
11248 |
|
|
do_t_orn (void)
|
11249 |
|
|
{
|
11250 |
|
|
unsigned Rd, Rn;
|
11251 |
|
|
|
11252 |
|
|
Rd = inst.operands[0].reg;
|
11253 |
|
|
Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
|
11254 |
|
|
|
11255 |
|
|
reject_bad_reg (Rd);
|
11256 |
|
|
/* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
|
11257 |
|
|
reject_bad_reg (Rn);
|
11258 |
|
|
|
11259 |
|
|
inst.instruction |= Rd << 8;
|
11260 |
|
|
inst.instruction |= Rn << 16;
|
11261 |
|
|
|
11262 |
|
|
if (!inst.operands[2].isreg)
|
11263 |
|
|
{
|
11264 |
|
|
inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
|
11265 |
|
|
inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
|
11266 |
|
|
}
|
11267 |
|
|
else
|
11268 |
|
|
{
|
11269 |
|
|
unsigned Rm;
|
11270 |
|
|
|
11271 |
|
|
Rm = inst.operands[2].reg;
|
11272 |
|
|
reject_bad_reg (Rm);
|
11273 |
|
|
|
11274 |
|
|
constraint (inst.operands[2].shifted
|
11275 |
|
|
&& inst.operands[2].immisreg,
|
11276 |
|
|
_("shift must be constant"));
|
11277 |
|
|
encode_thumb32_shifted_operand (2);
|
11278 |
|
|
}
|
11279 |
|
|
}
|
11280 |
|
|
|
11281 |
|
|
static void
|
11282 |
|
|
do_t_pkhbt (void)
|
11283 |
|
|
{
|
11284 |
|
|
unsigned Rd, Rn, Rm;
|
11285 |
|
|
|
11286 |
|
|
Rd = inst.operands[0].reg;
|
11287 |
|
|
Rn = inst.operands[1].reg;
|
11288 |
|
|
Rm = inst.operands[2].reg;
|
11289 |
|
|
|
11290 |
|
|
reject_bad_reg (Rd);
|
11291 |
|
|
reject_bad_reg (Rn);
|
11292 |
|
|
reject_bad_reg (Rm);
|
11293 |
|
|
|
11294 |
|
|
inst.instruction |= Rd << 8;
|
11295 |
|
|
inst.instruction |= Rn << 16;
|
11296 |
|
|
inst.instruction |= Rm;
|
11297 |
|
|
if (inst.operands[3].present)
|
11298 |
|
|
{
|
11299 |
|
|
unsigned int val = inst.reloc.exp.X_add_number;
|
11300 |
|
|
constraint (inst.reloc.exp.X_op != O_constant,
|
11301 |
|
|
_("expression too complex"));
|
11302 |
|
|
inst.instruction |= (val & 0x1c) << 10;
|
11303 |
|
|
inst.instruction |= (val & 0x03) << 6;
|
11304 |
|
|
}
|
11305 |
|
|
}
|
11306 |
|
|
|
11307 |
|
|
static void
|
11308 |
|
|
do_t_pkhtb (void)
|
11309 |
|
|
{
|
11310 |
|
|
if (!inst.operands[3].present)
|
11311 |
|
|
{
|
11312 |
|
|
unsigned Rtmp;
|
11313 |
|
|
|
11314 |
|
|
inst.instruction &= ~0x00000020;
|
11315 |
|
|
|
11316 |
|
|
/* PR 10168. Swap the Rm and Rn registers. */
|
11317 |
|
|
Rtmp = inst.operands[1].reg;
|
11318 |
|
|
inst.operands[1].reg = inst.operands[2].reg;
|
11319 |
|
|
inst.operands[2].reg = Rtmp;
|
11320 |
|
|
}
|
11321 |
|
|
do_t_pkhbt ();
|
11322 |
|
|
}
|
11323 |
|
|
|
11324 |
|
|
static void
|
11325 |
|
|
do_t_pld (void)
|
11326 |
|
|
{
|
11327 |
|
|
if (inst.operands[0].immisreg)
|
11328 |
|
|
reject_bad_reg (inst.operands[0].imm);
|
11329 |
|
|
|
11330 |
|
|
encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
|
11331 |
|
|
}
|
11332 |
|
|
|
11333 |
|
|
static void
|
11334 |
|
|
do_t_push_pop (void)
|
11335 |
|
|
{
|
11336 |
|
|
unsigned mask;
|
11337 |
|
|
|
11338 |
|
|
constraint (inst.operands[0].writeback,
|
11339 |
|
|
_("push/pop do not support {reglist}^"));
|
11340 |
|
|
constraint (inst.reloc.type != BFD_RELOC_UNUSED,
|
11341 |
|
|
_("expression too complex"));
|
11342 |
|
|
|
11343 |
|
|
mask = inst.operands[0].imm;
|
11344 |
|
|
if ((mask & ~0xff) == 0)
|
11345 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction) | mask;
|
11346 |
|
|
else if ((inst.instruction == T_MNEM_push
|
11347 |
|
|
&& (mask & ~0xff) == 1 << REG_LR)
|
11348 |
|
|
|| (inst.instruction == T_MNEM_pop
|
11349 |
|
|
&& (mask & ~0xff) == 1 << REG_PC))
|
11350 |
|
|
{
|
11351 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
11352 |
|
|
inst.instruction |= THUMB_PP_PC_LR;
|
11353 |
|
|
inst.instruction |= mask & 0xff;
|
11354 |
|
|
}
|
11355 |
|
|
else if (unified_syntax)
|
11356 |
|
|
{
|
11357 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
11358 |
|
|
encode_thumb2_ldmstm (13, mask, TRUE);
|
11359 |
|
|
}
|
11360 |
|
|
else
|
11361 |
|
|
{
|
11362 |
|
|
inst.error = _("invalid register list to push/pop instruction");
|
11363 |
|
|
return;
|
11364 |
|
|
}
|
11365 |
|
|
}
|
11366 |
|
|
|
11367 |
|
|
static void
|
11368 |
|
|
do_t_rbit (void)
|
11369 |
|
|
{
|
11370 |
|
|
unsigned Rd, Rm;
|
11371 |
|
|
|
11372 |
|
|
Rd = inst.operands[0].reg;
|
11373 |
|
|
Rm = inst.operands[1].reg;
|
11374 |
|
|
|
11375 |
|
|
reject_bad_reg (Rd);
|
11376 |
|
|
reject_bad_reg (Rm);
|
11377 |
|
|
|
11378 |
|
|
inst.instruction |= Rd << 8;
|
11379 |
|
|
inst.instruction |= Rm << 16;
|
11380 |
|
|
inst.instruction |= Rm;
|
11381 |
|
|
}
|
11382 |
|
|
|
11383 |
|
|
static void
|
11384 |
|
|
do_t_rev (void)
|
11385 |
|
|
{
|
11386 |
|
|
unsigned Rd, Rm;
|
11387 |
|
|
|
11388 |
|
|
Rd = inst.operands[0].reg;
|
11389 |
|
|
Rm = inst.operands[1].reg;
|
11390 |
|
|
|
11391 |
|
|
reject_bad_reg (Rd);
|
11392 |
|
|
reject_bad_reg (Rm);
|
11393 |
|
|
|
11394 |
|
|
if (Rd <= 7 && Rm <= 7
|
11395 |
|
|
&& inst.size_req != 4)
|
11396 |
|
|
{
|
11397 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
11398 |
|
|
inst.instruction |= Rd;
|
11399 |
|
|
inst.instruction |= Rm << 3;
|
11400 |
|
|
}
|
11401 |
|
|
else if (unified_syntax)
|
11402 |
|
|
{
|
11403 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
11404 |
|
|
inst.instruction |= Rd << 8;
|
11405 |
|
|
inst.instruction |= Rm << 16;
|
11406 |
|
|
inst.instruction |= Rm;
|
11407 |
|
|
}
|
11408 |
|
|
else
|
11409 |
|
|
inst.error = BAD_HIREG;
|
11410 |
|
|
}
|
11411 |
|
|
|
11412 |
|
|
static void
|
11413 |
|
|
do_t_rrx (void)
|
11414 |
|
|
{
|
11415 |
|
|
unsigned Rd, Rm;
|
11416 |
|
|
|
11417 |
|
|
Rd = inst.operands[0].reg;
|
11418 |
|
|
Rm = inst.operands[1].reg;
|
11419 |
|
|
|
11420 |
|
|
reject_bad_reg (Rd);
|
11421 |
|
|
reject_bad_reg (Rm);
|
11422 |
|
|
|
11423 |
|
|
inst.instruction |= Rd << 8;
|
11424 |
|
|
inst.instruction |= Rm;
|
11425 |
|
|
}
|
11426 |
|
|
|
11427 |
|
|
static void
|
11428 |
|
|
do_t_rsb (void)
|
11429 |
|
|
{
|
11430 |
|
|
unsigned Rd, Rs;
|
11431 |
|
|
|
11432 |
|
|
Rd = inst.operands[0].reg;
|
11433 |
|
|
Rs = (inst.operands[1].present
|
11434 |
|
|
? inst.operands[1].reg /* Rd, Rs, foo */
|
11435 |
|
|
: inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
|
11436 |
|
|
|
11437 |
|
|
reject_bad_reg (Rd);
|
11438 |
|
|
reject_bad_reg (Rs);
|
11439 |
|
|
if (inst.operands[2].isreg)
|
11440 |
|
|
reject_bad_reg (inst.operands[2].reg);
|
11441 |
|
|
|
11442 |
|
|
inst.instruction |= Rd << 8;
|
11443 |
|
|
inst.instruction |= Rs << 16;
|
11444 |
|
|
if (!inst.operands[2].isreg)
|
11445 |
|
|
{
|
11446 |
|
|
bfd_boolean narrow;
|
11447 |
|
|
|
11448 |
|
|
if ((inst.instruction & 0x00100000) != 0)
|
11449 |
|
|
narrow = !in_it_block ();
|
11450 |
|
|
else
|
11451 |
|
|
narrow = in_it_block ();
|
11452 |
|
|
|
11453 |
|
|
if (Rd > 7 || Rs > 7)
|
11454 |
|
|
narrow = FALSE;
|
11455 |
|
|
|
11456 |
|
|
if (inst.size_req == 4 || !unified_syntax)
|
11457 |
|
|
narrow = FALSE;
|
11458 |
|
|
|
11459 |
|
|
if (inst.reloc.exp.X_op != O_constant
|
11460 |
|
|
|| inst.reloc.exp.X_add_number != 0)
|
11461 |
|
|
narrow = FALSE;
|
11462 |
|
|
|
11463 |
|
|
/* Turn rsb #0 into 16-bit neg. We should probably do this via
|
11464 |
|
|
relaxation, but it doesn't seem worth the hassle. */
|
11465 |
|
|
if (narrow)
|
11466 |
|
|
{
|
11467 |
|
|
inst.reloc.type = BFD_RELOC_UNUSED;
|
11468 |
|
|
inst.instruction = THUMB_OP16 (T_MNEM_negs);
|
11469 |
|
|
inst.instruction |= Rs << 3;
|
11470 |
|
|
inst.instruction |= Rd;
|
11471 |
|
|
}
|
11472 |
|
|
else
|
11473 |
|
|
{
|
11474 |
|
|
inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
|
11475 |
|
|
inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
|
11476 |
|
|
}
|
11477 |
|
|
}
|
11478 |
|
|
else
|
11479 |
|
|
encode_thumb32_shifted_operand (2);
|
11480 |
|
|
}
|
11481 |
|
|
|
11482 |
|
|
static void
|
11483 |
|
|
do_t_setend (void)
|
11484 |
|
|
{
|
11485 |
|
|
set_it_insn_type (OUTSIDE_IT_INSN);
|
11486 |
|
|
if (inst.operands[0].imm)
|
11487 |
|
|
inst.instruction |= 0x8;
|
11488 |
|
|
}
|
11489 |
|
|
|
11490 |
|
|
static void
|
11491 |
|
|
do_t_shift (void)
|
11492 |
|
|
{
|
11493 |
|
|
if (!inst.operands[1].present)
|
11494 |
|
|
inst.operands[1].reg = inst.operands[0].reg;
|
11495 |
|
|
|
11496 |
|
|
if (unified_syntax)
|
11497 |
|
|
{
|
11498 |
|
|
bfd_boolean narrow;
|
11499 |
|
|
int shift_kind;
|
11500 |
|
|
|
11501 |
|
|
switch (inst.instruction)
|
11502 |
|
|
{
|
11503 |
|
|
case T_MNEM_asr:
|
11504 |
|
|
case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
|
11505 |
|
|
case T_MNEM_lsl:
|
11506 |
|
|
case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
|
11507 |
|
|
case T_MNEM_lsr:
|
11508 |
|
|
case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
|
11509 |
|
|
case T_MNEM_ror:
|
11510 |
|
|
case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
|
11511 |
|
|
default: abort ();
|
11512 |
|
|
}
|
11513 |
|
|
|
11514 |
|
|
if (THUMB_SETS_FLAGS (inst.instruction))
|
11515 |
|
|
narrow = !in_it_block ();
|
11516 |
|
|
else
|
11517 |
|
|
narrow = in_it_block ();
|
11518 |
|
|
if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
|
11519 |
|
|
narrow = FALSE;
|
11520 |
|
|
if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
|
11521 |
|
|
narrow = FALSE;
|
11522 |
|
|
if (inst.operands[2].isreg
|
11523 |
|
|
&& (inst.operands[1].reg != inst.operands[0].reg
|
11524 |
|
|
|| inst.operands[2].reg > 7))
|
11525 |
|
|
narrow = FALSE;
|
11526 |
|
|
if (inst.size_req == 4)
|
11527 |
|
|
narrow = FALSE;
|
11528 |
|
|
|
11529 |
|
|
reject_bad_reg (inst.operands[0].reg);
|
11530 |
|
|
reject_bad_reg (inst.operands[1].reg);
|
11531 |
|
|
|
11532 |
|
|
if (!narrow)
|
11533 |
|
|
{
|
11534 |
|
|
if (inst.operands[2].isreg)
|
11535 |
|
|
{
|
11536 |
|
|
reject_bad_reg (inst.operands[2].reg);
|
11537 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
11538 |
|
|
inst.instruction |= inst.operands[0].reg << 8;
|
11539 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
11540 |
|
|
inst.instruction |= inst.operands[2].reg;
|
11541 |
148 |
khays |
|
11542 |
|
|
/* PR 12854: Error on extraneous shifts. */
|
11543 |
|
|
constraint (inst.operands[2].shifted,
|
11544 |
|
|
_("extraneous shift as part of operand to shift insn"));
|
11545 |
16 |
khays |
}
|
11546 |
|
|
else
|
11547 |
|
|
{
|
11548 |
|
|
inst.operands[1].shifted = 1;
|
11549 |
|
|
inst.operands[1].shift_kind = shift_kind;
|
11550 |
|
|
inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
|
11551 |
|
|
? T_MNEM_movs : T_MNEM_mov);
|
11552 |
|
|
inst.instruction |= inst.operands[0].reg << 8;
|
11553 |
|
|
encode_thumb32_shifted_operand (1);
|
11554 |
|
|
/* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
|
11555 |
|
|
inst.reloc.type = BFD_RELOC_UNUSED;
|
11556 |
|
|
}
|
11557 |
|
|
}
|
11558 |
|
|
else
|
11559 |
|
|
{
|
11560 |
|
|
if (inst.operands[2].isreg)
|
11561 |
|
|
{
|
11562 |
|
|
switch (shift_kind)
|
11563 |
|
|
{
|
11564 |
|
|
case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
|
11565 |
|
|
case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
|
11566 |
|
|
case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
|
11567 |
|
|
case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
|
11568 |
|
|
default: abort ();
|
11569 |
|
|
}
|
11570 |
|
|
|
11571 |
|
|
inst.instruction |= inst.operands[0].reg;
|
11572 |
|
|
inst.instruction |= inst.operands[2].reg << 3;
|
11573 |
148 |
khays |
|
11574 |
|
|
/* PR 12854: Error on extraneous shifts. */
|
11575 |
|
|
constraint (inst.operands[2].shifted,
|
11576 |
|
|
_("extraneous shift as part of operand to shift insn"));
|
11577 |
16 |
khays |
}
|
11578 |
|
|
else
|
11579 |
|
|
{
|
11580 |
|
|
switch (shift_kind)
|
11581 |
|
|
{
|
11582 |
|
|
case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
|
11583 |
|
|
case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
|
11584 |
|
|
case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
|
11585 |
|
|
default: abort ();
|
11586 |
|
|
}
|
11587 |
|
|
inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
|
11588 |
|
|
inst.instruction |= inst.operands[0].reg;
|
11589 |
|
|
inst.instruction |= inst.operands[1].reg << 3;
|
11590 |
|
|
}
|
11591 |
|
|
}
|
11592 |
|
|
}
|
11593 |
|
|
else
|
11594 |
|
|
{
|
11595 |
|
|
constraint (inst.operands[0].reg > 7
|
11596 |
|
|
|| inst.operands[1].reg > 7, BAD_HIREG);
|
11597 |
|
|
constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
|
11598 |
|
|
|
11599 |
|
|
if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
|
11600 |
|
|
{
|
11601 |
|
|
constraint (inst.operands[2].reg > 7, BAD_HIREG);
|
11602 |
|
|
constraint (inst.operands[0].reg != inst.operands[1].reg,
|
11603 |
|
|
_("source1 and dest must be same register"));
|
11604 |
|
|
|
11605 |
|
|
switch (inst.instruction)
|
11606 |
|
|
{
|
11607 |
|
|
case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
|
11608 |
|
|
case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
|
11609 |
|
|
case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
|
11610 |
|
|
case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
|
11611 |
|
|
default: abort ();
|
11612 |
|
|
}
|
11613 |
|
|
|
11614 |
|
|
inst.instruction |= inst.operands[0].reg;
|
11615 |
|
|
inst.instruction |= inst.operands[2].reg << 3;
|
11616 |
148 |
khays |
|
11617 |
|
|
/* PR 12854: Error on extraneous shifts. */
|
11618 |
|
|
constraint (inst.operands[2].shifted,
|
11619 |
|
|
_("extraneous shift as part of operand to shift insn"));
|
11620 |
16 |
khays |
}
|
11621 |
|
|
else
|
11622 |
|
|
{
|
11623 |
|
|
switch (inst.instruction)
|
11624 |
|
|
{
|
11625 |
|
|
case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
|
11626 |
|
|
case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
|
11627 |
|
|
case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
|
11628 |
|
|
case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
|
11629 |
|
|
default: abort ();
|
11630 |
|
|
}
|
11631 |
|
|
inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
|
11632 |
|
|
inst.instruction |= inst.operands[0].reg;
|
11633 |
|
|
inst.instruction |= inst.operands[1].reg << 3;
|
11634 |
|
|
}
|
11635 |
|
|
}
|
11636 |
|
|
}
|
11637 |
|
|
|
11638 |
|
|
static void
|
11639 |
|
|
do_t_simd (void)
|
11640 |
|
|
{
|
11641 |
|
|
unsigned Rd, Rn, Rm;
|
11642 |
|
|
|
11643 |
|
|
Rd = inst.operands[0].reg;
|
11644 |
|
|
Rn = inst.operands[1].reg;
|
11645 |
|
|
Rm = inst.operands[2].reg;
|
11646 |
|
|
|
11647 |
|
|
reject_bad_reg (Rd);
|
11648 |
|
|
reject_bad_reg (Rn);
|
11649 |
|
|
reject_bad_reg (Rm);
|
11650 |
|
|
|
11651 |
|
|
inst.instruction |= Rd << 8;
|
11652 |
|
|
inst.instruction |= Rn << 16;
|
11653 |
|
|
inst.instruction |= Rm;
|
11654 |
|
|
}
|
11655 |
|
|
|
11656 |
|
|
static void
|
11657 |
|
|
do_t_simd2 (void)
|
11658 |
|
|
{
|
11659 |
|
|
unsigned Rd, Rn, Rm;
|
11660 |
|
|
|
11661 |
|
|
Rd = inst.operands[0].reg;
|
11662 |
|
|
Rm = inst.operands[1].reg;
|
11663 |
|
|
Rn = inst.operands[2].reg;
|
11664 |
|
|
|
11665 |
|
|
reject_bad_reg (Rd);
|
11666 |
|
|
reject_bad_reg (Rn);
|
11667 |
|
|
reject_bad_reg (Rm);
|
11668 |
|
|
|
11669 |
|
|
inst.instruction |= Rd << 8;
|
11670 |
|
|
inst.instruction |= Rn << 16;
|
11671 |
|
|
inst.instruction |= Rm;
|
11672 |
|
|
}
|
11673 |
|
|
|
11674 |
|
|
static void
|
11675 |
|
|
do_t_smc (void)
|
11676 |
|
|
{
|
11677 |
|
|
unsigned int value = inst.reloc.exp.X_add_number;
|
11678 |
|
|
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
|
11679 |
|
|
_("SMC is not permitted on this architecture"));
|
11680 |
|
|
constraint (inst.reloc.exp.X_op != O_constant,
|
11681 |
|
|
_("expression too complex"));
|
11682 |
|
|
inst.reloc.type = BFD_RELOC_UNUSED;
|
11683 |
|
|
inst.instruction |= (value & 0xf000) >> 12;
|
11684 |
|
|
inst.instruction |= (value & 0x0ff0);
|
11685 |
|
|
inst.instruction |= (value & 0x000f) << 16;
|
11686 |
|
|
}
|
11687 |
|
|
|
11688 |
|
|
static void
|
11689 |
|
|
do_t_hvc (void)
|
11690 |
|
|
{
|
11691 |
|
|
unsigned int value = inst.reloc.exp.X_add_number;
|
11692 |
|
|
|
11693 |
|
|
inst.reloc.type = BFD_RELOC_UNUSED;
|
11694 |
|
|
inst.instruction |= (value & 0x0fff);
|
11695 |
|
|
inst.instruction |= (value & 0xf000) << 4;
|
11696 |
|
|
}
|
11697 |
|
|
|
11698 |
|
|
static void
|
11699 |
|
|
do_t_ssat_usat (int bias)
|
11700 |
|
|
{
|
11701 |
|
|
unsigned Rd, Rn;
|
11702 |
|
|
|
11703 |
|
|
Rd = inst.operands[0].reg;
|
11704 |
|
|
Rn = inst.operands[2].reg;
|
11705 |
|
|
|
11706 |
|
|
reject_bad_reg (Rd);
|
11707 |
|
|
reject_bad_reg (Rn);
|
11708 |
|
|
|
11709 |
|
|
inst.instruction |= Rd << 8;
|
11710 |
|
|
inst.instruction |= inst.operands[1].imm - bias;
|
11711 |
|
|
inst.instruction |= Rn << 16;
|
11712 |
|
|
|
11713 |
|
|
if (inst.operands[3].present)
|
11714 |
|
|
{
|
11715 |
|
|
offsetT shift_amount = inst.reloc.exp.X_add_number;
|
11716 |
|
|
|
11717 |
|
|
inst.reloc.type = BFD_RELOC_UNUSED;
|
11718 |
|
|
|
11719 |
|
|
constraint (inst.reloc.exp.X_op != O_constant,
|
11720 |
|
|
_("expression too complex"));
|
11721 |
|
|
|
11722 |
|
|
if (shift_amount != 0)
|
11723 |
|
|
{
|
11724 |
|
|
constraint (shift_amount > 31,
|
11725 |
|
|
_("shift expression is too large"));
|
11726 |
|
|
|
11727 |
|
|
if (inst.operands[3].shift_kind == SHIFT_ASR)
|
11728 |
|
|
inst.instruction |= 0x00200000; /* sh bit. */
|
11729 |
|
|
|
11730 |
|
|
inst.instruction |= (shift_amount & 0x1c) << 10;
|
11731 |
|
|
inst.instruction |= (shift_amount & 0x03) << 6;
|
11732 |
|
|
}
|
11733 |
|
|
}
|
11734 |
|
|
}
|
11735 |
|
|
|
11736 |
|
|
static void
|
11737 |
|
|
do_t_ssat (void)
|
11738 |
|
|
{
|
11739 |
|
|
do_t_ssat_usat (1);
|
11740 |
|
|
}
|
11741 |
|
|
|
11742 |
|
|
static void
|
11743 |
|
|
do_t_ssat16 (void)
|
11744 |
|
|
{
|
11745 |
|
|
unsigned Rd, Rn;
|
11746 |
|
|
|
11747 |
|
|
Rd = inst.operands[0].reg;
|
11748 |
|
|
Rn = inst.operands[2].reg;
|
11749 |
|
|
|
11750 |
|
|
reject_bad_reg (Rd);
|
11751 |
|
|
reject_bad_reg (Rn);
|
11752 |
|
|
|
11753 |
|
|
inst.instruction |= Rd << 8;
|
11754 |
|
|
inst.instruction |= inst.operands[1].imm - 1;
|
11755 |
|
|
inst.instruction |= Rn << 16;
|
11756 |
|
|
}
|
11757 |
|
|
|
11758 |
|
|
static void
|
11759 |
|
|
do_t_strex (void)
|
11760 |
|
|
{
|
11761 |
|
|
constraint (!inst.operands[2].isreg || !inst.operands[2].preind
|
11762 |
|
|
|| inst.operands[2].postind || inst.operands[2].writeback
|
11763 |
|
|
|| inst.operands[2].immisreg || inst.operands[2].shifted
|
11764 |
|
|
|| inst.operands[2].negative,
|
11765 |
|
|
BAD_ADDR_MODE);
|
11766 |
|
|
|
11767 |
|
|
constraint (inst.operands[2].reg == REG_PC, BAD_PC);
|
11768 |
|
|
|
11769 |
|
|
inst.instruction |= inst.operands[0].reg << 8;
|
11770 |
|
|
inst.instruction |= inst.operands[1].reg << 12;
|
11771 |
|
|
inst.instruction |= inst.operands[2].reg << 16;
|
11772 |
|
|
inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
|
11773 |
|
|
}
|
11774 |
|
|
|
11775 |
|
|
static void
|
11776 |
|
|
do_t_strexd (void)
|
11777 |
|
|
{
|
11778 |
|
|
if (!inst.operands[2].present)
|
11779 |
|
|
inst.operands[2].reg = inst.operands[1].reg + 1;
|
11780 |
|
|
|
11781 |
|
|
constraint (inst.operands[0].reg == inst.operands[1].reg
|
11782 |
|
|
|| inst.operands[0].reg == inst.operands[2].reg
|
11783 |
|
|
|| inst.operands[0].reg == inst.operands[3].reg,
|
11784 |
|
|
BAD_OVERLAP);
|
11785 |
|
|
|
11786 |
|
|
inst.instruction |= inst.operands[0].reg;
|
11787 |
|
|
inst.instruction |= inst.operands[1].reg << 12;
|
11788 |
|
|
inst.instruction |= inst.operands[2].reg << 8;
|
11789 |
|
|
inst.instruction |= inst.operands[3].reg << 16;
|
11790 |
|
|
}
|
11791 |
|
|
|
11792 |
|
|
static void
|
11793 |
|
|
do_t_sxtah (void)
|
11794 |
|
|
{
|
11795 |
|
|
unsigned Rd, Rn, Rm;
|
11796 |
|
|
|
11797 |
|
|
Rd = inst.operands[0].reg;
|
11798 |
|
|
Rn = inst.operands[1].reg;
|
11799 |
|
|
Rm = inst.operands[2].reg;
|
11800 |
|
|
|
11801 |
|
|
reject_bad_reg (Rd);
|
11802 |
|
|
reject_bad_reg (Rn);
|
11803 |
|
|
reject_bad_reg (Rm);
|
11804 |
|
|
|
11805 |
|
|
inst.instruction |= Rd << 8;
|
11806 |
|
|
inst.instruction |= Rn << 16;
|
11807 |
|
|
inst.instruction |= Rm;
|
11808 |
|
|
inst.instruction |= inst.operands[3].imm << 4;
|
11809 |
|
|
}
|
11810 |
|
|
|
11811 |
|
|
static void
|
11812 |
|
|
do_t_sxth (void)
|
11813 |
|
|
{
|
11814 |
|
|
unsigned Rd, Rm;
|
11815 |
|
|
|
11816 |
|
|
Rd = inst.operands[0].reg;
|
11817 |
|
|
Rm = inst.operands[1].reg;
|
11818 |
|
|
|
11819 |
|
|
reject_bad_reg (Rd);
|
11820 |
|
|
reject_bad_reg (Rm);
|
11821 |
|
|
|
11822 |
|
|
if (inst.instruction <= 0xffff
|
11823 |
|
|
&& inst.size_req != 4
|
11824 |
|
|
&& Rd <= 7 && Rm <= 7
|
11825 |
|
|
&& (!inst.operands[2].present || inst.operands[2].imm == 0))
|
11826 |
|
|
{
|
11827 |
|
|
inst.instruction = THUMB_OP16 (inst.instruction);
|
11828 |
|
|
inst.instruction |= Rd;
|
11829 |
|
|
inst.instruction |= Rm << 3;
|
11830 |
|
|
}
|
11831 |
|
|
else if (unified_syntax)
|
11832 |
|
|
{
|
11833 |
|
|
if (inst.instruction <= 0xffff)
|
11834 |
|
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
11835 |
|
|
inst.instruction |= Rd << 8;
|
11836 |
|
|
inst.instruction |= Rm;
|
11837 |
|
|
inst.instruction |= inst.operands[2].imm << 4;
|
11838 |
|
|
}
|
11839 |
|
|
else
|
11840 |
|
|
{
|
11841 |
|
|
constraint (inst.operands[2].present && inst.operands[2].imm != 0,
|
11842 |
|
|
_("Thumb encoding does not support rotation"));
|
11843 |
|
|
constraint (1, BAD_HIREG);
|
11844 |
|
|
}
|
11845 |
|
|
}
|
11846 |
|
|
|
11847 |
|
|
static void
|
11848 |
|
|
do_t_swi (void)
|
11849 |
|
|
{
|
11850 |
|
|
/* We have to do the following check manually as ARM_EXT_OS only applies
|
11851 |
|
|
to ARM_EXT_V6M. */
|
11852 |
|
|
if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
|
11853 |
|
|
{
|
11854 |
|
|
if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
|
11855 |
|
|
/* This only applies to the v6m howver, not later architectures. */
|
11856 |
|
|
&& ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
|
11857 |
|
|
as_bad (_("SVC is not permitted on this architecture"));
|
11858 |
|
|
ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
|
11859 |
|
|
}
|
11860 |
|
|
|
11861 |
|
|
inst.reloc.type = BFD_RELOC_ARM_SWI;
|
11862 |
|
|
}
|
11863 |
|
|
|
11864 |
|
|
static void
|
11865 |
|
|
do_t_tb (void)
|
11866 |
|
|
{
|
11867 |
|
|
unsigned Rn, Rm;
|
11868 |
|
|
int half;
|
11869 |
|
|
|
11870 |
|
|
half = (inst.instruction & 0x10) != 0;
|
11871 |
|
|
set_it_insn_type_last ();
|
11872 |
|
|
constraint (inst.operands[0].immisreg,
|
11873 |
|
|
_("instruction requires register index"));
|
11874 |
|
|
|
11875 |
|
|
Rn = inst.operands[0].reg;
|
11876 |
|
|
Rm = inst.operands[0].imm;
|
11877 |
|
|
|
11878 |
|
|
constraint (Rn == REG_SP, BAD_SP);
|
11879 |
|
|
reject_bad_reg (Rm);
|
11880 |
|
|
|
11881 |
|
|
constraint (!half && inst.operands[0].shifted,
|
11882 |
|
|
_("instruction does not allow shifted index"));
|
11883 |
|
|
inst.instruction |= (Rn << 16) | Rm;
|
11884 |
|
|
}
|
11885 |
|
|
|
11886 |
|
|
static void
|
11887 |
|
|
do_t_usat (void)
|
11888 |
|
|
{
|
11889 |
|
|
do_t_ssat_usat (0);
|
11890 |
|
|
}
|
11891 |
|
|
|
11892 |
|
|
static void
|
11893 |
|
|
do_t_usat16 (void)
|
11894 |
|
|
{
|
11895 |
|
|
unsigned Rd, Rn;
|
11896 |
|
|
|
11897 |
|
|
Rd = inst.operands[0].reg;
|
11898 |
|
|
Rn = inst.operands[2].reg;
|
11899 |
|
|
|
11900 |
|
|
reject_bad_reg (Rd);
|
11901 |
|
|
reject_bad_reg (Rn);
|
11902 |
|
|
|
11903 |
|
|
inst.instruction |= Rd << 8;
|
11904 |
|
|
inst.instruction |= inst.operands[1].imm;
|
11905 |
|
|
inst.instruction |= Rn << 16;
|
11906 |
|
|
}
|
11907 |
|
|
|
11908 |
|
|
/* Neon instruction encoder helpers. */
|
11909 |
|
|
|
11910 |
|
|
/* Encodings for the different types for various Neon opcodes. */
|
11911 |
|
|
|
11912 |
|
|
/* An "invalid" code for the following tables. */
|
11913 |
|
|
#define N_INV -1u
|
11914 |
|
|
|
11915 |
|
|
struct neon_tab_entry
|
11916 |
|
|
{
|
11917 |
|
|
unsigned integer;
|
11918 |
|
|
unsigned float_or_poly;
|
11919 |
|
|
unsigned scalar_or_imm;
|
11920 |
|
|
};
|
11921 |
|
|
|
11922 |
|
|
/* Map overloaded Neon opcodes to their respective encodings. */
|
11923 |
|
|
#define NEON_ENC_TAB \
|
11924 |
|
|
X(vabd, 0x0000700, 0x1200d00, N_INV), \
|
11925 |
|
|
X(vmax, 0x0000600, 0x0000f00, N_INV), \
|
11926 |
|
|
X(vmin, 0x0000610, 0x0200f00, N_INV), \
|
11927 |
|
|
X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
|
11928 |
|
|
X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
|
11929 |
|
|
X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
|
11930 |
|
|
X(vadd, 0x0000800, 0x0000d00, N_INV), \
|
11931 |
|
|
X(vsub, 0x1000800, 0x0200d00, N_INV), \
|
11932 |
|
|
X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
|
11933 |
|
|
X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
|
11934 |
|
|
X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
|
11935 |
|
|
/* Register variants of the following two instructions are encoded as
|
11936 |
|
|
vcge / vcgt with the operands reversed. */ \
|
11937 |
|
|
X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
|
11938 |
|
|
X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
|
11939 |
|
|
X(vfma, N_INV, 0x0000c10, N_INV), \
|
11940 |
|
|
X(vfms, N_INV, 0x0200c10, N_INV), \
|
11941 |
|
|
X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
|
11942 |
|
|
X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
|
11943 |
|
|
X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
|
11944 |
|
|
X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
|
11945 |
|
|
X(vmlal, 0x0800800, N_INV, 0x0800240), \
|
11946 |
|
|
X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
|
11947 |
|
|
X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
|
11948 |
|
|
X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
|
11949 |
|
|
X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
|
11950 |
|
|
X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
|
11951 |
|
|
X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
|
11952 |
|
|
X(vshl, 0x0000400, N_INV, 0x0800510), \
|
11953 |
|
|
X(vqshl, 0x0000410, N_INV, 0x0800710), \
|
11954 |
|
|
X(vand, 0x0000110, N_INV, 0x0800030), \
|
11955 |
|
|
X(vbic, 0x0100110, N_INV, 0x0800030), \
|
11956 |
|
|
X(veor, 0x1000110, N_INV, N_INV), \
|
11957 |
|
|
X(vorn, 0x0300110, N_INV, 0x0800010), \
|
11958 |
|
|
X(vorr, 0x0200110, N_INV, 0x0800010), \
|
11959 |
|
|
X(vmvn, 0x1b00580, N_INV, 0x0800030), \
|
11960 |
|
|
X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
|
11961 |
|
|
X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
|
11962 |
|
|
X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
|
11963 |
|
|
X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
|
11964 |
|
|
X(vst1, 0x0000000, 0x0800000, N_INV), \
|
11965 |
|
|
X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
|
11966 |
|
|
X(vst2, 0x0000100, 0x0800100, N_INV), \
|
11967 |
|
|
X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
|
11968 |
|
|
X(vst3, 0x0000200, 0x0800200, N_INV), \
|
11969 |
|
|
X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
|
11970 |
|
|
X(vst4, 0x0000300, 0x0800300, N_INV), \
|
11971 |
|
|
X(vmovn, 0x1b20200, N_INV, N_INV), \
|
11972 |
|
|
X(vtrn, 0x1b20080, N_INV, N_INV), \
|
11973 |
|
|
X(vqmovn, 0x1b20200, N_INV, N_INV), \
|
11974 |
|
|
X(vqmovun, 0x1b20240, N_INV, N_INV), \
|
11975 |
|
|
X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
|
11976 |
|
|
X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
|
11977 |
|
|
X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
|
11978 |
|
|
X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
|
11979 |
|
|
X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
|
11980 |
|
|
X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
|
11981 |
|
|
X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
|
11982 |
|
|
X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
|
11983 |
|
|
X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
|
11984 |
|
|
|
11985 |
|
|
enum neon_opc
|
11986 |
|
|
{
|
11987 |
|
|
#define X(OPC,I,F,S) N_MNEM_##OPC
|
11988 |
|
|
NEON_ENC_TAB
|
11989 |
|
|
#undef X
|
11990 |
|
|
};
|
11991 |
|
|
|
11992 |
|
|
static const struct neon_tab_entry neon_enc_tab[] =
|
11993 |
|
|
{
|
11994 |
|
|
#define X(OPC,I,F,S) { (I), (F), (S) }
|
11995 |
|
|
NEON_ENC_TAB
|
11996 |
|
|
#undef X
|
11997 |
|
|
};
|
11998 |
|
|
|
11999 |
|
|
/* Do not use these macros; instead, use NEON_ENCODE defined below. */
|
12000 |
|
|
#define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
|
12001 |
|
|
#define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
|
12002 |
|
|
#define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
|
12003 |
|
|
#define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
|
12004 |
|
|
#define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
|
12005 |
|
|
#define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
|
12006 |
|
|
#define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
|
12007 |
|
|
#define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
|
12008 |
|
|
#define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
|
12009 |
|
|
#define NEON_ENC_SINGLE_(X) \
|
12010 |
|
|
((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
|
12011 |
|
|
#define NEON_ENC_DOUBLE_(X) \
|
12012 |
|
|
((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
|
12013 |
|
|
|
12014 |
|
|
#define NEON_ENCODE(type, inst) \
|
12015 |
|
|
do \
|
12016 |
|
|
{ \
|
12017 |
|
|
inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
|
12018 |
|
|
inst.is_neon = 1; \
|
12019 |
|
|
} \
|
12020 |
|
|
while (0)
|
12021 |
|
|
|
12022 |
|
|
#define check_neon_suffixes \
|
12023 |
|
|
do \
|
12024 |
|
|
{ \
|
12025 |
|
|
if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
|
12026 |
|
|
{ \
|
12027 |
|
|
as_bad (_("invalid neon suffix for non neon instruction")); \
|
12028 |
|
|
return; \
|
12029 |
|
|
} \
|
12030 |
|
|
} \
|
12031 |
|
|
while (0)
|
12032 |
|
|
|
12033 |
|
|
/* Define shapes for instruction operands. The following mnemonic characters
|
12034 |
|
|
are used in this table:
|
12035 |
|
|
|
12036 |
|
|
F - VFP S<n> register
|
12037 |
|
|
D - Neon D<n> register
|
12038 |
|
|
Q - Neon Q<n> register
|
12039 |
|
|
I - Immediate
|
12040 |
|
|
S - Scalar
|
12041 |
|
|
R - ARM register
|
12042 |
|
|
L - D<n> register list
|
12043 |
|
|
|
12044 |
|
|
This table is used to generate various data:
|
12045 |
|
|
- enumerations of the form NS_DDR to be used as arguments to
|
12046 |
|
|
neon_select_shape.
|
12047 |
|
|
- a table classifying shapes into single, double, quad, mixed.
|
12048 |
|
|
- a table used to drive neon_select_shape. */
|
12049 |
|
|
|
12050 |
|
|
#define NEON_SHAPE_DEF \
|
12051 |
|
|
X(3, (D, D, D), DOUBLE), \
|
12052 |
|
|
X(3, (Q, Q, Q), QUAD), \
|
12053 |
|
|
X(3, (D, D, I), DOUBLE), \
|
12054 |
|
|
X(3, (Q, Q, I), QUAD), \
|
12055 |
|
|
X(3, (D, D, S), DOUBLE), \
|
12056 |
|
|
X(3, (Q, Q, S), QUAD), \
|
12057 |
|
|
X(2, (D, D), DOUBLE), \
|
12058 |
|
|
X(2, (Q, Q), QUAD), \
|
12059 |
|
|
X(2, (D, S), DOUBLE), \
|
12060 |
|
|
X(2, (Q, S), QUAD), \
|
12061 |
|
|
X(2, (D, R), DOUBLE), \
|
12062 |
|
|
X(2, (Q, R), QUAD), \
|
12063 |
|
|
X(2, (D, I), DOUBLE), \
|
12064 |
|
|
X(2, (Q, I), QUAD), \
|
12065 |
|
|
X(3, (D, L, D), DOUBLE), \
|
12066 |
|
|
X(2, (D, Q), MIXED), \
|
12067 |
|
|
X(2, (Q, D), MIXED), \
|
12068 |
|
|
X(3, (D, Q, I), MIXED), \
|
12069 |
|
|
X(3, (Q, D, I), MIXED), \
|
12070 |
|
|
X(3, (Q, D, D), MIXED), \
|
12071 |
|
|
X(3, (D, Q, Q), MIXED), \
|
12072 |
|
|
X(3, (Q, Q, D), MIXED), \
|
12073 |
|
|
X(3, (Q, D, S), MIXED), \
|
12074 |
|
|
X(3, (D, Q, S), MIXED), \
|
12075 |
|
|
X(4, (D, D, D, I), DOUBLE), \
|
12076 |
|
|
X(4, (Q, Q, Q, I), QUAD), \
|
12077 |
|
|
X(2, (F, F), SINGLE), \
|
12078 |
|
|
X(3, (F, F, F), SINGLE), \
|
12079 |
|
|
X(2, (F, I), SINGLE), \
|
12080 |
|
|
X(2, (F, D), MIXED), \
|
12081 |
|
|
X(2, (D, F), MIXED), \
|
12082 |
|
|
X(3, (F, F, I), MIXED), \
|
12083 |
|
|
X(4, (R, R, F, F), SINGLE), \
|
12084 |
|
|
X(4, (F, F, R, R), SINGLE), \
|
12085 |
|
|
X(3, (D, R, R), DOUBLE), \
|
12086 |
|
|
X(3, (R, R, D), DOUBLE), \
|
12087 |
|
|
X(2, (S, R), SINGLE), \
|
12088 |
|
|
X(2, (R, S), SINGLE), \
|
12089 |
|
|
X(2, (F, R), SINGLE), \
|
12090 |
|
|
X(2, (R, F), SINGLE)
|
12091 |
|
|
|
12092 |
|
|
#define S2(A,B) NS_##A##B
|
12093 |
|
|
#define S3(A,B,C) NS_##A##B##C
|
12094 |
|
|
#define S4(A,B,C,D) NS_##A##B##C##D
|
12095 |
|
|
|
12096 |
|
|
#define X(N, L, C) S##N L
|
12097 |
|
|
|
12098 |
|
|
enum neon_shape
|
12099 |
|
|
{
|
12100 |
|
|
NEON_SHAPE_DEF,
|
12101 |
|
|
NS_NULL
|
12102 |
|
|
};
|
12103 |
|
|
|
12104 |
|
|
#undef X
|
12105 |
|
|
#undef S2
|
12106 |
|
|
#undef S3
|
12107 |
|
|
#undef S4
|
12108 |
|
|
|
12109 |
|
|
enum neon_shape_class
|
12110 |
|
|
{
|
12111 |
|
|
SC_SINGLE,
|
12112 |
|
|
SC_DOUBLE,
|
12113 |
|
|
SC_QUAD,
|
12114 |
|
|
SC_MIXED
|
12115 |
|
|
};
|
12116 |
|
|
|
12117 |
|
|
#define X(N, L, C) SC_##C
|
12118 |
|
|
|
12119 |
|
|
static enum neon_shape_class neon_shape_class[] =
|
12120 |
|
|
{
|
12121 |
|
|
NEON_SHAPE_DEF
|
12122 |
|
|
};
|
12123 |
|
|
|
12124 |
|
|
#undef X
|
12125 |
|
|
|
12126 |
|
|
enum neon_shape_el
|
12127 |
|
|
{
|
12128 |
|
|
SE_F,
|
12129 |
|
|
SE_D,
|
12130 |
|
|
SE_Q,
|
12131 |
|
|
SE_I,
|
12132 |
|
|
SE_S,
|
12133 |
|
|
SE_R,
|
12134 |
|
|
SE_L
|
12135 |
|
|
};
|
12136 |
|
|
|
12137 |
|
|
/* Register widths of above. */
|
12138 |
|
|
static unsigned neon_shape_el_size[] =
|
12139 |
|
|
{
|
12140 |
|
|
32,
|
12141 |
|
|
64,
|
12142 |
|
|
128,
|
12143 |
|
|
0,
|
12144 |
|
|
32,
|
12145 |
|
|
32,
|
12146 |
|
|
|
12147 |
|
|
};
|
12148 |
|
|
|
12149 |
|
|
struct neon_shape_info
|
12150 |
|
|
{
|
12151 |
|
|
unsigned els;
|
12152 |
|
|
enum neon_shape_el el[NEON_MAX_TYPE_ELS];
|
12153 |
|
|
};
|
12154 |
|
|
|
12155 |
|
|
#define S2(A,B) { SE_##A, SE_##B }
|
12156 |
|
|
#define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
|
12157 |
|
|
#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
|
12158 |
|
|
|
12159 |
|
|
#define X(N, L, C) { N, S##N L }
|
12160 |
|
|
|
12161 |
|
|
static struct neon_shape_info neon_shape_tab[] =
|
12162 |
|
|
{
|
12163 |
|
|
NEON_SHAPE_DEF
|
12164 |
|
|
};
|
12165 |
|
|
|
12166 |
|
|
#undef X
|
12167 |
|
|
#undef S2
|
12168 |
|
|
#undef S3
|
12169 |
|
|
#undef S4
|
12170 |
|
|
|
12171 |
|
|
/* Bit masks used in type checking given instructions.
|
12172 |
|
|
'N_EQK' means the type must be the same as (or based on in some way) the key
|
12173 |
|
|
type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
|
12174 |
|
|
set, various other bits can be set as well in order to modify the meaning of
|
12175 |
|
|
the type constraint. */
|
12176 |
|
|
|
12177 |
|
|
enum neon_type_mask
|
12178 |
|
|
{
|
12179 |
|
|
N_S8 = 0x0000001,
|
12180 |
|
|
N_S16 = 0x0000002,
|
12181 |
|
|
N_S32 = 0x0000004,
|
12182 |
|
|
N_S64 = 0x0000008,
|
12183 |
|
|
N_U8 = 0x0000010,
|
12184 |
|
|
N_U16 = 0x0000020,
|
12185 |
|
|
N_U32 = 0x0000040,
|
12186 |
|
|
N_U64 = 0x0000080,
|
12187 |
|
|
N_I8 = 0x0000100,
|
12188 |
|
|
N_I16 = 0x0000200,
|
12189 |
|
|
N_I32 = 0x0000400,
|
12190 |
|
|
N_I64 = 0x0000800,
|
12191 |
|
|
N_8 = 0x0001000,
|
12192 |
|
|
N_16 = 0x0002000,
|
12193 |
|
|
N_32 = 0x0004000,
|
12194 |
|
|
N_64 = 0x0008000,
|
12195 |
|
|
N_P8 = 0x0010000,
|
12196 |
|
|
N_P16 = 0x0020000,
|
12197 |
|
|
N_F16 = 0x0040000,
|
12198 |
|
|
N_F32 = 0x0080000,
|
12199 |
|
|
N_F64 = 0x0100000,
|
12200 |
|
|
N_KEY = 0x1000000, /* Key element (main type specifier). */
|
12201 |
|
|
N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
|
12202 |
|
|
N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
|
12203 |
|
|
N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
|
12204 |
|
|
N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
|
12205 |
|
|
N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
|
12206 |
|
|
N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
|
12207 |
|
|
N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
|
12208 |
|
|
N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
|
12209 |
|
|
N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
|
12210 |
|
|
N_UTYP = 0,
|
12211 |
|
|
N_MAX_NONSPECIAL = N_F64
|
12212 |
|
|
};
|
12213 |
|
|
|
12214 |
|
|
#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
|
12215 |
|
|
|
12216 |
|
|
#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
|
12217 |
|
|
#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
|
12218 |
|
|
#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
|
12219 |
|
|
#define N_SUF_32 (N_SU_32 | N_F32)
|
12220 |
|
|
#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
|
12221 |
|
|
#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
|
12222 |
|
|
|
12223 |
|
|
/* Pass this as the first type argument to neon_check_type to ignore types
|
12224 |
|
|
altogether. */
|
12225 |
|
|
#define N_IGNORE_TYPE (N_KEY | N_EQK)
|
12226 |
|
|
|
12227 |
|
|
/* Select a "shape" for the current instruction (describing register types or
|
12228 |
|
|
sizes) from a list of alternatives. Return NS_NULL if the current instruction
|
12229 |
|
|
doesn't fit. For non-polymorphic shapes, checking is usually done as a
|
12230 |
|
|
function of operand parsing, so this function doesn't need to be called.
|
12231 |
|
|
Shapes should be listed in order of decreasing length. */
|
12232 |
|
|
|
12233 |
|
|
static enum neon_shape
|
12234 |
|
|
neon_select_shape (enum neon_shape shape, ...)
|
12235 |
|
|
{
|
12236 |
|
|
va_list ap;
|
12237 |
|
|
enum neon_shape first_shape = shape;
|
12238 |
|
|
|
12239 |
|
|
/* Fix missing optional operands. FIXME: we don't know at this point how
|
12240 |
|
|
many arguments we should have, so this makes the assumption that we have
|
12241 |
|
|
> 1. This is true of all current Neon opcodes, I think, but may not be
|
12242 |
|
|
true in the future. */
|
12243 |
|
|
if (!inst.operands[1].present)
|
12244 |
|
|
inst.operands[1] = inst.operands[0];
|
12245 |
|
|
|
12246 |
|
|
va_start (ap, shape);
|
12247 |
|
|
|
12248 |
|
|
for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
|
12249 |
|
|
{
|
12250 |
|
|
unsigned j;
|
12251 |
|
|
int matches = 1;
|
12252 |
|
|
|
12253 |
|
|
for (j = 0; j < neon_shape_tab[shape].els; j++)
|
12254 |
|
|
{
|
12255 |
|
|
if (!inst.operands[j].present)
|
12256 |
|
|
{
|
12257 |
|
|
matches = 0;
|
12258 |
|
|
break;
|
12259 |
|
|
}
|
12260 |
|
|
|
12261 |
|
|
switch (neon_shape_tab[shape].el[j])
|
12262 |
|
|
{
|
12263 |
|
|
case SE_F:
|
12264 |
|
|
if (!(inst.operands[j].isreg
|
12265 |
|
|
&& inst.operands[j].isvec
|
12266 |
|
|
&& inst.operands[j].issingle
|
12267 |
|
|
&& !inst.operands[j].isquad))
|
12268 |
|
|
matches = 0;
|
12269 |
|
|
break;
|
12270 |
|
|
|
12271 |
|
|
case SE_D:
|
12272 |
|
|
if (!(inst.operands[j].isreg
|
12273 |
|
|
&& inst.operands[j].isvec
|
12274 |
|
|
&& !inst.operands[j].isquad
|
12275 |
|
|
&& !inst.operands[j].issingle))
|
12276 |
|
|
matches = 0;
|
12277 |
|
|
break;
|
12278 |
|
|
|
12279 |
|
|
case SE_R:
|
12280 |
|
|
if (!(inst.operands[j].isreg
|
12281 |
|
|
&& !inst.operands[j].isvec))
|
12282 |
|
|
matches = 0;
|
12283 |
|
|
break;
|
12284 |
|
|
|
12285 |
|
|
case SE_Q:
|
12286 |
|
|
if (!(inst.operands[j].isreg
|
12287 |
|
|
&& inst.operands[j].isvec
|
12288 |
|
|
&& inst.operands[j].isquad
|
12289 |
|
|
&& !inst.operands[j].issingle))
|
12290 |
|
|
matches = 0;
|
12291 |
|
|
break;
|
12292 |
|
|
|
12293 |
|
|
case SE_I:
|
12294 |
|
|
if (!(!inst.operands[j].isreg
|
12295 |
|
|
&& !inst.operands[j].isscalar))
|
12296 |
|
|
matches = 0;
|
12297 |
|
|
break;
|
12298 |
|
|
|
12299 |
|
|
case SE_S:
|
12300 |
|
|
if (!(!inst.operands[j].isreg
|
12301 |
|
|
&& inst.operands[j].isscalar))
|
12302 |
|
|
matches = 0;
|
12303 |
|
|
break;
|
12304 |
|
|
|
12305 |
|
|
case SE_L:
|
12306 |
|
|
break;
|
12307 |
|
|
}
|
12308 |
|
|
if (!matches)
|
12309 |
|
|
break;
|
12310 |
|
|
}
|
12311 |
|
|
if (matches)
|
12312 |
|
|
break;
|
12313 |
|
|
}
|
12314 |
|
|
|
12315 |
|
|
va_end (ap);
|
12316 |
|
|
|
12317 |
|
|
if (shape == NS_NULL && first_shape != NS_NULL)
|
12318 |
|
|
first_error (_("invalid instruction shape"));
|
12319 |
|
|
|
12320 |
|
|
return shape;
|
12321 |
|
|
}
|
12322 |
|
|
|
12323 |
|
|
/* True if SHAPE is predominantly a quadword operation (most of the time, this
|
12324 |
|
|
means the Q bit should be set). */
|
12325 |
|
|
|
12326 |
|
|
static int
|
12327 |
|
|
neon_quad (enum neon_shape shape)
|
12328 |
|
|
{
|
12329 |
|
|
return neon_shape_class[shape] == SC_QUAD;
|
12330 |
|
|
}
|
12331 |
|
|
|
12332 |
|
|
static void
|
12333 |
|
|
neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
|
12334 |
|
|
unsigned *g_size)
|
12335 |
|
|
{
|
12336 |
|
|
/* Allow modification to be made to types which are constrained to be
|
12337 |
|
|
based on the key element, based on bits set alongside N_EQK. */
|
12338 |
|
|
if ((typebits & N_EQK) != 0)
|
12339 |
|
|
{
|
12340 |
|
|
if ((typebits & N_HLF) != 0)
|
12341 |
|
|
*g_size /= 2;
|
12342 |
|
|
else if ((typebits & N_DBL) != 0)
|
12343 |
|
|
*g_size *= 2;
|
12344 |
|
|
if ((typebits & N_SGN) != 0)
|
12345 |
|
|
*g_type = NT_signed;
|
12346 |
|
|
else if ((typebits & N_UNS) != 0)
|
12347 |
|
|
*g_type = NT_unsigned;
|
12348 |
|
|
else if ((typebits & N_INT) != 0)
|
12349 |
|
|
*g_type = NT_integer;
|
12350 |
|
|
else if ((typebits & N_FLT) != 0)
|
12351 |
|
|
*g_type = NT_float;
|
12352 |
|
|
else if ((typebits & N_SIZ) != 0)
|
12353 |
|
|
*g_type = NT_untyped;
|
12354 |
|
|
}
|
12355 |
|
|
}
|
12356 |
|
|
|
12357 |
|
|
/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
|
12358 |
|
|
operand type, i.e. the single type specified in a Neon instruction when it
|
12359 |
|
|
is the only one given. */
|
12360 |
|
|
|
12361 |
|
|
static struct neon_type_el
|
12362 |
|
|
neon_type_promote (struct neon_type_el *key, unsigned thisarg)
|
12363 |
|
|
{
|
12364 |
|
|
struct neon_type_el dest = *key;
|
12365 |
|
|
|
12366 |
|
|
gas_assert ((thisarg & N_EQK) != 0);
|
12367 |
|
|
|
12368 |
|
|
neon_modify_type_size (thisarg, &dest.type, &dest.size);
|
12369 |
|
|
|
12370 |
|
|
return dest;
|
12371 |
|
|
}
|
12372 |
|
|
|
12373 |
|
|
/* Convert Neon type and size into compact bitmask representation. */
|
12374 |
|
|
|
12375 |
|
|
static enum neon_type_mask
|
12376 |
|
|
type_chk_of_el_type (enum neon_el_type type, unsigned size)
|
12377 |
|
|
{
|
12378 |
|
|
switch (type)
|
12379 |
|
|
{
|
12380 |
|
|
case NT_untyped:
|
12381 |
|
|
switch (size)
|
12382 |
|
|
{
|
12383 |
|
|
case 8: return N_8;
|
12384 |
|
|
case 16: return N_16;
|
12385 |
|
|
case 32: return N_32;
|
12386 |
|
|
case 64: return N_64;
|
12387 |
|
|
default: ;
|
12388 |
|
|
}
|
12389 |
|
|
break;
|
12390 |
|
|
|
12391 |
|
|
case NT_integer:
|
12392 |
|
|
switch (size)
|
12393 |
|
|
{
|
12394 |
|
|
case 8: return N_I8;
|
12395 |
|
|
case 16: return N_I16;
|
12396 |
|
|
case 32: return N_I32;
|
12397 |
|
|
case 64: return N_I64;
|
12398 |
|
|
default: ;
|
12399 |
|
|
}
|
12400 |
|
|
break;
|
12401 |
|
|
|
12402 |
|
|
case NT_float:
|
12403 |
|
|
switch (size)
|
12404 |
|
|
{
|
12405 |
|
|
case 16: return N_F16;
|
12406 |
|
|
case 32: return N_F32;
|
12407 |
|
|
case 64: return N_F64;
|
12408 |
|
|
default: ;
|
12409 |
|
|
}
|
12410 |
|
|
break;
|
12411 |
|
|
|
12412 |
|
|
case NT_poly:
|
12413 |
|
|
switch (size)
|
12414 |
|
|
{
|
12415 |
|
|
case 8: return N_P8;
|
12416 |
|
|
case 16: return N_P16;
|
12417 |
|
|
default: ;
|
12418 |
|
|
}
|
12419 |
|
|
break;
|
12420 |
|
|
|
12421 |
|
|
case NT_signed:
|
12422 |
|
|
switch (size)
|
12423 |
|
|
{
|
12424 |
|
|
case 8: return N_S8;
|
12425 |
|
|
case 16: return N_S16;
|
12426 |
|
|
case 32: return N_S32;
|
12427 |
|
|
case 64: return N_S64;
|
12428 |
|
|
default: ;
|
12429 |
|
|
}
|
12430 |
|
|
break;
|
12431 |
|
|
|
12432 |
|
|
case NT_unsigned:
|
12433 |
|
|
switch (size)
|
12434 |
|
|
{
|
12435 |
|
|
case 8: return N_U8;
|
12436 |
|
|
case 16: return N_U16;
|
12437 |
|
|
case 32: return N_U32;
|
12438 |
|
|
case 64: return N_U64;
|
12439 |
|
|
default: ;
|
12440 |
|
|
}
|
12441 |
|
|
break;
|
12442 |
|
|
|
12443 |
|
|
default: ;
|
12444 |
|
|
}
|
12445 |
|
|
|
12446 |
|
|
return N_UTYP;
|
12447 |
|
|
}
|
12448 |
|
|
|
12449 |
|
|
/* Convert compact Neon bitmask type representation to a type and size. Only
|
12450 |
|
|
handles the case where a single bit is set in the mask. */
|
12451 |
|
|
|
12452 |
|
|
static int
|
12453 |
|
|
el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
|
12454 |
|
|
enum neon_type_mask mask)
|
12455 |
|
|
{
|
12456 |
|
|
if ((mask & N_EQK) != 0)
|
12457 |
|
|
return FAIL;
|
12458 |
|
|
|
12459 |
|
|
if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
|
12460 |
|
|
*size = 8;
|
12461 |
|
|
else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
|
12462 |
|
|
*size = 16;
|
12463 |
|
|
else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
|
12464 |
|
|
*size = 32;
|
12465 |
|
|
else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
|
12466 |
|
|
*size = 64;
|
12467 |
|
|
else
|
12468 |
|
|
return FAIL;
|
12469 |
|
|
|
12470 |
|
|
if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
|
12471 |
|
|
*type = NT_signed;
|
12472 |
|
|
else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
|
12473 |
|
|
*type = NT_unsigned;
|
12474 |
|
|
else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
|
12475 |
|
|
*type = NT_integer;
|
12476 |
|
|
else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
|
12477 |
|
|
*type = NT_untyped;
|
12478 |
|
|
else if ((mask & (N_P8 | N_P16)) != 0)
|
12479 |
|
|
*type = NT_poly;
|
12480 |
|
|
else if ((mask & (N_F32 | N_F64)) != 0)
|
12481 |
|
|
*type = NT_float;
|
12482 |
|
|
else
|
12483 |
|
|
return FAIL;
|
12484 |
|
|
|
12485 |
|
|
return SUCCESS;
|
12486 |
|
|
}
|
12487 |
|
|
|
12488 |
|
|
/* Modify a bitmask of allowed types. This is only needed for type
|
12489 |
|
|
relaxation. */
|
12490 |
|
|
|
12491 |
|
|
static unsigned
|
12492 |
|
|
modify_types_allowed (unsigned allowed, unsigned mods)
|
12493 |
|
|
{
|
12494 |
|
|
unsigned size;
|
12495 |
|
|
enum neon_el_type type;
|
12496 |
|
|
unsigned destmask;
|
12497 |
|
|
int i;
|
12498 |
|
|
|
12499 |
|
|
destmask = 0;
|
12500 |
|
|
|
12501 |
|
|
for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
|
12502 |
|
|
{
|
12503 |
|
|
if (el_type_of_type_chk (&type, &size,
|
12504 |
|
|
(enum neon_type_mask) (allowed & i)) == SUCCESS)
|
12505 |
|
|
{
|
12506 |
|
|
neon_modify_type_size (mods, &type, &size);
|
12507 |
|
|
destmask |= type_chk_of_el_type (type, size);
|
12508 |
|
|
}
|
12509 |
|
|
}
|
12510 |
|
|
|
12511 |
|
|
return destmask;
|
12512 |
|
|
}
|
12513 |
|
|
|
12514 |
|
|
/* Check type and return type classification.
|
12515 |
|
|
The manual states (paraphrase): If one datatype is given, it indicates the
|
12516 |
|
|
type given in:
|
12517 |
|
|
- the second operand, if there is one
|
12518 |
|
|
- the operand, if there is no second operand
|
12519 |
|
|
- the result, if there are no operands.
|
12520 |
|
|
This isn't quite good enough though, so we use a concept of a "key" datatype
|
12521 |
|
|
which is set on a per-instruction basis, which is the one which matters when
|
12522 |
|
|
only one data type is written.
|
12523 |
|
|
Note: this function has side-effects (e.g. filling in missing operands). All
|
12524 |
|
|
Neon instructions should call it before performing bit encoding. */
|
12525 |
|
|
|
12526 |
|
|
static struct neon_type_el
|
12527 |
|
|
neon_check_type (unsigned els, enum neon_shape ns, ...)
|
12528 |
|
|
{
|
12529 |
|
|
va_list ap;
|
12530 |
|
|
unsigned i, pass, key_el = 0;
|
12531 |
|
|
unsigned types[NEON_MAX_TYPE_ELS];
|
12532 |
|
|
enum neon_el_type k_type = NT_invtype;
|
12533 |
|
|
unsigned k_size = -1u;
|
12534 |
|
|
struct neon_type_el badtype = {NT_invtype, -1};
|
12535 |
|
|
unsigned key_allowed = 0;
|
12536 |
|
|
|
12537 |
|
|
/* Optional registers in Neon instructions are always (not) in operand 1.
|
12538 |
|
|
Fill in the missing operand here, if it was omitted. */
|
12539 |
|
|
if (els > 1 && !inst.operands[1].present)
|
12540 |
|
|
inst.operands[1] = inst.operands[0];
|
12541 |
|
|
|
12542 |
|
|
/* Suck up all the varargs. */
|
12543 |
|
|
va_start (ap, ns);
|
12544 |
|
|
for (i = 0; i < els; i++)
|
12545 |
|
|
{
|
12546 |
|
|
unsigned thisarg = va_arg (ap, unsigned);
|
12547 |
|
|
if (thisarg == N_IGNORE_TYPE)
|
12548 |
|
|
{
|
12549 |
|
|
va_end (ap);
|
12550 |
|
|
return badtype;
|
12551 |
|
|
}
|
12552 |
|
|
types[i] = thisarg;
|
12553 |
|
|
if ((thisarg & N_KEY) != 0)
|
12554 |
|
|
key_el = i;
|
12555 |
|
|
}
|
12556 |
|
|
va_end (ap);
|
12557 |
|
|
|
12558 |
|
|
if (inst.vectype.elems > 0)
|
12559 |
|
|
for (i = 0; i < els; i++)
|
12560 |
|
|
if (inst.operands[i].vectype.type != NT_invtype)
|
12561 |
|
|
{
|
12562 |
|
|
first_error (_("types specified in both the mnemonic and operands"));
|
12563 |
|
|
return badtype;
|
12564 |
|
|
}
|
12565 |
|
|
|
12566 |
|
|
/* Duplicate inst.vectype elements here as necessary.
|
12567 |
|
|
FIXME: No idea if this is exactly the same as the ARM assembler,
|
12568 |
|
|
particularly when an insn takes one register and one non-register
|
12569 |
|
|
operand. */
|
12570 |
|
|
if (inst.vectype.elems == 1 && els > 1)
|
12571 |
|
|
{
|
12572 |
|
|
unsigned j;
|
12573 |
|
|
inst.vectype.elems = els;
|
12574 |
|
|
inst.vectype.el[key_el] = inst.vectype.el[0];
|
12575 |
|
|
for (j = 0; j < els; j++)
|
12576 |
|
|
if (j != key_el)
|
12577 |
|
|
inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
|
12578 |
|
|
types[j]);
|
12579 |
|
|
}
|
12580 |
|
|
else if (inst.vectype.elems == 0 && els > 0)
|
12581 |
|
|
{
|
12582 |
|
|
unsigned j;
|
12583 |
|
|
/* No types were given after the mnemonic, so look for types specified
|
12584 |
|
|
after each operand. We allow some flexibility here; as long as the
|
12585 |
|
|
"key" operand has a type, we can infer the others. */
|
12586 |
|
|
for (j = 0; j < els; j++)
|
12587 |
|
|
if (inst.operands[j].vectype.type != NT_invtype)
|
12588 |
|
|
inst.vectype.el[j] = inst.operands[j].vectype;
|
12589 |
|
|
|
12590 |
|
|
if (inst.operands[key_el].vectype.type != NT_invtype)
|
12591 |
|
|
{
|
12592 |
|
|
for (j = 0; j < els; j++)
|
12593 |
|
|
if (inst.operands[j].vectype.type == NT_invtype)
|
12594 |
|
|
inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
|
12595 |
|
|
types[j]);
|
12596 |
|
|
}
|
12597 |
|
|
else
|
12598 |
|
|
{
|
12599 |
|
|
first_error (_("operand types can't be inferred"));
|
12600 |
|
|
return badtype;
|
12601 |
|
|
}
|
12602 |
|
|
}
|
12603 |
|
|
else if (inst.vectype.elems != els)
|
12604 |
|
|
{
|
12605 |
|
|
first_error (_("type specifier has the wrong number of parts"));
|
12606 |
|
|
return badtype;
|
12607 |
|
|
}
|
12608 |
|
|
|
12609 |
|
|
for (pass = 0; pass < 2; pass++)
|
12610 |
|
|
{
|
12611 |
|
|
for (i = 0; i < els; i++)
|
12612 |
|
|
{
|
12613 |
|
|
unsigned thisarg = types[i];
|
12614 |
|
|
unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
|
12615 |
|
|
? modify_types_allowed (key_allowed, thisarg) : thisarg;
|
12616 |
|
|
enum neon_el_type g_type = inst.vectype.el[i].type;
|
12617 |
|
|
unsigned g_size = inst.vectype.el[i].size;
|
12618 |
|
|
|
12619 |
|
|
/* Decay more-specific signed & unsigned types to sign-insensitive
|
12620 |
|
|
integer types if sign-specific variants are unavailable. */
|
12621 |
|
|
if ((g_type == NT_signed || g_type == NT_unsigned)
|
12622 |
|
|
&& (types_allowed & N_SU_ALL) == 0)
|
12623 |
|
|
g_type = NT_integer;
|
12624 |
|
|
|
12625 |
|
|
/* If only untyped args are allowed, decay any more specific types to
|
12626 |
|
|
them. Some instructions only care about signs for some element
|
12627 |
|
|
sizes, so handle that properly. */
|
12628 |
|
|
if ((g_size == 8 && (types_allowed & N_8) != 0)
|
12629 |
|
|
|| (g_size == 16 && (types_allowed & N_16) != 0)
|
12630 |
|
|
|| (g_size == 32 && (types_allowed & N_32) != 0)
|
12631 |
|
|
|| (g_size == 64 && (types_allowed & N_64) != 0))
|
12632 |
|
|
g_type = NT_untyped;
|
12633 |
|
|
|
12634 |
|
|
if (pass == 0)
|
12635 |
|
|
{
|
12636 |
|
|
if ((thisarg & N_KEY) != 0)
|
12637 |
|
|
{
|
12638 |
|
|
k_type = g_type;
|
12639 |
|
|
k_size = g_size;
|
12640 |
|
|
key_allowed = thisarg & ~N_KEY;
|
12641 |
|
|
}
|
12642 |
|
|
}
|
12643 |
|
|
else
|
12644 |
|
|
{
|
12645 |
|
|
if ((thisarg & N_VFP) != 0)
|
12646 |
|
|
{
|
12647 |
|
|
enum neon_shape_el regshape;
|
12648 |
|
|
unsigned regwidth, match;
|
12649 |
|
|
|
12650 |
|
|
/* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
|
12651 |
|
|
if (ns == NS_NULL)
|
12652 |
|
|
{
|
12653 |
|
|
first_error (_("invalid instruction shape"));
|
12654 |
|
|
return badtype;
|
12655 |
|
|
}
|
12656 |
|
|
regshape = neon_shape_tab[ns].el[i];
|
12657 |
|
|
regwidth = neon_shape_el_size[regshape];
|
12658 |
|
|
|
12659 |
|
|
/* In VFP mode, operands must match register widths. If we
|
12660 |
|
|
have a key operand, use its width, else use the width of
|
12661 |
|
|
the current operand. */
|
12662 |
|
|
if (k_size != -1u)
|
12663 |
|
|
match = k_size;
|
12664 |
|
|
else
|
12665 |
|
|
match = g_size;
|
12666 |
|
|
|
12667 |
|
|
if (regwidth != match)
|
12668 |
|
|
{
|
12669 |
|
|
first_error (_("operand size must match register width"));
|
12670 |
|
|
return badtype;
|
12671 |
|
|
}
|
12672 |
|
|
}
|
12673 |
|
|
|
12674 |
|
|
if ((thisarg & N_EQK) == 0)
|
12675 |
|
|
{
|
12676 |
|
|
unsigned given_type = type_chk_of_el_type (g_type, g_size);
|
12677 |
|
|
|
12678 |
|
|
if ((given_type & types_allowed) == 0)
|
12679 |
|
|
{
|
12680 |
|
|
first_error (_("bad type in Neon instruction"));
|
12681 |
|
|
return badtype;
|
12682 |
|
|
}
|
12683 |
|
|
}
|
12684 |
|
|
else
|
12685 |
|
|
{
|
12686 |
|
|
enum neon_el_type mod_k_type = k_type;
|
12687 |
|
|
unsigned mod_k_size = k_size;
|
12688 |
|
|
neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
|
12689 |
|
|
if (g_type != mod_k_type || g_size != mod_k_size)
|
12690 |
|
|
{
|
12691 |
|
|
first_error (_("inconsistent types in Neon instruction"));
|
12692 |
|
|
return badtype;
|
12693 |
|
|
}
|
12694 |
|
|
}
|
12695 |
|
|
}
|
12696 |
|
|
}
|
12697 |
|
|
}
|
12698 |
|
|
|
12699 |
|
|
return inst.vectype.el[key_el];
|
12700 |
|
|
}
|
12701 |
|
|
|
12702 |
|
|
/* Neon-style VFP instruction forwarding. */
|
12703 |
|
|
|
12704 |
|
|
/* Thumb VFP instructions have 0xE in the condition field. */
|
12705 |
|
|
|
12706 |
|
|
static void
|
12707 |
|
|
do_vfp_cond_or_thumb (void)
|
12708 |
|
|
{
|
12709 |
|
|
inst.is_neon = 1;
|
12710 |
|
|
|
12711 |
|
|
if (thumb_mode)
|
12712 |
|
|
inst.instruction |= 0xe0000000;
|
12713 |
|
|
else
|
12714 |
|
|
inst.instruction |= inst.cond << 28;
|
12715 |
|
|
}
|
12716 |
|
|
|
12717 |
|
|
/* Look up and encode a simple mnemonic, for use as a helper function for the
|
12718 |
|
|
Neon-style VFP syntax. This avoids duplication of bits of the insns table,
|
12719 |
|
|
etc. It is assumed that operand parsing has already been done, and that the
|
12720 |
|
|
operands are in the form expected by the given opcode (this isn't necessarily
|
12721 |
|
|
the same as the form in which they were parsed, hence some massaging must
|
12722 |
|
|
take place before this function is called).
|
12723 |
|
|
Checks current arch version against that in the looked-up opcode. */
|
12724 |
|
|
|
12725 |
|
|
static void
|
12726 |
|
|
do_vfp_nsyn_opcode (const char *opname)
|
12727 |
|
|
{
|
12728 |
|
|
const struct asm_opcode *opcode;
|
12729 |
|
|
|
12730 |
|
|
opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
|
12731 |
|
|
|
12732 |
|
|
if (!opcode)
|
12733 |
|
|
abort ();
|
12734 |
|
|
|
12735 |
|
|
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
|
12736 |
|
|
thumb_mode ? *opcode->tvariant : *opcode->avariant),
|
12737 |
|
|
_(BAD_FPU));
|
12738 |
|
|
|
12739 |
|
|
inst.is_neon = 1;
|
12740 |
|
|
|
12741 |
|
|
if (thumb_mode)
|
12742 |
|
|
{
|
12743 |
|
|
inst.instruction = opcode->tvalue;
|
12744 |
|
|
opcode->tencode ();
|
12745 |
|
|
}
|
12746 |
|
|
else
|
12747 |
|
|
{
|
12748 |
|
|
inst.instruction = (inst.cond << 28) | opcode->avalue;
|
12749 |
|
|
opcode->aencode ();
|
12750 |
|
|
}
|
12751 |
|
|
}
|
12752 |
|
|
|
12753 |
|
|
static void
|
12754 |
|
|
do_vfp_nsyn_add_sub (enum neon_shape rs)
|
12755 |
|
|
{
|
12756 |
|
|
int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
|
12757 |
|
|
|
12758 |
|
|
if (rs == NS_FFF)
|
12759 |
|
|
{
|
12760 |
|
|
if (is_add)
|
12761 |
|
|
do_vfp_nsyn_opcode ("fadds");
|
12762 |
|
|
else
|
12763 |
|
|
do_vfp_nsyn_opcode ("fsubs");
|
12764 |
|
|
}
|
12765 |
|
|
else
|
12766 |
|
|
{
|
12767 |
|
|
if (is_add)
|
12768 |
|
|
do_vfp_nsyn_opcode ("faddd");
|
12769 |
|
|
else
|
12770 |
|
|
do_vfp_nsyn_opcode ("fsubd");
|
12771 |
|
|
}
|
12772 |
|
|
}
|
12773 |
|
|
|
12774 |
|
|
/* Check operand types to see if this is a VFP instruction, and if so call
|
12775 |
|
|
PFN (). */
|
12776 |
|
|
|
12777 |
|
|
static int
|
12778 |
|
|
try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
|
12779 |
|
|
{
|
12780 |
|
|
enum neon_shape rs;
|
12781 |
|
|
struct neon_type_el et;
|
12782 |
|
|
|
12783 |
|
|
switch (args)
|
12784 |
|
|
{
|
12785 |
|
|
case 2:
|
12786 |
|
|
rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
|
12787 |
|
|
et = neon_check_type (2, rs,
|
12788 |
|
|
N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
|
12789 |
|
|
break;
|
12790 |
|
|
|
12791 |
|
|
case 3:
|
12792 |
|
|
rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
|
12793 |
|
|
et = neon_check_type (3, rs,
|
12794 |
|
|
N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
|
12795 |
|
|
break;
|
12796 |
|
|
|
12797 |
|
|
default:
|
12798 |
|
|
abort ();
|
12799 |
|
|
}
|
12800 |
|
|
|
12801 |
|
|
if (et.type != NT_invtype)
|
12802 |
|
|
{
|
12803 |
|
|
pfn (rs);
|
12804 |
|
|
return SUCCESS;
|
12805 |
|
|
}
|
12806 |
|
|
|
12807 |
|
|
inst.error = NULL;
|
12808 |
|
|
return FAIL;
|
12809 |
|
|
}
|
12810 |
|
|
|
12811 |
|
|
static void
|
12812 |
|
|
do_vfp_nsyn_mla_mls (enum neon_shape rs)
|
12813 |
|
|
{
|
12814 |
|
|
int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
|
12815 |
|
|
|
12816 |
|
|
if (rs == NS_FFF)
|
12817 |
|
|
{
|
12818 |
|
|
if (is_mla)
|
12819 |
|
|
do_vfp_nsyn_opcode ("fmacs");
|
12820 |
|
|
else
|
12821 |
|
|
do_vfp_nsyn_opcode ("fnmacs");
|
12822 |
|
|
}
|
12823 |
|
|
else
|
12824 |
|
|
{
|
12825 |
|
|
if (is_mla)
|
12826 |
|
|
do_vfp_nsyn_opcode ("fmacd");
|
12827 |
|
|
else
|
12828 |
|
|
do_vfp_nsyn_opcode ("fnmacd");
|
12829 |
|
|
}
|
12830 |
|
|
}
|
12831 |
|
|
|
12832 |
|
|
static void
|
12833 |
|
|
do_vfp_nsyn_fma_fms (enum neon_shape rs)
|
12834 |
|
|
{
|
12835 |
|
|
int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
|
12836 |
|
|
|
12837 |
|
|
if (rs == NS_FFF)
|
12838 |
|
|
{
|
12839 |
|
|
if (is_fma)
|
12840 |
|
|
do_vfp_nsyn_opcode ("ffmas");
|
12841 |
|
|
else
|
12842 |
|
|
do_vfp_nsyn_opcode ("ffnmas");
|
12843 |
|
|
}
|
12844 |
|
|
else
|
12845 |
|
|
{
|
12846 |
|
|
if (is_fma)
|
12847 |
|
|
do_vfp_nsyn_opcode ("ffmad");
|
12848 |
|
|
else
|
12849 |
|
|
do_vfp_nsyn_opcode ("ffnmad");
|
12850 |
|
|
}
|
12851 |
|
|
}
|
12852 |
|
|
|
12853 |
|
|
static void
|
12854 |
|
|
do_vfp_nsyn_mul (enum neon_shape rs)
|
12855 |
|
|
{
|
12856 |
|
|
if (rs == NS_FFF)
|
12857 |
|
|
do_vfp_nsyn_opcode ("fmuls");
|
12858 |
|
|
else
|
12859 |
|
|
do_vfp_nsyn_opcode ("fmuld");
|
12860 |
|
|
}
|
12861 |
|
|
|
12862 |
|
|
static void
|
12863 |
|
|
do_vfp_nsyn_abs_neg (enum neon_shape rs)
|
12864 |
|
|
{
|
12865 |
|
|
int is_neg = (inst.instruction & 0x80) != 0;
|
12866 |
|
|
neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
|
12867 |
|
|
|
12868 |
|
|
if (rs == NS_FF)
|
12869 |
|
|
{
|
12870 |
|
|
if (is_neg)
|
12871 |
|
|
do_vfp_nsyn_opcode ("fnegs");
|
12872 |
|
|
else
|
12873 |
|
|
do_vfp_nsyn_opcode ("fabss");
|
12874 |
|
|
}
|
12875 |
|
|
else
|
12876 |
|
|
{
|
12877 |
|
|
if (is_neg)
|
12878 |
|
|
do_vfp_nsyn_opcode ("fnegd");
|
12879 |
|
|
else
|
12880 |
|
|
do_vfp_nsyn_opcode ("fabsd");
|
12881 |
|
|
}
|
12882 |
|
|
}
|
12883 |
|
|
|
12884 |
|
|
/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
|
12885 |
|
|
insns belong to Neon, and are handled elsewhere. */
|
12886 |
|
|
|
12887 |
|
|
static void
|
12888 |
|
|
do_vfp_nsyn_ldm_stm (int is_dbmode)
|
12889 |
|
|
{
|
12890 |
|
|
int is_ldm = (inst.instruction & (1 << 20)) != 0;
|
12891 |
|
|
if (is_ldm)
|
12892 |
|
|
{
|
12893 |
|
|
if (is_dbmode)
|
12894 |
|
|
do_vfp_nsyn_opcode ("fldmdbs");
|
12895 |
|
|
else
|
12896 |
|
|
do_vfp_nsyn_opcode ("fldmias");
|
12897 |
|
|
}
|
12898 |
|
|
else
|
12899 |
|
|
{
|
12900 |
|
|
if (is_dbmode)
|
12901 |
|
|
do_vfp_nsyn_opcode ("fstmdbs");
|
12902 |
|
|
else
|
12903 |
|
|
do_vfp_nsyn_opcode ("fstmias");
|
12904 |
|
|
}
|
12905 |
|
|
}
|
12906 |
|
|
|
12907 |
|
|
static void
|
12908 |
|
|
do_vfp_nsyn_sqrt (void)
|
12909 |
|
|
{
|
12910 |
|
|
enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
|
12911 |
|
|
neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
|
12912 |
|
|
|
12913 |
|
|
if (rs == NS_FF)
|
12914 |
|
|
do_vfp_nsyn_opcode ("fsqrts");
|
12915 |
|
|
else
|
12916 |
|
|
do_vfp_nsyn_opcode ("fsqrtd");
|
12917 |
|
|
}
|
12918 |
|
|
|
12919 |
|
|
static void
|
12920 |
|
|
do_vfp_nsyn_div (void)
|
12921 |
|
|
{
|
12922 |
|
|
enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
|
12923 |
|
|
neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
|
12924 |
|
|
N_F32 | N_F64 | N_KEY | N_VFP);
|
12925 |
|
|
|
12926 |
|
|
if (rs == NS_FFF)
|
12927 |
|
|
do_vfp_nsyn_opcode ("fdivs");
|
12928 |
|
|
else
|
12929 |
|
|
do_vfp_nsyn_opcode ("fdivd");
|
12930 |
|
|
}
|
12931 |
|
|
|
12932 |
|
|
static void
|
12933 |
|
|
do_vfp_nsyn_nmul (void)
|
12934 |
|
|
{
|
12935 |
|
|
enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
|
12936 |
|
|
neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
|
12937 |
|
|
N_F32 | N_F64 | N_KEY | N_VFP);
|
12938 |
|
|
|
12939 |
|
|
if (rs == NS_FFF)
|
12940 |
|
|
{
|
12941 |
|
|
NEON_ENCODE (SINGLE, inst);
|
12942 |
|
|
do_vfp_sp_dyadic ();
|
12943 |
|
|
}
|
12944 |
|
|
else
|
12945 |
|
|
{
|
12946 |
|
|
NEON_ENCODE (DOUBLE, inst);
|
12947 |
|
|
do_vfp_dp_rd_rn_rm ();
|
12948 |
|
|
}
|
12949 |
|
|
do_vfp_cond_or_thumb ();
|
12950 |
|
|
}
|
12951 |
|
|
|
12952 |
|
|
static void
|
12953 |
|
|
do_vfp_nsyn_cmp (void)
|
12954 |
|
|
{
|
12955 |
|
|
if (inst.operands[1].isreg)
|
12956 |
|
|
{
|
12957 |
|
|
enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
|
12958 |
|
|
neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
|
12959 |
|
|
|
12960 |
|
|
if (rs == NS_FF)
|
12961 |
|
|
{
|
12962 |
|
|
NEON_ENCODE (SINGLE, inst);
|
12963 |
|
|
do_vfp_sp_monadic ();
|
12964 |
|
|
}
|
12965 |
|
|
else
|
12966 |
|
|
{
|
12967 |
|
|
NEON_ENCODE (DOUBLE, inst);
|
12968 |
|
|
do_vfp_dp_rd_rm ();
|
12969 |
|
|
}
|
12970 |
|
|
}
|
12971 |
|
|
else
|
12972 |
|
|
{
|
12973 |
|
|
enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
|
12974 |
|
|
neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
|
12975 |
|
|
|
12976 |
|
|
switch (inst.instruction & 0x0fffffff)
|
12977 |
|
|
{
|
12978 |
|
|
case N_MNEM_vcmp:
|
12979 |
|
|
inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
|
12980 |
|
|
break;
|
12981 |
|
|
case N_MNEM_vcmpe:
|
12982 |
|
|
inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
|
12983 |
|
|
break;
|
12984 |
|
|
default:
|
12985 |
|
|
abort ();
|
12986 |
|
|
}
|
12987 |
|
|
|
12988 |
|
|
if (rs == NS_FI)
|
12989 |
|
|
{
|
12990 |
|
|
NEON_ENCODE (SINGLE, inst);
|
12991 |
|
|
do_vfp_sp_compare_z ();
|
12992 |
|
|
}
|
12993 |
|
|
else
|
12994 |
|
|
{
|
12995 |
|
|
NEON_ENCODE (DOUBLE, inst);
|
12996 |
|
|
do_vfp_dp_rd ();
|
12997 |
|
|
}
|
12998 |
|
|
}
|
12999 |
|
|
do_vfp_cond_or_thumb ();
|
13000 |
|
|
}
|
13001 |
|
|
|
13002 |
|
|
static void
|
13003 |
|
|
nsyn_insert_sp (void)
|
13004 |
|
|
{
|
13005 |
|
|
inst.operands[1] = inst.operands[0];
|
13006 |
|
|
memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
|
13007 |
|
|
inst.operands[0].reg = REG_SP;
|
13008 |
|
|
inst.operands[0].isreg = 1;
|
13009 |
|
|
inst.operands[0].writeback = 1;
|
13010 |
|
|
inst.operands[0].present = 1;
|
13011 |
|
|
}
|
13012 |
|
|
|
13013 |
|
|
static void
|
13014 |
|
|
do_vfp_nsyn_push (void)
|
13015 |
|
|
{
|
13016 |
|
|
nsyn_insert_sp ();
|
13017 |
|
|
if (inst.operands[1].issingle)
|
13018 |
|
|
do_vfp_nsyn_opcode ("fstmdbs");
|
13019 |
|
|
else
|
13020 |
|
|
do_vfp_nsyn_opcode ("fstmdbd");
|
13021 |
|
|
}
|
13022 |
|
|
|
13023 |
|
|
static void
|
13024 |
|
|
do_vfp_nsyn_pop (void)
|
13025 |
|
|
{
|
13026 |
|
|
nsyn_insert_sp ();
|
13027 |
|
|
if (inst.operands[1].issingle)
|
13028 |
|
|
do_vfp_nsyn_opcode ("fldmias");
|
13029 |
|
|
else
|
13030 |
|
|
do_vfp_nsyn_opcode ("fldmiad");
|
13031 |
|
|
}
|
13032 |
|
|
|
13033 |
|
|
/* Fix up Neon data-processing instructions, ORing in the correct bits for
|
13034 |
|
|
ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
|
13035 |
|
|
|
13036 |
|
|
static void
|
13037 |
|
|
neon_dp_fixup (struct arm_it* insn)
|
13038 |
|
|
{
|
13039 |
|
|
unsigned int i = insn->instruction;
|
13040 |
|
|
insn->is_neon = 1;
|
13041 |
|
|
|
13042 |
|
|
if (thumb_mode)
|
13043 |
|
|
{
|
13044 |
|
|
/* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
|
13045 |
|
|
if (i & (1 << 24))
|
13046 |
|
|
i |= 1 << 28;
|
13047 |
|
|
|
13048 |
|
|
i &= ~(1 << 24);
|
13049 |
|
|
|
13050 |
|
|
i |= 0xef000000;
|
13051 |
|
|
}
|
13052 |
|
|
else
|
13053 |
|
|
i |= 0xf2000000;
|
13054 |
|
|
|
13055 |
|
|
insn->instruction = i;
|
13056 |
|
|
}
|
13057 |
|
|
|
13058 |
|
|
/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
|
13059 |
|
|
(0, 1, 2, 3). */
|
13060 |
|
|
|
13061 |
|
|
static unsigned
|
13062 |
|
|
neon_logbits (unsigned x)
|
13063 |
|
|
{
|
13064 |
|
|
return ffs (x) - 4;
|
13065 |
|
|
}
|
13066 |
|
|
|
13067 |
|
|
#define LOW4(R) ((R) & 0xf)
|
13068 |
|
|
#define HI1(R) (((R) >> 4) & 1)
|
13069 |
|
|
|
13070 |
|
|
/* Encode insns with bit pattern:
|
13071 |
|
|
|
13072 |
|
|
|28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
|
13073 |
|
|
| U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
|
13074 |
|
|
|
13075 |
|
|
SIZE is passed in bits. -1 means size field isn't changed, in case it has a
|
13076 |
|
|
different meaning for some instruction. */
|
13077 |
|
|
|
13078 |
|
|
static void
|
13079 |
|
|
neon_three_same (int isquad, int ubit, int size)
|
13080 |
|
|
{
|
13081 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
13082 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
13083 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
|
13084 |
|
|
inst.instruction |= HI1 (inst.operands[1].reg) << 7;
|
13085 |
|
|
inst.instruction |= LOW4 (inst.operands[2].reg);
|
13086 |
|
|
inst.instruction |= HI1 (inst.operands[2].reg) << 5;
|
13087 |
|
|
inst.instruction |= (isquad != 0) << 6;
|
13088 |
|
|
inst.instruction |= (ubit != 0) << 24;
|
13089 |
|
|
if (size != -1)
|
13090 |
|
|
inst.instruction |= neon_logbits (size) << 20;
|
13091 |
|
|
|
13092 |
|
|
neon_dp_fixup (&inst);
|
13093 |
|
|
}
|
13094 |
|
|
|
13095 |
|
|
/* Encode instructions of the form:
|
13096 |
|
|
|
13097 |
|
|
|28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
|
13098 |
|
|
| U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
|
13099 |
|
|
|
13100 |
|
|
Don't write size if SIZE == -1. */
|
13101 |
|
|
|
13102 |
|
|
static void
|
13103 |
|
|
neon_two_same (int qbit, int ubit, int size)
|
13104 |
|
|
{
|
13105 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
13106 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
13107 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg);
|
13108 |
|
|
inst.instruction |= HI1 (inst.operands[1].reg) << 5;
|
13109 |
|
|
inst.instruction |= (qbit != 0) << 6;
|
13110 |
|
|
inst.instruction |= (ubit != 0) << 24;
|
13111 |
|
|
|
13112 |
|
|
if (size != -1)
|
13113 |
|
|
inst.instruction |= neon_logbits (size) << 18;
|
13114 |
|
|
|
13115 |
|
|
neon_dp_fixup (&inst);
|
13116 |
|
|
}
|
13117 |
|
|
|
13118 |
|
|
/* Neon instruction encoders, in approximate order of appearance. */
|
13119 |
|
|
|
13120 |
|
|
static void
|
13121 |
|
|
do_neon_dyadic_i_su (void)
|
13122 |
|
|
{
|
13123 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
|
13124 |
|
|
struct neon_type_el et = neon_check_type (3, rs,
|
13125 |
|
|
N_EQK, N_EQK, N_SU_32 | N_KEY);
|
13126 |
|
|
neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
|
13127 |
|
|
}
|
13128 |
|
|
|
13129 |
|
|
static void
|
13130 |
|
|
do_neon_dyadic_i64_su (void)
|
13131 |
|
|
{
|
13132 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
|
13133 |
|
|
struct neon_type_el et = neon_check_type (3, rs,
|
13134 |
|
|
N_EQK, N_EQK, N_SU_ALL | N_KEY);
|
13135 |
|
|
neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
|
13136 |
|
|
}
|
13137 |
|
|
|
13138 |
|
|
static void
|
13139 |
|
|
neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
|
13140 |
|
|
unsigned immbits)
|
13141 |
|
|
{
|
13142 |
|
|
unsigned size = et.size >> 3;
|
13143 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
13144 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
13145 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg);
|
13146 |
|
|
inst.instruction |= HI1 (inst.operands[1].reg) << 5;
|
13147 |
|
|
inst.instruction |= (isquad != 0) << 6;
|
13148 |
|
|
inst.instruction |= immbits << 16;
|
13149 |
|
|
inst.instruction |= (size >> 3) << 7;
|
13150 |
|
|
inst.instruction |= (size & 0x7) << 19;
|
13151 |
|
|
if (write_ubit)
|
13152 |
|
|
inst.instruction |= (uval != 0) << 24;
|
13153 |
|
|
|
13154 |
|
|
neon_dp_fixup (&inst);
|
13155 |
|
|
}
|
13156 |
|
|
|
13157 |
|
|
static void
|
13158 |
|
|
do_neon_shl_imm (void)
|
13159 |
|
|
{
|
13160 |
|
|
if (!inst.operands[2].isreg)
|
13161 |
|
|
{
|
13162 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
|
13163 |
|
|
struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
|
13164 |
|
|
NEON_ENCODE (IMMED, inst);
|
13165 |
|
|
neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
|
13166 |
|
|
}
|
13167 |
|
|
else
|
13168 |
|
|
{
|
13169 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
|
13170 |
|
|
struct neon_type_el et = neon_check_type (3, rs,
|
13171 |
|
|
N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
|
13172 |
|
|
unsigned int tmp;
|
13173 |
|
|
|
13174 |
|
|
/* VSHL/VQSHL 3-register variants have syntax such as:
|
13175 |
|
|
vshl.xx Dd, Dm, Dn
|
13176 |
|
|
whereas other 3-register operations encoded by neon_three_same have
|
13177 |
|
|
syntax like:
|
13178 |
|
|
vadd.xx Dd, Dn, Dm
|
13179 |
|
|
(i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
|
13180 |
|
|
here. */
|
13181 |
|
|
tmp = inst.operands[2].reg;
|
13182 |
|
|
inst.operands[2].reg = inst.operands[1].reg;
|
13183 |
|
|
inst.operands[1].reg = tmp;
|
13184 |
|
|
NEON_ENCODE (INTEGER, inst);
|
13185 |
|
|
neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
|
13186 |
|
|
}
|
13187 |
|
|
}
|
13188 |
|
|
|
13189 |
|
|
static void
|
13190 |
|
|
do_neon_qshl_imm (void)
|
13191 |
|
|
{
|
13192 |
|
|
if (!inst.operands[2].isreg)
|
13193 |
|
|
{
|
13194 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
|
13195 |
|
|
struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
|
13196 |
|
|
|
13197 |
|
|
NEON_ENCODE (IMMED, inst);
|
13198 |
|
|
neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
|
13199 |
|
|
inst.operands[2].imm);
|
13200 |
|
|
}
|
13201 |
|
|
else
|
13202 |
|
|
{
|
13203 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
|
13204 |
|
|
struct neon_type_el et = neon_check_type (3, rs,
|
13205 |
|
|
N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
|
13206 |
|
|
unsigned int tmp;
|
13207 |
|
|
|
13208 |
|
|
/* See note in do_neon_shl_imm. */
|
13209 |
|
|
tmp = inst.operands[2].reg;
|
13210 |
|
|
inst.operands[2].reg = inst.operands[1].reg;
|
13211 |
|
|
inst.operands[1].reg = tmp;
|
13212 |
|
|
NEON_ENCODE (INTEGER, inst);
|
13213 |
|
|
neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
|
13214 |
|
|
}
|
13215 |
|
|
}
|
13216 |
|
|
|
13217 |
|
|
static void
|
13218 |
|
|
do_neon_rshl (void)
|
13219 |
|
|
{
|
13220 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
|
13221 |
|
|
struct neon_type_el et = neon_check_type (3, rs,
|
13222 |
|
|
N_EQK, N_EQK, N_SU_ALL | N_KEY);
|
13223 |
|
|
unsigned int tmp;
|
13224 |
|
|
|
13225 |
|
|
tmp = inst.operands[2].reg;
|
13226 |
|
|
inst.operands[2].reg = inst.operands[1].reg;
|
13227 |
|
|
inst.operands[1].reg = tmp;
|
13228 |
|
|
neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
|
13229 |
|
|
}
|
13230 |
|
|
|
13231 |
|
|
static int
|
13232 |
|
|
neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
|
13233 |
|
|
{
|
13234 |
|
|
/* Handle .I8 pseudo-instructions. */
|
13235 |
|
|
if (size == 8)
|
13236 |
|
|
{
|
13237 |
|
|
/* Unfortunately, this will make everything apart from zero out-of-range.
|
13238 |
|
|
FIXME is this the intended semantics? There doesn't seem much point in
|
13239 |
|
|
accepting .I8 if so. */
|
13240 |
|
|
immediate |= immediate << 8;
|
13241 |
|
|
size = 16;
|
13242 |
|
|
}
|
13243 |
|
|
|
13244 |
|
|
if (size >= 32)
|
13245 |
|
|
{
|
13246 |
|
|
if (immediate == (immediate & 0x000000ff))
|
13247 |
|
|
{
|
13248 |
|
|
*immbits = immediate;
|
13249 |
|
|
return 0x1;
|
13250 |
|
|
}
|
13251 |
|
|
else if (immediate == (immediate & 0x0000ff00))
|
13252 |
|
|
{
|
13253 |
|
|
*immbits = immediate >> 8;
|
13254 |
|
|
return 0x3;
|
13255 |
|
|
}
|
13256 |
|
|
else if (immediate == (immediate & 0x00ff0000))
|
13257 |
|
|
{
|
13258 |
|
|
*immbits = immediate >> 16;
|
13259 |
|
|
return 0x5;
|
13260 |
|
|
}
|
13261 |
|
|
else if (immediate == (immediate & 0xff000000))
|
13262 |
|
|
{
|
13263 |
|
|
*immbits = immediate >> 24;
|
13264 |
|
|
return 0x7;
|
13265 |
|
|
}
|
13266 |
|
|
if ((immediate & 0xffff) != (immediate >> 16))
|
13267 |
|
|
goto bad_immediate;
|
13268 |
|
|
immediate &= 0xffff;
|
13269 |
|
|
}
|
13270 |
|
|
|
13271 |
|
|
if (immediate == (immediate & 0x000000ff))
|
13272 |
|
|
{
|
13273 |
|
|
*immbits = immediate;
|
13274 |
|
|
return 0x9;
|
13275 |
|
|
}
|
13276 |
|
|
else if (immediate == (immediate & 0x0000ff00))
|
13277 |
|
|
{
|
13278 |
|
|
*immbits = immediate >> 8;
|
13279 |
|
|
return 0xb;
|
13280 |
|
|
}
|
13281 |
|
|
|
13282 |
|
|
bad_immediate:
|
13283 |
|
|
first_error (_("immediate value out of range"));
|
13284 |
|
|
return FAIL;
|
13285 |
|
|
}
|
13286 |
|
|
|
13287 |
|
|
/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
|
13288 |
|
|
A, B, C, D. */
|
13289 |
|
|
|
13290 |
|
|
static int
|
13291 |
|
|
neon_bits_same_in_bytes (unsigned imm)
|
13292 |
|
|
{
|
13293 |
|
|
return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
|
13294 |
|
|
&& ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
|
13295 |
|
|
&& ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
|
13296 |
|
|
&& ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
|
13297 |
|
|
}
|
13298 |
|
|
|
13299 |
|
|
/* For immediate of above form, return 0bABCD. */
|
13300 |
|
|
|
13301 |
|
|
static unsigned
|
13302 |
|
|
neon_squash_bits (unsigned imm)
|
13303 |
|
|
{
|
13304 |
|
|
return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
|
13305 |
|
|
| ((imm & 0x01000000) >> 21);
|
13306 |
|
|
}
|
13307 |
|
|
|
13308 |
|
|
/* Compress quarter-float representation to 0b...000 abcdefgh. */
|
13309 |
|
|
|
13310 |
|
|
static unsigned
|
13311 |
|
|
neon_qfloat_bits (unsigned imm)
|
13312 |
|
|
{
|
13313 |
|
|
return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
|
13314 |
|
|
}
|
13315 |
|
|
|
13316 |
|
|
/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
|
13317 |
|
|
the instruction. *OP is passed as the initial value of the op field, and
|
13318 |
|
|
may be set to a different value depending on the constant (i.e.
|
13319 |
|
|
"MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
|
13320 |
|
|
MVN). If the immediate looks like a repeated pattern then also
|
13321 |
|
|
try smaller element sizes. */
|
13322 |
|
|
|
13323 |
|
|
static int
|
13324 |
|
|
neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
|
13325 |
|
|
unsigned *immbits, int *op, int size,
|
13326 |
|
|
enum neon_el_type type)
|
13327 |
|
|
{
|
13328 |
|
|
/* Only permit float immediates (including 0.0/-0.0) if the operand type is
|
13329 |
|
|
float. */
|
13330 |
|
|
if (type == NT_float && !float_p)
|
13331 |
|
|
return FAIL;
|
13332 |
|
|
|
13333 |
|
|
if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
|
13334 |
|
|
{
|
13335 |
|
|
if (size != 32 || *op == 1)
|
13336 |
|
|
return FAIL;
|
13337 |
|
|
*immbits = neon_qfloat_bits (immlo);
|
13338 |
|
|
return 0xf;
|
13339 |
|
|
}
|
13340 |
|
|
|
13341 |
|
|
if (size == 64)
|
13342 |
|
|
{
|
13343 |
|
|
if (neon_bits_same_in_bytes (immhi)
|
13344 |
|
|
&& neon_bits_same_in_bytes (immlo))
|
13345 |
|
|
{
|
13346 |
|
|
if (*op == 1)
|
13347 |
|
|
return FAIL;
|
13348 |
|
|
*immbits = (neon_squash_bits (immhi) << 4)
|
13349 |
|
|
| neon_squash_bits (immlo);
|
13350 |
|
|
*op = 1;
|
13351 |
|
|
return 0xe;
|
13352 |
|
|
}
|
13353 |
|
|
|
13354 |
|
|
if (immhi != immlo)
|
13355 |
|
|
return FAIL;
|
13356 |
|
|
}
|
13357 |
|
|
|
13358 |
|
|
if (size >= 32)
|
13359 |
|
|
{
|
13360 |
|
|
if (immlo == (immlo & 0x000000ff))
|
13361 |
|
|
{
|
13362 |
|
|
*immbits = immlo;
|
13363 |
|
|
return 0x0;
|
13364 |
|
|
}
|
13365 |
|
|
else if (immlo == (immlo & 0x0000ff00))
|
13366 |
|
|
{
|
13367 |
|
|
*immbits = immlo >> 8;
|
13368 |
|
|
return 0x2;
|
13369 |
|
|
}
|
13370 |
|
|
else if (immlo == (immlo & 0x00ff0000))
|
13371 |
|
|
{
|
13372 |
|
|
*immbits = immlo >> 16;
|
13373 |
|
|
return 0x4;
|
13374 |
|
|
}
|
13375 |
|
|
else if (immlo == (immlo & 0xff000000))
|
13376 |
|
|
{
|
13377 |
|
|
*immbits = immlo >> 24;
|
13378 |
|
|
return 0x6;
|
13379 |
|
|
}
|
13380 |
|
|
else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
|
13381 |
|
|
{
|
13382 |
|
|
*immbits = (immlo >> 8) & 0xff;
|
13383 |
|
|
return 0xc;
|
13384 |
|
|
}
|
13385 |
|
|
else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
|
13386 |
|
|
{
|
13387 |
|
|
*immbits = (immlo >> 16) & 0xff;
|
13388 |
|
|
return 0xd;
|
13389 |
|
|
}
|
13390 |
|
|
|
13391 |
|
|
if ((immlo & 0xffff) != (immlo >> 16))
|
13392 |
|
|
return FAIL;
|
13393 |
|
|
immlo &= 0xffff;
|
13394 |
|
|
}
|
13395 |
|
|
|
13396 |
|
|
if (size >= 16)
|
13397 |
|
|
{
|
13398 |
|
|
if (immlo == (immlo & 0x000000ff))
|
13399 |
|
|
{
|
13400 |
|
|
*immbits = immlo;
|
13401 |
|
|
return 0x8;
|
13402 |
|
|
}
|
13403 |
|
|
else if (immlo == (immlo & 0x0000ff00))
|
13404 |
|
|
{
|
13405 |
|
|
*immbits = immlo >> 8;
|
13406 |
|
|
return 0xa;
|
13407 |
|
|
}
|
13408 |
|
|
|
13409 |
|
|
if ((immlo & 0xff) != (immlo >> 8))
|
13410 |
|
|
return FAIL;
|
13411 |
|
|
immlo &= 0xff;
|
13412 |
|
|
}
|
13413 |
|
|
|
13414 |
|
|
if (immlo == (immlo & 0x000000ff))
|
13415 |
|
|
{
|
13416 |
|
|
/* Don't allow MVN with 8-bit immediate. */
|
13417 |
|
|
if (*op == 1)
|
13418 |
|
|
return FAIL;
|
13419 |
|
|
*immbits = immlo;
|
13420 |
|
|
return 0xe;
|
13421 |
|
|
}
|
13422 |
|
|
|
13423 |
|
|
return FAIL;
|
13424 |
|
|
}
|
13425 |
|
|
|
13426 |
|
|
/* Write immediate bits [7:0] to the following locations:
|
13427 |
|
|
|
13428 |
|
|
|28/24|23 19|18 16|15 4|3 0|
|
13429 |
|
|
| a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
|
13430 |
|
|
|
13431 |
|
|
This function is used by VMOV/VMVN/VORR/VBIC. */
|
13432 |
|
|
|
13433 |
|
|
static void
|
13434 |
|
|
neon_write_immbits (unsigned immbits)
|
13435 |
|
|
{
|
13436 |
|
|
inst.instruction |= immbits & 0xf;
|
13437 |
|
|
inst.instruction |= ((immbits >> 4) & 0x7) << 16;
|
13438 |
|
|
inst.instruction |= ((immbits >> 7) & 0x1) << 24;
|
13439 |
|
|
}
|
13440 |
|
|
|
13441 |
|
|
/* Invert low-order SIZE bits of XHI:XLO. */
|
13442 |
|
|
|
13443 |
|
|
static void
|
13444 |
|
|
neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
|
13445 |
|
|
{
|
13446 |
|
|
unsigned immlo = xlo ? *xlo : 0;
|
13447 |
|
|
unsigned immhi = xhi ? *xhi : 0;
|
13448 |
|
|
|
13449 |
|
|
switch (size)
|
13450 |
|
|
{
|
13451 |
|
|
case 8:
|
13452 |
|
|
immlo = (~immlo) & 0xff;
|
13453 |
|
|
break;
|
13454 |
|
|
|
13455 |
|
|
case 16:
|
13456 |
|
|
immlo = (~immlo) & 0xffff;
|
13457 |
|
|
break;
|
13458 |
|
|
|
13459 |
|
|
case 64:
|
13460 |
|
|
immhi = (~immhi) & 0xffffffff;
|
13461 |
|
|
/* fall through. */
|
13462 |
|
|
|
13463 |
|
|
case 32:
|
13464 |
|
|
immlo = (~immlo) & 0xffffffff;
|
13465 |
|
|
break;
|
13466 |
|
|
|
13467 |
|
|
default:
|
13468 |
|
|
abort ();
|
13469 |
|
|
}
|
13470 |
|
|
|
13471 |
|
|
if (xlo)
|
13472 |
|
|
*xlo = immlo;
|
13473 |
|
|
|
13474 |
|
|
if (xhi)
|
13475 |
|
|
*xhi = immhi;
|
13476 |
|
|
}
|
13477 |
|
|
|
13478 |
|
|
static void
|
13479 |
|
|
do_neon_logic (void)
|
13480 |
|
|
{
|
13481 |
|
|
if (inst.operands[2].present && inst.operands[2].isreg)
|
13482 |
|
|
{
|
13483 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
|
13484 |
|
|
neon_check_type (3, rs, N_IGNORE_TYPE);
|
13485 |
|
|
/* U bit and size field were set as part of the bitmask. */
|
13486 |
|
|
NEON_ENCODE (INTEGER, inst);
|
13487 |
|
|
neon_three_same (neon_quad (rs), 0, -1);
|
13488 |
|
|
}
|
13489 |
|
|
else
|
13490 |
|
|
{
|
13491 |
|
|
const int three_ops_form = (inst.operands[2].present
|
13492 |
|
|
&& !inst.operands[2].isreg);
|
13493 |
|
|
const int immoperand = (three_ops_form ? 2 : 1);
|
13494 |
|
|
enum neon_shape rs = (three_ops_form
|
13495 |
|
|
? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
|
13496 |
|
|
: neon_select_shape (NS_DI, NS_QI, NS_NULL));
|
13497 |
|
|
struct neon_type_el et = neon_check_type (2, rs,
|
13498 |
|
|
N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
|
13499 |
|
|
enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
|
13500 |
|
|
unsigned immbits;
|
13501 |
|
|
int cmode;
|
13502 |
|
|
|
13503 |
|
|
if (et.type == NT_invtype)
|
13504 |
|
|
return;
|
13505 |
|
|
|
13506 |
|
|
if (three_ops_form)
|
13507 |
|
|
constraint (inst.operands[0].reg != inst.operands[1].reg,
|
13508 |
|
|
_("first and second operands shall be the same register"));
|
13509 |
|
|
|
13510 |
|
|
NEON_ENCODE (IMMED, inst);
|
13511 |
|
|
|
13512 |
|
|
immbits = inst.operands[immoperand].imm;
|
13513 |
|
|
if (et.size == 64)
|
13514 |
|
|
{
|
13515 |
|
|
/* .i64 is a pseudo-op, so the immediate must be a repeating
|
13516 |
|
|
pattern. */
|
13517 |
|
|
if (immbits != (inst.operands[immoperand].regisimm ?
|
13518 |
|
|
inst.operands[immoperand].reg : 0))
|
13519 |
|
|
{
|
13520 |
|
|
/* Set immbits to an invalid constant. */
|
13521 |
|
|
immbits = 0xdeadbeef;
|
13522 |
|
|
}
|
13523 |
|
|
}
|
13524 |
|
|
|
13525 |
|
|
switch (opcode)
|
13526 |
|
|
{
|
13527 |
|
|
case N_MNEM_vbic:
|
13528 |
|
|
cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
|
13529 |
|
|
break;
|
13530 |
|
|
|
13531 |
|
|
case N_MNEM_vorr:
|
13532 |
|
|
cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
|
13533 |
|
|
break;
|
13534 |
|
|
|
13535 |
|
|
case N_MNEM_vand:
|
13536 |
|
|
/* Pseudo-instruction for VBIC. */
|
13537 |
|
|
neon_invert_size (&immbits, 0, et.size);
|
13538 |
|
|
cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
|
13539 |
|
|
break;
|
13540 |
|
|
|
13541 |
|
|
case N_MNEM_vorn:
|
13542 |
|
|
/* Pseudo-instruction for VORR. */
|
13543 |
|
|
neon_invert_size (&immbits, 0, et.size);
|
13544 |
|
|
cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
|
13545 |
|
|
break;
|
13546 |
|
|
|
13547 |
|
|
default:
|
13548 |
|
|
abort ();
|
13549 |
|
|
}
|
13550 |
|
|
|
13551 |
|
|
if (cmode == FAIL)
|
13552 |
|
|
return;
|
13553 |
|
|
|
13554 |
|
|
inst.instruction |= neon_quad (rs) << 6;
|
13555 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
13556 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
13557 |
|
|
inst.instruction |= cmode << 8;
|
13558 |
|
|
neon_write_immbits (immbits);
|
13559 |
|
|
|
13560 |
|
|
neon_dp_fixup (&inst);
|
13561 |
|
|
}
|
13562 |
|
|
}
|
13563 |
|
|
|
13564 |
|
|
static void
|
13565 |
|
|
do_neon_bitfield (void)
|
13566 |
|
|
{
|
13567 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
|
13568 |
|
|
neon_check_type (3, rs, N_IGNORE_TYPE);
|
13569 |
|
|
neon_three_same (neon_quad (rs), 0, -1);
|
13570 |
|
|
}
|
13571 |
|
|
|
13572 |
|
|
static void
|
13573 |
|
|
neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
|
13574 |
|
|
unsigned destbits)
|
13575 |
|
|
{
|
13576 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
|
13577 |
|
|
struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
|
13578 |
|
|
types | N_KEY);
|
13579 |
|
|
if (et.type == NT_float)
|
13580 |
|
|
{
|
13581 |
|
|
NEON_ENCODE (FLOAT, inst);
|
13582 |
|
|
neon_three_same (neon_quad (rs), 0, -1);
|
13583 |
|
|
}
|
13584 |
|
|
else
|
13585 |
|
|
{
|
13586 |
|
|
NEON_ENCODE (INTEGER, inst);
|
13587 |
|
|
neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
|
13588 |
|
|
}
|
13589 |
|
|
}
|
13590 |
|
|
|
13591 |
|
|
static void
|
13592 |
|
|
do_neon_dyadic_if_su (void)
|
13593 |
|
|
{
|
13594 |
|
|
neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
|
13595 |
|
|
}
|
13596 |
|
|
|
13597 |
|
|
static void
|
13598 |
|
|
do_neon_dyadic_if_su_d (void)
|
13599 |
|
|
{
|
13600 |
|
|
/* This version only allow D registers, but that constraint is enforced during
|
13601 |
|
|
operand parsing so we don't need to do anything extra here. */
|
13602 |
|
|
neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
|
13603 |
|
|
}
|
13604 |
|
|
|
13605 |
|
|
static void
|
13606 |
|
|
do_neon_dyadic_if_i_d (void)
|
13607 |
|
|
{
|
13608 |
|
|
/* The "untyped" case can't happen. Do this to stop the "U" bit being
|
13609 |
|
|
affected if we specify unsigned args. */
|
13610 |
|
|
neon_dyadic_misc (NT_untyped, N_IF_32, 0);
|
13611 |
|
|
}
|
13612 |
|
|
|
13613 |
|
|
enum vfp_or_neon_is_neon_bits
|
13614 |
|
|
{
|
13615 |
|
|
NEON_CHECK_CC = 1,
|
13616 |
|
|
NEON_CHECK_ARCH = 2
|
13617 |
|
|
};
|
13618 |
|
|
|
13619 |
|
|
/* Call this function if an instruction which may have belonged to the VFP or
|
13620 |
|
|
Neon instruction sets, but turned out to be a Neon instruction (due to the
|
13621 |
|
|
operand types involved, etc.). We have to check and/or fix-up a couple of
|
13622 |
|
|
things:
|
13623 |
|
|
|
13624 |
|
|
- Make sure the user hasn't attempted to make a Neon instruction
|
13625 |
|
|
conditional.
|
13626 |
|
|
- Alter the value in the condition code field if necessary.
|
13627 |
|
|
- Make sure that the arch supports Neon instructions.
|
13628 |
|
|
|
13629 |
|
|
Which of these operations take place depends on bits from enum
|
13630 |
|
|
vfp_or_neon_is_neon_bits.
|
13631 |
|
|
|
13632 |
|
|
WARNING: This function has side effects! If NEON_CHECK_CC is used and the
|
13633 |
|
|
current instruction's condition is COND_ALWAYS, the condition field is
|
13634 |
|
|
changed to inst.uncond_value. This is necessary because instructions shared
|
13635 |
|
|
between VFP and Neon may be conditional for the VFP variants only, and the
|
13636 |
|
|
unconditional Neon version must have, e.g., 0xF in the condition field. */
|
13637 |
|
|
|
13638 |
|
|
static int
|
13639 |
|
|
vfp_or_neon_is_neon (unsigned check)
|
13640 |
|
|
{
|
13641 |
|
|
/* Conditions are always legal in Thumb mode (IT blocks). */
|
13642 |
|
|
if (!thumb_mode && (check & NEON_CHECK_CC))
|
13643 |
|
|
{
|
13644 |
|
|
if (inst.cond != COND_ALWAYS)
|
13645 |
|
|
{
|
13646 |
|
|
first_error (_(BAD_COND));
|
13647 |
|
|
return FAIL;
|
13648 |
|
|
}
|
13649 |
|
|
if (inst.uncond_value != -1)
|
13650 |
|
|
inst.instruction |= inst.uncond_value << 28;
|
13651 |
|
|
}
|
13652 |
|
|
|
13653 |
|
|
if ((check & NEON_CHECK_ARCH)
|
13654 |
|
|
&& !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
|
13655 |
|
|
{
|
13656 |
|
|
first_error (_(BAD_FPU));
|
13657 |
|
|
return FAIL;
|
13658 |
|
|
}
|
13659 |
|
|
|
13660 |
|
|
return SUCCESS;
|
13661 |
|
|
}
|
13662 |
|
|
|
13663 |
|
|
static void
|
13664 |
|
|
do_neon_addsub_if_i (void)
|
13665 |
|
|
{
|
13666 |
|
|
if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
|
13667 |
|
|
return;
|
13668 |
|
|
|
13669 |
|
|
if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
|
13670 |
|
|
return;
|
13671 |
|
|
|
13672 |
|
|
/* The "untyped" case can't happen. Do this to stop the "U" bit being
|
13673 |
|
|
affected if we specify unsigned args. */
|
13674 |
|
|
neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
|
13675 |
|
|
}
|
13676 |
|
|
|
13677 |
|
|
/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
|
13678 |
|
|
result to be:
|
13679 |
|
|
V<op> A,B (A is operand 0, B is operand 2)
|
13680 |
|
|
to mean:
|
13681 |
|
|
V<op> A,B,A
|
13682 |
|
|
not:
|
13683 |
|
|
V<op> A,B,B
|
13684 |
|
|
so handle that case specially. */
|
13685 |
|
|
|
13686 |
|
|
static void
|
13687 |
|
|
neon_exchange_operands (void)
|
13688 |
|
|
{
|
13689 |
|
|
void *scratch = alloca (sizeof (inst.operands[0]));
|
13690 |
|
|
if (inst.operands[1].present)
|
13691 |
|
|
{
|
13692 |
|
|
/* Swap operands[1] and operands[2]. */
|
13693 |
|
|
memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
|
13694 |
|
|
inst.operands[1] = inst.operands[2];
|
13695 |
|
|
memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
|
13696 |
|
|
}
|
13697 |
|
|
else
|
13698 |
|
|
{
|
13699 |
|
|
inst.operands[1] = inst.operands[2];
|
13700 |
|
|
inst.operands[2] = inst.operands[0];
|
13701 |
|
|
}
|
13702 |
|
|
}
|
13703 |
|
|
|
13704 |
|
|
static void
|
13705 |
|
|
neon_compare (unsigned regtypes, unsigned immtypes, int invert)
|
13706 |
|
|
{
|
13707 |
|
|
if (inst.operands[2].isreg)
|
13708 |
|
|
{
|
13709 |
|
|
if (invert)
|
13710 |
|
|
neon_exchange_operands ();
|
13711 |
|
|
neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
|
13712 |
|
|
}
|
13713 |
|
|
else
|
13714 |
|
|
{
|
13715 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
|
13716 |
|
|
struct neon_type_el et = neon_check_type (2, rs,
|
13717 |
|
|
N_EQK | N_SIZ, immtypes | N_KEY);
|
13718 |
|
|
|
13719 |
|
|
NEON_ENCODE (IMMED, inst);
|
13720 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
13721 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
13722 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg);
|
13723 |
|
|
inst.instruction |= HI1 (inst.operands[1].reg) << 5;
|
13724 |
|
|
inst.instruction |= neon_quad (rs) << 6;
|
13725 |
|
|
inst.instruction |= (et.type == NT_float) << 10;
|
13726 |
|
|
inst.instruction |= neon_logbits (et.size) << 18;
|
13727 |
|
|
|
13728 |
|
|
neon_dp_fixup (&inst);
|
13729 |
|
|
}
|
13730 |
|
|
}
|
13731 |
|
|
|
13732 |
|
|
static void
|
13733 |
|
|
do_neon_cmp (void)
|
13734 |
|
|
{
|
13735 |
|
|
neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
|
13736 |
|
|
}
|
13737 |
|
|
|
13738 |
|
|
static void
|
13739 |
|
|
do_neon_cmp_inv (void)
|
13740 |
|
|
{
|
13741 |
|
|
neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
|
13742 |
|
|
}
|
13743 |
|
|
|
13744 |
|
|
static void
|
13745 |
|
|
do_neon_ceq (void)
|
13746 |
|
|
{
|
13747 |
|
|
neon_compare (N_IF_32, N_IF_32, FALSE);
|
13748 |
|
|
}
|
13749 |
|
|
|
13750 |
|
|
/* For multiply instructions, we have the possibility of 16-bit or 32-bit
|
13751 |
|
|
scalars, which are encoded in 5 bits, M : Rm.
|
13752 |
|
|
For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
|
13753 |
|
|
M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
|
13754 |
|
|
index in M. */
|
13755 |
|
|
|
13756 |
|
|
static unsigned
|
13757 |
|
|
neon_scalar_for_mul (unsigned scalar, unsigned elsize)
|
13758 |
|
|
{
|
13759 |
|
|
unsigned regno = NEON_SCALAR_REG (scalar);
|
13760 |
|
|
unsigned elno = NEON_SCALAR_INDEX (scalar);
|
13761 |
|
|
|
13762 |
|
|
switch (elsize)
|
13763 |
|
|
{
|
13764 |
|
|
case 16:
|
13765 |
|
|
if (regno > 7 || elno > 3)
|
13766 |
|
|
goto bad_scalar;
|
13767 |
|
|
return regno | (elno << 3);
|
13768 |
|
|
|
13769 |
|
|
case 32:
|
13770 |
|
|
if (regno > 15 || elno > 1)
|
13771 |
|
|
goto bad_scalar;
|
13772 |
|
|
return regno | (elno << 4);
|
13773 |
|
|
|
13774 |
|
|
default:
|
13775 |
|
|
bad_scalar:
|
13776 |
|
|
first_error (_("scalar out of range for multiply instruction"));
|
13777 |
|
|
}
|
13778 |
|
|
|
13779 |
|
|
return 0;
|
13780 |
|
|
}
|
13781 |
|
|
|
13782 |
|
|
/* Encode multiply / multiply-accumulate scalar instructions. */
|
13783 |
|
|
|
13784 |
|
|
static void
|
13785 |
|
|
neon_mul_mac (struct neon_type_el et, int ubit)
|
13786 |
|
|
{
|
13787 |
|
|
unsigned scalar;
|
13788 |
|
|
|
13789 |
|
|
/* Give a more helpful error message if we have an invalid type. */
|
13790 |
|
|
if (et.type == NT_invtype)
|
13791 |
|
|
return;
|
13792 |
|
|
|
13793 |
|
|
scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
|
13794 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
13795 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
13796 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
|
13797 |
|
|
inst.instruction |= HI1 (inst.operands[1].reg) << 7;
|
13798 |
|
|
inst.instruction |= LOW4 (scalar);
|
13799 |
|
|
inst.instruction |= HI1 (scalar) << 5;
|
13800 |
|
|
inst.instruction |= (et.type == NT_float) << 8;
|
13801 |
|
|
inst.instruction |= neon_logbits (et.size) << 20;
|
13802 |
|
|
inst.instruction |= (ubit != 0) << 24;
|
13803 |
|
|
|
13804 |
|
|
neon_dp_fixup (&inst);
|
13805 |
|
|
}
|
13806 |
|
|
|
13807 |
|
|
static void
|
13808 |
|
|
do_neon_mac_maybe_scalar (void)
|
13809 |
|
|
{
|
13810 |
|
|
if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
|
13811 |
|
|
return;
|
13812 |
|
|
|
13813 |
|
|
if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
|
13814 |
|
|
return;
|
13815 |
|
|
|
13816 |
|
|
if (inst.operands[2].isscalar)
|
13817 |
|
|
{
|
13818 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
|
13819 |
|
|
struct neon_type_el et = neon_check_type (3, rs,
|
13820 |
|
|
N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
|
13821 |
|
|
NEON_ENCODE (SCALAR, inst);
|
13822 |
|
|
neon_mul_mac (et, neon_quad (rs));
|
13823 |
|
|
}
|
13824 |
|
|
else
|
13825 |
|
|
{
|
13826 |
|
|
/* The "untyped" case can't happen. Do this to stop the "U" bit being
|
13827 |
|
|
affected if we specify unsigned args. */
|
13828 |
|
|
neon_dyadic_misc (NT_untyped, N_IF_32, 0);
|
13829 |
|
|
}
|
13830 |
|
|
}
|
13831 |
|
|
|
13832 |
|
|
static void
|
13833 |
|
|
do_neon_fmac (void)
|
13834 |
|
|
{
|
13835 |
|
|
if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
|
13836 |
|
|
return;
|
13837 |
|
|
|
13838 |
|
|
if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
|
13839 |
|
|
return;
|
13840 |
|
|
|
13841 |
|
|
neon_dyadic_misc (NT_untyped, N_IF_32, 0);
|
13842 |
|
|
}
|
13843 |
|
|
|
13844 |
|
|
static void
|
13845 |
|
|
do_neon_tst (void)
|
13846 |
|
|
{
|
13847 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
|
13848 |
|
|
struct neon_type_el et = neon_check_type (3, rs,
|
13849 |
|
|
N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
|
13850 |
|
|
neon_three_same (neon_quad (rs), 0, et.size);
|
13851 |
|
|
}
|
13852 |
|
|
|
13853 |
|
|
/* VMUL with 3 registers allows the P8 type. The scalar version supports the
|
13854 |
|
|
same types as the MAC equivalents. The polynomial type for this instruction
|
13855 |
|
|
is encoded the same as the integer type. */
|
13856 |
|
|
|
13857 |
|
|
static void
|
13858 |
|
|
do_neon_mul (void)
|
13859 |
|
|
{
|
13860 |
|
|
if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
|
13861 |
|
|
return;
|
13862 |
|
|
|
13863 |
|
|
if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
|
13864 |
|
|
return;
|
13865 |
|
|
|
13866 |
|
|
if (inst.operands[2].isscalar)
|
13867 |
|
|
do_neon_mac_maybe_scalar ();
|
13868 |
|
|
else
|
13869 |
|
|
neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
|
13870 |
|
|
}
|
13871 |
|
|
|
13872 |
|
|
static void
|
13873 |
|
|
do_neon_qdmulh (void)
|
13874 |
|
|
{
|
13875 |
|
|
if (inst.operands[2].isscalar)
|
13876 |
|
|
{
|
13877 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
|
13878 |
|
|
struct neon_type_el et = neon_check_type (3, rs,
|
13879 |
|
|
N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
|
13880 |
|
|
NEON_ENCODE (SCALAR, inst);
|
13881 |
|
|
neon_mul_mac (et, neon_quad (rs));
|
13882 |
|
|
}
|
13883 |
|
|
else
|
13884 |
|
|
{
|
13885 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
|
13886 |
|
|
struct neon_type_el et = neon_check_type (3, rs,
|
13887 |
|
|
N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
|
13888 |
|
|
NEON_ENCODE (INTEGER, inst);
|
13889 |
|
|
/* The U bit (rounding) comes from bit mask. */
|
13890 |
|
|
neon_three_same (neon_quad (rs), 0, et.size);
|
13891 |
|
|
}
|
13892 |
|
|
}
|
13893 |
|
|
|
13894 |
|
|
static void
|
13895 |
|
|
do_neon_fcmp_absolute (void)
|
13896 |
|
|
{
|
13897 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
|
13898 |
|
|
neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
|
13899 |
|
|
/* Size field comes from bit mask. */
|
13900 |
|
|
neon_three_same (neon_quad (rs), 1, -1);
|
13901 |
|
|
}
|
13902 |
|
|
|
13903 |
|
|
static void
|
13904 |
|
|
do_neon_fcmp_absolute_inv (void)
|
13905 |
|
|
{
|
13906 |
|
|
neon_exchange_operands ();
|
13907 |
|
|
do_neon_fcmp_absolute ();
|
13908 |
|
|
}
|
13909 |
|
|
|
13910 |
|
|
static void
|
13911 |
|
|
do_neon_step (void)
|
13912 |
|
|
{
|
13913 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
|
13914 |
|
|
neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
|
13915 |
|
|
neon_three_same (neon_quad (rs), 0, -1);
|
13916 |
|
|
}
|
13917 |
|
|
|
13918 |
|
|
static void
|
13919 |
|
|
do_neon_abs_neg (void)
|
13920 |
|
|
{
|
13921 |
|
|
enum neon_shape rs;
|
13922 |
|
|
struct neon_type_el et;
|
13923 |
|
|
|
13924 |
|
|
if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
|
13925 |
|
|
return;
|
13926 |
|
|
|
13927 |
|
|
if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
|
13928 |
|
|
return;
|
13929 |
|
|
|
13930 |
|
|
rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
|
13931 |
|
|
et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
|
13932 |
|
|
|
13933 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
13934 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
13935 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg);
|
13936 |
|
|
inst.instruction |= HI1 (inst.operands[1].reg) << 5;
|
13937 |
|
|
inst.instruction |= neon_quad (rs) << 6;
|
13938 |
|
|
inst.instruction |= (et.type == NT_float) << 10;
|
13939 |
|
|
inst.instruction |= neon_logbits (et.size) << 18;
|
13940 |
|
|
|
13941 |
|
|
neon_dp_fixup (&inst);
|
13942 |
|
|
}
|
13943 |
|
|
|
13944 |
|
|
static void
|
13945 |
|
|
do_neon_sli (void)
|
13946 |
|
|
{
|
13947 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
|
13948 |
|
|
struct neon_type_el et = neon_check_type (2, rs,
|
13949 |
|
|
N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
|
13950 |
|
|
int imm = inst.operands[2].imm;
|
13951 |
|
|
constraint (imm < 0 || (unsigned)imm >= et.size,
|
13952 |
|
|
_("immediate out of range for insert"));
|
13953 |
|
|
neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
|
13954 |
|
|
}
|
13955 |
|
|
|
13956 |
|
|
static void
|
13957 |
|
|
do_neon_sri (void)
|
13958 |
|
|
{
|
13959 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
|
13960 |
|
|
struct neon_type_el et = neon_check_type (2, rs,
|
13961 |
|
|
N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
|
13962 |
|
|
int imm = inst.operands[2].imm;
|
13963 |
|
|
constraint (imm < 1 || (unsigned)imm > et.size,
|
13964 |
|
|
_("immediate out of range for insert"));
|
13965 |
|
|
neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
|
13966 |
|
|
}
|
13967 |
|
|
|
13968 |
|
|
static void
|
13969 |
|
|
do_neon_qshlu_imm (void)
|
13970 |
|
|
{
|
13971 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
|
13972 |
|
|
struct neon_type_el et = neon_check_type (2, rs,
|
13973 |
|
|
N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
|
13974 |
|
|
int imm = inst.operands[2].imm;
|
13975 |
|
|
constraint (imm < 0 || (unsigned)imm >= et.size,
|
13976 |
|
|
_("immediate out of range for shift"));
|
13977 |
|
|
/* Only encodes the 'U present' variant of the instruction.
|
13978 |
|
|
In this case, signed types have OP (bit 8) set to 0.
|
13979 |
|
|
Unsigned types have OP set to 1. */
|
13980 |
|
|
inst.instruction |= (et.type == NT_unsigned) << 8;
|
13981 |
|
|
/* The rest of the bits are the same as other immediate shifts. */
|
13982 |
|
|
neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
|
13983 |
|
|
}
|
13984 |
|
|
|
13985 |
|
|
static void
|
13986 |
|
|
do_neon_qmovn (void)
|
13987 |
|
|
{
|
13988 |
|
|
struct neon_type_el et = neon_check_type (2, NS_DQ,
|
13989 |
|
|
N_EQK | N_HLF, N_SU_16_64 | N_KEY);
|
13990 |
|
|
/* Saturating move where operands can be signed or unsigned, and the
|
13991 |
|
|
destination has the same signedness. */
|
13992 |
|
|
NEON_ENCODE (INTEGER, inst);
|
13993 |
|
|
if (et.type == NT_unsigned)
|
13994 |
|
|
inst.instruction |= 0xc0;
|
13995 |
|
|
else
|
13996 |
|
|
inst.instruction |= 0x80;
|
13997 |
|
|
neon_two_same (0, 1, et.size / 2);
|
13998 |
|
|
}
|
13999 |
|
|
|
14000 |
|
|
static void
|
14001 |
|
|
do_neon_qmovun (void)
|
14002 |
|
|
{
|
14003 |
|
|
struct neon_type_el et = neon_check_type (2, NS_DQ,
|
14004 |
|
|
N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
|
14005 |
|
|
/* Saturating move with unsigned results. Operands must be signed. */
|
14006 |
|
|
NEON_ENCODE (INTEGER, inst);
|
14007 |
|
|
neon_two_same (0, 1, et.size / 2);
|
14008 |
|
|
}
|
14009 |
|
|
|
14010 |
|
|
static void
|
14011 |
|
|
do_neon_rshift_sat_narrow (void)
|
14012 |
|
|
{
|
14013 |
|
|
/* FIXME: Types for narrowing. If operands are signed, results can be signed
|
14014 |
|
|
or unsigned. If operands are unsigned, results must also be unsigned. */
|
14015 |
|
|
struct neon_type_el et = neon_check_type (2, NS_DQI,
|
14016 |
|
|
N_EQK | N_HLF, N_SU_16_64 | N_KEY);
|
14017 |
|
|
int imm = inst.operands[2].imm;
|
14018 |
|
|
/* This gets the bounds check, size encoding and immediate bits calculation
|
14019 |
|
|
right. */
|
14020 |
|
|
et.size /= 2;
|
14021 |
|
|
|
14022 |
|
|
/* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
|
14023 |
|
|
VQMOVN.I<size> <Dd>, <Qm>. */
|
14024 |
|
|
if (imm == 0)
|
14025 |
|
|
{
|
14026 |
|
|
inst.operands[2].present = 0;
|
14027 |
|
|
inst.instruction = N_MNEM_vqmovn;
|
14028 |
|
|
do_neon_qmovn ();
|
14029 |
|
|
return;
|
14030 |
|
|
}
|
14031 |
|
|
|
14032 |
|
|
constraint (imm < 1 || (unsigned)imm > et.size,
|
14033 |
|
|
_("immediate out of range"));
|
14034 |
|
|
neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
|
14035 |
|
|
}
|
14036 |
|
|
|
14037 |
|
|
static void
|
14038 |
|
|
do_neon_rshift_sat_narrow_u (void)
|
14039 |
|
|
{
|
14040 |
|
|
/* FIXME: Types for narrowing. If operands are signed, results can be signed
|
14041 |
|
|
or unsigned. If operands are unsigned, results must also be unsigned. */
|
14042 |
|
|
struct neon_type_el et = neon_check_type (2, NS_DQI,
|
14043 |
|
|
N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
|
14044 |
|
|
int imm = inst.operands[2].imm;
|
14045 |
|
|
/* This gets the bounds check, size encoding and immediate bits calculation
|
14046 |
|
|
right. */
|
14047 |
|
|
et.size /= 2;
|
14048 |
|
|
|
14049 |
|
|
/* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
|
14050 |
|
|
VQMOVUN.I<size> <Dd>, <Qm>. */
|
14051 |
|
|
if (imm == 0)
|
14052 |
|
|
{
|
14053 |
|
|
inst.operands[2].present = 0;
|
14054 |
|
|
inst.instruction = N_MNEM_vqmovun;
|
14055 |
|
|
do_neon_qmovun ();
|
14056 |
|
|
return;
|
14057 |
|
|
}
|
14058 |
|
|
|
14059 |
|
|
constraint (imm < 1 || (unsigned)imm > et.size,
|
14060 |
|
|
_("immediate out of range"));
|
14061 |
|
|
/* FIXME: The manual is kind of unclear about what value U should have in
|
14062 |
|
|
VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
|
14063 |
|
|
must be 1. */
|
14064 |
|
|
neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
|
14065 |
|
|
}
|
14066 |
|
|
|
14067 |
|
|
static void
|
14068 |
|
|
do_neon_movn (void)
|
14069 |
|
|
{
|
14070 |
|
|
struct neon_type_el et = neon_check_type (2, NS_DQ,
|
14071 |
|
|
N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
|
14072 |
|
|
NEON_ENCODE (INTEGER, inst);
|
14073 |
|
|
neon_two_same (0, 1, et.size / 2);
|
14074 |
|
|
}
|
14075 |
|
|
|
14076 |
|
|
static void
|
14077 |
|
|
do_neon_rshift_narrow (void)
|
14078 |
|
|
{
|
14079 |
|
|
struct neon_type_el et = neon_check_type (2, NS_DQI,
|
14080 |
|
|
N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
|
14081 |
|
|
int imm = inst.operands[2].imm;
|
14082 |
|
|
/* This gets the bounds check, size encoding and immediate bits calculation
|
14083 |
|
|
right. */
|
14084 |
|
|
et.size /= 2;
|
14085 |
|
|
|
14086 |
|
|
/* If immediate is zero then we are a pseudo-instruction for
|
14087 |
|
|
VMOVN.I<size> <Dd>, <Qm> */
|
14088 |
|
|
if (imm == 0)
|
14089 |
|
|
{
|
14090 |
|
|
inst.operands[2].present = 0;
|
14091 |
|
|
inst.instruction = N_MNEM_vmovn;
|
14092 |
|
|
do_neon_movn ();
|
14093 |
|
|
return;
|
14094 |
|
|
}
|
14095 |
|
|
|
14096 |
|
|
constraint (imm < 1 || (unsigned)imm > et.size,
|
14097 |
|
|
_("immediate out of range for narrowing operation"));
|
14098 |
|
|
neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
|
14099 |
|
|
}
|
14100 |
|
|
|
14101 |
|
|
static void
|
14102 |
|
|
do_neon_shll (void)
|
14103 |
|
|
{
|
14104 |
|
|
/* FIXME: Type checking when lengthening. */
|
14105 |
|
|
struct neon_type_el et = neon_check_type (2, NS_QDI,
|
14106 |
|
|
N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
|
14107 |
|
|
unsigned imm = inst.operands[2].imm;
|
14108 |
|
|
|
14109 |
|
|
if (imm == et.size)
|
14110 |
|
|
{
|
14111 |
|
|
/* Maximum shift variant. */
|
14112 |
|
|
NEON_ENCODE (INTEGER, inst);
|
14113 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
14114 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
14115 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg);
|
14116 |
|
|
inst.instruction |= HI1 (inst.operands[1].reg) << 5;
|
14117 |
|
|
inst.instruction |= neon_logbits (et.size) << 18;
|
14118 |
|
|
|
14119 |
|
|
neon_dp_fixup (&inst);
|
14120 |
|
|
}
|
14121 |
|
|
else
|
14122 |
|
|
{
|
14123 |
|
|
/* A more-specific type check for non-max versions. */
|
14124 |
|
|
et = neon_check_type (2, NS_QDI,
|
14125 |
|
|
N_EQK | N_DBL, N_SU_32 | N_KEY);
|
14126 |
|
|
NEON_ENCODE (IMMED, inst);
|
14127 |
|
|
neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
|
14128 |
|
|
}
|
14129 |
|
|
}
|
14130 |
|
|
|
14131 |
|
|
/* Check the various types for the VCVT instruction, and return which version
|
14132 |
|
|
the current instruction is. */
|
14133 |
|
|
|
14134 |
|
|
static int
|
14135 |
|
|
neon_cvt_flavour (enum neon_shape rs)
|
14136 |
|
|
{
|
14137 |
|
|
#define CVT_VAR(C,X,Y) \
|
14138 |
|
|
et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
|
14139 |
|
|
if (et.type != NT_invtype) \
|
14140 |
|
|
{ \
|
14141 |
|
|
inst.error = NULL; \
|
14142 |
|
|
return (C); \
|
14143 |
|
|
}
|
14144 |
|
|
struct neon_type_el et;
|
14145 |
|
|
unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
|
14146 |
|
|
|| rs == NS_FF) ? N_VFP : 0;
|
14147 |
|
|
/* The instruction versions which take an immediate take one register
|
14148 |
|
|
argument, which is extended to the width of the full register. Thus the
|
14149 |
|
|
"source" and "destination" registers must have the same width. Hack that
|
14150 |
|
|
here by making the size equal to the key (wider, in this case) operand. */
|
14151 |
|
|
unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
|
14152 |
|
|
|
14153 |
|
|
CVT_VAR (0, N_S32, N_F32);
|
14154 |
|
|
CVT_VAR (1, N_U32, N_F32);
|
14155 |
|
|
CVT_VAR (2, N_F32, N_S32);
|
14156 |
|
|
CVT_VAR (3, N_F32, N_U32);
|
14157 |
|
|
/* Half-precision conversions. */
|
14158 |
|
|
CVT_VAR (4, N_F32, N_F16);
|
14159 |
|
|
CVT_VAR (5, N_F16, N_F32);
|
14160 |
|
|
|
14161 |
|
|
whole_reg = N_VFP;
|
14162 |
|
|
|
14163 |
|
|
/* VFP instructions. */
|
14164 |
|
|
CVT_VAR (6, N_F32, N_F64);
|
14165 |
|
|
CVT_VAR (7, N_F64, N_F32);
|
14166 |
|
|
CVT_VAR (8, N_S32, N_F64 | key);
|
14167 |
|
|
CVT_VAR (9, N_U32, N_F64 | key);
|
14168 |
|
|
CVT_VAR (10, N_F64 | key, N_S32);
|
14169 |
|
|
CVT_VAR (11, N_F64 | key, N_U32);
|
14170 |
|
|
/* VFP instructions with bitshift. */
|
14171 |
|
|
CVT_VAR (12, N_F32 | key, N_S16);
|
14172 |
|
|
CVT_VAR (13, N_F32 | key, N_U16);
|
14173 |
|
|
CVT_VAR (14, N_F64 | key, N_S16);
|
14174 |
|
|
CVT_VAR (15, N_F64 | key, N_U16);
|
14175 |
|
|
CVT_VAR (16, N_S16, N_F32 | key);
|
14176 |
|
|
CVT_VAR (17, N_U16, N_F32 | key);
|
14177 |
|
|
CVT_VAR (18, N_S16, N_F64 | key);
|
14178 |
|
|
CVT_VAR (19, N_U16, N_F64 | key);
|
14179 |
|
|
|
14180 |
|
|
return -1;
|
14181 |
|
|
#undef CVT_VAR
|
14182 |
|
|
}
|
14183 |
|
|
|
14184 |
|
|
/* Neon-syntax VFP conversions. */
|
14185 |
|
|
|
14186 |
|
|
static void
|
14187 |
|
|
do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
|
14188 |
|
|
{
|
14189 |
|
|
const char *opname = 0;
|
14190 |
|
|
|
14191 |
|
|
if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
|
14192 |
|
|
{
|
14193 |
|
|
/* Conversions with immediate bitshift. */
|
14194 |
|
|
const char *enc[] =
|
14195 |
|
|
{
|
14196 |
|
|
"ftosls",
|
14197 |
|
|
"ftouls",
|
14198 |
|
|
"fsltos",
|
14199 |
|
|
"fultos",
|
14200 |
|
|
NULL,
|
14201 |
|
|
NULL,
|
14202 |
|
|
NULL,
|
14203 |
|
|
NULL,
|
14204 |
|
|
"ftosld",
|
14205 |
|
|
"ftould",
|
14206 |
|
|
"fsltod",
|
14207 |
|
|
"fultod",
|
14208 |
|
|
"fshtos",
|
14209 |
|
|
"fuhtos",
|
14210 |
|
|
"fshtod",
|
14211 |
|
|
"fuhtod",
|
14212 |
|
|
"ftoshs",
|
14213 |
|
|
"ftouhs",
|
14214 |
|
|
"ftoshd",
|
14215 |
|
|
"ftouhd"
|
14216 |
|
|
};
|
14217 |
|
|
|
14218 |
|
|
if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
|
14219 |
|
|
{
|
14220 |
|
|
opname = enc[flavour];
|
14221 |
|
|
constraint (inst.operands[0].reg != inst.operands[1].reg,
|
14222 |
|
|
_("operands 0 and 1 must be the same register"));
|
14223 |
|
|
inst.operands[1] = inst.operands[2];
|
14224 |
|
|
memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
|
14225 |
|
|
}
|
14226 |
|
|
}
|
14227 |
|
|
else
|
14228 |
|
|
{
|
14229 |
|
|
/* Conversions without bitshift. */
|
14230 |
|
|
const char *enc[] =
|
14231 |
|
|
{
|
14232 |
|
|
"ftosis",
|
14233 |
|
|
"ftouis",
|
14234 |
|
|
"fsitos",
|
14235 |
|
|
"fuitos",
|
14236 |
|
|
"NULL",
|
14237 |
|
|
"NULL",
|
14238 |
|
|
"fcvtsd",
|
14239 |
|
|
"fcvtds",
|
14240 |
|
|
"ftosid",
|
14241 |
|
|
"ftouid",
|
14242 |
|
|
"fsitod",
|
14243 |
|
|
"fuitod"
|
14244 |
|
|
};
|
14245 |
|
|
|
14246 |
|
|
if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
|
14247 |
|
|
opname = enc[flavour];
|
14248 |
|
|
}
|
14249 |
|
|
|
14250 |
|
|
if (opname)
|
14251 |
|
|
do_vfp_nsyn_opcode (opname);
|
14252 |
|
|
}
|
14253 |
|
|
|
14254 |
|
|
static void
|
14255 |
|
|
do_vfp_nsyn_cvtz (void)
|
14256 |
|
|
{
|
14257 |
|
|
enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
|
14258 |
|
|
int flavour = neon_cvt_flavour (rs);
|
14259 |
|
|
const char *enc[] =
|
14260 |
|
|
{
|
14261 |
|
|
"ftosizs",
|
14262 |
|
|
"ftouizs",
|
14263 |
|
|
NULL,
|
14264 |
|
|
NULL,
|
14265 |
|
|
NULL,
|
14266 |
|
|
NULL,
|
14267 |
|
|
NULL,
|
14268 |
|
|
NULL,
|
14269 |
|
|
"ftosizd",
|
14270 |
|
|
"ftouizd"
|
14271 |
|
|
};
|
14272 |
|
|
|
14273 |
|
|
if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
|
14274 |
|
|
do_vfp_nsyn_opcode (enc[flavour]);
|
14275 |
|
|
}
|
14276 |
|
|
|
14277 |
|
|
static void
|
14278 |
|
|
do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
|
14279 |
|
|
{
|
14280 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
|
14281 |
|
|
NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
|
14282 |
|
|
int flavour = neon_cvt_flavour (rs);
|
14283 |
|
|
|
14284 |
|
|
/* PR11109: Handle round-to-zero for VCVT conversions. */
|
14285 |
|
|
if (round_to_zero
|
14286 |
|
|
&& ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
|
14287 |
|
|
&& (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9)
|
14288 |
|
|
&& (rs == NS_FD || rs == NS_FF))
|
14289 |
|
|
{
|
14290 |
|
|
do_vfp_nsyn_cvtz ();
|
14291 |
|
|
return;
|
14292 |
|
|
}
|
14293 |
|
|
|
14294 |
|
|
/* VFP rather than Neon conversions. */
|
14295 |
|
|
if (flavour >= 6)
|
14296 |
|
|
{
|
14297 |
|
|
do_vfp_nsyn_cvt (rs, flavour);
|
14298 |
|
|
return;
|
14299 |
|
|
}
|
14300 |
|
|
|
14301 |
|
|
switch (rs)
|
14302 |
|
|
{
|
14303 |
|
|
case NS_DDI:
|
14304 |
|
|
case NS_QQI:
|
14305 |
|
|
{
|
14306 |
|
|
unsigned immbits;
|
14307 |
|
|
unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
|
14308 |
|
|
|
14309 |
|
|
if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
|
14310 |
|
|
return;
|
14311 |
|
|
|
14312 |
|
|
/* Fixed-point conversion with #0 immediate is encoded as an
|
14313 |
|
|
integer conversion. */
|
14314 |
|
|
if (inst.operands[2].present && inst.operands[2].imm == 0)
|
14315 |
|
|
goto int_encode;
|
14316 |
|
|
immbits = 32 - inst.operands[2].imm;
|
14317 |
|
|
NEON_ENCODE (IMMED, inst);
|
14318 |
|
|
if (flavour != -1)
|
14319 |
|
|
inst.instruction |= enctab[flavour];
|
14320 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
14321 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
14322 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg);
|
14323 |
|
|
inst.instruction |= HI1 (inst.operands[1].reg) << 5;
|
14324 |
|
|
inst.instruction |= neon_quad (rs) << 6;
|
14325 |
|
|
inst.instruction |= 1 << 21;
|
14326 |
|
|
inst.instruction |= immbits << 16;
|
14327 |
|
|
|
14328 |
|
|
neon_dp_fixup (&inst);
|
14329 |
|
|
}
|
14330 |
|
|
break;
|
14331 |
|
|
|
14332 |
|
|
case NS_DD:
|
14333 |
|
|
case NS_QQ:
|
14334 |
|
|
int_encode:
|
14335 |
|
|
{
|
14336 |
|
|
unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
|
14337 |
|
|
|
14338 |
|
|
NEON_ENCODE (INTEGER, inst);
|
14339 |
|
|
|
14340 |
|
|
if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
|
14341 |
|
|
return;
|
14342 |
|
|
|
14343 |
|
|
if (flavour != -1)
|
14344 |
|
|
inst.instruction |= enctab[flavour];
|
14345 |
|
|
|
14346 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
14347 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
14348 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg);
|
14349 |
|
|
inst.instruction |= HI1 (inst.operands[1].reg) << 5;
|
14350 |
|
|
inst.instruction |= neon_quad (rs) << 6;
|
14351 |
|
|
inst.instruction |= 2 << 18;
|
14352 |
|
|
|
14353 |
|
|
neon_dp_fixup (&inst);
|
14354 |
|
|
}
|
14355 |
|
|
break;
|
14356 |
|
|
|
14357 |
|
|
/* Half-precision conversions for Advanced SIMD -- neon. */
|
14358 |
|
|
case NS_QD:
|
14359 |
|
|
case NS_DQ:
|
14360 |
|
|
|
14361 |
|
|
if ((rs == NS_DQ)
|
14362 |
|
|
&& (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
|
14363 |
|
|
{
|
14364 |
|
|
as_bad (_("operand size must match register width"));
|
14365 |
|
|
break;
|
14366 |
|
|
}
|
14367 |
|
|
|
14368 |
|
|
if ((rs == NS_QD)
|
14369 |
|
|
&& ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
|
14370 |
|
|
{
|
14371 |
|
|
as_bad (_("operand size must match register width"));
|
14372 |
|
|
break;
|
14373 |
|
|
}
|
14374 |
|
|
|
14375 |
|
|
if (rs == NS_DQ)
|
14376 |
|
|
inst.instruction = 0x3b60600;
|
14377 |
|
|
else
|
14378 |
|
|
inst.instruction = 0x3b60700;
|
14379 |
|
|
|
14380 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
14381 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
14382 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg);
|
14383 |
|
|
inst.instruction |= HI1 (inst.operands[1].reg) << 5;
|
14384 |
|
|
neon_dp_fixup (&inst);
|
14385 |
|
|
break;
|
14386 |
|
|
|
14387 |
|
|
default:
|
14388 |
|
|
/* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
|
14389 |
|
|
do_vfp_nsyn_cvt (rs, flavour);
|
14390 |
|
|
}
|
14391 |
|
|
}
|
14392 |
|
|
|
14393 |
|
|
static void
|
14394 |
|
|
do_neon_cvtr (void)
|
14395 |
|
|
{
|
14396 |
|
|
do_neon_cvt_1 (FALSE);
|
14397 |
|
|
}
|
14398 |
|
|
|
14399 |
|
|
static void
|
14400 |
|
|
do_neon_cvt (void)
|
14401 |
|
|
{
|
14402 |
|
|
do_neon_cvt_1 (TRUE);
|
14403 |
|
|
}
|
14404 |
|
|
|
14405 |
|
|
static void
|
14406 |
|
|
do_neon_cvtb (void)
|
14407 |
|
|
{
|
14408 |
|
|
inst.instruction = 0xeb20a40;
|
14409 |
|
|
|
14410 |
|
|
/* The sizes are attached to the mnemonic. */
|
14411 |
|
|
if (inst.vectype.el[0].type != NT_invtype
|
14412 |
|
|
&& inst.vectype.el[0].size == 16)
|
14413 |
|
|
inst.instruction |= 0x00010000;
|
14414 |
|
|
|
14415 |
|
|
/* Programmer's syntax: the sizes are attached to the operands. */
|
14416 |
|
|
else if (inst.operands[0].vectype.type != NT_invtype
|
14417 |
|
|
&& inst.operands[0].vectype.size == 16)
|
14418 |
|
|
inst.instruction |= 0x00010000;
|
14419 |
|
|
|
14420 |
|
|
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
|
14421 |
|
|
encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
|
14422 |
|
|
do_vfp_cond_or_thumb ();
|
14423 |
|
|
}
|
14424 |
|
|
|
14425 |
|
|
|
14426 |
|
|
static void
|
14427 |
|
|
do_neon_cvtt (void)
|
14428 |
|
|
{
|
14429 |
|
|
do_neon_cvtb ();
|
14430 |
|
|
inst.instruction |= 0x80;
|
14431 |
|
|
}
|
14432 |
|
|
|
14433 |
|
|
static void
|
14434 |
|
|
neon_move_immediate (void)
|
14435 |
|
|
{
|
14436 |
|
|
enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
|
14437 |
|
|
struct neon_type_el et = neon_check_type (2, rs,
|
14438 |
|
|
N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
|
14439 |
|
|
unsigned immlo, immhi = 0, immbits;
|
14440 |
|
|
int op, cmode, float_p;
|
14441 |
|
|
|
14442 |
|
|
constraint (et.type == NT_invtype,
|
14443 |
|
|
_("operand size must be specified for immediate VMOV"));
|
14444 |
|
|
|
14445 |
|
|
/* We start out as an MVN instruction if OP = 1, MOV otherwise. */
|
14446 |
|
|
op = (inst.instruction & (1 << 5)) != 0;
|
14447 |
|
|
|
14448 |
|
|
immlo = inst.operands[1].imm;
|
14449 |
|
|
if (inst.operands[1].regisimm)
|
14450 |
|
|
immhi = inst.operands[1].reg;
|
14451 |
|
|
|
14452 |
|
|
constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
|
14453 |
|
|
_("immediate has bits set outside the operand size"));
|
14454 |
|
|
|
14455 |
|
|
float_p = inst.operands[1].immisfloat;
|
14456 |
|
|
|
14457 |
|
|
if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
|
14458 |
|
|
et.size, et.type)) == FAIL)
|
14459 |
|
|
{
|
14460 |
|
|
/* Invert relevant bits only. */
|
14461 |
|
|
neon_invert_size (&immlo, &immhi, et.size);
|
14462 |
|
|
/* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
|
14463 |
|
|
with one or the other; those cases are caught by
|
14464 |
|
|
neon_cmode_for_move_imm. */
|
14465 |
|
|
op = !op;
|
14466 |
|
|
if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
|
14467 |
|
|
&op, et.size, et.type)) == FAIL)
|
14468 |
|
|
{
|
14469 |
|
|
first_error (_("immediate out of range"));
|
14470 |
|
|
return;
|
14471 |
|
|
}
|
14472 |
|
|
}
|
14473 |
|
|
|
14474 |
|
|
inst.instruction &= ~(1 << 5);
|
14475 |
|
|
inst.instruction |= op << 5;
|
14476 |
|
|
|
14477 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
14478 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
14479 |
|
|
inst.instruction |= neon_quad (rs) << 6;
|
14480 |
|
|
inst.instruction |= cmode << 8;
|
14481 |
|
|
|
14482 |
|
|
neon_write_immbits (immbits);
|
14483 |
|
|
}
|
14484 |
|
|
|
14485 |
|
|
static void
|
14486 |
|
|
do_neon_mvn (void)
|
14487 |
|
|
{
|
14488 |
|
|
if (inst.operands[1].isreg)
|
14489 |
|
|
{
|
14490 |
|
|
enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
|
14491 |
|
|
|
14492 |
|
|
NEON_ENCODE (INTEGER, inst);
|
14493 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
14494 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
14495 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg);
|
14496 |
|
|
inst.instruction |= HI1 (inst.operands[1].reg) << 5;
|
14497 |
|
|
inst.instruction |= neon_quad (rs) << 6;
|
14498 |
|
|
}
|
14499 |
|
|
else
|
14500 |
|
|
{
|
14501 |
|
|
NEON_ENCODE (IMMED, inst);
|
14502 |
|
|
neon_move_immediate ();
|
14503 |
|
|
}
|
14504 |
|
|
|
14505 |
|
|
neon_dp_fixup (&inst);
|
14506 |
|
|
}
|
14507 |
|
|
|
14508 |
|
|
/* Encode instructions of form:
|
14509 |
|
|
|
14510 |
|
|
|28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
|
14511 |
|
|
| U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
|
14512 |
|
|
|
14513 |
|
|
static void
|
14514 |
|
|
neon_mixed_length (struct neon_type_el et, unsigned size)
|
14515 |
|
|
{
|
14516 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
14517 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
14518 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
|
14519 |
|
|
inst.instruction |= HI1 (inst.operands[1].reg) << 7;
|
14520 |
|
|
inst.instruction |= LOW4 (inst.operands[2].reg);
|
14521 |
|
|
inst.instruction |= HI1 (inst.operands[2].reg) << 5;
|
14522 |
|
|
inst.instruction |= (et.type == NT_unsigned) << 24;
|
14523 |
|
|
inst.instruction |= neon_logbits (size) << 20;
|
14524 |
|
|
|
14525 |
|
|
neon_dp_fixup (&inst);
|
14526 |
|
|
}
|
14527 |
|
|
|
14528 |
|
|
static void
|
14529 |
|
|
do_neon_dyadic_long (void)
|
14530 |
|
|
{
|
14531 |
|
|
/* FIXME: Type checking for lengthening op. */
|
14532 |
|
|
struct neon_type_el et = neon_check_type (3, NS_QDD,
|
14533 |
|
|
N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
|
14534 |
|
|
neon_mixed_length (et, et.size);
|
14535 |
|
|
}
|
14536 |
|
|
|
14537 |
|
|
static void
|
14538 |
|
|
do_neon_abal (void)
|
14539 |
|
|
{
|
14540 |
|
|
struct neon_type_el et = neon_check_type (3, NS_QDD,
|
14541 |
|
|
N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
|
14542 |
|
|
neon_mixed_length (et, et.size);
|
14543 |
|
|
}
|
14544 |
|
|
|
14545 |
|
|
static void
|
14546 |
|
|
neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
|
14547 |
|
|
{
|
14548 |
|
|
if (inst.operands[2].isscalar)
|
14549 |
|
|
{
|
14550 |
|
|
struct neon_type_el et = neon_check_type (3, NS_QDS,
|
14551 |
|
|
N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
|
14552 |
|
|
NEON_ENCODE (SCALAR, inst);
|
14553 |
|
|
neon_mul_mac (et, et.type == NT_unsigned);
|
14554 |
|
|
}
|
14555 |
|
|
else
|
14556 |
|
|
{
|
14557 |
|
|
struct neon_type_el et = neon_check_type (3, NS_QDD,
|
14558 |
|
|
N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
|
14559 |
|
|
NEON_ENCODE (INTEGER, inst);
|
14560 |
|
|
neon_mixed_length (et, et.size);
|
14561 |
|
|
}
|
14562 |
|
|
}
|
14563 |
|
|
|
14564 |
|
|
static void
|
14565 |
|
|
do_neon_mac_maybe_scalar_long (void)
|
14566 |
|
|
{
|
14567 |
|
|
neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
|
14568 |
|
|
}
|
14569 |
|
|
|
14570 |
|
|
static void
|
14571 |
|
|
do_neon_dyadic_wide (void)
|
14572 |
|
|
{
|
14573 |
|
|
struct neon_type_el et = neon_check_type (3, NS_QQD,
|
14574 |
|
|
N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
|
14575 |
|
|
neon_mixed_length (et, et.size);
|
14576 |
|
|
}
|
14577 |
|
|
|
14578 |
|
|
static void
|
14579 |
|
|
do_neon_dyadic_narrow (void)
|
14580 |
|
|
{
|
14581 |
|
|
struct neon_type_el et = neon_check_type (3, NS_QDD,
|
14582 |
|
|
N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
|
14583 |
|
|
/* Operand sign is unimportant, and the U bit is part of the opcode,
|
14584 |
|
|
so force the operand type to integer. */
|
14585 |
|
|
et.type = NT_integer;
|
14586 |
|
|
neon_mixed_length (et, et.size / 2);
|
14587 |
|
|
}
|
14588 |
|
|
|
14589 |
|
|
static void
|
14590 |
|
|
do_neon_mul_sat_scalar_long (void)
|
14591 |
|
|
{
|
14592 |
|
|
neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
|
14593 |
|
|
}
|
14594 |
|
|
|
14595 |
|
|
static void
|
14596 |
|
|
do_neon_vmull (void)
|
14597 |
|
|
{
|
14598 |
|
|
if (inst.operands[2].isscalar)
|
14599 |
|
|
do_neon_mac_maybe_scalar_long ();
|
14600 |
|
|
else
|
14601 |
|
|
{
|
14602 |
|
|
struct neon_type_el et = neon_check_type (3, NS_QDD,
|
14603 |
|
|
N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
|
14604 |
|
|
if (et.type == NT_poly)
|
14605 |
|
|
NEON_ENCODE (POLY, inst);
|
14606 |
|
|
else
|
14607 |
|
|
NEON_ENCODE (INTEGER, inst);
|
14608 |
|
|
/* For polynomial encoding, size field must be 0b00 and the U bit must be
|
14609 |
|
|
zero. Should be OK as-is. */
|
14610 |
|
|
neon_mixed_length (et, et.size);
|
14611 |
|
|
}
|
14612 |
|
|
}
|
14613 |
|
|
|
14614 |
|
|
static void
|
14615 |
|
|
do_neon_ext (void)
|
14616 |
|
|
{
|
14617 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
|
14618 |
|
|
struct neon_type_el et = neon_check_type (3, rs,
|
14619 |
|
|
N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
|
14620 |
|
|
unsigned imm = (inst.operands[3].imm * et.size) / 8;
|
14621 |
|
|
|
14622 |
|
|
constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
|
14623 |
|
|
_("shift out of range"));
|
14624 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
14625 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
14626 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
|
14627 |
|
|
inst.instruction |= HI1 (inst.operands[1].reg) << 7;
|
14628 |
|
|
inst.instruction |= LOW4 (inst.operands[2].reg);
|
14629 |
|
|
inst.instruction |= HI1 (inst.operands[2].reg) << 5;
|
14630 |
|
|
inst.instruction |= neon_quad (rs) << 6;
|
14631 |
|
|
inst.instruction |= imm << 8;
|
14632 |
|
|
|
14633 |
|
|
neon_dp_fixup (&inst);
|
14634 |
|
|
}
|
14635 |
|
|
|
14636 |
|
|
static void
|
14637 |
|
|
do_neon_rev (void)
|
14638 |
|
|
{
|
14639 |
|
|
enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
|
14640 |
|
|
struct neon_type_el et = neon_check_type (2, rs,
|
14641 |
|
|
N_EQK, N_8 | N_16 | N_32 | N_KEY);
|
14642 |
|
|
unsigned op = (inst.instruction >> 7) & 3;
|
14643 |
|
|
/* N (width of reversed regions) is encoded as part of the bitmask. We
|
14644 |
|
|
extract it here to check the elements to be reversed are smaller.
|
14645 |
|
|
Otherwise we'd get a reserved instruction. */
|
14646 |
|
|
unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
|
14647 |
|
|
gas_assert (elsize != 0);
|
14648 |
|
|
constraint (et.size >= elsize,
|
14649 |
|
|
_("elements must be smaller than reversal region"));
|
14650 |
|
|
neon_two_same (neon_quad (rs), 1, et.size);
|
14651 |
|
|
}
|
14652 |
|
|
|
14653 |
|
|
static void
|
14654 |
|
|
do_neon_dup (void)
|
14655 |
|
|
{
|
14656 |
|
|
if (inst.operands[1].isscalar)
|
14657 |
|
|
{
|
14658 |
|
|
enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
|
14659 |
|
|
struct neon_type_el et = neon_check_type (2, rs,
|
14660 |
|
|
N_EQK, N_8 | N_16 | N_32 | N_KEY);
|
14661 |
|
|
unsigned sizebits = et.size >> 3;
|
14662 |
|
|
unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
|
14663 |
|
|
int logsize = neon_logbits (et.size);
|
14664 |
|
|
unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
|
14665 |
|
|
|
14666 |
|
|
if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
|
14667 |
|
|
return;
|
14668 |
|
|
|
14669 |
|
|
NEON_ENCODE (SCALAR, inst);
|
14670 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
14671 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
14672 |
|
|
inst.instruction |= LOW4 (dm);
|
14673 |
|
|
inst.instruction |= HI1 (dm) << 5;
|
14674 |
|
|
inst.instruction |= neon_quad (rs) << 6;
|
14675 |
|
|
inst.instruction |= x << 17;
|
14676 |
|
|
inst.instruction |= sizebits << 16;
|
14677 |
|
|
|
14678 |
|
|
neon_dp_fixup (&inst);
|
14679 |
|
|
}
|
14680 |
|
|
else
|
14681 |
|
|
{
|
14682 |
|
|
enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
|
14683 |
|
|
struct neon_type_el et = neon_check_type (2, rs,
|
14684 |
|
|
N_8 | N_16 | N_32 | N_KEY, N_EQK);
|
14685 |
|
|
/* Duplicate ARM register to lanes of vector. */
|
14686 |
|
|
NEON_ENCODE (ARMREG, inst);
|
14687 |
|
|
switch (et.size)
|
14688 |
|
|
{
|
14689 |
|
|
case 8: inst.instruction |= 0x400000; break;
|
14690 |
|
|
case 16: inst.instruction |= 0x000020; break;
|
14691 |
|
|
case 32: inst.instruction |= 0x000000; break;
|
14692 |
|
|
default: break;
|
14693 |
|
|
}
|
14694 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
|
14695 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
|
14696 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 7;
|
14697 |
|
|
inst.instruction |= neon_quad (rs) << 21;
|
14698 |
|
|
/* The encoding for this instruction is identical for the ARM and Thumb
|
14699 |
|
|
variants, except for the condition field. */
|
14700 |
|
|
do_vfp_cond_or_thumb ();
|
14701 |
|
|
}
|
14702 |
|
|
}
|
14703 |
|
|
|
14704 |
|
|
/* VMOV has particularly many variations. It can be one of:
|
14705 |
|
|
0. VMOV<c><q> <Qd>, <Qm>
|
14706 |
|
|
1. VMOV<c><q> <Dd>, <Dm>
|
14707 |
|
|
(Register operations, which are VORR with Rm = Rn.)
|
14708 |
|
|
2. VMOV<c><q>.<dt> <Qd>, #<imm>
|
14709 |
|
|
3. VMOV<c><q>.<dt> <Dd>, #<imm>
|
14710 |
|
|
(Immediate loads.)
|
14711 |
|
|
4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
|
14712 |
|
|
(ARM register to scalar.)
|
14713 |
|
|
5. VMOV<c><q> <Dm>, <Rd>, <Rn>
|
14714 |
|
|
(Two ARM registers to vector.)
|
14715 |
|
|
6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
|
14716 |
|
|
(Scalar to ARM register.)
|
14717 |
|
|
7. VMOV<c><q> <Rd>, <Rn>, <Dm>
|
14718 |
|
|
(Vector to two ARM registers.)
|
14719 |
|
|
8. VMOV.F32 <Sd>, <Sm>
|
14720 |
|
|
9. VMOV.F64 <Dd>, <Dm>
|
14721 |
|
|
(VFP register moves.)
|
14722 |
|
|
10. VMOV.F32 <Sd>, #imm
|
14723 |
|
|
11. VMOV.F64 <Dd>, #imm
|
14724 |
|
|
(VFP float immediate load.)
|
14725 |
|
|
12. VMOV <Rd>, <Sm>
|
14726 |
|
|
(VFP single to ARM reg.)
|
14727 |
|
|
13. VMOV <Sd>, <Rm>
|
14728 |
|
|
(ARM reg to VFP single.)
|
14729 |
|
|
14. VMOV <Rd>, <Re>, <Sn>, <Sm>
|
14730 |
|
|
(Two ARM regs to two VFP singles.)
|
14731 |
|
|
15. VMOV <Sd>, <Se>, <Rn>, <Rm>
|
14732 |
|
|
(Two VFP singles to two ARM regs.)
|
14733 |
|
|
|
14734 |
|
|
These cases can be disambiguated using neon_select_shape, except cases 1/9
|
14735 |
|
|
and 3/11 which depend on the operand type too.
|
14736 |
|
|
|
14737 |
|
|
All the encoded bits are hardcoded by this function.
|
14738 |
|
|
|
14739 |
|
|
Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
|
14740 |
|
|
Cases 5, 7 may be used with VFPv2 and above.
|
14741 |
|
|
|
14742 |
|
|
FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
|
14743 |
|
|
can specify a type where it doesn't make sense to, and is ignored). */
|
14744 |
|
|
|
14745 |
|
|
static void
|
14746 |
|
|
do_neon_mov (void)
|
14747 |
|
|
{
|
14748 |
|
|
enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
|
14749 |
|
|
NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
|
14750 |
|
|
NS_NULL);
|
14751 |
|
|
struct neon_type_el et;
|
14752 |
|
|
const char *ldconst = 0;
|
14753 |
|
|
|
14754 |
|
|
switch (rs)
|
14755 |
|
|
{
|
14756 |
|
|
case NS_DD: /* case 1/9. */
|
14757 |
|
|
et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
|
14758 |
|
|
/* It is not an error here if no type is given. */
|
14759 |
|
|
inst.error = NULL;
|
14760 |
|
|
if (et.type == NT_float && et.size == 64)
|
14761 |
|
|
{
|
14762 |
|
|
do_vfp_nsyn_opcode ("fcpyd");
|
14763 |
|
|
break;
|
14764 |
|
|
}
|
14765 |
|
|
/* fall through. */
|
14766 |
|
|
|
14767 |
|
|
case NS_QQ: /* case 0/1. */
|
14768 |
|
|
{
|
14769 |
|
|
if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
|
14770 |
|
|
return;
|
14771 |
|
|
/* The architecture manual I have doesn't explicitly state which
|
14772 |
|
|
value the U bit should have for register->register moves, but
|
14773 |
|
|
the equivalent VORR instruction has U = 0, so do that. */
|
14774 |
|
|
inst.instruction = 0x0200110;
|
14775 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
14776 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
14777 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg);
|
14778 |
|
|
inst.instruction |= HI1 (inst.operands[1].reg) << 5;
|
14779 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
|
14780 |
|
|
inst.instruction |= HI1 (inst.operands[1].reg) << 7;
|
14781 |
|
|
inst.instruction |= neon_quad (rs) << 6;
|
14782 |
|
|
|
14783 |
|
|
neon_dp_fixup (&inst);
|
14784 |
|
|
}
|
14785 |
|
|
break;
|
14786 |
|
|
|
14787 |
|
|
case NS_DI: /* case 3/11. */
|
14788 |
|
|
et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
|
14789 |
|
|
inst.error = NULL;
|
14790 |
|
|
if (et.type == NT_float && et.size == 64)
|
14791 |
|
|
{
|
14792 |
|
|
/* case 11 (fconstd). */
|
14793 |
|
|
ldconst = "fconstd";
|
14794 |
|
|
goto encode_fconstd;
|
14795 |
|
|
}
|
14796 |
|
|
/* fall through. */
|
14797 |
|
|
|
14798 |
|
|
case NS_QI: /* case 2/3. */
|
14799 |
|
|
if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
|
14800 |
|
|
return;
|
14801 |
|
|
inst.instruction = 0x0800010;
|
14802 |
|
|
neon_move_immediate ();
|
14803 |
|
|
neon_dp_fixup (&inst);
|
14804 |
|
|
break;
|
14805 |
|
|
|
14806 |
|
|
case NS_SR: /* case 4. */
|
14807 |
|
|
{
|
14808 |
|
|
unsigned bcdebits = 0;
|
14809 |
|
|
int logsize;
|
14810 |
|
|
unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
|
14811 |
|
|
unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
|
14812 |
|
|
|
14813 |
|
|
et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
|
14814 |
|
|
logsize = neon_logbits (et.size);
|
14815 |
|
|
|
14816 |
|
|
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
|
14817 |
|
|
_(BAD_FPU));
|
14818 |
|
|
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
|
14819 |
|
|
&& et.size != 32, _(BAD_FPU));
|
14820 |
|
|
constraint (et.type == NT_invtype, _("bad type for scalar"));
|
14821 |
|
|
constraint (x >= 64 / et.size, _("scalar index out of range"));
|
14822 |
|
|
|
14823 |
|
|
switch (et.size)
|
14824 |
|
|
{
|
14825 |
|
|
case 8: bcdebits = 0x8; break;
|
14826 |
|
|
case 16: bcdebits = 0x1; break;
|
14827 |
|
|
case 32: bcdebits = 0x0; break;
|
14828 |
|
|
default: ;
|
14829 |
|
|
}
|
14830 |
|
|
|
14831 |
|
|
bcdebits |= x << logsize;
|
14832 |
|
|
|
14833 |
|
|
inst.instruction = 0xe000b10;
|
14834 |
|
|
do_vfp_cond_or_thumb ();
|
14835 |
|
|
inst.instruction |= LOW4 (dn) << 16;
|
14836 |
|
|
inst.instruction |= HI1 (dn) << 7;
|
14837 |
|
|
inst.instruction |= inst.operands[1].reg << 12;
|
14838 |
|
|
inst.instruction |= (bcdebits & 3) << 5;
|
14839 |
|
|
inst.instruction |= (bcdebits >> 2) << 21;
|
14840 |
|
|
}
|
14841 |
|
|
break;
|
14842 |
|
|
|
14843 |
|
|
case NS_DRR: /* case 5 (fmdrr). */
|
14844 |
|
|
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
|
14845 |
|
|
_(BAD_FPU));
|
14846 |
|
|
|
14847 |
|
|
inst.instruction = 0xc400b10;
|
14848 |
|
|
do_vfp_cond_or_thumb ();
|
14849 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg);
|
14850 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 5;
|
14851 |
|
|
inst.instruction |= inst.operands[1].reg << 12;
|
14852 |
|
|
inst.instruction |= inst.operands[2].reg << 16;
|
14853 |
|
|
break;
|
14854 |
|
|
|
14855 |
|
|
case NS_RS: /* case 6. */
|
14856 |
|
|
{
|
14857 |
|
|
unsigned logsize;
|
14858 |
|
|
unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
|
14859 |
|
|
unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
|
14860 |
|
|
unsigned abcdebits = 0;
|
14861 |
|
|
|
14862 |
|
|
et = neon_check_type (2, NS_NULL,
|
14863 |
|
|
N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
|
14864 |
|
|
logsize = neon_logbits (et.size);
|
14865 |
|
|
|
14866 |
|
|
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
|
14867 |
|
|
_(BAD_FPU));
|
14868 |
|
|
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
|
14869 |
|
|
&& et.size != 32, _(BAD_FPU));
|
14870 |
|
|
constraint (et.type == NT_invtype, _("bad type for scalar"));
|
14871 |
|
|
constraint (x >= 64 / et.size, _("scalar index out of range"));
|
14872 |
|
|
|
14873 |
|
|
switch (et.size)
|
14874 |
|
|
{
|
14875 |
|
|
case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
|
14876 |
|
|
case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
|
14877 |
|
|
case 32: abcdebits = 0x00; break;
|
14878 |
|
|
default: ;
|
14879 |
|
|
}
|
14880 |
|
|
|
14881 |
|
|
abcdebits |= x << logsize;
|
14882 |
|
|
inst.instruction = 0xe100b10;
|
14883 |
|
|
do_vfp_cond_or_thumb ();
|
14884 |
|
|
inst.instruction |= LOW4 (dn) << 16;
|
14885 |
|
|
inst.instruction |= HI1 (dn) << 7;
|
14886 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
14887 |
|
|
inst.instruction |= (abcdebits & 3) << 5;
|
14888 |
|
|
inst.instruction |= (abcdebits >> 2) << 21;
|
14889 |
|
|
}
|
14890 |
|
|
break;
|
14891 |
|
|
|
14892 |
|
|
case NS_RRD: /* case 7 (fmrrd). */
|
14893 |
|
|
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
|
14894 |
|
|
_(BAD_FPU));
|
14895 |
|
|
|
14896 |
|
|
inst.instruction = 0xc500b10;
|
14897 |
|
|
do_vfp_cond_or_thumb ();
|
14898 |
|
|
inst.instruction |= inst.operands[0].reg << 12;
|
14899 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
14900 |
|
|
inst.instruction |= LOW4 (inst.operands[2].reg);
|
14901 |
|
|
inst.instruction |= HI1 (inst.operands[2].reg) << 5;
|
14902 |
|
|
break;
|
14903 |
|
|
|
14904 |
|
|
case NS_FF: /* case 8 (fcpys). */
|
14905 |
|
|
do_vfp_nsyn_opcode ("fcpys");
|
14906 |
|
|
break;
|
14907 |
|
|
|
14908 |
|
|
case NS_FI: /* case 10 (fconsts). */
|
14909 |
|
|
ldconst = "fconsts";
|
14910 |
|
|
encode_fconstd:
|
14911 |
|
|
if (is_quarter_float (inst.operands[1].imm))
|
14912 |
|
|
{
|
14913 |
|
|
inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
|
14914 |
|
|
do_vfp_nsyn_opcode (ldconst);
|
14915 |
|
|
}
|
14916 |
|
|
else
|
14917 |
|
|
first_error (_("immediate out of range"));
|
14918 |
|
|
break;
|
14919 |
|
|
|
14920 |
|
|
case NS_RF: /* case 12 (fmrs). */
|
14921 |
|
|
do_vfp_nsyn_opcode ("fmrs");
|
14922 |
|
|
break;
|
14923 |
|
|
|
14924 |
|
|
case NS_FR: /* case 13 (fmsr). */
|
14925 |
|
|
do_vfp_nsyn_opcode ("fmsr");
|
14926 |
|
|
break;
|
14927 |
|
|
|
14928 |
|
|
/* The encoders for the fmrrs and fmsrr instructions expect three operands
|
14929 |
|
|
(one of which is a list), but we have parsed four. Do some fiddling to
|
14930 |
|
|
make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
|
14931 |
|
|
expect. */
|
14932 |
|
|
case NS_RRFF: /* case 14 (fmrrs). */
|
14933 |
|
|
constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
|
14934 |
|
|
_("VFP registers must be adjacent"));
|
14935 |
|
|
inst.operands[2].imm = 2;
|
14936 |
|
|
memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
|
14937 |
|
|
do_vfp_nsyn_opcode ("fmrrs");
|
14938 |
|
|
break;
|
14939 |
|
|
|
14940 |
|
|
case NS_FFRR: /* case 15 (fmsrr). */
|
14941 |
|
|
constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
|
14942 |
|
|
_("VFP registers must be adjacent"));
|
14943 |
|
|
inst.operands[1] = inst.operands[2];
|
14944 |
|
|
inst.operands[2] = inst.operands[3];
|
14945 |
|
|
inst.operands[0].imm = 2;
|
14946 |
|
|
memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
|
14947 |
|
|
do_vfp_nsyn_opcode ("fmsrr");
|
14948 |
|
|
break;
|
14949 |
|
|
|
14950 |
|
|
default:
|
14951 |
|
|
abort ();
|
14952 |
|
|
}
|
14953 |
|
|
}
|
14954 |
|
|
|
14955 |
|
|
static void
|
14956 |
|
|
do_neon_rshift_round_imm (void)
|
14957 |
|
|
{
|
14958 |
|
|
enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
|
14959 |
|
|
struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
|
14960 |
|
|
int imm = inst.operands[2].imm;
|
14961 |
|
|
|
14962 |
|
|
/* imm == 0 case is encoded as VMOV for V{R}SHR. */
|
14963 |
|
|
if (imm == 0)
|
14964 |
|
|
{
|
14965 |
|
|
inst.operands[2].present = 0;
|
14966 |
|
|
do_neon_mov ();
|
14967 |
|
|
return;
|
14968 |
|
|
}
|
14969 |
|
|
|
14970 |
|
|
constraint (imm < 1 || (unsigned)imm > et.size,
|
14971 |
|
|
_("immediate out of range for shift"));
|
14972 |
|
|
neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
|
14973 |
|
|
et.size - imm);
|
14974 |
|
|
}
|
14975 |
|
|
|
14976 |
|
|
static void
|
14977 |
|
|
do_neon_movl (void)
|
14978 |
|
|
{
|
14979 |
|
|
struct neon_type_el et = neon_check_type (2, NS_QD,
|
14980 |
|
|
N_EQK | N_DBL, N_SU_32 | N_KEY);
|
14981 |
|
|
unsigned sizebits = et.size >> 3;
|
14982 |
|
|
inst.instruction |= sizebits << 19;
|
14983 |
|
|
neon_two_same (0, et.type == NT_unsigned, -1);
|
14984 |
|
|
}
|
14985 |
|
|
|
14986 |
|
|
static void
|
14987 |
|
|
do_neon_trn (void)
|
14988 |
|
|
{
|
14989 |
|
|
enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
|
14990 |
|
|
struct neon_type_el et = neon_check_type (2, rs,
|
14991 |
|
|
N_EQK, N_8 | N_16 | N_32 | N_KEY);
|
14992 |
|
|
NEON_ENCODE (INTEGER, inst);
|
14993 |
|
|
neon_two_same (neon_quad (rs), 1, et.size);
|
14994 |
|
|
}
|
14995 |
|
|
|
14996 |
|
|
static void
|
14997 |
|
|
do_neon_zip_uzp (void)
|
14998 |
|
|
{
|
14999 |
|
|
enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
|
15000 |
|
|
struct neon_type_el et = neon_check_type (2, rs,
|
15001 |
|
|
N_EQK, N_8 | N_16 | N_32 | N_KEY);
|
15002 |
|
|
if (rs == NS_DD && et.size == 32)
|
15003 |
|
|
{
|
15004 |
|
|
/* Special case: encode as VTRN.32 <Dd>, <Dm>. */
|
15005 |
|
|
inst.instruction = N_MNEM_vtrn;
|
15006 |
|
|
do_neon_trn ();
|
15007 |
|
|
return;
|
15008 |
|
|
}
|
15009 |
|
|
neon_two_same (neon_quad (rs), 1, et.size);
|
15010 |
|
|
}
|
15011 |
|
|
|
15012 |
|
|
static void
|
15013 |
|
|
do_neon_sat_abs_neg (void)
|
15014 |
|
|
{
|
15015 |
|
|
enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
|
15016 |
|
|
struct neon_type_el et = neon_check_type (2, rs,
|
15017 |
|
|
N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
|
15018 |
|
|
neon_two_same (neon_quad (rs), 1, et.size);
|
15019 |
|
|
}
|
15020 |
|
|
|
15021 |
|
|
static void
|
15022 |
|
|
do_neon_pair_long (void)
|
15023 |
|
|
{
|
15024 |
|
|
enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
|
15025 |
|
|
struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
|
15026 |
|
|
/* Unsigned is encoded in OP field (bit 7) for these instruction. */
|
15027 |
|
|
inst.instruction |= (et.type == NT_unsigned) << 7;
|
15028 |
|
|
neon_two_same (neon_quad (rs), 1, et.size);
|
15029 |
|
|
}
|
15030 |
|
|
|
15031 |
|
|
static void
|
15032 |
|
|
do_neon_recip_est (void)
|
15033 |
|
|
{
|
15034 |
|
|
enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
|
15035 |
|
|
struct neon_type_el et = neon_check_type (2, rs,
|
15036 |
|
|
N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
|
15037 |
|
|
inst.instruction |= (et.type == NT_float) << 8;
|
15038 |
|
|
neon_two_same (neon_quad (rs), 1, et.size);
|
15039 |
|
|
}
|
15040 |
|
|
|
15041 |
|
|
static void
|
15042 |
|
|
do_neon_cls (void)
|
15043 |
|
|
{
|
15044 |
|
|
enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
|
15045 |
|
|
struct neon_type_el et = neon_check_type (2, rs,
|
15046 |
|
|
N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
|
15047 |
|
|
neon_two_same (neon_quad (rs), 1, et.size);
|
15048 |
|
|
}
|
15049 |
|
|
|
15050 |
|
|
static void
|
15051 |
|
|
do_neon_clz (void)
|
15052 |
|
|
{
|
15053 |
|
|
enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
|
15054 |
|
|
struct neon_type_el et = neon_check_type (2, rs,
|
15055 |
|
|
N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
|
15056 |
|
|
neon_two_same (neon_quad (rs), 1, et.size);
|
15057 |
|
|
}
|
15058 |
|
|
|
15059 |
|
|
static void
|
15060 |
|
|
do_neon_cnt (void)
|
15061 |
|
|
{
|
15062 |
|
|
enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
|
15063 |
|
|
struct neon_type_el et = neon_check_type (2, rs,
|
15064 |
|
|
N_EQK | N_INT, N_8 | N_KEY);
|
15065 |
|
|
neon_two_same (neon_quad (rs), 1, et.size);
|
15066 |
|
|
}
|
15067 |
|
|
|
15068 |
|
|
static void
|
15069 |
|
|
do_neon_swp (void)
|
15070 |
|
|
{
|
15071 |
|
|
enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
|
15072 |
|
|
neon_two_same (neon_quad (rs), 1, -1);
|
15073 |
|
|
}
|
15074 |
|
|
|
15075 |
|
|
static void
|
15076 |
|
|
do_neon_tbl_tbx (void)
|
15077 |
|
|
{
|
15078 |
|
|
unsigned listlenbits;
|
15079 |
|
|
neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
|
15080 |
|
|
|
15081 |
|
|
if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
|
15082 |
|
|
{
|
15083 |
|
|
first_error (_("bad list length for table lookup"));
|
15084 |
|
|
return;
|
15085 |
|
|
}
|
15086 |
|
|
|
15087 |
|
|
listlenbits = inst.operands[1].imm - 1;
|
15088 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
15089 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
15090 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
|
15091 |
|
|
inst.instruction |= HI1 (inst.operands[1].reg) << 7;
|
15092 |
|
|
inst.instruction |= LOW4 (inst.operands[2].reg);
|
15093 |
|
|
inst.instruction |= HI1 (inst.operands[2].reg) << 5;
|
15094 |
|
|
inst.instruction |= listlenbits << 8;
|
15095 |
|
|
|
15096 |
|
|
neon_dp_fixup (&inst);
|
15097 |
|
|
}
|
15098 |
|
|
|
15099 |
|
|
static void
|
15100 |
|
|
do_neon_ldm_stm (void)
|
15101 |
|
|
{
|
15102 |
|
|
/* P, U and L bits are part of bitmask. */
|
15103 |
|
|
int is_dbmode = (inst.instruction & (1 << 24)) != 0;
|
15104 |
|
|
unsigned offsetbits = inst.operands[1].imm * 2;
|
15105 |
|
|
|
15106 |
|
|
if (inst.operands[1].issingle)
|
15107 |
|
|
{
|
15108 |
|
|
do_vfp_nsyn_ldm_stm (is_dbmode);
|
15109 |
|
|
return;
|
15110 |
|
|
}
|
15111 |
|
|
|
15112 |
|
|
constraint (is_dbmode && !inst.operands[0].writeback,
|
15113 |
|
|
_("writeback (!) must be used for VLDMDB and VSTMDB"));
|
15114 |
|
|
|
15115 |
|
|
constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
|
15116 |
|
|
_("register list must contain at least 1 and at most 16 "
|
15117 |
|
|
"registers"));
|
15118 |
|
|
|
15119 |
|
|
inst.instruction |= inst.operands[0].reg << 16;
|
15120 |
|
|
inst.instruction |= inst.operands[0].writeback << 21;
|
15121 |
|
|
inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
|
15122 |
|
|
inst.instruction |= HI1 (inst.operands[1].reg) << 22;
|
15123 |
|
|
|
15124 |
|
|
inst.instruction |= offsetbits;
|
15125 |
|
|
|
15126 |
|
|
do_vfp_cond_or_thumb ();
|
15127 |
|
|
}
|
15128 |
|
|
|
15129 |
|
|
static void
|
15130 |
|
|
do_neon_ldr_str (void)
|
15131 |
|
|
{
|
15132 |
|
|
int is_ldr = (inst.instruction & (1 << 20)) != 0;
|
15133 |
|
|
|
15134 |
|
|
/* Use of PC in vstr in ARM mode is deprecated in ARMv7.
|
15135 |
|
|
And is UNPREDICTABLE in thumb mode. */
|
15136 |
|
|
if (!is_ldr
|
15137 |
|
|
&& inst.operands[1].reg == REG_PC
|
15138 |
|
|
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
|
15139 |
|
|
{
|
15140 |
|
|
if (!thumb_mode && warn_on_deprecated)
|
15141 |
|
|
as_warn (_("Use of PC here is deprecated"));
|
15142 |
|
|
else
|
15143 |
|
|
inst.error = _("Use of PC here is UNPREDICTABLE");
|
15144 |
|
|
}
|
15145 |
|
|
|
15146 |
|
|
if (inst.operands[0].issingle)
|
15147 |
|
|
{
|
15148 |
|
|
if (is_ldr)
|
15149 |
|
|
do_vfp_nsyn_opcode ("flds");
|
15150 |
|
|
else
|
15151 |
|
|
do_vfp_nsyn_opcode ("fsts");
|
15152 |
|
|
}
|
15153 |
|
|
else
|
15154 |
|
|
{
|
15155 |
|
|
if (is_ldr)
|
15156 |
|
|
do_vfp_nsyn_opcode ("fldd");
|
15157 |
|
|
else
|
15158 |
|
|
do_vfp_nsyn_opcode ("fstd");
|
15159 |
|
|
}
|
15160 |
|
|
}
|
15161 |
|
|
|
15162 |
|
|
/* "interleave" version also handles non-interleaving register VLD1/VST1
|
15163 |
|
|
instructions. */
|
15164 |
|
|
|
15165 |
|
|
static void
|
15166 |
|
|
do_neon_ld_st_interleave (void)
|
15167 |
|
|
{
|
15168 |
|
|
struct neon_type_el et = neon_check_type (1, NS_NULL,
|
15169 |
|
|
N_8 | N_16 | N_32 | N_64);
|
15170 |
|
|
unsigned alignbits = 0;
|
15171 |
|
|
unsigned idx;
|
15172 |
|
|
/* The bits in this table go:
|
15173 |
|
|
0: register stride of one (0) or two (1)
|
15174 |
|
|
1,2: register list length, minus one (1, 2, 3, 4).
|
15175 |
|
|
3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
|
15176 |
|
|
We use -1 for invalid entries. */
|
15177 |
|
|
const int typetable[] =
|
15178 |
|
|
{
|
15179 |
|
|
0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
|
15180 |
|
|
-1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
|
15181 |
|
|
-1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
|
15182 |
|
|
-1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
|
15183 |
|
|
};
|
15184 |
|
|
int typebits;
|
15185 |
|
|
|
15186 |
|
|
if (et.type == NT_invtype)
|
15187 |
|
|
return;
|
15188 |
|
|
|
15189 |
|
|
if (inst.operands[1].immisalign)
|
15190 |
|
|
switch (inst.operands[1].imm >> 8)
|
15191 |
|
|
{
|
15192 |
|
|
case 64: alignbits = 1; break;
|
15193 |
|
|
case 128:
|
15194 |
|
|
if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
|
15195 |
|
|
&& NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
|
15196 |
|
|
goto bad_alignment;
|
15197 |
|
|
alignbits = 2;
|
15198 |
|
|
break;
|
15199 |
|
|
case 256:
|
15200 |
|
|
if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
|
15201 |
|
|
goto bad_alignment;
|
15202 |
|
|
alignbits = 3;
|
15203 |
|
|
break;
|
15204 |
|
|
default:
|
15205 |
|
|
bad_alignment:
|
15206 |
|
|
first_error (_("bad alignment"));
|
15207 |
|
|
return;
|
15208 |
|
|
}
|
15209 |
|
|
|
15210 |
|
|
inst.instruction |= alignbits << 4;
|
15211 |
|
|
inst.instruction |= neon_logbits (et.size) << 6;
|
15212 |
|
|
|
15213 |
|
|
/* Bits [4:6] of the immediate in a list specifier encode register stride
|
15214 |
|
|
(minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
|
15215 |
|
|
VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
|
15216 |
|
|
up the right value for "type" in a table based on this value and the given
|
15217 |
|
|
list style, then stick it back. */
|
15218 |
|
|
idx = ((inst.operands[0].imm >> 4) & 7)
|
15219 |
|
|
| (((inst.instruction >> 8) & 3) << 3);
|
15220 |
|
|
|
15221 |
|
|
typebits = typetable[idx];
|
15222 |
|
|
|
15223 |
|
|
constraint (typebits == -1, _("bad list type for instruction"));
|
15224 |
|
|
|
15225 |
|
|
inst.instruction &= ~0xf00;
|
15226 |
|
|
inst.instruction |= typebits << 8;
|
15227 |
|
|
}
|
15228 |
|
|
|
15229 |
|
|
/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
|
15230 |
|
|
*DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
|
15231 |
|
|
otherwise. The variable arguments are a list of pairs of legal (size, align)
|
15232 |
|
|
values, terminated with -1. */
|
15233 |
|
|
|
15234 |
|
|
static int
|
15235 |
|
|
neon_alignment_bit (int size, int align, int *do_align, ...)
|
15236 |
|
|
{
|
15237 |
|
|
va_list ap;
|
15238 |
|
|
int result = FAIL, thissize, thisalign;
|
15239 |
|
|
|
15240 |
|
|
if (!inst.operands[1].immisalign)
|
15241 |
|
|
{
|
15242 |
|
|
*do_align = 0;
|
15243 |
|
|
return SUCCESS;
|
15244 |
|
|
}
|
15245 |
|
|
|
15246 |
|
|
va_start (ap, do_align);
|
15247 |
|
|
|
15248 |
|
|
do
|
15249 |
|
|
{
|
15250 |
|
|
thissize = va_arg (ap, int);
|
15251 |
|
|
if (thissize == -1)
|
15252 |
|
|
break;
|
15253 |
|
|
thisalign = va_arg (ap, int);
|
15254 |
|
|
|
15255 |
|
|
if (size == thissize && align == thisalign)
|
15256 |
|
|
result = SUCCESS;
|
15257 |
|
|
}
|
15258 |
|
|
while (result != SUCCESS);
|
15259 |
|
|
|
15260 |
|
|
va_end (ap);
|
15261 |
|
|
|
15262 |
|
|
if (result == SUCCESS)
|
15263 |
|
|
*do_align = 1;
|
15264 |
|
|
else
|
15265 |
|
|
first_error (_("unsupported alignment for instruction"));
|
15266 |
|
|
|
15267 |
|
|
return result;
|
15268 |
|
|
}
|
15269 |
|
|
|
15270 |
|
|
static void
|
15271 |
|
|
do_neon_ld_st_lane (void)
|
15272 |
|
|
{
|
15273 |
|
|
struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
|
15274 |
|
|
int align_good, do_align = 0;
|
15275 |
|
|
int logsize = neon_logbits (et.size);
|
15276 |
|
|
int align = inst.operands[1].imm >> 8;
|
15277 |
|
|
int n = (inst.instruction >> 8) & 3;
|
15278 |
|
|
int max_el = 64 / et.size;
|
15279 |
|
|
|
15280 |
|
|
if (et.type == NT_invtype)
|
15281 |
|
|
return;
|
15282 |
|
|
|
15283 |
|
|
constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
|
15284 |
|
|
_("bad list length"));
|
15285 |
|
|
constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
|
15286 |
|
|
_("scalar index out of range"));
|
15287 |
|
|
constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
|
15288 |
|
|
&& et.size == 8,
|
15289 |
|
|
_("stride of 2 unavailable when element size is 8"));
|
15290 |
|
|
|
15291 |
|
|
switch (n)
|
15292 |
|
|
{
|
15293 |
|
|
case 0: /* VLD1 / VST1. */
|
15294 |
|
|
align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
|
15295 |
|
|
32, 32, -1);
|
15296 |
|
|
if (align_good == FAIL)
|
15297 |
|
|
return;
|
15298 |
|
|
if (do_align)
|
15299 |
|
|
{
|
15300 |
|
|
unsigned alignbits = 0;
|
15301 |
|
|
switch (et.size)
|
15302 |
|
|
{
|
15303 |
|
|
case 16: alignbits = 0x1; break;
|
15304 |
|
|
case 32: alignbits = 0x3; break;
|
15305 |
|
|
default: ;
|
15306 |
|
|
}
|
15307 |
|
|
inst.instruction |= alignbits << 4;
|
15308 |
|
|
}
|
15309 |
|
|
break;
|
15310 |
|
|
|
15311 |
|
|
case 1: /* VLD2 / VST2. */
|
15312 |
|
|
align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
|
15313 |
|
|
32, 64, -1);
|
15314 |
|
|
if (align_good == FAIL)
|
15315 |
|
|
return;
|
15316 |
|
|
if (do_align)
|
15317 |
|
|
inst.instruction |= 1 << 4;
|
15318 |
|
|
break;
|
15319 |
|
|
|
15320 |
|
|
case 2: /* VLD3 / VST3. */
|
15321 |
|
|
constraint (inst.operands[1].immisalign,
|
15322 |
|
|
_("can't use alignment with this instruction"));
|
15323 |
|
|
break;
|
15324 |
|
|
|
15325 |
|
|
case 3: /* VLD4 / VST4. */
|
15326 |
|
|
align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
|
15327 |
|
|
16, 64, 32, 64, 32, 128, -1);
|
15328 |
|
|
if (align_good == FAIL)
|
15329 |
|
|
return;
|
15330 |
|
|
if (do_align)
|
15331 |
|
|
{
|
15332 |
|
|
unsigned alignbits = 0;
|
15333 |
|
|
switch (et.size)
|
15334 |
|
|
{
|
15335 |
|
|
case 8: alignbits = 0x1; break;
|
15336 |
|
|
case 16: alignbits = 0x1; break;
|
15337 |
|
|
case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
|
15338 |
|
|
default: ;
|
15339 |
|
|
}
|
15340 |
|
|
inst.instruction |= alignbits << 4;
|
15341 |
|
|
}
|
15342 |
|
|
break;
|
15343 |
|
|
|
15344 |
|
|
default: ;
|
15345 |
|
|
}
|
15346 |
|
|
|
15347 |
|
|
/* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
|
15348 |
|
|
if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
|
15349 |
|
|
inst.instruction |= 1 << (4 + logsize);
|
15350 |
|
|
|
15351 |
|
|
inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
|
15352 |
|
|
inst.instruction |= logsize << 10;
|
15353 |
|
|
}
|
15354 |
|
|
|
15355 |
|
|
/* Encode single n-element structure to all lanes VLD<n> instructions. */
|
15356 |
|
|
|
15357 |
|
|
static void
|
15358 |
|
|
do_neon_ld_dup (void)
|
15359 |
|
|
{
|
15360 |
|
|
struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
|
15361 |
|
|
int align_good, do_align = 0;
|
15362 |
|
|
|
15363 |
|
|
if (et.type == NT_invtype)
|
15364 |
|
|
return;
|
15365 |
|
|
|
15366 |
|
|
switch ((inst.instruction >> 8) & 3)
|
15367 |
|
|
{
|
15368 |
|
|
case 0: /* VLD1. */
|
15369 |
|
|
gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
|
15370 |
|
|
align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
|
15371 |
|
|
&do_align, 16, 16, 32, 32, -1);
|
15372 |
|
|
if (align_good == FAIL)
|
15373 |
|
|
return;
|
15374 |
|
|
switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
|
15375 |
|
|
{
|
15376 |
|
|
case 1: break;
|
15377 |
|
|
case 2: inst.instruction |= 1 << 5; break;
|
15378 |
|
|
default: first_error (_("bad list length")); return;
|
15379 |
|
|
}
|
15380 |
|
|
inst.instruction |= neon_logbits (et.size) << 6;
|
15381 |
|
|
break;
|
15382 |
|
|
|
15383 |
|
|
case 1: /* VLD2. */
|
15384 |
|
|
align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
|
15385 |
|
|
&do_align, 8, 16, 16, 32, 32, 64, -1);
|
15386 |
|
|
if (align_good == FAIL)
|
15387 |
|
|
return;
|
15388 |
|
|
constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
|
15389 |
|
|
_("bad list length"));
|
15390 |
|
|
if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
|
15391 |
|
|
inst.instruction |= 1 << 5;
|
15392 |
|
|
inst.instruction |= neon_logbits (et.size) << 6;
|
15393 |
|
|
break;
|
15394 |
|
|
|
15395 |
|
|
case 2: /* VLD3. */
|
15396 |
|
|
constraint (inst.operands[1].immisalign,
|
15397 |
|
|
_("can't use alignment with this instruction"));
|
15398 |
|
|
constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
|
15399 |
|
|
_("bad list length"));
|
15400 |
|
|
if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
|
15401 |
|
|
inst.instruction |= 1 << 5;
|
15402 |
|
|
inst.instruction |= neon_logbits (et.size) << 6;
|
15403 |
|
|
break;
|
15404 |
|
|
|
15405 |
|
|
case 3: /* VLD4. */
|
15406 |
|
|
{
|
15407 |
|
|
int align = inst.operands[1].imm >> 8;
|
15408 |
|
|
align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
|
15409 |
|
|
16, 64, 32, 64, 32, 128, -1);
|
15410 |
|
|
if (align_good == FAIL)
|
15411 |
|
|
return;
|
15412 |
|
|
constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
|
15413 |
|
|
_("bad list length"));
|
15414 |
|
|
if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
|
15415 |
|
|
inst.instruction |= 1 << 5;
|
15416 |
|
|
if (et.size == 32 && align == 128)
|
15417 |
|
|
inst.instruction |= 0x3 << 6;
|
15418 |
|
|
else
|
15419 |
|
|
inst.instruction |= neon_logbits (et.size) << 6;
|
15420 |
|
|
}
|
15421 |
|
|
break;
|
15422 |
|
|
|
15423 |
|
|
default: ;
|
15424 |
|
|
}
|
15425 |
|
|
|
15426 |
|
|
inst.instruction |= do_align << 4;
|
15427 |
|
|
}
|
15428 |
|
|
|
15429 |
|
|
/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
|
15430 |
|
|
apart from bits [11:4]. */
|
15431 |
|
|
|
15432 |
|
|
static void
|
15433 |
|
|
do_neon_ldx_stx (void)
|
15434 |
|
|
{
|
15435 |
|
|
if (inst.operands[1].isreg)
|
15436 |
|
|
constraint (inst.operands[1].reg == REG_PC, BAD_PC);
|
15437 |
|
|
|
15438 |
|
|
switch (NEON_LANE (inst.operands[0].imm))
|
15439 |
|
|
{
|
15440 |
|
|
case NEON_INTERLEAVE_LANES:
|
15441 |
|
|
NEON_ENCODE (INTERLV, inst);
|
15442 |
|
|
do_neon_ld_st_interleave ();
|
15443 |
|
|
break;
|
15444 |
|
|
|
15445 |
|
|
case NEON_ALL_LANES:
|
15446 |
|
|
NEON_ENCODE (DUP, inst);
|
15447 |
|
|
do_neon_ld_dup ();
|
15448 |
|
|
break;
|
15449 |
|
|
|
15450 |
|
|
default:
|
15451 |
|
|
NEON_ENCODE (LANE, inst);
|
15452 |
|
|
do_neon_ld_st_lane ();
|
15453 |
|
|
}
|
15454 |
|
|
|
15455 |
|
|
/* L bit comes from bit mask. */
|
15456 |
|
|
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
|
15457 |
|
|
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
|
15458 |
|
|
inst.instruction |= inst.operands[1].reg << 16;
|
15459 |
|
|
|
15460 |
|
|
if (inst.operands[1].postind)
|
15461 |
|
|
{
|
15462 |
|
|
int postreg = inst.operands[1].imm & 0xf;
|
15463 |
|
|
constraint (!inst.operands[1].immisreg,
|
15464 |
|
|
_("post-index must be a register"));
|
15465 |
|
|
constraint (postreg == 0xd || postreg == 0xf,
|
15466 |
|
|
_("bad register for post-index"));
|
15467 |
|
|
inst.instruction |= postreg;
|
15468 |
|
|
}
|
15469 |
|
|
else if (inst.operands[1].writeback)
|
15470 |
|
|
{
|
15471 |
|
|
inst.instruction |= 0xd;
|
15472 |
|
|
}
|
15473 |
|
|
else
|
15474 |
|
|
inst.instruction |= 0xf;
|
15475 |
|
|
|
15476 |
|
|
if (thumb_mode)
|
15477 |
|
|
inst.instruction |= 0xf9000000;
|
15478 |
|
|
else
|
15479 |
|
|
inst.instruction |= 0xf4000000;
|
15480 |
|
|
}
|
15481 |
|
|
|
15482 |
|
|
/* Overall per-instruction processing. */
|
15483 |
|
|
|
15484 |
|
|
/* We need to be able to fix up arbitrary expressions in some statements.
|
15485 |
|
|
This is so that we can handle symbols that are an arbitrary distance from
|
15486 |
|
|
the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
|
15487 |
|
|
which returns part of an address in a form which will be valid for
|
15488 |
|
|
a data instruction. We do this by pushing the expression into a symbol
|
15489 |
|
|
in the expr_section, and creating a fix for that. */
|
15490 |
|
|
|
15491 |
|
|
static void
|
15492 |
|
|
fix_new_arm (fragS * frag,
|
15493 |
|
|
int where,
|
15494 |
|
|
short int size,
|
15495 |
|
|
expressionS * exp,
|
15496 |
|
|
int pc_rel,
|
15497 |
|
|
int reloc)
|
15498 |
|
|
{
|
15499 |
|
|
fixS * new_fix;
|
15500 |
|
|
|
15501 |
|
|
switch (exp->X_op)
|
15502 |
|
|
{
|
15503 |
|
|
case O_constant:
|
15504 |
|
|
if (pc_rel)
|
15505 |
|
|
{
|
15506 |
|
|
/* Create an absolute valued symbol, so we have something to
|
15507 |
|
|
refer to in the object file. Unfortunately for us, gas's
|
15508 |
|
|
generic expression parsing will already have folded out
|
15509 |
|
|
any use of .set foo/.type foo %function that may have
|
15510 |
|
|
been used to set type information of the target location,
|
15511 |
|
|
that's being specified symbolically. We have to presume
|
15512 |
|
|
the user knows what they are doing. */
|
15513 |
|
|
char name[16 + 8];
|
15514 |
|
|
symbolS *symbol;
|
15515 |
|
|
|
15516 |
|
|
sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
|
15517 |
|
|
|
15518 |
|
|
symbol = symbol_find_or_make (name);
|
15519 |
|
|
S_SET_SEGMENT (symbol, absolute_section);
|
15520 |
|
|
symbol_set_frag (symbol, &zero_address_frag);
|
15521 |
|
|
S_SET_VALUE (symbol, exp->X_add_number);
|
15522 |
|
|
exp->X_op = O_symbol;
|
15523 |
|
|
exp->X_add_symbol = symbol;
|
15524 |
|
|
exp->X_add_number = 0;
|
15525 |
|
|
}
|
15526 |
|
|
/* FALLTHROUGH */
|
15527 |
|
|
case O_symbol:
|
15528 |
|
|
case O_add:
|
15529 |
|
|
case O_subtract:
|
15530 |
|
|
new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
|
15531 |
|
|
(enum bfd_reloc_code_real) reloc);
|
15532 |
|
|
break;
|
15533 |
|
|
|
15534 |
|
|
default:
|
15535 |
|
|
new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
|
15536 |
|
|
pc_rel, (enum bfd_reloc_code_real) reloc);
|
15537 |
|
|
break;
|
15538 |
|
|
}
|
15539 |
|
|
|
15540 |
|
|
/* Mark whether the fix is to a THUMB instruction, or an ARM
|
15541 |
|
|
instruction. */
|
15542 |
|
|
new_fix->tc_fix_data = thumb_mode;
|
15543 |
|
|
}
|
15544 |
|
|
|
15545 |
|
|
/* Create a frg for an instruction requiring relaxation. */
|
15546 |
|
|
static void
|
15547 |
|
|
output_relax_insn (void)
|
15548 |
|
|
{
|
15549 |
|
|
char * to;
|
15550 |
|
|
symbolS *sym;
|
15551 |
|
|
int offset;
|
15552 |
|
|
|
15553 |
|
|
/* The size of the instruction is unknown, so tie the debug info to the
|
15554 |
|
|
start of the instruction. */
|
15555 |
|
|
dwarf2_emit_insn (0);
|
15556 |
|
|
|
15557 |
|
|
switch (inst.reloc.exp.X_op)
|
15558 |
|
|
{
|
15559 |
|
|
case O_symbol:
|
15560 |
|
|
sym = inst.reloc.exp.X_add_symbol;
|
15561 |
|
|
offset = inst.reloc.exp.X_add_number;
|
15562 |
|
|
break;
|
15563 |
|
|
case O_constant:
|
15564 |
|
|
sym = NULL;
|
15565 |
|
|
offset = inst.reloc.exp.X_add_number;
|
15566 |
|
|
break;
|
15567 |
|
|
default:
|
15568 |
|
|
sym = make_expr_symbol (&inst.reloc.exp);
|
15569 |
|
|
offset = 0;
|
15570 |
|
|
break;
|
15571 |
|
|
}
|
15572 |
|
|
to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
|
15573 |
|
|
inst.relax, sym, offset, NULL/*offset, opcode*/);
|
15574 |
|
|
md_number_to_chars (to, inst.instruction, THUMB_SIZE);
|
15575 |
|
|
}
|
15576 |
|
|
|
15577 |
|
|
/* Write a 32-bit thumb instruction to buf. */
|
15578 |
|
|
static void
|
15579 |
|
|
put_thumb32_insn (char * buf, unsigned long insn)
|
15580 |
|
|
{
|
15581 |
|
|
md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
|
15582 |
|
|
md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
|
15583 |
|
|
}
|
15584 |
|
|
|
15585 |
|
|
static void
|
15586 |
|
|
output_inst (const char * str)
|
15587 |
|
|
{
|
15588 |
|
|
char * to = NULL;
|
15589 |
|
|
|
15590 |
|
|
if (inst.error)
|
15591 |
|
|
{
|
15592 |
|
|
as_bad ("%s -- `%s'", inst.error, str);
|
15593 |
|
|
return;
|
15594 |
|
|
}
|
15595 |
|
|
if (inst.relax)
|
15596 |
|
|
{
|
15597 |
|
|
output_relax_insn ();
|
15598 |
|
|
return;
|
15599 |
|
|
}
|
15600 |
|
|
if (inst.size == 0)
|
15601 |
|
|
return;
|
15602 |
|
|
|
15603 |
|
|
to = frag_more (inst.size);
|
15604 |
|
|
/* PR 9814: Record the thumb mode into the current frag so that we know
|
15605 |
|
|
what type of NOP padding to use, if necessary. We override any previous
|
15606 |
|
|
setting so that if the mode has changed then the NOPS that we use will
|
15607 |
|
|
match the encoding of the last instruction in the frag. */
|
15608 |
|
|
frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
|
15609 |
|
|
|
15610 |
|
|
if (thumb_mode && (inst.size > THUMB_SIZE))
|
15611 |
|
|
{
|
15612 |
|
|
gas_assert (inst.size == (2 * THUMB_SIZE));
|
15613 |
|
|
put_thumb32_insn (to, inst.instruction);
|
15614 |
|
|
}
|
15615 |
|
|
else if (inst.size > INSN_SIZE)
|
15616 |
|
|
{
|
15617 |
|
|
gas_assert (inst.size == (2 * INSN_SIZE));
|
15618 |
|
|
md_number_to_chars (to, inst.instruction, INSN_SIZE);
|
15619 |
|
|
md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
|
15620 |
|
|
}
|
15621 |
|
|
else
|
15622 |
|
|
md_number_to_chars (to, inst.instruction, inst.size);
|
15623 |
|
|
|
15624 |
|
|
if (inst.reloc.type != BFD_RELOC_UNUSED)
|
15625 |
|
|
fix_new_arm (frag_now, to - frag_now->fr_literal,
|
15626 |
|
|
inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
|
15627 |
|
|
inst.reloc.type);
|
15628 |
|
|
|
15629 |
|
|
dwarf2_emit_insn (inst.size);
|
15630 |
|
|
}
|
15631 |
|
|
|
15632 |
|
|
static char *
|
15633 |
|
|
output_it_inst (int cond, int mask, char * to)
|
15634 |
|
|
{
|
15635 |
|
|
unsigned long instruction = 0xbf00;
|
15636 |
|
|
|
15637 |
|
|
mask &= 0xf;
|
15638 |
|
|
instruction |= mask;
|
15639 |
|
|
instruction |= cond << 4;
|
15640 |
|
|
|
15641 |
|
|
if (to == NULL)
|
15642 |
|
|
{
|
15643 |
|
|
to = frag_more (2);
|
15644 |
|
|
#ifdef OBJ_ELF
|
15645 |
|
|
dwarf2_emit_insn (2);
|
15646 |
|
|
#endif
|
15647 |
|
|
}
|
15648 |
|
|
|
15649 |
|
|
md_number_to_chars (to, instruction, 2);
|
15650 |
|
|
|
15651 |
|
|
return to;
|
15652 |
|
|
}
|
15653 |
|
|
|
15654 |
|
|
/* Tag values used in struct asm_opcode's tag field. */
|
15655 |
|
|
enum opcode_tag
|
15656 |
|
|
{
|
15657 |
|
|
OT_unconditional, /* Instruction cannot be conditionalized.
|
15658 |
|
|
The ARM condition field is still 0xE. */
|
15659 |
|
|
OT_unconditionalF, /* Instruction cannot be conditionalized
|
15660 |
|
|
and carries 0xF in its ARM condition field. */
|
15661 |
|
|
OT_csuffix, /* Instruction takes a conditional suffix. */
|
15662 |
|
|
OT_csuffixF, /* Some forms of the instruction take a conditional
|
15663 |
|
|
suffix, others place 0xF where the condition field
|
15664 |
|
|
would be. */
|
15665 |
|
|
OT_cinfix3, /* Instruction takes a conditional infix,
|
15666 |
|
|
beginning at character index 3. (In
|
15667 |
|
|
unified mode, it becomes a suffix.) */
|
15668 |
|
|
OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
|
15669 |
|
|
tsts, cmps, cmns, and teqs. */
|
15670 |
|
|
OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
|
15671 |
|
|
character index 3, even in unified mode. Used for
|
15672 |
|
|
legacy instructions where suffix and infix forms
|
15673 |
|
|
may be ambiguous. */
|
15674 |
|
|
OT_csuf_or_in3, /* Instruction takes either a conditional
|
15675 |
|
|
suffix or an infix at character index 3. */
|
15676 |
|
|
OT_odd_infix_unc, /* This is the unconditional variant of an
|
15677 |
|
|
instruction that takes a conditional infix
|
15678 |
|
|
at an unusual position. In unified mode,
|
15679 |
|
|
this variant will accept a suffix. */
|
15680 |
|
|
OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
|
15681 |
|
|
are the conditional variants of instructions that
|
15682 |
|
|
take conditional infixes in unusual positions.
|
15683 |
|
|
The infix appears at character index
|
15684 |
|
|
(tag - OT_odd_infix_0). These are not accepted
|
15685 |
|
|
in unified mode. */
|
15686 |
|
|
};
|
15687 |
|
|
|
15688 |
|
|
/* Subroutine of md_assemble, responsible for looking up the primary
|
15689 |
|
|
opcode from the mnemonic the user wrote. STR points to the
|
15690 |
|
|
beginning of the mnemonic.
|
15691 |
|
|
|
15692 |
|
|
This is not simply a hash table lookup, because of conditional
|
15693 |
|
|
variants. Most instructions have conditional variants, which are
|
15694 |
|
|
expressed with a _conditional affix_ to the mnemonic. If we were
|
15695 |
|
|
to encode each conditional variant as a literal string in the opcode
|
15696 |
|
|
table, it would have approximately 20,000 entries.
|
15697 |
|
|
|
15698 |
|
|
Most mnemonics take this affix as a suffix, and in unified syntax,
|
15699 |
|
|
'most' is upgraded to 'all'. However, in the divided syntax, some
|
15700 |
|
|
instructions take the affix as an infix, notably the s-variants of
|
15701 |
|
|
the arithmetic instructions. Of those instructions, all but six
|
15702 |
|
|
have the infix appear after the third character of the mnemonic.
|
15703 |
|
|
|
15704 |
|
|
Accordingly, the algorithm for looking up primary opcodes given
|
15705 |
|
|
an identifier is:
|
15706 |
|
|
|
15707 |
|
|
1. Look up the identifier in the opcode table.
|
15708 |
|
|
If we find a match, go to step U.
|
15709 |
|
|
|
15710 |
|
|
2. Look up the last two characters of the identifier in the
|
15711 |
|
|
conditions table. If we find a match, look up the first N-2
|
15712 |
|
|
characters of the identifier in the opcode table. If we
|
15713 |
|
|
find a match, go to step CE.
|
15714 |
|
|
|
15715 |
|
|
3. Look up the fourth and fifth characters of the identifier in
|
15716 |
|
|
the conditions table. If we find a match, extract those
|
15717 |
|
|
characters from the identifier, and look up the remaining
|
15718 |
|
|
characters in the opcode table. If we find a match, go
|
15719 |
|
|
to step CM.
|
15720 |
|
|
|
15721 |
|
|
4. Fail.
|
15722 |
|
|
|
15723 |
|
|
U. Examine the tag field of the opcode structure, in case this is
|
15724 |
|
|
one of the six instructions with its conditional infix in an
|
15725 |
|
|
unusual place. If it is, the tag tells us where to find the
|
15726 |
|
|
infix; look it up in the conditions table and set inst.cond
|
15727 |
|
|
accordingly. Otherwise, this is an unconditional instruction.
|
15728 |
|
|
Again set inst.cond accordingly. Return the opcode structure.
|
15729 |
|
|
|
15730 |
|
|
CE. Examine the tag field to make sure this is an instruction that
|
15731 |
|
|
should receive a conditional suffix. If it is not, fail.
|
15732 |
|
|
Otherwise, set inst.cond from the suffix we already looked up,
|
15733 |
|
|
and return the opcode structure.
|
15734 |
|
|
|
15735 |
|
|
CM. Examine the tag field to make sure this is an instruction that
|
15736 |
|
|
should receive a conditional infix after the third character.
|
15737 |
|
|
If it is not, fail. Otherwise, undo the edits to the current
|
15738 |
|
|
line of input and proceed as for case CE. */
|
15739 |
|
|
|
15740 |
|
|
static const struct asm_opcode *
|
15741 |
|
|
opcode_lookup (char **str)
|
15742 |
|
|
{
|
15743 |
|
|
char *end, *base;
|
15744 |
|
|
char *affix;
|
15745 |
|
|
const struct asm_opcode *opcode;
|
15746 |
|
|
const struct asm_cond *cond;
|
15747 |
|
|
char save[2];
|
15748 |
|
|
|
15749 |
|
|
/* Scan up to the end of the mnemonic, which must end in white space,
|
15750 |
|
|
'.' (in unified mode, or for Neon/VFP instructions), or end of string. */
|
15751 |
|
|
for (base = end = *str; *end != '\0'; end++)
|
15752 |
|
|
if (*end == ' ' || *end == '.')
|
15753 |
|
|
break;
|
15754 |
|
|
|
15755 |
|
|
if (end == base)
|
15756 |
|
|
return NULL;
|
15757 |
|
|
|
15758 |
|
|
/* Handle a possible width suffix and/or Neon type suffix. */
|
15759 |
|
|
if (end[0] == '.')
|
15760 |
|
|
{
|
15761 |
|
|
int offset = 2;
|
15762 |
|
|
|
15763 |
|
|
/* The .w and .n suffixes are only valid if the unified syntax is in
|
15764 |
|
|
use. */
|
15765 |
|
|
if (unified_syntax && end[1] == 'w')
|
15766 |
|
|
inst.size_req = 4;
|
15767 |
|
|
else if (unified_syntax && end[1] == 'n')
|
15768 |
|
|
inst.size_req = 2;
|
15769 |
|
|
else
|
15770 |
|
|
offset = 0;
|
15771 |
|
|
|
15772 |
|
|
inst.vectype.elems = 0;
|
15773 |
|
|
|
15774 |
|
|
*str = end + offset;
|
15775 |
|
|
|
15776 |
|
|
if (end[offset] == '.')
|
15777 |
|
|
{
|
15778 |
|
|
/* See if we have a Neon type suffix (possible in either unified or
|
15779 |
|
|
non-unified ARM syntax mode). */
|
15780 |
|
|
if (parse_neon_type (&inst.vectype, str) == FAIL)
|
15781 |
|
|
return NULL;
|
15782 |
|
|
}
|
15783 |
|
|
else if (end[offset] != '\0' && end[offset] != ' ')
|
15784 |
|
|
return NULL;
|
15785 |
|
|
}
|
15786 |
|
|
else
|
15787 |
|
|
*str = end;
|
15788 |
|
|
|
15789 |
|
|
/* Look for unaffixed or special-case affixed mnemonic. */
|
15790 |
|
|
opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
|
15791 |
|
|
end - base);
|
15792 |
|
|
if (opcode)
|
15793 |
|
|
{
|
15794 |
|
|
/* step U */
|
15795 |
|
|
if (opcode->tag < OT_odd_infix_0)
|
15796 |
|
|
{
|
15797 |
|
|
inst.cond = COND_ALWAYS;
|
15798 |
|
|
return opcode;
|
15799 |
|
|
}
|
15800 |
|
|
|
15801 |
|
|
if (warn_on_deprecated && unified_syntax)
|
15802 |
|
|
as_warn (_("conditional infixes are deprecated in unified syntax"));
|
15803 |
|
|
affix = base + (opcode->tag - OT_odd_infix_0);
|
15804 |
|
|
cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
|
15805 |
|
|
gas_assert (cond);
|
15806 |
|
|
|
15807 |
|
|
inst.cond = cond->value;
|
15808 |
|
|
return opcode;
|
15809 |
|
|
}
|
15810 |
|
|
|
15811 |
|
|
/* Cannot have a conditional suffix on a mnemonic of less than two
|
15812 |
|
|
characters. */
|
15813 |
|
|
if (end - base < 3)
|
15814 |
|
|
return NULL;
|
15815 |
|
|
|
15816 |
|
|
/* Look for suffixed mnemonic. */
|
15817 |
|
|
affix = end - 2;
|
15818 |
|
|
cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
|
15819 |
|
|
opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
|
15820 |
|
|
affix - base);
|
15821 |
|
|
if (opcode && cond)
|
15822 |
|
|
{
|
15823 |
|
|
/* step CE */
|
15824 |
|
|
switch (opcode->tag)
|
15825 |
|
|
{
|
15826 |
|
|
case OT_cinfix3_legacy:
|
15827 |
|
|
/* Ignore conditional suffixes matched on infix only mnemonics. */
|
15828 |
|
|
break;
|
15829 |
|
|
|
15830 |
|
|
case OT_cinfix3:
|
15831 |
|
|
case OT_cinfix3_deprecated:
|
15832 |
|
|
case OT_odd_infix_unc:
|
15833 |
|
|
if (!unified_syntax)
|
15834 |
|
|
return 0;
|
15835 |
|
|
/* else fall through */
|
15836 |
|
|
|
15837 |
|
|
case OT_csuffix:
|
15838 |
|
|
case OT_csuffixF:
|
15839 |
|
|
case OT_csuf_or_in3:
|
15840 |
|
|
inst.cond = cond->value;
|
15841 |
|
|
return opcode;
|
15842 |
|
|
|
15843 |
|
|
case OT_unconditional:
|
15844 |
|
|
case OT_unconditionalF:
|
15845 |
|
|
if (thumb_mode)
|
15846 |
|
|
inst.cond = cond->value;
|
15847 |
|
|
else
|
15848 |
|
|
{
|
15849 |
|
|
/* Delayed diagnostic. */
|
15850 |
|
|
inst.error = BAD_COND;
|
15851 |
|
|
inst.cond = COND_ALWAYS;
|
15852 |
|
|
}
|
15853 |
|
|
return opcode;
|
15854 |
|
|
|
15855 |
|
|
default:
|
15856 |
|
|
return NULL;
|
15857 |
|
|
}
|
15858 |
|
|
}
|
15859 |
|
|
|
15860 |
|
|
/* Cannot have a usual-position infix on a mnemonic of less than
|
15861 |
|
|
six characters (five would be a suffix). */
|
15862 |
|
|
if (end - base < 6)
|
15863 |
|
|
return NULL;
|
15864 |
|
|
|
15865 |
|
|
/* Look for infixed mnemonic in the usual position. */
|
15866 |
|
|
affix = base + 3;
|
15867 |
|
|
cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
|
15868 |
|
|
if (!cond)
|
15869 |
|
|
return NULL;
|
15870 |
|
|
|
15871 |
|
|
memcpy (save, affix, 2);
|
15872 |
|
|
memmove (affix, affix + 2, (end - affix) - 2);
|
15873 |
|
|
opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
|
15874 |
|
|
(end - base) - 2);
|
15875 |
|
|
memmove (affix + 2, affix, (end - affix) - 2);
|
15876 |
|
|
memcpy (affix, save, 2);
|
15877 |
|
|
|
15878 |
|
|
if (opcode
|
15879 |
|
|
&& (opcode->tag == OT_cinfix3
|
15880 |
|
|
|| opcode->tag == OT_cinfix3_deprecated
|
15881 |
|
|
|| opcode->tag == OT_csuf_or_in3
|
15882 |
|
|
|| opcode->tag == OT_cinfix3_legacy))
|
15883 |
|
|
{
|
15884 |
|
|
/* Step CM. */
|
15885 |
|
|
if (warn_on_deprecated && unified_syntax
|
15886 |
|
|
&& (opcode->tag == OT_cinfix3
|
15887 |
|
|
|| opcode->tag == OT_cinfix3_deprecated))
|
15888 |
|
|
as_warn (_("conditional infixes are deprecated in unified syntax"));
|
15889 |
|
|
|
15890 |
|
|
inst.cond = cond->value;
|
15891 |
|
|
return opcode;
|
15892 |
|
|
}
|
15893 |
|
|
|
15894 |
|
|
return NULL;
|
15895 |
|
|
}
|
15896 |
|
|
|
15897 |
|
|
/* This function generates an initial IT instruction, leaving its block
|
15898 |
|
|
virtually open for the new instructions. Eventually,
|
15899 |
|
|
the mask will be updated by now_it_add_mask () each time
|
15900 |
|
|
a new instruction needs to be included in the IT block.
|
15901 |
|
|
Finally, the block is closed with close_automatic_it_block ().
|
15902 |
|
|
The block closure can be requested either from md_assemble (),
|
15903 |
|
|
a tencode (), or due to a label hook. */
|
15904 |
|
|
|
15905 |
|
|
static void
|
15906 |
|
|
new_automatic_it_block (int cond)
|
15907 |
|
|
{
|
15908 |
|
|
now_it.state = AUTOMATIC_IT_BLOCK;
|
15909 |
|
|
now_it.mask = 0x18;
|
15910 |
|
|
now_it.cc = cond;
|
15911 |
|
|
now_it.block_length = 1;
|
15912 |
|
|
mapping_state (MAP_THUMB);
|
15913 |
|
|
now_it.insn = output_it_inst (cond, now_it.mask, NULL);
|
15914 |
|
|
}
|
15915 |
|
|
|
15916 |
|
|
/* Close an automatic IT block.
|
15917 |
|
|
See comments in new_automatic_it_block (). */
|
15918 |
|
|
|
15919 |
|
|
static void
|
15920 |
|
|
close_automatic_it_block (void)
|
15921 |
|
|
{
|
15922 |
|
|
now_it.mask = 0x10;
|
15923 |
|
|
now_it.block_length = 0;
|
15924 |
|
|
}
|
15925 |
|
|
|
15926 |
|
|
/* Update the mask of the current automatically-generated IT
|
15927 |
|
|
instruction. See comments in new_automatic_it_block (). */
|
15928 |
|
|
|
15929 |
|
|
static void
|
15930 |
|
|
now_it_add_mask (int cond)
|
15931 |
|
|
{
|
15932 |
|
|
#define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
|
15933 |
|
|
#define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
|
15934 |
|
|
| ((bitvalue) << (nbit)))
|
15935 |
|
|
const int resulting_bit = (cond & 1);
|
15936 |
|
|
|
15937 |
|
|
now_it.mask &= 0xf;
|
15938 |
|
|
now_it.mask = SET_BIT_VALUE (now_it.mask,
|
15939 |
|
|
resulting_bit,
|
15940 |
|
|
(5 - now_it.block_length));
|
15941 |
|
|
now_it.mask = SET_BIT_VALUE (now_it.mask,
|
15942 |
|
|
1,
|
15943 |
|
|
((5 - now_it.block_length) - 1) );
|
15944 |
|
|
output_it_inst (now_it.cc, now_it.mask, now_it.insn);
|
15945 |
|
|
|
15946 |
|
|
#undef CLEAR_BIT
|
15947 |
|
|
#undef SET_BIT_VALUE
|
15948 |
|
|
}
|
15949 |
|
|
|
15950 |
|
|
/* The IT blocks handling machinery is accessed through the these functions:
|
15951 |
|
|
it_fsm_pre_encode () from md_assemble ()
|
15952 |
|
|
set_it_insn_type () optional, from the tencode functions
|
15953 |
|
|
set_it_insn_type_last () ditto
|
15954 |
|
|
in_it_block () ditto
|
15955 |
|
|
it_fsm_post_encode () from md_assemble ()
|
15956 |
|
|
force_automatic_it_block_close () from label habdling functions
|
15957 |
|
|
|
15958 |
|
|
Rationale:
|
15959 |
|
|
1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
|
15960 |
|
|
initializing the IT insn type with a generic initial value depending
|
15961 |
|
|
on the inst.condition.
|
15962 |
|
|
2) During the tencode function, two things may happen:
|
15963 |
|
|
a) The tencode function overrides the IT insn type by
|
15964 |
|
|
calling either set_it_insn_type (type) or set_it_insn_type_last ().
|
15965 |
|
|
b) The tencode function queries the IT block state by
|
15966 |
|
|
calling in_it_block () (i.e. to determine narrow/not narrow mode).
|
15967 |
|
|
|
15968 |
|
|
Both set_it_insn_type and in_it_block run the internal FSM state
|
15969 |
|
|
handling function (handle_it_state), because: a) setting the IT insn
|
15970 |
|
|
type may incur in an invalid state (exiting the function),
|
15971 |
|
|
and b) querying the state requires the FSM to be updated.
|
15972 |
|
|
Specifically we want to avoid creating an IT block for conditional
|
15973 |
|
|
branches, so it_fsm_pre_encode is actually a guess and we can't
|
15974 |
|
|
determine whether an IT block is required until the tencode () routine
|
15975 |
|
|
has decided what type of instruction this actually it.
|
15976 |
|
|
Because of this, if set_it_insn_type and in_it_block have to be used,
|
15977 |
|
|
set_it_insn_type has to be called first.
|
15978 |
|
|
|
15979 |
|
|
set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
|
15980 |
|
|
determines the insn IT type depending on the inst.cond code.
|
15981 |
|
|
When a tencode () routine encodes an instruction that can be
|
15982 |
|
|
either outside an IT block, or, in the case of being inside, has to be
|
15983 |
|
|
the last one, set_it_insn_type_last () will determine the proper
|
15984 |
|
|
IT instruction type based on the inst.cond code. Otherwise,
|
15985 |
|
|
set_it_insn_type can be called for overriding that logic or
|
15986 |
|
|
for covering other cases.
|
15987 |
|
|
|
15988 |
|
|
Calling handle_it_state () may not transition the IT block state to
|
15989 |
|
|
OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
|
15990 |
|
|
still queried. Instead, if the FSM determines that the state should
|
15991 |
|
|
be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
|
15992 |
|
|
after the tencode () function: that's what it_fsm_post_encode () does.
|
15993 |
|
|
|
15994 |
|
|
Since in_it_block () calls the state handling function to get an
|
15995 |
|
|
updated state, an error may occur (due to invalid insns combination).
|
15996 |
|
|
In that case, inst.error is set.
|
15997 |
|
|
Therefore, inst.error has to be checked after the execution of
|
15998 |
|
|
the tencode () routine.
|
15999 |
|
|
|
16000 |
|
|
3) Back in md_assemble(), it_fsm_post_encode () is called to commit
|
16001 |
|
|
any pending state change (if any) that didn't take place in
|
16002 |
|
|
handle_it_state () as explained above. */
|
16003 |
|
|
|
16004 |
|
|
static void
|
16005 |
|
|
it_fsm_pre_encode (void)
|
16006 |
|
|
{
|
16007 |
|
|
if (inst.cond != COND_ALWAYS)
|
16008 |
|
|
inst.it_insn_type = INSIDE_IT_INSN;
|
16009 |
|
|
else
|
16010 |
|
|
inst.it_insn_type = OUTSIDE_IT_INSN;
|
16011 |
|
|
|
16012 |
|
|
now_it.state_handled = 0;
|
16013 |
|
|
}
|
16014 |
|
|
|
16015 |
|
|
/* IT state FSM handling function. */
|
16016 |
|
|
|
16017 |
|
|
static int
|
16018 |
|
|
handle_it_state (void)
|
16019 |
|
|
{
|
16020 |
|
|
now_it.state_handled = 1;
|
16021 |
|
|
|
16022 |
|
|
switch (now_it.state)
|
16023 |
|
|
{
|
16024 |
|
|
case OUTSIDE_IT_BLOCK:
|
16025 |
|
|
switch (inst.it_insn_type)
|
16026 |
|
|
{
|
16027 |
|
|
case OUTSIDE_IT_INSN:
|
16028 |
|
|
break;
|
16029 |
|
|
|
16030 |
|
|
case INSIDE_IT_INSN:
|
16031 |
|
|
case INSIDE_IT_LAST_INSN:
|
16032 |
|
|
if (thumb_mode == 0)
|
16033 |
|
|
{
|
16034 |
|
|
if (unified_syntax
|
16035 |
|
|
&& !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
|
16036 |
|
|
as_tsktsk (_("Warning: conditional outside an IT block"\
|
16037 |
|
|
" for Thumb."));
|
16038 |
|
|
}
|
16039 |
|
|
else
|
16040 |
|
|
{
|
16041 |
|
|
if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
|
16042 |
|
|
&& ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
|
16043 |
|
|
{
|
16044 |
|
|
/* Automatically generate the IT instruction. */
|
16045 |
|
|
new_automatic_it_block (inst.cond);
|
16046 |
|
|
if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
|
16047 |
|
|
close_automatic_it_block ();
|
16048 |
|
|
}
|
16049 |
|
|
else
|
16050 |
|
|
{
|
16051 |
|
|
inst.error = BAD_OUT_IT;
|
16052 |
|
|
return FAIL;
|
16053 |
|
|
}
|
16054 |
|
|
}
|
16055 |
|
|
break;
|
16056 |
|
|
|
16057 |
|
|
case IF_INSIDE_IT_LAST_INSN:
|
16058 |
|
|
case NEUTRAL_IT_INSN:
|
16059 |
|
|
break;
|
16060 |
|
|
|
16061 |
|
|
case IT_INSN:
|
16062 |
|
|
now_it.state = MANUAL_IT_BLOCK;
|
16063 |
|
|
now_it.block_length = 0;
|
16064 |
|
|
break;
|
16065 |
|
|
}
|
16066 |
|
|
break;
|
16067 |
|
|
|
16068 |
|
|
case AUTOMATIC_IT_BLOCK:
|
16069 |
|
|
/* Three things may happen now:
|
16070 |
|
|
a) We should increment current it block size;
|
16071 |
|
|
b) We should close current it block (closing insn or 4 insns);
|
16072 |
|
|
c) We should close current it block and start a new one (due
|
16073 |
|
|
to incompatible conditions or
|
16074 |
|
|
4 insns-length block reached). */
|
16075 |
|
|
|
16076 |
|
|
switch (inst.it_insn_type)
|
16077 |
|
|
{
|
16078 |
|
|
case OUTSIDE_IT_INSN:
|
16079 |
|
|
/* The closure of the block shall happen immediatelly,
|
16080 |
|
|
so any in_it_block () call reports the block as closed. */
|
16081 |
|
|
force_automatic_it_block_close ();
|
16082 |
|
|
break;
|
16083 |
|
|
|
16084 |
|
|
case INSIDE_IT_INSN:
|
16085 |
|
|
case INSIDE_IT_LAST_INSN:
|
16086 |
|
|
case IF_INSIDE_IT_LAST_INSN:
|
16087 |
|
|
now_it.block_length++;
|
16088 |
|
|
|
16089 |
|
|
if (now_it.block_length > 4
|
16090 |
|
|
|| !now_it_compatible (inst.cond))
|
16091 |
|
|
{
|
16092 |
|
|
force_automatic_it_block_close ();
|
16093 |
|
|
if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
|
16094 |
|
|
new_automatic_it_block (inst.cond);
|
16095 |
|
|
}
|
16096 |
|
|
else
|
16097 |
|
|
{
|
16098 |
|
|
now_it_add_mask (inst.cond);
|
16099 |
|
|
}
|
16100 |
|
|
|
16101 |
|
|
if (now_it.state == AUTOMATIC_IT_BLOCK
|
16102 |
|
|
&& (inst.it_insn_type == INSIDE_IT_LAST_INSN
|
16103 |
|
|
|| inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
|
16104 |
|
|
close_automatic_it_block ();
|
16105 |
|
|
break;
|
16106 |
|
|
|
16107 |
|
|
case NEUTRAL_IT_INSN:
|
16108 |
|
|
now_it.block_length++;
|
16109 |
|
|
|
16110 |
|
|
if (now_it.block_length > 4)
|
16111 |
|
|
force_automatic_it_block_close ();
|
16112 |
|
|
else
|
16113 |
|
|
now_it_add_mask (now_it.cc & 1);
|
16114 |
|
|
break;
|
16115 |
|
|
|
16116 |
|
|
case IT_INSN:
|
16117 |
|
|
close_automatic_it_block ();
|
16118 |
|
|
now_it.state = MANUAL_IT_BLOCK;
|
16119 |
|
|
break;
|
16120 |
|
|
}
|
16121 |
|
|
break;
|
16122 |
|
|
|
16123 |
|
|
case MANUAL_IT_BLOCK:
|
16124 |
|
|
{
|
16125 |
|
|
/* Check conditional suffixes. */
|
16126 |
|
|
const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
|
16127 |
|
|
int is_last;
|
16128 |
|
|
now_it.mask <<= 1;
|
16129 |
|
|
now_it.mask &= 0x1f;
|
16130 |
|
|
is_last = (now_it.mask == 0x10);
|
16131 |
|
|
|
16132 |
|
|
switch (inst.it_insn_type)
|
16133 |
|
|
{
|
16134 |
|
|
case OUTSIDE_IT_INSN:
|
16135 |
|
|
inst.error = BAD_NOT_IT;
|
16136 |
|
|
return FAIL;
|
16137 |
|
|
|
16138 |
|
|
case INSIDE_IT_INSN:
|
16139 |
|
|
if (cond != inst.cond)
|
16140 |
|
|
{
|
16141 |
|
|
inst.error = BAD_IT_COND;
|
16142 |
|
|
return FAIL;
|
16143 |
|
|
}
|
16144 |
|
|
break;
|
16145 |
|
|
|
16146 |
|
|
case INSIDE_IT_LAST_INSN:
|
16147 |
|
|
case IF_INSIDE_IT_LAST_INSN:
|
16148 |
|
|
if (cond != inst.cond)
|
16149 |
|
|
{
|
16150 |
|
|
inst.error = BAD_IT_COND;
|
16151 |
|
|
return FAIL;
|
16152 |
|
|
}
|
16153 |
|
|
if (!is_last)
|
16154 |
|
|
{
|
16155 |
|
|
inst.error = BAD_BRANCH;
|
16156 |
|
|
return FAIL;
|
16157 |
|
|
}
|
16158 |
|
|
break;
|
16159 |
|
|
|
16160 |
|
|
case NEUTRAL_IT_INSN:
|
16161 |
|
|
/* The BKPT instruction is unconditional even in an IT block. */
|
16162 |
|
|
break;
|
16163 |
|
|
|
16164 |
|
|
case IT_INSN:
|
16165 |
|
|
inst.error = BAD_IT_IT;
|
16166 |
|
|
return FAIL;
|
16167 |
|
|
}
|
16168 |
|
|
}
|
16169 |
|
|
break;
|
16170 |
|
|
}
|
16171 |
|
|
|
16172 |
|
|
return SUCCESS;
|
16173 |
|
|
}
|
16174 |
|
|
|
16175 |
|
|
static void
|
16176 |
|
|
it_fsm_post_encode (void)
|
16177 |
|
|
{
|
16178 |
|
|
int is_last;
|
16179 |
|
|
|
16180 |
|
|
if (!now_it.state_handled)
|
16181 |
|
|
handle_it_state ();
|
16182 |
|
|
|
16183 |
|
|
is_last = (now_it.mask == 0x10);
|
16184 |
|
|
if (is_last)
|
16185 |
|
|
{
|
16186 |
|
|
now_it.state = OUTSIDE_IT_BLOCK;
|
16187 |
|
|
now_it.mask = 0;
|
16188 |
|
|
}
|
16189 |
|
|
}
|
16190 |
|
|
|
16191 |
|
|
static void
|
16192 |
|
|
force_automatic_it_block_close (void)
|
16193 |
|
|
{
|
16194 |
|
|
if (now_it.state == AUTOMATIC_IT_BLOCK)
|
16195 |
|
|
{
|
16196 |
|
|
close_automatic_it_block ();
|
16197 |
|
|
now_it.state = OUTSIDE_IT_BLOCK;
|
16198 |
|
|
now_it.mask = 0;
|
16199 |
|
|
}
|
16200 |
|
|
}
|
16201 |
|
|
|
16202 |
|
|
static int
|
16203 |
|
|
in_it_block (void)
|
16204 |
|
|
{
|
16205 |
|
|
if (!now_it.state_handled)
|
16206 |
|
|
handle_it_state ();
|
16207 |
|
|
|
16208 |
|
|
return now_it.state != OUTSIDE_IT_BLOCK;
|
16209 |
|
|
}
|
16210 |
|
|
|
16211 |
|
|
void
|
16212 |
|
|
md_assemble (char *str)
|
16213 |
|
|
{
|
16214 |
|
|
char *p = str;
|
16215 |
|
|
const struct asm_opcode * opcode;
|
16216 |
|
|
|
16217 |
|
|
/* Align the previous label if needed. */
|
16218 |
|
|
if (last_label_seen != NULL)
|
16219 |
|
|
{
|
16220 |
|
|
symbol_set_frag (last_label_seen, frag_now);
|
16221 |
|
|
S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
|
16222 |
|
|
S_SET_SEGMENT (last_label_seen, now_seg);
|
16223 |
|
|
}
|
16224 |
|
|
|
16225 |
|
|
memset (&inst, '\0', sizeof (inst));
|
16226 |
|
|
inst.reloc.type = BFD_RELOC_UNUSED;
|
16227 |
|
|
|
16228 |
|
|
opcode = opcode_lookup (&p);
|
16229 |
|
|
if (!opcode)
|
16230 |
|
|
{
|
16231 |
|
|
/* It wasn't an instruction, but it might be a register alias of
|
16232 |
|
|
the form alias .req reg, or a Neon .dn/.qn directive. */
|
16233 |
|
|
if (! create_register_alias (str, p)
|
16234 |
|
|
&& ! create_neon_reg_alias (str, p))
|
16235 |
|
|
as_bad (_("bad instruction `%s'"), str);
|
16236 |
|
|
|
16237 |
|
|
return;
|
16238 |
|
|
}
|
16239 |
|
|
|
16240 |
|
|
if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
|
16241 |
|
|
as_warn (_("s suffix on comparison instruction is deprecated"));
|
16242 |
|
|
|
16243 |
|
|
/* The value which unconditional instructions should have in place of the
|
16244 |
|
|
condition field. */
|
16245 |
|
|
inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
|
16246 |
|
|
|
16247 |
|
|
if (thumb_mode)
|
16248 |
|
|
{
|
16249 |
|
|
arm_feature_set variant;
|
16250 |
|
|
|
16251 |
|
|
variant = cpu_variant;
|
16252 |
|
|
/* Only allow coprocessor instructions on Thumb-2 capable devices. */
|
16253 |
|
|
if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
|
16254 |
|
|
ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
|
16255 |
|
|
/* Check that this instruction is supported for this CPU. */
|
16256 |
|
|
if (!opcode->tvariant
|
16257 |
|
|
|| (thumb_mode == 1
|
16258 |
|
|
&& !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
|
16259 |
|
|
{
|
16260 |
|
|
as_bad (_("selected processor does not support Thumb mode `%s'"), str);
|
16261 |
|
|
return;
|
16262 |
|
|
}
|
16263 |
|
|
if (inst.cond != COND_ALWAYS && !unified_syntax
|
16264 |
|
|
&& opcode->tencode != do_t_branch)
|
16265 |
|
|
{
|
16266 |
|
|
as_bad (_("Thumb does not support conditional execution"));
|
16267 |
|
|
return;
|
16268 |
|
|
}
|
16269 |
|
|
|
16270 |
|
|
if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
|
16271 |
|
|
{
|
16272 |
|
|
if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
|
16273 |
|
|
&& !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
|
16274 |
|
|
|| ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
|
16275 |
|
|
{
|
16276 |
|
|
/* Two things are addressed here.
|
16277 |
|
|
1) Implicit require narrow instructions on Thumb-1.
|
16278 |
|
|
This avoids relaxation accidentally introducing Thumb-2
|
16279 |
|
|
instructions.
|
16280 |
|
|
2) Reject wide instructions in non Thumb-2 cores. */
|
16281 |
|
|
if (inst.size_req == 0)
|
16282 |
|
|
inst.size_req = 2;
|
16283 |
|
|
else if (inst.size_req == 4)
|
16284 |
|
|
{
|
16285 |
|
|
as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
|
16286 |
|
|
return;
|
16287 |
|
|
}
|
16288 |
|
|
}
|
16289 |
|
|
}
|
16290 |
|
|
|
16291 |
|
|
inst.instruction = opcode->tvalue;
|
16292 |
|
|
|
16293 |
|
|
if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
|
16294 |
|
|
{
|
16295 |
|
|
/* Prepare the it_insn_type for those encodings that don't set
|
16296 |
|
|
it. */
|
16297 |
|
|
it_fsm_pre_encode ();
|
16298 |
|
|
|
16299 |
|
|
opcode->tencode ();
|
16300 |
|
|
|
16301 |
|
|
it_fsm_post_encode ();
|
16302 |
|
|
}
|
16303 |
|
|
|
16304 |
|
|
if (!(inst.error || inst.relax))
|
16305 |
|
|
{
|
16306 |
|
|
gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
|
16307 |
|
|
inst.size = (inst.instruction > 0xffff ? 4 : 2);
|
16308 |
|
|
if (inst.size_req && inst.size_req != inst.size)
|
16309 |
|
|
{
|
16310 |
|
|
as_bad (_("cannot honor width suffix -- `%s'"), str);
|
16311 |
|
|
return;
|
16312 |
|
|
}
|
16313 |
|
|
}
|
16314 |
|
|
|
16315 |
|
|
/* Something has gone badly wrong if we try to relax a fixed size
|
16316 |
|
|
instruction. */
|
16317 |
|
|
gas_assert (inst.size_req == 0 || !inst.relax);
|
16318 |
|
|
|
16319 |
|
|
ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
|
16320 |
|
|
*opcode->tvariant);
|
16321 |
|
|
/* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
|
16322 |
|
|
set those bits when Thumb-2 32-bit instructions are seen. ie.
|
16323 |
|
|
anything other than bl/blx and v6-M instructions.
|
16324 |
|
|
This is overly pessimistic for relaxable instructions. */
|
16325 |
|
|
if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
|
16326 |
|
|
|| inst.relax)
|
16327 |
|
|
&& !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
|
16328 |
|
|
|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
|
16329 |
|
|
ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
|
16330 |
|
|
arm_ext_v6t2);
|
16331 |
|
|
|
16332 |
|
|
check_neon_suffixes;
|
16333 |
|
|
|
16334 |
|
|
if (!inst.error)
|
16335 |
|
|
{
|
16336 |
|
|
mapping_state (MAP_THUMB);
|
16337 |
|
|
}
|
16338 |
|
|
}
|
16339 |
|
|
else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
|
16340 |
|
|
{
|
16341 |
|
|
bfd_boolean is_bx;
|
16342 |
|
|
|
16343 |
|
|
/* bx is allowed on v5 cores, and sometimes on v4 cores. */
|
16344 |
|
|
is_bx = (opcode->aencode == do_bx);
|
16345 |
|
|
|
16346 |
|
|
/* Check that this instruction is supported for this CPU. */
|
16347 |
|
|
if (!(is_bx && fix_v4bx)
|
16348 |
|
|
&& !(opcode->avariant &&
|
16349 |
|
|
ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
|
16350 |
|
|
{
|
16351 |
|
|
as_bad (_("selected processor does not support ARM mode `%s'"), str);
|
16352 |
|
|
return;
|
16353 |
|
|
}
|
16354 |
|
|
if (inst.size_req)
|
16355 |
|
|
{
|
16356 |
|
|
as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
|
16357 |
|
|
return;
|
16358 |
|
|
}
|
16359 |
|
|
|
16360 |
|
|
inst.instruction = opcode->avalue;
|
16361 |
|
|
if (opcode->tag == OT_unconditionalF)
|
16362 |
|
|
inst.instruction |= 0xF << 28;
|
16363 |
|
|
else
|
16364 |
|
|
inst.instruction |= inst.cond << 28;
|
16365 |
|
|
inst.size = INSN_SIZE;
|
16366 |
|
|
if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
|
16367 |
|
|
{
|
16368 |
|
|
it_fsm_pre_encode ();
|
16369 |
|
|
opcode->aencode ();
|
16370 |
|
|
it_fsm_post_encode ();
|
16371 |
|
|
}
|
16372 |
|
|
/* Arm mode bx is marked as both v4T and v5 because it's still required
|
16373 |
|
|
on a hypothetical non-thumb v5 core. */
|
16374 |
|
|
if (is_bx)
|
16375 |
|
|
ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
|
16376 |
|
|
else
|
16377 |
|
|
ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
|
16378 |
|
|
*opcode->avariant);
|
16379 |
|
|
|
16380 |
|
|
check_neon_suffixes;
|
16381 |
|
|
|
16382 |
|
|
if (!inst.error)
|
16383 |
|
|
{
|
16384 |
|
|
mapping_state (MAP_ARM);
|
16385 |
|
|
}
|
16386 |
|
|
}
|
16387 |
|
|
else
|
16388 |
|
|
{
|
16389 |
|
|
as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
|
16390 |
|
|
"-- `%s'"), str);
|
16391 |
|
|
return;
|
16392 |
|
|
}
|
16393 |
|
|
output_inst (str);
|
16394 |
|
|
}
|
16395 |
|
|
|
16396 |
|
|
static void
|
16397 |
|
|
check_it_blocks_finished (void)
|
16398 |
|
|
{
|
16399 |
|
|
#ifdef OBJ_ELF
|
16400 |
|
|
asection *sect;
|
16401 |
|
|
|
16402 |
|
|
for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
|
16403 |
|
|
if (seg_info (sect)->tc_segment_info_data.current_it.state
|
16404 |
|
|
== MANUAL_IT_BLOCK)
|
16405 |
|
|
{
|
16406 |
|
|
as_warn (_("section '%s' finished with an open IT block."),
|
16407 |
|
|
sect->name);
|
16408 |
|
|
}
|
16409 |
|
|
#else
|
16410 |
|
|
if (now_it.state == MANUAL_IT_BLOCK)
|
16411 |
|
|
as_warn (_("file finished with an open IT block."));
|
16412 |
|
|
#endif
|
16413 |
|
|
}
|
16414 |
|
|
|
16415 |
|
|
/* Various frobbings of labels and their addresses. */
|
16416 |
|
|
|
16417 |
|
|
void
|
16418 |
|
|
arm_start_line_hook (void)
|
16419 |
|
|
{
|
16420 |
|
|
last_label_seen = NULL;
|
16421 |
|
|
}
|
16422 |
|
|
|
16423 |
|
|
void
|
16424 |
|
|
arm_frob_label (symbolS * sym)
|
16425 |
|
|
{
|
16426 |
|
|
last_label_seen = sym;
|
16427 |
|
|
|
16428 |
|
|
ARM_SET_THUMB (sym, thumb_mode);
|
16429 |
|
|
|
16430 |
|
|
#if defined OBJ_COFF || defined OBJ_ELF
|
16431 |
|
|
ARM_SET_INTERWORK (sym, support_interwork);
|
16432 |
|
|
#endif
|
16433 |
|
|
|
16434 |
|
|
force_automatic_it_block_close ();
|
16435 |
|
|
|
16436 |
|
|
/* Note - do not allow local symbols (.Lxxx) to be labelled
|
16437 |
|
|
as Thumb functions. This is because these labels, whilst
|
16438 |
|
|
they exist inside Thumb code, are not the entry points for
|
16439 |
|
|
possible ARM->Thumb calls. Also, these labels can be used
|
16440 |
|
|
as part of a computed goto or switch statement. eg gcc
|
16441 |
|
|
can generate code that looks like this:
|
16442 |
|
|
|
16443 |
|
|
ldr r2, [pc, .Laaa]
|
16444 |
|
|
lsl r3, r3, #2
|
16445 |
|
|
ldr r2, [r3, r2]
|
16446 |
|
|
mov pc, r2
|
16447 |
|
|
|
16448 |
|
|
.Lbbb: .word .Lxxx
|
16449 |
|
|
.Lccc: .word .Lyyy
|
16450 |
|
|
..etc...
|
16451 |
|
|
.Laaa: .word Lbbb
|
16452 |
|
|
|
16453 |
|
|
The first instruction loads the address of the jump table.
|
16454 |
|
|
The second instruction converts a table index into a byte offset.
|
16455 |
|
|
The third instruction gets the jump address out of the table.
|
16456 |
|
|
The fourth instruction performs the jump.
|
16457 |
|
|
|
16458 |
|
|
If the address stored at .Laaa is that of a symbol which has the
|
16459 |
|
|
Thumb_Func bit set, then the linker will arrange for this address
|
16460 |
|
|
to have the bottom bit set, which in turn would mean that the
|
16461 |
|
|
address computation performed by the third instruction would end
|
16462 |
|
|
up with the bottom bit set. Since the ARM is capable of unaligned
|
16463 |
|
|
word loads, the instruction would then load the incorrect address
|
16464 |
|
|
out of the jump table, and chaos would ensue. */
|
16465 |
|
|
if (label_is_thumb_function_name
|
16466 |
|
|
&& (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
|
16467 |
|
|
&& (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
|
16468 |
|
|
{
|
16469 |
|
|
/* When the address of a Thumb function is taken the bottom
|
16470 |
|
|
bit of that address should be set. This will allow
|
16471 |
|
|
interworking between Arm and Thumb functions to work
|
16472 |
|
|
correctly. */
|
16473 |
|
|
|
16474 |
|
|
THUMB_SET_FUNC (sym, 1);
|
16475 |
|
|
|
16476 |
|
|
label_is_thumb_function_name = FALSE;
|
16477 |
|
|
}
|
16478 |
|
|
|
16479 |
|
|
dwarf2_emit_label (sym);
|
16480 |
|
|
}
|
16481 |
|
|
|
16482 |
|
|
bfd_boolean
|
16483 |
|
|
arm_data_in_code (void)
|
16484 |
|
|
{
|
16485 |
|
|
if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
|
16486 |
|
|
{
|
16487 |
|
|
*input_line_pointer = '/';
|
16488 |
|
|
input_line_pointer += 5;
|
16489 |
|
|
*input_line_pointer = 0;
|
16490 |
|
|
return TRUE;
|
16491 |
|
|
}
|
16492 |
|
|
|
16493 |
|
|
return FALSE;
|
16494 |
|
|
}
|
16495 |
|
|
|
16496 |
|
|
char *
|
16497 |
|
|
arm_canonicalize_symbol_name (char * name)
|
16498 |
|
|
{
|
16499 |
|
|
int len;
|
16500 |
|
|
|
16501 |
|
|
if (thumb_mode && (len = strlen (name)) > 5
|
16502 |
|
|
&& streq (name + len - 5, "/data"))
|
16503 |
|
|
*(name + len - 5) = 0;
|
16504 |
|
|
|
16505 |
|
|
return name;
|
16506 |
|
|
}
|
16507 |
|
|
|
16508 |
|
|
/* Table of all register names defined by default. The user can
|
16509 |
|
|
define additional names with .req. Note that all register names
|
16510 |
|
|
should appear in both upper and lowercase variants. Some registers
|
16511 |
|
|
also have mixed-case names. */
|
16512 |
|
|
|
16513 |
|
|
#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
|
16514 |
|
|
#define REGNUM(p,n,t) REGDEF(p##n, n, t)
|
16515 |
|
|
#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
|
16516 |
|
|
#define REGSET(p,t) \
|
16517 |
|
|
REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
|
16518 |
|
|
REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
|
16519 |
|
|
REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
|
16520 |
|
|
REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
|
16521 |
|
|
#define REGSETH(p,t) \
|
16522 |
|
|
REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
|
16523 |
|
|
REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
|
16524 |
|
|
REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
|
16525 |
|
|
REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
|
16526 |
|
|
#define REGSET2(p,t) \
|
16527 |
|
|
REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
|
16528 |
|
|
REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
|
16529 |
|
|
REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
|
16530 |
|
|
REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
|
16531 |
|
|
#define SPLRBANK(base,bank,t) \
|
16532 |
|
|
REGDEF(lr_##bank, 768|((base+0)<<16), t), \
|
16533 |
|
|
REGDEF(sp_##bank, 768|((base+1)<<16), t), \
|
16534 |
|
|
REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
|
16535 |
|
|
REGDEF(LR_##bank, 768|((base+0)<<16), t), \
|
16536 |
|
|
REGDEF(SP_##bank, 768|((base+1)<<16), t), \
|
16537 |
|
|
REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
|
16538 |
|
|
|
16539 |
|
|
static const struct reg_entry reg_names[] =
|
16540 |
|
|
{
|
16541 |
|
|
/* ARM integer registers. */
|
16542 |
|
|
REGSET(r, RN), REGSET(R, RN),
|
16543 |
|
|
|
16544 |
|
|
/* ATPCS synonyms. */
|
16545 |
|
|
REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
|
16546 |
|
|
REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
|
16547 |
|
|
REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
|
16548 |
|
|
|
16549 |
|
|
REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
|
16550 |
|
|
REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
|
16551 |
|
|
REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
|
16552 |
|
|
|
16553 |
|
|
/* Well-known aliases. */
|
16554 |
|
|
REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
|
16555 |
|
|
REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
|
16556 |
|
|
|
16557 |
|
|
REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
|
16558 |
|
|
REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
|
16559 |
|
|
|
16560 |
|
|
/* Coprocessor numbers. */
|
16561 |
|
|
REGSET(p, CP), REGSET(P, CP),
|
16562 |
|
|
|
16563 |
|
|
/* Coprocessor register numbers. The "cr" variants are for backward
|
16564 |
|
|
compatibility. */
|
16565 |
|
|
REGSET(c, CN), REGSET(C, CN),
|
16566 |
|
|
REGSET(cr, CN), REGSET(CR, CN),
|
16567 |
|
|
|
16568 |
|
|
/* ARM banked registers. */
|
16569 |
|
|
REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
|
16570 |
|
|
REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
|
16571 |
|
|
REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
|
16572 |
|
|
REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
|
16573 |
|
|
REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
|
16574 |
|
|
REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
|
16575 |
|
|
REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
|
16576 |
|
|
|
16577 |
|
|
REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
|
16578 |
|
|
REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
|
16579 |
|
|
REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
|
16580 |
|
|
REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
|
16581 |
|
|
REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
|
16582 |
|
|
REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB),
|
16583 |
|
|
REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
|
16584 |
|
|
REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
|
16585 |
|
|
|
16586 |
|
|
SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
|
16587 |
|
|
SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
|
16588 |
|
|
SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
|
16589 |
|
|
SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
|
16590 |
|
|
SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
|
16591 |
|
|
REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
|
16592 |
|
|
REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
|
16593 |
|
|
REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
|
16594 |
|
|
REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
|
16595 |
|
|
|
16596 |
|
|
/* FPA registers. */
|
16597 |
|
|
REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
|
16598 |
|
|
REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
|
16599 |
|
|
|
16600 |
|
|
REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
|
16601 |
|
|
REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
|
16602 |
|
|
|
16603 |
|
|
/* VFP SP registers. */
|
16604 |
|
|
REGSET(s,VFS), REGSET(S,VFS),
|
16605 |
|
|
REGSETH(s,VFS), REGSETH(S,VFS),
|
16606 |
|
|
|
16607 |
|
|
/* VFP DP Registers. */
|
16608 |
|
|
REGSET(d,VFD), REGSET(D,VFD),
|
16609 |
|
|
/* Extra Neon DP registers. */
|
16610 |
|
|
REGSETH(d,VFD), REGSETH(D,VFD),
|
16611 |
|
|
|
16612 |
|
|
/* Neon QP registers. */
|
16613 |
|
|
REGSET2(q,NQ), REGSET2(Q,NQ),
|
16614 |
|
|
|
16615 |
|
|
/* VFP control registers. */
|
16616 |
|
|
REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
|
16617 |
|
|
REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
|
16618 |
|
|
REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
|
16619 |
|
|
REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
|
16620 |
|
|
REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
|
16621 |
|
|
REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
|
16622 |
|
|
|
16623 |
|
|
/* Maverick DSP coprocessor registers. */
|
16624 |
|
|
REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
|
16625 |
|
|
REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
|
16626 |
|
|
|
16627 |
|
|
REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
|
16628 |
|
|
REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
|
16629 |
|
|
REGDEF(dspsc,0,DSPSC),
|
16630 |
|
|
|
16631 |
|
|
REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
|
16632 |
|
|
REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
|
16633 |
|
|
REGDEF(DSPSC,0,DSPSC),
|
16634 |
|
|
|
16635 |
|
|
/* iWMMXt data registers - p0, c0-15. */
|
16636 |
|
|
REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
|
16637 |
|
|
|
16638 |
|
|
/* iWMMXt control registers - p1, c0-3. */
|
16639 |
|
|
REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
|
16640 |
|
|
REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
|
16641 |
|
|
REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
|
16642 |
|
|
REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
|
16643 |
|
|
|
16644 |
|
|
/* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
|
16645 |
|
|
REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
|
16646 |
|
|
REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
|
16647 |
|
|
REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
|
16648 |
|
|
REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
|
16649 |
|
|
|
16650 |
|
|
/* XScale accumulator registers. */
|
16651 |
|
|
REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
|
16652 |
|
|
};
|
16653 |
|
|
#undef REGDEF
|
16654 |
|
|
#undef REGNUM
|
16655 |
|
|
#undef REGSET
|
16656 |
|
|
|
16657 |
|
|
/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
|
16658 |
|
|
within psr_required_here. */
|
16659 |
|
|
static const struct asm_psr psrs[] =
|
16660 |
|
|
{
|
16661 |
|
|
/* Backward compatibility notation. Note that "all" is no longer
|
16662 |
|
|
truly all possible PSR bits. */
|
16663 |
|
|
{"all", PSR_c | PSR_f},
|
16664 |
|
|
{"flg", PSR_f},
|
16665 |
|
|
{"ctl", PSR_c},
|
16666 |
|
|
|
16667 |
|
|
/* Individual flags. */
|
16668 |
|
|
{"f", PSR_f},
|
16669 |
|
|
{"c", PSR_c},
|
16670 |
|
|
{"x", PSR_x},
|
16671 |
|
|
{"s", PSR_s},
|
16672 |
|
|
|
16673 |
|
|
/* Combinations of flags. */
|
16674 |
|
|
{"fs", PSR_f | PSR_s},
|
16675 |
|
|
{"fx", PSR_f | PSR_x},
|
16676 |
|
|
{"fc", PSR_f | PSR_c},
|
16677 |
|
|
{"sf", PSR_s | PSR_f},
|
16678 |
|
|
{"sx", PSR_s | PSR_x},
|
16679 |
|
|
{"sc", PSR_s | PSR_c},
|
16680 |
|
|
{"xf", PSR_x | PSR_f},
|
16681 |
|
|
{"xs", PSR_x | PSR_s},
|
16682 |
|
|
{"xc", PSR_x | PSR_c},
|
16683 |
|
|
{"cf", PSR_c | PSR_f},
|
16684 |
|
|
{"cs", PSR_c | PSR_s},
|
16685 |
|
|
{"cx", PSR_c | PSR_x},
|
16686 |
|
|
{"fsx", PSR_f | PSR_s | PSR_x},
|
16687 |
|
|
{"fsc", PSR_f | PSR_s | PSR_c},
|
16688 |
|
|
{"fxs", PSR_f | PSR_x | PSR_s},
|
16689 |
|
|
{"fxc", PSR_f | PSR_x | PSR_c},
|
16690 |
|
|
{"fcs", PSR_f | PSR_c | PSR_s},
|
16691 |
|
|
{"fcx", PSR_f | PSR_c | PSR_x},
|
16692 |
|
|
{"sfx", PSR_s | PSR_f | PSR_x},
|
16693 |
|
|
{"sfc", PSR_s | PSR_f | PSR_c},
|
16694 |
|
|
{"sxf", PSR_s | PSR_x | PSR_f},
|
16695 |
|
|
{"sxc", PSR_s | PSR_x | PSR_c},
|
16696 |
|
|
{"scf", PSR_s | PSR_c | PSR_f},
|
16697 |
|
|
{"scx", PSR_s | PSR_c | PSR_x},
|
16698 |
|
|
{"xfs", PSR_x | PSR_f | PSR_s},
|
16699 |
|
|
{"xfc", PSR_x | PSR_f | PSR_c},
|
16700 |
|
|
{"xsf", PSR_x | PSR_s | PSR_f},
|
16701 |
|
|
{"xsc", PSR_x | PSR_s | PSR_c},
|
16702 |
|
|
{"xcf", PSR_x | PSR_c | PSR_f},
|
16703 |
|
|
{"xcs", PSR_x | PSR_c | PSR_s},
|
16704 |
|
|
{"cfs", PSR_c | PSR_f | PSR_s},
|
16705 |
|
|
{"cfx", PSR_c | PSR_f | PSR_x},
|
16706 |
|
|
{"csf", PSR_c | PSR_s | PSR_f},
|
16707 |
|
|
{"csx", PSR_c | PSR_s | PSR_x},
|
16708 |
|
|
{"cxf", PSR_c | PSR_x | PSR_f},
|
16709 |
|
|
{"cxs", PSR_c | PSR_x | PSR_s},
|
16710 |
|
|
{"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
|
16711 |
|
|
{"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
|
16712 |
|
|
{"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
|
16713 |
|
|
{"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
|
16714 |
|
|
{"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
|
16715 |
|
|
{"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
|
16716 |
|
|
{"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
|
16717 |
|
|
{"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
|
16718 |
|
|
{"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
|
16719 |
|
|
{"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
|
16720 |
|
|
{"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
|
16721 |
|
|
{"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
|
16722 |
|
|
{"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
|
16723 |
|
|
{"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
|
16724 |
|
|
{"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
|
16725 |
|
|
{"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
|
16726 |
|
|
{"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
|
16727 |
|
|
{"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
|
16728 |
|
|
{"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
|
16729 |
|
|
{"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
|
16730 |
|
|
{"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
|
16731 |
|
|
{"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
|
16732 |
|
|
{"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
|
16733 |
|
|
{"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
|
16734 |
|
|
};
|
16735 |
|
|
|
16736 |
|
|
/* Table of V7M psr names. */
|
16737 |
|
|
static const struct asm_psr v7m_psrs[] =
|
16738 |
|
|
{
|
16739 |
|
|
{"apsr", 0 }, {"APSR", 0 },
|
16740 |
|
|
{"iapsr", 1 }, {"IAPSR", 1 },
|
16741 |
|
|
{"eapsr", 2 }, {"EAPSR", 2 },
|
16742 |
|
|
{"psr", 3 }, {"PSR", 3 },
|
16743 |
|
|
{"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
|
16744 |
|
|
{"ipsr", 5 }, {"IPSR", 5 },
|
16745 |
|
|
{"epsr", 6 }, {"EPSR", 6 },
|
16746 |
|
|
{"iepsr", 7 }, {"IEPSR", 7 },
|
16747 |
|
|
{"msp", 8 }, {"MSP", 8 },
|
16748 |
|
|
{"psp", 9 }, {"PSP", 9 },
|
16749 |
|
|
{"primask", 16}, {"PRIMASK", 16},
|
16750 |
|
|
{"basepri", 17}, {"BASEPRI", 17},
|
16751 |
|
|
{"basepri_max", 18}, {"BASEPRI_MAX", 18},
|
16752 |
|
|
{"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
|
16753 |
|
|
{"faultmask", 19}, {"FAULTMASK", 19},
|
16754 |
|
|
{"control", 20}, {"CONTROL", 20}
|
16755 |
|
|
};
|
16756 |
|
|
|
16757 |
|
|
/* Table of all shift-in-operand names. */
|
16758 |
|
|
static const struct asm_shift_name shift_names [] =
|
16759 |
|
|
{
|
16760 |
|
|
{ "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
|
16761 |
|
|
{ "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
|
16762 |
|
|
{ "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
|
16763 |
|
|
{ "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
|
16764 |
|
|
{ "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
|
16765 |
|
|
{ "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
|
16766 |
|
|
};
|
16767 |
|
|
|
16768 |
|
|
/* Table of all explicit relocation names. */
|
16769 |
|
|
#ifdef OBJ_ELF
|
16770 |
|
|
static struct reloc_entry reloc_names[] =
|
16771 |
|
|
{
|
16772 |
|
|
{ "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
|
16773 |
|
|
{ "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
|
16774 |
|
|
{ "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
|
16775 |
|
|
{ "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
|
16776 |
|
|
{ "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
|
16777 |
|
|
{ "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
|
16778 |
|
|
{ "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
|
16779 |
|
|
{ "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
|
16780 |
|
|
{ "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
|
16781 |
|
|
{ "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
|
16782 |
|
|
{ "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
|
16783 |
|
|
{ "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
|
16784 |
|
|
{ "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
|
16785 |
|
|
{ "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
|
16786 |
|
|
{ "tlscall", BFD_RELOC_ARM_TLS_CALL},
|
16787 |
|
|
{ "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
|
16788 |
|
|
{ "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
|
16789 |
|
|
{ "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
|
16790 |
|
|
};
|
16791 |
|
|
#endif
|
16792 |
|
|
|
16793 |
|
|
/* Table of all conditional affixes. 0xF is not defined as a condition code. */
|
16794 |
|
|
static const struct asm_cond conds[] =
|
16795 |
|
|
{
|
16796 |
|
|
{"eq", 0x0},
|
16797 |
|
|
{"ne", 0x1},
|
16798 |
|
|
{"cs", 0x2}, {"hs", 0x2},
|
16799 |
|
|
{"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
|
16800 |
|
|
{"mi", 0x4},
|
16801 |
|
|
{"pl", 0x5},
|
16802 |
|
|
{"vs", 0x6},
|
16803 |
|
|
{"vc", 0x7},
|
16804 |
|
|
{"hi", 0x8},
|
16805 |
|
|
{"ls", 0x9},
|
16806 |
|
|
{"ge", 0xa},
|
16807 |
|
|
{"lt", 0xb},
|
16808 |
|
|
{"gt", 0xc},
|
16809 |
|
|
{"le", 0xd},
|
16810 |
|
|
{"al", 0xe}
|
16811 |
|
|
};
|
16812 |
|
|
|
16813 |
|
|
static struct asm_barrier_opt barrier_opt_names[] =
|
16814 |
|
|
{
|
16815 |
|
|
{ "sy", 0xf }, { "SY", 0xf },
|
16816 |
|
|
{ "un", 0x7 }, { "UN", 0x7 },
|
16817 |
|
|
{ "st", 0xe }, { "ST", 0xe },
|
16818 |
|
|
{ "unst", 0x6 }, { "UNST", 0x6 },
|
16819 |
|
|
{ "ish", 0xb }, { "ISH", 0xb },
|
16820 |
|
|
{ "sh", 0xb }, { "SH", 0xb },
|
16821 |
|
|
{ "ishst", 0xa }, { "ISHST", 0xa },
|
16822 |
|
|
{ "shst", 0xa }, { "SHST", 0xa },
|
16823 |
|
|
{ "nsh", 0x7 }, { "NSH", 0x7 },
|
16824 |
|
|
{ "nshst", 0x6 }, { "NSHST", 0x6 },
|
16825 |
|
|
{ "osh", 0x3 }, { "OSH", 0x3 },
|
16826 |
|
|
{ "oshst", 0x2 }, { "OSHST", 0x2 }
|
16827 |
|
|
};
|
16828 |
|
|
|
16829 |
|
|
/* Table of ARM-format instructions. */
|
16830 |
|
|
|
16831 |
|
|
/* Macros for gluing together operand strings. N.B. In all cases
|
16832 |
|
|
other than OPS0, the trailing OP_stop comes from default
|
16833 |
|
|
zero-initialization of the unspecified elements of the array. */
|
16834 |
|
|
#define OPS0() { OP_stop, }
|
16835 |
|
|
#define OPS1(a) { OP_##a, }
|
16836 |
|
|
#define OPS2(a,b) { OP_##a,OP_##b, }
|
16837 |
|
|
#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
|
16838 |
|
|
#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
|
16839 |
|
|
#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
|
16840 |
|
|
#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
|
16841 |
|
|
|
16842 |
|
|
/* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
|
16843 |
|
|
This is useful when mixing operands for ARM and THUMB, i.e. using the
|
16844 |
|
|
MIX_ARM_THUMB_OPERANDS macro.
|
16845 |
|
|
In order to use these macros, prefix the number of operands with _
|
16846 |
|
|
e.g. _3. */
|
16847 |
|
|
#define OPS_1(a) { a, }
|
16848 |
|
|
#define OPS_2(a,b) { a,b, }
|
16849 |
|
|
#define OPS_3(a,b,c) { a,b,c, }
|
16850 |
|
|
#define OPS_4(a,b,c,d) { a,b,c,d, }
|
16851 |
|
|
#define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
|
16852 |
|
|
#define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
|
16853 |
|
|
|
16854 |
|
|
/* These macros abstract out the exact format of the mnemonic table and
|
16855 |
|
|
save some repeated characters. */
|
16856 |
|
|
|
16857 |
|
|
/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
|
16858 |
|
|
#define TxCE(mnem, op, top, nops, ops, ae, te) \
|
16859 |
|
|
{ mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
|
16860 |
|
|
THUMB_VARIANT, do_##ae, do_##te }
|
16861 |
|
|
|
16862 |
|
|
/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
|
16863 |
|
|
a T_MNEM_xyz enumerator. */
|
16864 |
|
|
#define TCE(mnem, aop, top, nops, ops, ae, te) \
|
16865 |
|
|
TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
|
16866 |
|
|
#define tCE(mnem, aop, top, nops, ops, ae, te) \
|
16867 |
|
|
TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
|
16868 |
|
|
|
16869 |
|
|
/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
|
16870 |
|
|
infix after the third character. */
|
16871 |
|
|
#define TxC3(mnem, op, top, nops, ops, ae, te) \
|
16872 |
|
|
{ mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
|
16873 |
|
|
THUMB_VARIANT, do_##ae, do_##te }
|
16874 |
|
|
#define TxC3w(mnem, op, top, nops, ops, ae, te) \
|
16875 |
|
|
{ mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
|
16876 |
|
|
THUMB_VARIANT, do_##ae, do_##te }
|
16877 |
|
|
#define TC3(mnem, aop, top, nops, ops, ae, te) \
|
16878 |
|
|
TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
|
16879 |
|
|
#define TC3w(mnem, aop, top, nops, ops, ae, te) \
|
16880 |
|
|
TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
|
16881 |
|
|
#define tC3(mnem, aop, top, nops, ops, ae, te) \
|
16882 |
|
|
TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
|
16883 |
|
|
#define tC3w(mnem, aop, top, nops, ops, ae, te) \
|
16884 |
|
|
TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
|
16885 |
|
|
|
16886 |
|
|
/* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
|
16887 |
|
|
appear in the condition table. */
|
16888 |
|
|
#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
|
16889 |
|
|
{ m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
|
16890 |
|
|
0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
|
16891 |
|
|
|
16892 |
|
|
#define TxCM(m1, m2, op, top, nops, ops, ae, te) \
|
16893 |
|
|
TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
|
16894 |
|
|
TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
|
16895 |
|
|
TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
|
16896 |
|
|
TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
|
16897 |
|
|
TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
|
16898 |
|
|
TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
|
16899 |
|
|
TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
|
16900 |
|
|
TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
|
16901 |
|
|
TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
|
16902 |
|
|
TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
|
16903 |
|
|
TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
|
16904 |
|
|
TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
|
16905 |
|
|
TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
|
16906 |
|
|
TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
|
16907 |
|
|
TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
|
16908 |
|
|
TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
|
16909 |
|
|
TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
|
16910 |
|
|
TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
|
16911 |
|
|
TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
|
16912 |
|
|
|
16913 |
|
|
#define TCM(m1,m2, aop, top, nops, ops, ae, te) \
|
16914 |
|
|
TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
|
16915 |
|
|
#define tCM(m1,m2, aop, top, nops, ops, ae, te) \
|
16916 |
|
|
TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
|
16917 |
|
|
|
16918 |
|
|
/* Mnemonic that cannot be conditionalized. The ARM condition-code
|
16919 |
|
|
field is still 0xE. Many of the Thumb variants can be executed
|
16920 |
|
|
conditionally, so this is checked separately. */
|
16921 |
|
|
#define TUE(mnem, op, top, nops, ops, ae, te) \
|
16922 |
|
|
{ mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
|
16923 |
|
|
THUMB_VARIANT, do_##ae, do_##te }
|
16924 |
|
|
|
16925 |
|
|
/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
|
16926 |
|
|
condition code field. */
|
16927 |
|
|
#define TUF(mnem, op, top, nops, ops, ae, te) \
|
16928 |
|
|
{ mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
|
16929 |
|
|
THUMB_VARIANT, do_##ae, do_##te }
|
16930 |
|
|
|
16931 |
|
|
/* ARM-only variants of all the above. */
|
16932 |
|
|
#define CE(mnem, op, nops, ops, ae) \
|
16933 |
|
|
{ mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
|
16934 |
|
|
|
16935 |
|
|
#define C3(mnem, op, nops, ops, ae) \
|
16936 |
|
|
{ #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
|
16937 |
|
|
|
16938 |
|
|
/* Legacy mnemonics that always have conditional infix after the third
|
16939 |
|
|
character. */
|
16940 |
|
|
#define CL(mnem, op, nops, ops, ae) \
|
16941 |
|
|
{ mnem, OPS##nops ops, OT_cinfix3_legacy, \
|
16942 |
|
|
0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
|
16943 |
|
|
|
16944 |
|
|
/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
|
16945 |
|
|
#define cCE(mnem, op, nops, ops, ae) \
|
16946 |
|
|
{ mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
|
16947 |
|
|
|
16948 |
|
|
/* Legacy coprocessor instructions where conditional infix and conditional
|
16949 |
|
|
suffix are ambiguous. For consistency this includes all FPA instructions,
|
16950 |
|
|
not just the potentially ambiguous ones. */
|
16951 |
|
|
#define cCL(mnem, op, nops, ops, ae) \
|
16952 |
|
|
{ mnem, OPS##nops ops, OT_cinfix3_legacy, \
|
16953 |
|
|
0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
|
16954 |
|
|
|
16955 |
|
|
/* Coprocessor, takes either a suffix or a position-3 infix
|
16956 |
|
|
(for an FPA corner case). */
|
16957 |
|
|
#define C3E(mnem, op, nops, ops, ae) \
|
16958 |
|
|
{ mnem, OPS##nops ops, OT_csuf_or_in3, \
|
16959 |
|
|
0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
|
16960 |
|
|
|
16961 |
|
|
#define xCM_(m1, m2, m3, op, nops, ops, ae) \
|
16962 |
|
|
{ m1 #m2 m3, OPS##nops ops, \
|
16963 |
|
|
sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
|
16964 |
|
|
0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
|
16965 |
|
|
|
16966 |
|
|
#define CM(m1, m2, op, nops, ops, ae) \
|
16967 |
|
|
xCM_ (m1, , m2, op, nops, ops, ae), \
|
16968 |
|
|
xCM_ (m1, eq, m2, op, nops, ops, ae), \
|
16969 |
|
|
xCM_ (m1, ne, m2, op, nops, ops, ae), \
|
16970 |
|
|
xCM_ (m1, cs, m2, op, nops, ops, ae), \
|
16971 |
|
|
xCM_ (m1, hs, m2, op, nops, ops, ae), \
|
16972 |
|
|
xCM_ (m1, cc, m2, op, nops, ops, ae), \
|
16973 |
|
|
xCM_ (m1, ul, m2, op, nops, ops, ae), \
|
16974 |
|
|
xCM_ (m1, lo, m2, op, nops, ops, ae), \
|
16975 |
|
|
xCM_ (m1, mi, m2, op, nops, ops, ae), \
|
16976 |
|
|
xCM_ (m1, pl, m2, op, nops, ops, ae), \
|
16977 |
|
|
xCM_ (m1, vs, m2, op, nops, ops, ae), \
|
16978 |
|
|
xCM_ (m1, vc, m2, op, nops, ops, ae), \
|
16979 |
|
|
xCM_ (m1, hi, m2, op, nops, ops, ae), \
|
16980 |
|
|
xCM_ (m1, ls, m2, op, nops, ops, ae), \
|
16981 |
|
|
xCM_ (m1, ge, m2, op, nops, ops, ae), \
|
16982 |
|
|
xCM_ (m1, lt, m2, op, nops, ops, ae), \
|
16983 |
|
|
xCM_ (m1, gt, m2, op, nops, ops, ae), \
|
16984 |
|
|
xCM_ (m1, le, m2, op, nops, ops, ae), \
|
16985 |
|
|
xCM_ (m1, al, m2, op, nops, ops, ae)
|
16986 |
|
|
|
16987 |
|
|
#define UE(mnem, op, nops, ops, ae) \
|
16988 |
|
|
{ #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
|
16989 |
|
|
|
16990 |
|
|
#define UF(mnem, op, nops, ops, ae) \
|
16991 |
|
|
{ #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
|
16992 |
|
|
|
16993 |
|
|
/* Neon data-processing. ARM versions are unconditional with cond=0xf.
|
16994 |
|
|
The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
|
16995 |
|
|
use the same encoding function for each. */
|
16996 |
|
|
#define NUF(mnem, op, nops, ops, enc) \
|
16997 |
|
|
{ #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
|
16998 |
|
|
ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
|
16999 |
|
|
|
17000 |
|
|
/* Neon data processing, version which indirects through neon_enc_tab for
|
17001 |
|
|
the various overloaded versions of opcodes. */
|
17002 |
|
|
#define nUF(mnem, op, nops, ops, enc) \
|
17003 |
|
|
{ #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
|
17004 |
|
|
ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
|
17005 |
|
|
|
17006 |
|
|
/* Neon insn with conditional suffix for the ARM version, non-overloaded
|
17007 |
|
|
version. */
|
17008 |
|
|
#define NCE_tag(mnem, op, nops, ops, enc, tag) \
|
17009 |
|
|
{ #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
|
17010 |
|
|
THUMB_VARIANT, do_##enc, do_##enc }
|
17011 |
|
|
|
17012 |
|
|
#define NCE(mnem, op, nops, ops, enc) \
|
17013 |
|
|
NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
|
17014 |
|
|
|
17015 |
|
|
#define NCEF(mnem, op, nops, ops, enc) \
|
17016 |
|
|
NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
|
17017 |
|
|
|
17018 |
|
|
/* Neon insn with conditional suffix for the ARM version, overloaded types. */
|
17019 |
|
|
#define nCE_tag(mnem, op, nops, ops, enc, tag) \
|
17020 |
|
|
{ #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
|
17021 |
|
|
ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
|
17022 |
|
|
|
17023 |
|
|
#define nCE(mnem, op, nops, ops, enc) \
|
17024 |
|
|
nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
|
17025 |
|
|
|
17026 |
|
|
#define nCEF(mnem, op, nops, ops, enc) \
|
17027 |
|
|
nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
|
17028 |
|
|
|
17029 |
|
|
#define do_0 0
|
17030 |
|
|
|
17031 |
|
|
static const struct asm_opcode insns[] =
|
17032 |
|
|
{
|
17033 |
|
|
#define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
|
17034 |
|
|
#define THUMB_VARIANT &arm_ext_v4t
|
17035 |
|
|
tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
|
17036 |
|
|
tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
|
17037 |
|
|
tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
|
17038 |
|
|
tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
|
17039 |
|
|
tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
|
17040 |
|
|
tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
|
17041 |
|
|
tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
|
17042 |
|
|
tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
|
17043 |
|
|
tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
|
17044 |
|
|
tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
|
17045 |
|
|
tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
|
17046 |
|
|
tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
|
17047 |
|
|
tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
|
17048 |
|
|
tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
|
17049 |
|
|
tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
|
17050 |
|
|
tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
|
17051 |
|
|
|
17052 |
|
|
/* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
|
17053 |
|
|
for setting PSR flag bits. They are obsolete in V6 and do not
|
17054 |
|
|
have Thumb equivalents. */
|
17055 |
|
|
tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
|
17056 |
|
|
tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
|
17057 |
|
|
CL("tstp", 110f000, 2, (RR, SH), cmp),
|
17058 |
|
|
tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
|
17059 |
|
|
tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
|
17060 |
|
|
CL("cmpp", 150f000, 2, (RR, SH), cmp),
|
17061 |
|
|
tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
|
17062 |
|
|
tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
|
17063 |
|
|
CL("cmnp", 170f000, 2, (RR, SH), cmp),
|
17064 |
|
|
|
17065 |
|
|
tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
|
17066 |
|
|
tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
|
17067 |
|
|
tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
|
17068 |
|
|
tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
|
17069 |
|
|
|
17070 |
|
|
tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
|
17071 |
|
|
tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
|
17072 |
|
|
tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
|
17073 |
|
|
OP_RRnpc),
|
17074 |
|
|
OP_ADDRGLDR),ldst, t_ldst),
|
17075 |
|
|
tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
|
17076 |
|
|
|
17077 |
|
|
tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
|
17078 |
|
|
tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
|
17079 |
|
|
tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
|
17080 |
|
|
tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
|
17081 |
|
|
tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
|
17082 |
|
|
tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
|
17083 |
|
|
|
17084 |
|
|
TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
|
17085 |
|
|
TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
|
17086 |
|
|
tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
|
17087 |
|
|
TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
|
17088 |
|
|
|
17089 |
|
|
/* Pseudo ops. */
|
17090 |
|
|
tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
|
17091 |
|
|
C3(adrl, 28f0000, 2, (RR, EXP), adrl),
|
17092 |
|
|
tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
|
17093 |
|
|
|
17094 |
|
|
/* Thumb-compatibility pseudo ops. */
|
17095 |
|
|
tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
|
17096 |
|
|
tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
|
17097 |
|
|
tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
|
17098 |
|
|
tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
|
17099 |
|
|
tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
|
17100 |
|
|
tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
|
17101 |
|
|
tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
|
17102 |
|
|
tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
|
17103 |
|
|
tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
|
17104 |
|
|
tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
|
17105 |
|
|
tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
|
17106 |
|
|
tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
|
17107 |
|
|
|
17108 |
|
|
/* These may simplify to neg. */
|
17109 |
|
|
TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
|
17110 |
|
|
TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
|
17111 |
|
|
|
17112 |
|
|
#undef THUMB_VARIANT
|
17113 |
|
|
#define THUMB_VARIANT & arm_ext_v6
|
17114 |
|
|
|
17115 |
|
|
TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
|
17116 |
|
|
|
17117 |
|
|
/* V1 instructions with no Thumb analogue prior to V6T2. */
|
17118 |
|
|
#undef THUMB_VARIANT
|
17119 |
|
|
#define THUMB_VARIANT & arm_ext_v6t2
|
17120 |
|
|
|
17121 |
|
|
TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
|
17122 |
|
|
TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
|
17123 |
|
|
CL("teqp", 130f000, 2, (RR, SH), cmp),
|
17124 |
|
|
|
17125 |
|
|
TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
|
17126 |
|
|
TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
|
17127 |
|
|
TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
|
17128 |
|
|
TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
|
17129 |
|
|
|
17130 |
|
|
TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
|
17131 |
|
|
TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
|
17132 |
|
|
|
17133 |
|
|
TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
|
17134 |
|
|
TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
|
17135 |
|
|
|
17136 |
|
|
/* V1 instructions with no Thumb analogue at all. */
|
17137 |
|
|
CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
|
17138 |
|
|
C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
|
17139 |
|
|
|
17140 |
|
|
C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
|
17141 |
|
|
C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
|
17142 |
|
|
C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
|
17143 |
|
|
C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
|
17144 |
|
|
C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
|
17145 |
|
|
C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
|
17146 |
|
|
C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
|
17147 |
|
|
C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
|
17148 |
|
|
|
17149 |
|
|
#undef ARM_VARIANT
|
17150 |
|
|
#define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
|
17151 |
|
|
#undef THUMB_VARIANT
|
17152 |
|
|
#define THUMB_VARIANT & arm_ext_v4t
|
17153 |
|
|
|
17154 |
|
|
tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
|
17155 |
|
|
tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
|
17156 |
|
|
|
17157 |
|
|
#undef THUMB_VARIANT
|
17158 |
|
|
#define THUMB_VARIANT & arm_ext_v6t2
|
17159 |
|
|
|
17160 |
|
|
TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
|
17161 |
|
|
C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
|
17162 |
|
|
|
17163 |
|
|
/* Generic coprocessor instructions. */
|
17164 |
|
|
TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
|
17165 |
|
|
TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
|
17166 |
|
|
TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
|
17167 |
|
|
TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
|
17168 |
|
|
TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
|
17169 |
|
|
TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
|
17170 |
|
|
TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
|
17171 |
|
|
|
17172 |
|
|
#undef ARM_VARIANT
|
17173 |
|
|
#define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
|
17174 |
|
|
|
17175 |
|
|
CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
|
17176 |
|
|
C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
|
17177 |
|
|
|
17178 |
|
|
#undef ARM_VARIANT
|
17179 |
|
|
#define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
|
17180 |
|
|
#undef THUMB_VARIANT
|
17181 |
|
|
#define THUMB_VARIANT & arm_ext_msr
|
17182 |
|
|
|
17183 |
|
|
TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
|
17184 |
|
|
TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
|
17185 |
|
|
|
17186 |
|
|
#undef ARM_VARIANT
|
17187 |
|
|
#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
|
17188 |
|
|
#undef THUMB_VARIANT
|
17189 |
|
|
#define THUMB_VARIANT & arm_ext_v6t2
|
17190 |
|
|
|
17191 |
|
|
TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
|
17192 |
|
|
CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
|
17193 |
|
|
TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
|
17194 |
|
|
CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
|
17195 |
|
|
TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
|
17196 |
|
|
CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
|
17197 |
|
|
TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
|
17198 |
|
|
CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
|
17199 |
|
|
|
17200 |
|
|
#undef ARM_VARIANT
|
17201 |
|
|
#define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
|
17202 |
|
|
#undef THUMB_VARIANT
|
17203 |
|
|
#define THUMB_VARIANT & arm_ext_v4t
|
17204 |
|
|
|
17205 |
|
|
tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
|
17206 |
|
|
tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
|
17207 |
|
|
tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
|
17208 |
|
|
tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
|
17209 |
|
|
tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
|
17210 |
|
|
tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
|
17211 |
|
|
|
17212 |
|
|
#undef ARM_VARIANT
|
17213 |
|
|
#define ARM_VARIANT & arm_ext_v4t_5
|
17214 |
|
|
|
17215 |
|
|
/* ARM Architecture 4T. */
|
17216 |
|
|
/* Note: bx (and blx) are required on V5, even if the processor does
|
17217 |
|
|
not support Thumb. */
|
17218 |
|
|
TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
|
17219 |
|
|
|
17220 |
|
|
#undef ARM_VARIANT
|
17221 |
|
|
#define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
|
17222 |
|
|
#undef THUMB_VARIANT
|
17223 |
|
|
#define THUMB_VARIANT & arm_ext_v5t
|
17224 |
|
|
|
17225 |
|
|
/* Note: blx has 2 variants; the .value coded here is for
|
17226 |
|
|
BLX(2). Only this variant has conditional execution. */
|
17227 |
|
|
TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
|
17228 |
|
|
TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
|
17229 |
|
|
|
17230 |
|
|
#undef THUMB_VARIANT
|
17231 |
|
|
#define THUMB_VARIANT & arm_ext_v6t2
|
17232 |
|
|
|
17233 |
|
|
TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
|
17234 |
|
|
TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
|
17235 |
|
|
TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
|
17236 |
|
|
TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
|
17237 |
|
|
TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
|
17238 |
|
|
TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
|
17239 |
|
|
TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
|
17240 |
|
|
TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
|
17241 |
|
|
|
17242 |
|
|
#undef ARM_VARIANT
|
17243 |
|
|
#define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
|
17244 |
|
|
#undef THUMB_VARIANT
|
17245 |
|
|
#define THUMB_VARIANT &arm_ext_v5exp
|
17246 |
|
|
|
17247 |
|
|
TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
|
17248 |
|
|
TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
|
17249 |
|
|
TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
|
17250 |
|
|
TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
|
17251 |
|
|
|
17252 |
|
|
TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
|
17253 |
|
|
TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
|
17254 |
|
|
|
17255 |
|
|
TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
|
17256 |
|
|
TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
|
17257 |
|
|
TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
|
17258 |
|
|
TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
|
17259 |
|
|
|
17260 |
|
|
TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
|
17261 |
|
|
TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
|
17262 |
|
|
TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
|
17263 |
|
|
TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
|
17264 |
|
|
|
17265 |
|
|
TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
|
17266 |
|
|
TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
|
17267 |
|
|
|
17268 |
|
|
TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
|
17269 |
|
|
TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
|
17270 |
|
|
TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
|
17271 |
|
|
TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
|
17272 |
|
|
|
17273 |
|
|
#undef ARM_VARIANT
|
17274 |
|
|
#define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
|
17275 |
|
|
#undef THUMB_VARIANT
|
17276 |
|
|
#define THUMB_VARIANT &arm_ext_v6t2
|
17277 |
|
|
|
17278 |
|
|
TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
|
17279 |
|
|
TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
|
17280 |
|
|
ldrd, t_ldstd),
|
17281 |
|
|
TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
|
17282 |
|
|
ADDRGLDRS), ldrd, t_ldstd),
|
17283 |
|
|
|
17284 |
|
|
TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
|
17285 |
|
|
TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
|
17286 |
|
|
|
17287 |
|
|
#undef ARM_VARIANT
|
17288 |
|
|
#define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
|
17289 |
|
|
|
17290 |
|
|
TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
|
17291 |
|
|
|
17292 |
|
|
#undef ARM_VARIANT
|
17293 |
|
|
#define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
|
17294 |
|
|
#undef THUMB_VARIANT
|
17295 |
|
|
#define THUMB_VARIANT & arm_ext_v6
|
17296 |
|
|
|
17297 |
|
|
TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
|
17298 |
|
|
TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
|
17299 |
|
|
tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
|
17300 |
|
|
tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
|
17301 |
|
|
tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
|
17302 |
|
|
tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
|
17303 |
|
|
tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
|
17304 |
|
|
tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
|
17305 |
|
|
tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
|
17306 |
|
|
TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
|
17307 |
|
|
|
17308 |
|
|
#undef THUMB_VARIANT
|
17309 |
|
|
#define THUMB_VARIANT & arm_ext_v6t2
|
17310 |
|
|
|
17311 |
|
|
TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
|
17312 |
|
|
TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
|
17313 |
|
|
strex, t_strex),
|
17314 |
|
|
TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
|
17315 |
|
|
TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
|
17316 |
|
|
|
17317 |
|
|
TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
|
17318 |
|
|
TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
|
17319 |
|
|
|
17320 |
|
|
/* ARM V6 not included in V7M. */
|
17321 |
|
|
#undef THUMB_VARIANT
|
17322 |
|
|
#define THUMB_VARIANT & arm_ext_v6_notm
|
17323 |
|
|
TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
|
17324 |
|
|
UF(rfeib, 9900a00, 1, (RRw), rfe),
|
17325 |
|
|
UF(rfeda, 8100a00, 1, (RRw), rfe),
|
17326 |
|
|
TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
|
17327 |
|
|
TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
|
17328 |
|
|
UF(rfefa, 9900a00, 1, (RRw), rfe),
|
17329 |
|
|
UF(rfeea, 8100a00, 1, (RRw), rfe),
|
17330 |
|
|
TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe),
|
17331 |
|
|
TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
|
17332 |
|
|
UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
|
17333 |
|
|
UF(srsda, 8400500, 2, (oRRw, I31w), srs),
|
17334 |
|
|
TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
|
17335 |
|
|
|
17336 |
|
|
/* ARM V6 not included in V7M (eg. integer SIMD). */
|
17337 |
|
|
#undef THUMB_VARIANT
|
17338 |
|
|
#define THUMB_VARIANT & arm_ext_v6_dsp
|
17339 |
|
|
TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
|
17340 |
|
|
TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
|
17341 |
|
|
TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
|
17342 |
|
|
TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17343 |
|
|
TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17344 |
|
|
TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17345 |
|
|
/* Old name for QASX. */
|
17346 |
|
|
TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17347 |
|
|
TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17348 |
|
|
/* Old name for QSAX. */
|
17349 |
|
|
TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17350 |
|
|
TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17351 |
|
|
TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17352 |
|
|
TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17353 |
|
|
TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17354 |
|
|
TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17355 |
|
|
/* Old name for SASX. */
|
17356 |
|
|
TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17357 |
|
|
TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17358 |
|
|
TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17359 |
|
|
TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17360 |
|
|
/* Old name for SHASX. */
|
17361 |
|
|
TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17362 |
|
|
TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17363 |
|
|
/* Old name for SHSAX. */
|
17364 |
|
|
TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17365 |
|
|
TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17366 |
|
|
TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17367 |
|
|
TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17368 |
|
|
/* Old name for SSAX. */
|
17369 |
|
|
TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17370 |
|
|
TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17371 |
|
|
TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17372 |
|
|
TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17373 |
|
|
TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17374 |
|
|
TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17375 |
|
|
/* Old name for UASX. */
|
17376 |
|
|
TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17377 |
|
|
TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17378 |
|
|
TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17379 |
|
|
TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17380 |
|
|
/* Old name for UHASX. */
|
17381 |
|
|
TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17382 |
|
|
TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17383 |
|
|
/* Old name for UHSAX. */
|
17384 |
|
|
TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17385 |
|
|
TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17386 |
|
|
TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17387 |
|
|
TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17388 |
|
|
TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17389 |
|
|
TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17390 |
|
|
/* Old name for UQASX. */
|
17391 |
|
|
TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17392 |
|
|
TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17393 |
|
|
/* Old name for UQSAX. */
|
17394 |
|
|
TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17395 |
|
|
TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17396 |
|
|
TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17397 |
|
|
TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17398 |
|
|
TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17399 |
|
|
/* Old name for USAX. */
|
17400 |
|
|
TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17401 |
|
|
TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17402 |
|
|
TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
|
17403 |
|
|
TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
|
17404 |
|
|
TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
|
17405 |
|
|
TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
|
17406 |
|
|
TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
|
17407 |
|
|
TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
|
17408 |
|
|
TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
|
17409 |
|
|
TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
|
17410 |
|
|
TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
|
17411 |
|
|
TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
|
17412 |
|
|
TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
|
17413 |
|
|
TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
|
17414 |
|
|
TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
|
17415 |
|
|
TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
|
17416 |
|
|
TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
|
17417 |
|
|
TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
|
17418 |
|
|
TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
|
17419 |
|
|
TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
|
17420 |
|
|
TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
|
17421 |
|
|
TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
|
17422 |
|
|
TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
|
17423 |
|
|
TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
|
17424 |
|
|
TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
|
17425 |
|
|
TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
|
17426 |
|
|
TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
|
17427 |
|
|
TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
|
17428 |
|
|
TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
|
17429 |
|
|
TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
|
17430 |
|
|
TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
|
17431 |
|
|
TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
|
17432 |
|
|
TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
|
17433 |
|
|
TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
|
17434 |
|
|
|
17435 |
|
|
#undef ARM_VARIANT
|
17436 |
|
|
#define ARM_VARIANT & arm_ext_v6k
|
17437 |
|
|
#undef THUMB_VARIANT
|
17438 |
|
|
#define THUMB_VARIANT & arm_ext_v6k
|
17439 |
|
|
|
17440 |
|
|
tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
|
17441 |
|
|
tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
|
17442 |
|
|
tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
|
17443 |
|
|
tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
|
17444 |
|
|
|
17445 |
|
|
#undef THUMB_VARIANT
|
17446 |
|
|
#define THUMB_VARIANT & arm_ext_v6_notm
|
17447 |
|
|
TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
|
17448 |
|
|
ldrexd, t_ldrexd),
|
17449 |
|
|
TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
|
17450 |
|
|
RRnpcb), strexd, t_strexd),
|
17451 |
|
|
|
17452 |
|
|
#undef THUMB_VARIANT
|
17453 |
|
|
#define THUMB_VARIANT & arm_ext_v6t2
|
17454 |
|
|
TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
|
17455 |
|
|
rd_rn, rd_rn),
|
17456 |
|
|
TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
|
17457 |
|
|
rd_rn, rd_rn),
|
17458 |
|
|
TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
|
17459 |
|
|
strex, rm_rd_rn),
|
17460 |
|
|
TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
|
17461 |
|
|
strex, rm_rd_rn),
|
17462 |
|
|
TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
|
17463 |
|
|
|
17464 |
|
|
#undef ARM_VARIANT
|
17465 |
|
|
#define ARM_VARIANT & arm_ext_sec
|
17466 |
|
|
#undef THUMB_VARIANT
|
17467 |
|
|
#define THUMB_VARIANT & arm_ext_sec
|
17468 |
|
|
|
17469 |
|
|
TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
|
17470 |
|
|
|
17471 |
|
|
#undef ARM_VARIANT
|
17472 |
|
|
#define ARM_VARIANT & arm_ext_virt
|
17473 |
|
|
#undef THUMB_VARIANT
|
17474 |
|
|
#define THUMB_VARIANT & arm_ext_virt
|
17475 |
|
|
|
17476 |
|
|
TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
|
17477 |
|
|
TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
|
17478 |
|
|
|
17479 |
|
|
#undef ARM_VARIANT
|
17480 |
|
|
#define ARM_VARIANT & arm_ext_v6t2
|
17481 |
|
|
#undef THUMB_VARIANT
|
17482 |
|
|
#define THUMB_VARIANT & arm_ext_v6t2
|
17483 |
|
|
|
17484 |
|
|
TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
|
17485 |
|
|
TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
|
17486 |
|
|
TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
|
17487 |
|
|
TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
|
17488 |
|
|
|
17489 |
|
|
TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
|
17490 |
|
|
TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
|
17491 |
|
|
TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
|
17492 |
|
|
TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
|
17493 |
|
|
|
17494 |
|
|
TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
|
17495 |
|
|
TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
|
17496 |
|
|
TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
|
17497 |
|
|
TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
|
17498 |
|
|
|
17499 |
|
|
/* Thumb-only instructions. */
|
17500 |
|
|
#undef ARM_VARIANT
|
17501 |
|
|
#define ARM_VARIANT NULL
|
17502 |
|
|
TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
|
17503 |
|
|
TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
|
17504 |
|
|
|
17505 |
|
|
/* ARM does not really have an IT instruction, so always allow it.
|
17506 |
|
|
The opcode is copied from Thumb in order to allow warnings in
|
17507 |
|
|
-mimplicit-it=[never | arm] modes. */
|
17508 |
|
|
#undef ARM_VARIANT
|
17509 |
|
|
#define ARM_VARIANT & arm_ext_v1
|
17510 |
|
|
|
17511 |
|
|
TUE("it", bf08, bf08, 1, (COND), it, t_it),
|
17512 |
|
|
TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
|
17513 |
|
|
TUE("ite", bf04, bf04, 1, (COND), it, t_it),
|
17514 |
|
|
TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
|
17515 |
|
|
TUE("itet", bf06, bf06, 1, (COND), it, t_it),
|
17516 |
|
|
TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
|
17517 |
|
|
TUE("itee", bf02, bf02, 1, (COND), it, t_it),
|
17518 |
|
|
TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
|
17519 |
|
|
TUE("itett", bf07, bf07, 1, (COND), it, t_it),
|
17520 |
|
|
TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
|
17521 |
|
|
TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
|
17522 |
|
|
TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
|
17523 |
|
|
TUE("itete", bf05, bf05, 1, (COND), it, t_it),
|
17524 |
|
|
TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
|
17525 |
|
|
TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
|
17526 |
|
|
/* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
|
17527 |
|
|
TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
|
17528 |
|
|
TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
|
17529 |
|
|
|
17530 |
|
|
/* Thumb2 only instructions. */
|
17531 |
|
|
#undef ARM_VARIANT
|
17532 |
|
|
#define ARM_VARIANT NULL
|
17533 |
|
|
|
17534 |
|
|
TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
|
17535 |
|
|
TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
|
17536 |
|
|
TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
|
17537 |
|
|
TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
|
17538 |
|
|
TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
|
17539 |
|
|
TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
|
17540 |
|
|
|
17541 |
|
|
/* Hardware division instructions. */
|
17542 |
|
|
#undef ARM_VARIANT
|
17543 |
|
|
#define ARM_VARIANT & arm_ext_adiv
|
17544 |
|
|
#undef THUMB_VARIANT
|
17545 |
|
|
#define THUMB_VARIANT & arm_ext_div
|
17546 |
|
|
|
17547 |
|
|
TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
|
17548 |
|
|
TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
|
17549 |
|
|
|
17550 |
|
|
/* ARM V6M/V7 instructions. */
|
17551 |
|
|
#undef ARM_VARIANT
|
17552 |
|
|
#define ARM_VARIANT & arm_ext_barrier
|
17553 |
|
|
#undef THUMB_VARIANT
|
17554 |
|
|
#define THUMB_VARIANT & arm_ext_barrier
|
17555 |
|
|
|
17556 |
|
|
TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
|
17557 |
|
|
TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
|
17558 |
|
|
TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
|
17559 |
|
|
|
17560 |
|
|
/* ARM V7 instructions. */
|
17561 |
|
|
#undef ARM_VARIANT
|
17562 |
|
|
#define ARM_VARIANT & arm_ext_v7
|
17563 |
|
|
#undef THUMB_VARIANT
|
17564 |
|
|
#define THUMB_VARIANT & arm_ext_v7
|
17565 |
|
|
|
17566 |
|
|
TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
|
17567 |
|
|
TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
|
17568 |
|
|
|
17569 |
|
|
#undef ARM_VARIANT
|
17570 |
|
|
#define ARM_VARIANT & arm_ext_mp
|
17571 |
|
|
#undef THUMB_VARIANT
|
17572 |
|
|
#define THUMB_VARIANT & arm_ext_mp
|
17573 |
|
|
|
17574 |
|
|
TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
|
17575 |
|
|
|
17576 |
|
|
#undef ARM_VARIANT
|
17577 |
|
|
#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
|
17578 |
|
|
|
17579 |
|
|
cCE("wfs", e200110, 1, (RR), rd),
|
17580 |
|
|
cCE("rfs", e300110, 1, (RR), rd),
|
17581 |
|
|
cCE("wfc", e400110, 1, (RR), rd),
|
17582 |
|
|
cCE("rfc", e500110, 1, (RR), rd),
|
17583 |
|
|
|
17584 |
|
|
cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
|
17585 |
|
|
cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
|
17586 |
|
|
cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
|
17587 |
|
|
cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
|
17588 |
|
|
|
17589 |
|
|
cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
|
17590 |
|
|
cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
|
17591 |
|
|
cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
|
17592 |
|
|
cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
|
17593 |
|
|
|
17594 |
|
|
cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
|
17595 |
|
|
cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
|
17596 |
|
|
cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
|
17597 |
|
|
cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
|
17598 |
|
|
cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
|
17599 |
|
|
cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
|
17600 |
|
|
cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
|
17601 |
|
|
cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
|
17602 |
|
|
cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
|
17603 |
|
|
cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
|
17604 |
|
|
cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
|
17605 |
|
|
cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
|
17606 |
|
|
|
17607 |
|
|
cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
|
17608 |
|
|
cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
|
17609 |
|
|
cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
|
17610 |
|
|
cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
|
17611 |
|
|
cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
|
17612 |
|
|
cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
|
17613 |
|
|
cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
|
17614 |
|
|
cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
|
17615 |
|
|
cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
|
17616 |
|
|
cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
|
17617 |
|
|
cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
|
17618 |
|
|
cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
|
17619 |
|
|
|
17620 |
|
|
cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
|
17621 |
|
|
cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
|
17622 |
|
|
cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
|
17623 |
|
|
cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
|
17624 |
|
|
cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
|
17625 |
|
|
cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
|
17626 |
|
|
cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
|
17627 |
|
|
cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
|
17628 |
|
|
cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
|
17629 |
|
|
cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
|
17630 |
|
|
cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
|
17631 |
|
|
cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
|
17632 |
|
|
|
17633 |
|
|
cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
|
17634 |
|
|
cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
|
17635 |
|
|
cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
|
17636 |
|
|
cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
|
17637 |
|
|
cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
|
17638 |
|
|
cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
|
17639 |
|
|
cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
|
17640 |
|
|
cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
|
17641 |
|
|
cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
|
17642 |
|
|
cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
|
17643 |
|
|
cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
|
17644 |
|
|
cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
|
17645 |
|
|
|
17646 |
|
|
cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
|
17647 |
|
|
cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
|
17648 |
|
|
cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
|
17649 |
|
|
cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
|
17650 |
|
|
cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
|
17651 |
|
|
cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
|
17652 |
|
|
cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
|
17653 |
|
|
cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
|
17654 |
|
|
cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
|
17655 |
|
|
cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
|
17656 |
|
|
cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
|
17657 |
|
|
cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
|
17658 |
|
|
|
17659 |
|
|
cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
|
17660 |
|
|
cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
|
17661 |
|
|
cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
|
17662 |
|
|
cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
|
17663 |
|
|
cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
|
17664 |
|
|
cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
|
17665 |
|
|
cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
|
17666 |
|
|
cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
|
17667 |
|
|
cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
|
17668 |
|
|
cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
|
17669 |
|
|
cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
|
17670 |
|
|
cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
|
17671 |
|
|
|
17672 |
|
|
cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
|
17673 |
|
|
cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
|
17674 |
|
|
cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
|
17675 |
|
|
cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
|
17676 |
|
|
cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
|
17677 |
|
|
cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
|
17678 |
|
|
cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
|
17679 |
|
|
cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
|
17680 |
|
|
cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
|
17681 |
|
|
cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
|
17682 |
|
|
cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
|
17683 |
|
|
cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
|
17684 |
|
|
|
17685 |
|
|
cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
|
17686 |
|
|
cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
|
17687 |
|
|
cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
|
17688 |
|
|
cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
|
17689 |
|
|
cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
|
17690 |
|
|
cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
|
17691 |
|
|
cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
|
17692 |
|
|
cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
|
17693 |
|
|
cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
|
17694 |
|
|
cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
|
17695 |
|
|
cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
|
17696 |
|
|
cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
|
17697 |
|
|
|
17698 |
|
|
cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
|
17699 |
|
|
cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
|
17700 |
|
|
cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
|
17701 |
|
|
cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
|
17702 |
|
|
cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
|
17703 |
|
|
cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
|
17704 |
|
|
cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
|
17705 |
|
|
cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
|
17706 |
|
|
cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
|
17707 |
|
|
cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
|
17708 |
|
|
cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
|
17709 |
|
|
cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
|
17710 |
|
|
|
17711 |
|
|
cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
|
17712 |
|
|
cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
|
17713 |
|
|
cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
|
17714 |
|
|
cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
|
17715 |
|
|
cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
|
17716 |
|
|
cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
|
17717 |
|
|
cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
|
17718 |
|
|
cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
|
17719 |
|
|
cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
|
17720 |
|
|
cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
|
17721 |
|
|
cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
|
17722 |
|
|
cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
|
17723 |
|
|
|
17724 |
|
|
cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
|
17725 |
|
|
cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
|
17726 |
|
|
cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
|
17727 |
|
|
cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
|
17728 |
|
|
cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
|
17729 |
|
|
cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
|
17730 |
|
|
cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
|
17731 |
|
|
cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
|
17732 |
|
|
cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
|
17733 |
|
|
cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
|
17734 |
|
|
cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
|
17735 |
|
|
cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
|
17736 |
|
|
|
17737 |
|
|
cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
|
17738 |
|
|
cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
|
17739 |
|
|
cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
|
17740 |
|
|
cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
|
17741 |
|
|
cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
|
17742 |
|
|
cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
|
17743 |
|
|
cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
|
17744 |
|
|
cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
|
17745 |
|
|
cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
|
17746 |
|
|
cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
|
17747 |
|
|
cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
|
17748 |
|
|
cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
|
17749 |
|
|
|
17750 |
|
|
cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
|
17751 |
|
|
cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
|
17752 |
|
|
cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
|
17753 |
|
|
cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
|
17754 |
|
|
cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
|
17755 |
|
|
cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
|
17756 |
|
|
cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
|
17757 |
|
|
cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
|
17758 |
|
|
cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
|
17759 |
|
|
cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
|
17760 |
|
|
cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
|
17761 |
|
|
cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
|
17762 |
|
|
|
17763 |
|
|
cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
|
17764 |
|
|
cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
|
17765 |
|
|
cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
|
17766 |
|
|
cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
|
17767 |
|
|
cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
|
17768 |
|
|
cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
|
17769 |
|
|
cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
|
17770 |
|
|
cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
|
17771 |
|
|
cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
|
17772 |
|
|
cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
|
17773 |
|
|
cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
|
17774 |
|
|
cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
|
17775 |
|
|
|
17776 |
|
|
cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
|
17777 |
|
|
cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
|
17778 |
|
|
cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
|
17779 |
|
|
cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
|
17780 |
|
|
cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
|
17781 |
|
|
cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
|
17782 |
|
|
cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
|
17783 |
|
|
cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
|
17784 |
|
|
cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
|
17785 |
|
|
cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
|
17786 |
|
|
cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
|
17787 |
|
|
cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
|
17788 |
|
|
|
17789 |
|
|
cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
|
17790 |
|
|
cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
|
17791 |
|
|
cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
|
17792 |
|
|
cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
|
17793 |
|
|
cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
|
17794 |
|
|
cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
|
17795 |
|
|
cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
|
17796 |
|
|
cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
|
17797 |
|
|
cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
|
17798 |
|
|
cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
|
17799 |
|
|
cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
|
17800 |
|
|
cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
|
17801 |
|
|
|
17802 |
|
|
cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17803 |
|
|
cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17804 |
|
|
cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17805 |
|
|
cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17806 |
|
|
cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17807 |
|
|
cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17808 |
|
|
cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17809 |
|
|
cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17810 |
|
|
cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17811 |
|
|
cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17812 |
|
|
cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17813 |
|
|
cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17814 |
|
|
|
17815 |
|
|
cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17816 |
|
|
cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17817 |
|
|
cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17818 |
|
|
cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17819 |
|
|
cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17820 |
|
|
cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17821 |
|
|
cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17822 |
|
|
cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17823 |
|
|
cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17824 |
|
|
cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17825 |
|
|
cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17826 |
|
|
cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17827 |
|
|
|
17828 |
|
|
cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17829 |
|
|
cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17830 |
|
|
cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17831 |
|
|
cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17832 |
|
|
cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17833 |
|
|
cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17834 |
|
|
cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17835 |
|
|
cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17836 |
|
|
cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17837 |
|
|
cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17838 |
|
|
cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17839 |
|
|
cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17840 |
|
|
|
17841 |
|
|
cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17842 |
|
|
cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17843 |
|
|
cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17844 |
|
|
cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17845 |
|
|
cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17846 |
|
|
cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17847 |
|
|
cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17848 |
|
|
cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17849 |
|
|
cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17850 |
|
|
cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17851 |
|
|
cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17852 |
|
|
cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17853 |
|
|
|
17854 |
|
|
cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17855 |
|
|
cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17856 |
|
|
cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17857 |
|
|
cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17858 |
|
|
cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17859 |
|
|
cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17860 |
|
|
cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17861 |
|
|
cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17862 |
|
|
cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17863 |
|
|
cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17864 |
|
|
cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17865 |
|
|
cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17866 |
|
|
|
17867 |
|
|
cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17868 |
|
|
cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17869 |
|
|
cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17870 |
|
|
cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17871 |
|
|
cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17872 |
|
|
cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17873 |
|
|
cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17874 |
|
|
cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17875 |
|
|
cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17876 |
|
|
cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17877 |
|
|
cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17878 |
|
|
cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17879 |
|
|
|
17880 |
|
|
cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17881 |
|
|
cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17882 |
|
|
cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17883 |
|
|
cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17884 |
|
|
cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17885 |
|
|
cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17886 |
|
|
cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17887 |
|
|
cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17888 |
|
|
cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17889 |
|
|
cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17890 |
|
|
cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17891 |
|
|
cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17892 |
|
|
|
17893 |
|
|
cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17894 |
|
|
cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17895 |
|
|
cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17896 |
|
|
cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17897 |
|
|
cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17898 |
|
|
cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17899 |
|
|
cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17900 |
|
|
cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17901 |
|
|
cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17902 |
|
|
cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17903 |
|
|
cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17904 |
|
|
cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17905 |
|
|
|
17906 |
|
|
cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17907 |
|
|
cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17908 |
|
|
cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17909 |
|
|
cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17910 |
|
|
cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17911 |
|
|
cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17912 |
|
|
cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17913 |
|
|
cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17914 |
|
|
cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17915 |
|
|
cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17916 |
|
|
cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17917 |
|
|
cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17918 |
|
|
|
17919 |
|
|
cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17920 |
|
|
cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17921 |
|
|
cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17922 |
|
|
cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17923 |
|
|
cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17924 |
|
|
cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17925 |
|
|
cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17926 |
|
|
cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17927 |
|
|
cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17928 |
|
|
cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17929 |
|
|
cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17930 |
|
|
cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17931 |
|
|
|
17932 |
|
|
cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17933 |
|
|
cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17934 |
|
|
cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17935 |
|
|
cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17936 |
|
|
cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17937 |
|
|
cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17938 |
|
|
cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17939 |
|
|
cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17940 |
|
|
cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17941 |
|
|
cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17942 |
|
|
cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17943 |
|
|
cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17944 |
|
|
|
17945 |
|
|
cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17946 |
|
|
cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17947 |
|
|
cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17948 |
|
|
cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17949 |
|
|
cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17950 |
|
|
cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17951 |
|
|
cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17952 |
|
|
cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17953 |
|
|
cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17954 |
|
|
cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17955 |
|
|
cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17956 |
|
|
cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17957 |
|
|
|
17958 |
|
|
cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17959 |
|
|
cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17960 |
|
|
cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17961 |
|
|
cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17962 |
|
|
cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17963 |
|
|
cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17964 |
|
|
cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17965 |
|
|
cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17966 |
|
|
cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17967 |
|
|
cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17968 |
|
|
cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17969 |
|
|
cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
|
17970 |
|
|
|
17971 |
|
|
cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
|
17972 |
|
|
C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
|
17973 |
|
|
cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
|
17974 |
|
|
C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
|
17975 |
|
|
|
17976 |
|
|
cCL("flts", e000110, 2, (RF, RR), rn_rd),
|
17977 |
|
|
cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
|
17978 |
|
|
cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
|
17979 |
|
|
cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
|
17980 |
|
|
cCL("fltd", e000190, 2, (RF, RR), rn_rd),
|
17981 |
|
|
cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
|
17982 |
|
|
cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
|
17983 |
|
|
cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
|
17984 |
|
|
cCL("flte", e080110, 2, (RF, RR), rn_rd),
|
17985 |
|
|
cCL("fltep", e080130, 2, (RF, RR), rn_rd),
|
17986 |
|
|
cCL("fltem", e080150, 2, (RF, RR), rn_rd),
|
17987 |
|
|
cCL("fltez", e080170, 2, (RF, RR), rn_rd),
|
17988 |
|
|
|
17989 |
|
|
/* The implementation of the FIX instruction is broken on some
|
17990 |
|
|
assemblers, in that it accepts a precision specifier as well as a
|
17991 |
|
|
rounding specifier, despite the fact that this is meaningless.
|
17992 |
|
|
To be more compatible, we accept it as well, though of course it
|
17993 |
|
|
does not set any bits. */
|
17994 |
|
|
cCE("fix", e100110, 2, (RR, RF), rd_rm),
|
17995 |
|
|
cCL("fixp", e100130, 2, (RR, RF), rd_rm),
|
17996 |
|
|
cCL("fixm", e100150, 2, (RR, RF), rd_rm),
|
17997 |
|
|
cCL("fixz", e100170, 2, (RR, RF), rd_rm),
|
17998 |
|
|
cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
|
17999 |
|
|
cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
|
18000 |
|
|
cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
|
18001 |
|
|
cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
|
18002 |
|
|
cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
|
18003 |
|
|
cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
|
18004 |
|
|
cCL("fixep", e100130, 2, (RR, RF), rd_rm),
|
18005 |
|
|
cCL("fixem", e100150, 2, (RR, RF), rd_rm),
|
18006 |
|
|
cCL("fixez", e100170, 2, (RR, RF), rd_rm),
|
18007 |
|
|
|
18008 |
|
|
/* Instructions that were new with the real FPA, call them V2. */
|
18009 |
|
|
#undef ARM_VARIANT
|
18010 |
|
|
#define ARM_VARIANT & fpu_fpa_ext_v2
|
18011 |
|
|
|
18012 |
|
|
cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
|
18013 |
|
|
cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
|
18014 |
|
|
cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
|
18015 |
|
|
cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
|
18016 |
|
|
cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
|
18017 |
|
|
cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
|
18018 |
|
|
|
18019 |
|
|
#undef ARM_VARIANT
|
18020 |
|
|
#define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
|
18021 |
|
|
|
18022 |
|
|
/* Moves and type conversions. */
|
18023 |
|
|
cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
|
18024 |
|
|
cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
|
18025 |
|
|
cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
|
18026 |
|
|
cCE("fmstat", ef1fa10, 0, (), noargs),
|
18027 |
|
|
cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs),
|
18028 |
|
|
cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr),
|
18029 |
|
|
cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
|
18030 |
|
|
cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
|
18031 |
|
|
cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
|
18032 |
|
|
cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
|
18033 |
|
|
cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
|
18034 |
|
|
cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
|
18035 |
|
|
cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
|
18036 |
|
|
cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
|
18037 |
|
|
|
18038 |
|
|
/* Memory operations. */
|
18039 |
|
|
cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
|
18040 |
|
|
cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
|
18041 |
|
|
cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
|
18042 |
|
|
cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
|
18043 |
|
|
cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
|
18044 |
|
|
cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
|
18045 |
|
|
cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
|
18046 |
|
|
cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
|
18047 |
|
|
cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
|
18048 |
|
|
cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
|
18049 |
|
|
cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
|
18050 |
|
|
cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
|
18051 |
|
|
cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
|
18052 |
|
|
cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
|
18053 |
|
|
cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
|
18054 |
|
|
cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
|
18055 |
|
|
cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
|
18056 |
|
|
cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
|
18057 |
|
|
|
18058 |
|
|
/* Monadic operations. */
|
18059 |
|
|
cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
|
18060 |
|
|
cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
|
18061 |
|
|
cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
|
18062 |
|
|
|
18063 |
|
|
/* Dyadic operations. */
|
18064 |
|
|
cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
|
18065 |
|
|
cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
|
18066 |
|
|
cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
|
18067 |
|
|
cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
|
18068 |
|
|
cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
|
18069 |
|
|
cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
|
18070 |
|
|
cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
|
18071 |
|
|
cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
|
18072 |
|
|
cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
|
18073 |
|
|
|
18074 |
|
|
/* Comparisons. */
|
18075 |
|
|
cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
|
18076 |
|
|
cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
|
18077 |
|
|
cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
|
18078 |
|
|
cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
|
18079 |
|
|
|
18080 |
|
|
/* Double precision load/store are still present on single precision
|
18081 |
|
|
implementations. */
|
18082 |
|
|
cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
|
18083 |
|
|
cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
|
18084 |
|
|
cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
|
18085 |
|
|
cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
|
18086 |
|
|
cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
|
18087 |
|
|
cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
|
18088 |
|
|
cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
|
18089 |
|
|
cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
|
18090 |
|
|
cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
|
18091 |
|
|
cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
|
18092 |
|
|
|
18093 |
|
|
#undef ARM_VARIANT
|
18094 |
|
|
#define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
|
18095 |
|
|
|
18096 |
|
|
/* Moves and type conversions. */
|
18097 |
|
|
cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
|
18098 |
|
|
cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
|
18099 |
|
|
cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
|
18100 |
|
|
cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
|
18101 |
|
|
cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
|
18102 |
|
|
cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
|
18103 |
|
|
cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
|
18104 |
|
|
cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
|
18105 |
|
|
cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
|
18106 |
|
|
cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
|
18107 |
|
|
cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
|
18108 |
|
|
cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
|
18109 |
|
|
cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
|
18110 |
|
|
|
18111 |
|
|
/* Monadic operations. */
|
18112 |
|
|
cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
|
18113 |
|
|
cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
|
18114 |
|
|
cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
|
18115 |
|
|
|
18116 |
|
|
/* Dyadic operations. */
|
18117 |
|
|
cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
|
18118 |
|
|
cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
|
18119 |
|
|
cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
|
18120 |
|
|
cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
|
18121 |
|
|
cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
|
18122 |
|
|
cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
|
18123 |
|
|
cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
|
18124 |
|
|
cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
|
18125 |
|
|
cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
|
18126 |
|
|
|
18127 |
|
|
/* Comparisons. */
|
18128 |
|
|
cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
|
18129 |
|
|
cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
|
18130 |
|
|
cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
|
18131 |
|
|
cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
|
18132 |
|
|
|
18133 |
|
|
#undef ARM_VARIANT
|
18134 |
|
|
#define ARM_VARIANT & fpu_vfp_ext_v2
|
18135 |
|
|
|
18136 |
|
|
cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
|
18137 |
|
|
cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
|
18138 |
|
|
cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
|
18139 |
|
|
cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
|
18140 |
|
|
|
18141 |
|
|
/* Instructions which may belong to either the Neon or VFP instruction sets.
|
18142 |
|
|
Individual encoder functions perform additional architecture checks. */
|
18143 |
|
|
#undef ARM_VARIANT
|
18144 |
|
|
#define ARM_VARIANT & fpu_vfp_ext_v1xd
|
18145 |
|
|
#undef THUMB_VARIANT
|
18146 |
|
|
#define THUMB_VARIANT & fpu_vfp_ext_v1xd
|
18147 |
|
|
|
18148 |
|
|
/* These mnemonics are unique to VFP. */
|
18149 |
|
|
NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
|
18150 |
|
|
NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
|
18151 |
|
|
nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
|
18152 |
|
|
nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
|
18153 |
|
|
nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
|
18154 |
|
|
nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
|
18155 |
|
|
nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
|
18156 |
|
|
NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
|
18157 |
|
|
NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
|
18158 |
|
|
NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
|
18159 |
|
|
|
18160 |
|
|
/* Mnemonics shared by Neon and VFP. */
|
18161 |
|
|
nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
|
18162 |
|
|
nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
|
18163 |
|
|
nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
|
18164 |
|
|
|
18165 |
|
|
nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
|
18166 |
|
|
nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
|
18167 |
|
|
|
18168 |
|
|
NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
|
18169 |
|
|
NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
|
18170 |
|
|
|
18171 |
|
|
NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
|
18172 |
|
|
NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
|
18173 |
|
|
NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
|
18174 |
|
|
NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
|
18175 |
|
|
NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
|
18176 |
|
|
NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
|
18177 |
|
|
NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
|
18178 |
|
|
NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
|
18179 |
|
|
|
18180 |
|
|
nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt),
|
18181 |
|
|
nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
|
18182 |
|
|
nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
|
18183 |
|
|
nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
|
18184 |
|
|
|
18185 |
|
|
|
18186 |
|
|
/* NOTE: All VMOV encoding is special-cased! */
|
18187 |
|
|
NCE(vmov, 0, 1, (VMOV), neon_mov),
|
18188 |
|
|
NCE(vmovq, 0, 1, (VMOV), neon_mov),
|
18189 |
|
|
|
18190 |
|
|
#undef THUMB_VARIANT
|
18191 |
|
|
#define THUMB_VARIANT & fpu_neon_ext_v1
|
18192 |
|
|
#undef ARM_VARIANT
|
18193 |
|
|
#define ARM_VARIANT & fpu_neon_ext_v1
|
18194 |
|
|
|
18195 |
|
|
/* Data processing with three registers of the same length. */
|
18196 |
|
|
/* integer ops, valid types S8 S16 S32 U8 U16 U32. */
|
18197 |
|
|
NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
|
18198 |
|
|
NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
|
18199 |
|
|
NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
|
18200 |
|
|
NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
|
18201 |
|
|
NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
|
18202 |
|
|
NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
|
18203 |
|
|
NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
|
18204 |
|
|
NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
|
18205 |
|
|
/* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
|
18206 |
|
|
NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
|
18207 |
|
|
NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
|
18208 |
|
|
NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
|
18209 |
|
|
NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
|
18210 |
|
|
NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
|
18211 |
|
|
NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
|
18212 |
|
|
NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
|
18213 |
|
|
NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
|
18214 |
|
|
/* If not immediate, fall back to neon_dyadic_i64_su.
|
18215 |
|
|
shl_imm should accept I8 I16 I32 I64,
|
18216 |
|
|
qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
|
18217 |
|
|
nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
|
18218 |
|
|
nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
|
18219 |
|
|
nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
|
18220 |
|
|
nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
|
18221 |
|
|
/* Logic ops, types optional & ignored. */
|
18222 |
|
|
nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
|
18223 |
|
|
nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
|
18224 |
|
|
nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
|
18225 |
|
|
nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
|
18226 |
|
|
nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
|
18227 |
|
|
nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
|
18228 |
|
|
nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
|
18229 |
|
|
nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
|
18230 |
|
|
nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
|
18231 |
|
|
nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
|
18232 |
|
|
/* Bitfield ops, untyped. */
|
18233 |
|
|
NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
|
18234 |
|
|
NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
|
18235 |
|
|
NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
|
18236 |
|
|
NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
|
18237 |
|
|
NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
|
18238 |
|
|
NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
|
18239 |
|
|
/* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
|
18240 |
|
|
nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
|
18241 |
|
|
nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
|
18242 |
|
|
nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
|
18243 |
|
|
nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
|
18244 |
|
|
nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
|
18245 |
|
|
nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
|
18246 |
|
|
/* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
|
18247 |
|
|
back to neon_dyadic_if_su. */
|
18248 |
|
|
nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
|
18249 |
|
|
nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
|
18250 |
|
|
nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
|
18251 |
|
|
nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
|
18252 |
|
|
nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
|
18253 |
|
|
nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
|
18254 |
|
|
nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
|
18255 |
|
|
nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
|
18256 |
|
|
/* Comparison. Type I8 I16 I32 F32. */
|
18257 |
|
|
nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
|
18258 |
|
|
nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
|
18259 |
|
|
/* As above, D registers only. */
|
18260 |
|
|
nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
|
18261 |
|
|
nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
|
18262 |
|
|
/* Int and float variants, signedness unimportant. */
|
18263 |
|
|
nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
|
18264 |
|
|
nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
|
18265 |
|
|
nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
|
18266 |
|
|
/* Add/sub take types I8 I16 I32 I64 F32. */
|
18267 |
|
|
nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
|
18268 |
|
|
nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
|
18269 |
|
|
/* vtst takes sizes 8, 16, 32. */
|
18270 |
|
|
NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
|
18271 |
|
|
NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
|
18272 |
|
|
/* VMUL takes I8 I16 I32 F32 P8. */
|
18273 |
|
|
nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
|
18274 |
|
|
/* VQD{R}MULH takes S16 S32. */
|
18275 |
|
|
nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
|
18276 |
|
|
nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
|
18277 |
|
|
nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
|
18278 |
|
|
nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
|
18279 |
|
|
NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
|
18280 |
|
|
NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
|
18281 |
|
|
NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
|
18282 |
|
|
NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
|
18283 |
|
|
NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
|
18284 |
|
|
NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
|
18285 |
|
|
NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
|
18286 |
|
|
NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
|
18287 |
|
|
NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
|
18288 |
|
|
NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
|
18289 |
|
|
NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
|
18290 |
|
|
NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
|
18291 |
|
|
|
18292 |
|
|
/* Two address, int/float. Types S8 S16 S32 F32. */
|
18293 |
|
|
NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
|
18294 |
|
|
NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
|
18295 |
|
|
|
18296 |
|
|
/* Data processing with two registers and a shift amount. */
|
18297 |
|
|
/* Right shifts, and variants with rounding.
|
18298 |
|
|
Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
|
18299 |
|
|
NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
|
18300 |
|
|
NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
|
18301 |
|
|
NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
|
18302 |
|
|
NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
|
18303 |
|
|
NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
|
18304 |
|
|
NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
|
18305 |
|
|
NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
|
18306 |
|
|
NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
|
18307 |
|
|
/* Shift and insert. Sizes accepted 8 16 32 64. */
|
18308 |
|
|
NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
|
18309 |
|
|
NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
|
18310 |
|
|
NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
|
18311 |
|
|
NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
|
18312 |
|
|
/* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
|
18313 |
|
|
NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
|
18314 |
|
|
NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
|
18315 |
|
|
/* Right shift immediate, saturating & narrowing, with rounding variants.
|
18316 |
|
|
Types accepted S16 S32 S64 U16 U32 U64. */
|
18317 |
|
|
NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
|
18318 |
|
|
NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
|
18319 |
|
|
/* As above, unsigned. Types accepted S16 S32 S64. */
|
18320 |
|
|
NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
|
18321 |
|
|
NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
|
18322 |
|
|
/* Right shift narrowing. Types accepted I16 I32 I64. */
|
18323 |
|
|
NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
|
18324 |
|
|
NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
|
18325 |
|
|
/* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
|
18326 |
|
|
nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
|
18327 |
|
|
/* CVT with optional immediate for fixed-point variant. */
|
18328 |
|
|
nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
|
18329 |
|
|
|
18330 |
|
|
nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
|
18331 |
|
|
nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
|
18332 |
|
|
|
18333 |
|
|
/* Data processing, three registers of different lengths. */
|
18334 |
|
|
/* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
|
18335 |
|
|
NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
|
18336 |
|
|
NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
|
18337 |
|
|
NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
|
18338 |
|
|
NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
|
18339 |
|
|
/* If not scalar, fall back to neon_dyadic_long.
|
18340 |
|
|
Vector types as above, scalar types S16 S32 U16 U32. */
|
18341 |
|
|
nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
|
18342 |
|
|
nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
|
18343 |
|
|
/* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
|
18344 |
|
|
NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
|
18345 |
|
|
NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
|
18346 |
|
|
/* Dyadic, narrowing insns. Types I16 I32 I64. */
|
18347 |
|
|
NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
|
18348 |
|
|
NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
|
18349 |
|
|
NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
|
18350 |
|
|
NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
|
18351 |
|
|
/* Saturating doubling multiplies. Types S16 S32. */
|
18352 |
|
|
nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
|
18353 |
|
|
nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
|
18354 |
|
|
nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
|
18355 |
|
|
/* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
|
18356 |
|
|
S16 S32 U16 U32. */
|
18357 |
|
|
nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
|
18358 |
|
|
|
18359 |
|
|
/* Extract. Size 8. */
|
18360 |
|
|
NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
|
18361 |
|
|
NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
|
18362 |
|
|
|
18363 |
|
|
/* Two registers, miscellaneous. */
|
18364 |
|
|
/* Reverse. Sizes 8 16 32 (must be < size in opcode). */
|
18365 |
|
|
NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
|
18366 |
|
|
NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
|
18367 |
|
|
NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
|
18368 |
|
|
NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
|
18369 |
|
|
NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
|
18370 |
|
|
NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
|
18371 |
|
|
/* Vector replicate. Sizes 8 16 32. */
|
18372 |
|
|
nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
|
18373 |
|
|
nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
|
18374 |
|
|
/* VMOVL. Types S8 S16 S32 U8 U16 U32. */
|
18375 |
|
|
NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
|
18376 |
|
|
/* VMOVN. Types I16 I32 I64. */
|
18377 |
|
|
nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
|
18378 |
|
|
/* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
|
18379 |
|
|
nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
|
18380 |
|
|
/* VQMOVUN. Types S16 S32 S64. */
|
18381 |
|
|
nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
|
18382 |
|
|
/* VZIP / VUZP. Sizes 8 16 32. */
|
18383 |
|
|
NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
|
18384 |
|
|
NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
|
18385 |
|
|
NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
|
18386 |
|
|
NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
|
18387 |
|
|
/* VQABS / VQNEG. Types S8 S16 S32. */
|
18388 |
|
|
NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
|
18389 |
|
|
NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
|
18390 |
|
|
NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
|
18391 |
|
|
NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
|
18392 |
|
|
/* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
|
18393 |
|
|
NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
|
18394 |
|
|
NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
|
18395 |
|
|
NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
|
18396 |
|
|
NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
|
18397 |
|
|
/* Reciprocal estimates. Types U32 F32. */
|
18398 |
|
|
NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
|
18399 |
|
|
NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
|
18400 |
|
|
NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
|
18401 |
|
|
NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
|
18402 |
|
|
/* VCLS. Types S8 S16 S32. */
|
18403 |
|
|
NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
|
18404 |
|
|
NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
|
18405 |
|
|
/* VCLZ. Types I8 I16 I32. */
|
18406 |
|
|
NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
|
18407 |
|
|
NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
|
18408 |
|
|
/* VCNT. Size 8. */
|
18409 |
|
|
NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
|
18410 |
|
|
NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
|
18411 |
|
|
/* Two address, untyped. */
|
18412 |
|
|
NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
|
18413 |
|
|
NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
|
18414 |
|
|
/* VTRN. Sizes 8 16 32. */
|
18415 |
|
|
nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
|
18416 |
|
|
nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
|
18417 |
|
|
|
18418 |
|
|
/* Table lookup. Size 8. */
|
18419 |
|
|
NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
|
18420 |
|
|
NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
|
18421 |
|
|
|
18422 |
|
|
#undef THUMB_VARIANT
|
18423 |
|
|
#define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
|
18424 |
|
|
#undef ARM_VARIANT
|
18425 |
|
|
#define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
|
18426 |
|
|
|
18427 |
|
|
/* Neon element/structure load/store. */
|
18428 |
|
|
nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
|
18429 |
|
|
nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
|
18430 |
|
|
nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
|
18431 |
|
|
nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
|
18432 |
|
|
nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
|
18433 |
|
|
nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
|
18434 |
|
|
nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
|
18435 |
|
|
nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
|
18436 |
|
|
|
18437 |
|
|
#undef THUMB_VARIANT
|
18438 |
|
|
#define THUMB_VARIANT &fpu_vfp_ext_v3xd
|
18439 |
|
|
#undef ARM_VARIANT
|
18440 |
|
|
#define ARM_VARIANT &fpu_vfp_ext_v3xd
|
18441 |
|
|
cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
|
18442 |
|
|
cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
|
18443 |
|
|
cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
|
18444 |
|
|
cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
|
18445 |
|
|
cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
|
18446 |
|
|
cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
|
18447 |
|
|
cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
|
18448 |
|
|
cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
|
18449 |
|
|
cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
|
18450 |
|
|
|
18451 |
|
|
#undef THUMB_VARIANT
|
18452 |
|
|
#define THUMB_VARIANT & fpu_vfp_ext_v3
|
18453 |
|
|
#undef ARM_VARIANT
|
18454 |
|
|
#define ARM_VARIANT & fpu_vfp_ext_v3
|
18455 |
|
|
|
18456 |
|
|
cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
|
18457 |
|
|
cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
|
18458 |
|
|
cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
|
18459 |
|
|
cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
|
18460 |
|
|
cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
|
18461 |
|
|
cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
|
18462 |
|
|
cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
|
18463 |
|
|
cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
|
18464 |
|
|
cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
|
18465 |
|
|
|
18466 |
|
|
#undef ARM_VARIANT
|
18467 |
|
|
#define ARM_VARIANT &fpu_vfp_ext_fma
|
18468 |
|
|
#undef THUMB_VARIANT
|
18469 |
|
|
#define THUMB_VARIANT &fpu_vfp_ext_fma
|
18470 |
|
|
/* Mnemonics shared by Neon and VFP. These are included in the
|
18471 |
|
|
VFP FMA variant; NEON and VFP FMA always includes the NEON
|
18472 |
|
|
FMA instructions. */
|
18473 |
|
|
nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
|
18474 |
|
|
nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
|
18475 |
|
|
/* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
|
18476 |
|
|
the v form should always be used. */
|
18477 |
|
|
cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
|
18478 |
|
|
cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
|
18479 |
|
|
cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
|
18480 |
|
|
cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
|
18481 |
|
|
nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
|
18482 |
|
|
nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
|
18483 |
|
|
|
18484 |
|
|
#undef THUMB_VARIANT
|
18485 |
|
|
#undef ARM_VARIANT
|
18486 |
|
|
#define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
|
18487 |
|
|
|
18488 |
|
|
cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
|
18489 |
|
|
cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
|
18490 |
|
|
cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
|
18491 |
|
|
cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
|
18492 |
|
|
cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
|
18493 |
|
|
cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
|
18494 |
|
|
cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
|
18495 |
|
|
cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
|
18496 |
|
|
|
18497 |
|
|
#undef ARM_VARIANT
|
18498 |
|
|
#define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
|
18499 |
|
|
|
18500 |
|
|
cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
|
18501 |
|
|
cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
|
18502 |
|
|
cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
|
18503 |
|
|
cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
|
18504 |
|
|
cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
|
18505 |
|
|
cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
|
18506 |
|
|
cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
|
18507 |
|
|
cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
|
18508 |
|
|
cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
|
18509 |
|
|
cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
|
18510 |
|
|
cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
|
18511 |
|
|
cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
|
18512 |
|
|
cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
|
18513 |
|
|
cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
|
18514 |
|
|
cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
|
18515 |
|
|
cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
|
18516 |
|
|
cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
|
18517 |
|
|
cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
|
18518 |
|
|
cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
|
18519 |
|
|
cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
|
18520 |
|
|
cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
|
18521 |
|
|
cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
|
18522 |
|
|
cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
|
18523 |
|
|
cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
|
18524 |
|
|
cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
|
18525 |
|
|
cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
|
18526 |
|
|
cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
|
18527 |
|
|
cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
|
18528 |
|
|
cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
|
18529 |
|
|
cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
|
18530 |
|
|
cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
|
18531 |
|
|
cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
|
18532 |
|
|
cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
|
18533 |
|
|
cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
|
18534 |
|
|
cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
|
18535 |
|
|
cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
|
18536 |
|
|
cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
|
18537 |
|
|
cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18538 |
|
|
cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18539 |
|
|
cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18540 |
|
|
cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18541 |
|
|
cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18542 |
|
|
cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18543 |
|
|
cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18544 |
|
|
cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18545 |
|
|
cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18546 |
|
|
cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
|
18547 |
|
|
cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18548 |
|
|
cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18549 |
|
|
cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18550 |
|
|
cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18551 |
|
|
cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18552 |
|
|
cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18553 |
|
|
cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18554 |
|
|
cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18555 |
|
|
cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18556 |
|
|
cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18557 |
|
|
cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18558 |
|
|
cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18559 |
|
|
cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18560 |
|
|
cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18561 |
|
|
cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18562 |
|
|
cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18563 |
|
|
cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18564 |
|
|
cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18565 |
|
|
cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18566 |
|
|
cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
|
18567 |
|
|
cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
|
18568 |
|
|
cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
|
18569 |
|
|
cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
|
18570 |
|
|
cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18571 |
|
|
cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18572 |
|
|
cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18573 |
|
|
cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18574 |
|
|
cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18575 |
|
|
cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18576 |
|
|
cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18577 |
|
|
cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18578 |
|
|
cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18579 |
|
|
cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18580 |
|
|
cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18581 |
|
|
cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18582 |
|
|
cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18583 |
|
|
cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18584 |
|
|
cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18585 |
|
|
cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18586 |
|
|
cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18587 |
|
|
cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18588 |
|
|
cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
|
18589 |
|
|
cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18590 |
|
|
cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18591 |
|
|
cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18592 |
|
|
cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18593 |
|
|
cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18594 |
|
|
cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18595 |
|
|
cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18596 |
|
|
cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18597 |
|
|
cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18598 |
|
|
cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18599 |
|
|
cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18600 |
|
|
cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
|
18601 |
|
|
cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
|
18602 |
|
|
cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
|
18603 |
|
|
cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
|
18604 |
|
|
cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
|
18605 |
|
|
cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
|
18606 |
|
|
cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18607 |
|
|
cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18608 |
|
|
cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18609 |
|
|
cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18610 |
|
|
cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
|
18611 |
|
|
cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
|
18612 |
|
|
cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
|
18613 |
|
|
cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
|
18614 |
|
|
cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
|
18615 |
|
|
cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
|
18616 |
|
|
cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
|
18617 |
|
|
cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
|
18618 |
|
|
cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
|
18619 |
|
|
cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
|
18620 |
|
|
cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
|
18621 |
|
|
cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
|
18622 |
|
|
cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
|
18623 |
|
|
cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
|
18624 |
|
|
cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
|
18625 |
|
|
cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
|
18626 |
|
|
cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
|
18627 |
|
|
cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
|
18628 |
|
|
cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
|
18629 |
|
|
cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
|
18630 |
|
|
cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
|
18631 |
|
|
cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
|
18632 |
|
|
cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
|
18633 |
|
|
cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18634 |
|
|
cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18635 |
|
|
cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18636 |
|
|
cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18637 |
|
|
cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18638 |
|
|
cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18639 |
|
|
cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18640 |
|
|
cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18641 |
|
|
cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18642 |
|
|
cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
|
18643 |
|
|
cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
|
18644 |
|
|
cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
|
18645 |
|
|
cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
|
18646 |
|
|
cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
|
18647 |
|
|
cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
|
18648 |
|
|
cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18649 |
|
|
cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18650 |
|
|
cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18651 |
|
|
cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
|
18652 |
|
|
cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
|
18653 |
|
|
cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
|
18654 |
|
|
cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
|
18655 |
|
|
cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
|
18656 |
|
|
cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
|
18657 |
|
|
cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18658 |
|
|
cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18659 |
|
|
cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18660 |
|
|
cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18661 |
|
|
cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
|
18662 |
|
|
|
18663 |
|
|
#undef ARM_VARIANT
|
18664 |
|
|
#define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
|
18665 |
|
|
|
18666 |
|
|
cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
|
18667 |
|
|
cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
|
18668 |
|
|
cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
|
18669 |
|
|
cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
|
18670 |
|
|
cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
|
18671 |
|
|
cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
|
18672 |
|
|
cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18673 |
|
|
cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18674 |
|
|
cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18675 |
|
|
cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18676 |
|
|
cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18677 |
|
|
cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18678 |
|
|
cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18679 |
|
|
cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18680 |
|
|
cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18681 |
|
|
cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18682 |
|
|
cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18683 |
|
|
cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18684 |
|
|
cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18685 |
|
|
cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18686 |
|
|
cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
|
18687 |
|
|
cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18688 |
|
|
cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18689 |
|
|
cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18690 |
|
|
cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18691 |
|
|
cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18692 |
|
|
cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18693 |
|
|
cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18694 |
|
|
cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18695 |
|
|
cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18696 |
|
|
cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18697 |
|
|
cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18698 |
|
|
cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18699 |
|
|
cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18700 |
|
|
cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18701 |
|
|
cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18702 |
|
|
cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18703 |
|
|
cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18704 |
|
|
cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18705 |
|
|
cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18706 |
|
|
cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18707 |
|
|
cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18708 |
|
|
cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18709 |
|
|
cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18710 |
|
|
cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18711 |
|
|
cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18712 |
|
|
cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18713 |
|
|
cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18714 |
|
|
cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18715 |
|
|
cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18716 |
|
|
cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18717 |
|
|
cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18718 |
|
|
cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18719 |
|
|
cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18720 |
|
|
cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18721 |
|
|
cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18722 |
|
|
cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
|
18723 |
|
|
|
18724 |
|
|
#undef ARM_VARIANT
|
18725 |
|
|
#define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
|
18726 |
|
|
|
18727 |
|
|
cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
|
18728 |
|
|
cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
|
18729 |
|
|
cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
|
18730 |
|
|
cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
|
18731 |
|
|
cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
|
18732 |
|
|
cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
|
18733 |
|
|
cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
|
18734 |
|
|
cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
|
18735 |
|
|
cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
|
18736 |
|
|
cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
|
18737 |
|
|
cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
|
18738 |
|
|
cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
|
18739 |
|
|
cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
|
18740 |
|
|
cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
|
18741 |
|
|
cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
|
18742 |
|
|
cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
|
18743 |
|
|
cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
|
18744 |
|
|
cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
|
18745 |
|
|
cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
|
18746 |
|
|
cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
|
18747 |
|
|
cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
|
18748 |
|
|
cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
|
18749 |
|
|
cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
|
18750 |
|
|
cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
|
18751 |
|
|
cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
|
18752 |
|
|
cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
|
18753 |
|
|
cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
|
18754 |
|
|
cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
|
18755 |
|
|
cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
|
18756 |
|
|
cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
|
18757 |
|
|
cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
|
18758 |
|
|
cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
|
18759 |
|
|
cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
|
18760 |
|
|
cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
|
18761 |
|
|
cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
|
18762 |
|
|
cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
|
18763 |
|
|
cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
|
18764 |
|
|
cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
|
18765 |
|
|
cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
|
18766 |
|
|
cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
|
18767 |
|
|
cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
|
18768 |
|
|
cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
|
18769 |
|
|
cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
|
18770 |
|
|
cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
|
18771 |
|
|
cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
|
18772 |
|
|
cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
|
18773 |
|
|
cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
|
18774 |
|
|
cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
|
18775 |
|
|
cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
|
18776 |
|
|
cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
|
18777 |
|
|
cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
|
18778 |
|
|
cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
|
18779 |
|
|
cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
|
18780 |
|
|
cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
|
18781 |
|
|
cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
|
18782 |
|
|
cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
|
18783 |
|
|
cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
|
18784 |
|
|
cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
|
18785 |
|
|
cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
|
18786 |
|
|
cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
|
18787 |
|
|
cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
|
18788 |
|
|
cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
|
18789 |
|
|
cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
|
18790 |
|
|
cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
|
18791 |
|
|
cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
|
18792 |
|
|
cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
|
18793 |
|
|
cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
|
18794 |
|
|
cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
|
18795 |
|
|
cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
|
18796 |
|
|
cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
|
18797 |
|
|
cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
|
18798 |
|
|
cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
|
18799 |
|
|
cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
|
18800 |
|
|
cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
|
18801 |
|
|
cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
|
18802 |
|
|
cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
|
18803 |
|
|
};
|
18804 |
|
|
#undef ARM_VARIANT
|
18805 |
|
|
#undef THUMB_VARIANT
|
18806 |
|
|
#undef TCE
|
18807 |
|
|
#undef TCM
|
18808 |
|
|
#undef TUE
|
18809 |
|
|
#undef TUF
|
18810 |
|
|
#undef TCC
|
18811 |
|
|
#undef cCE
|
18812 |
|
|
#undef cCL
|
18813 |
|
|
#undef C3E
|
18814 |
|
|
#undef CE
|
18815 |
|
|
#undef CM
|
18816 |
|
|
#undef UE
|
18817 |
|
|
#undef UF
|
18818 |
|
|
#undef UT
|
18819 |
|
|
#undef NUF
|
18820 |
|
|
#undef nUF
|
18821 |
|
|
#undef NCE
|
18822 |
|
|
#undef nCE
|
18823 |
|
|
#undef OPS0
|
18824 |
|
|
#undef OPS1
|
18825 |
|
|
#undef OPS2
|
18826 |
|
|
#undef OPS3
|
18827 |
|
|
#undef OPS4
|
18828 |
|
|
#undef OPS5
|
18829 |
|
|
#undef OPS6
|
18830 |
|
|
#undef do_0
|
18831 |
|
|
|
18832 |
|
|
/* MD interface: bits in the object file. */
|
18833 |
|
|
|
18834 |
|
|
/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
|
18835 |
|
|
for use in the a.out file, and stores them in the array pointed to by buf.
|
18836 |
|
|
This knows about the endian-ness of the target machine and does
|
18837 |
|
|
THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
|
18838 |
|
|
2 (short) and 4 (long) Floating numbers are put out as a series of
|
18839 |
|
|
LITTLENUMS (shorts, here at least). */
|
18840 |
|
|
|
18841 |
|
|
void
|
18842 |
|
|
md_number_to_chars (char * buf, valueT val, int n)
|
18843 |
|
|
{
|
18844 |
|
|
if (target_big_endian)
|
18845 |
|
|
number_to_chars_bigendian (buf, val, n);
|
18846 |
|
|
else
|
18847 |
|
|
number_to_chars_littleendian (buf, val, n);
|
18848 |
|
|
}
|
18849 |
|
|
|
18850 |
|
|
static valueT
|
18851 |
|
|
md_chars_to_number (char * buf, int n)
|
18852 |
|
|
{
|
18853 |
|
|
valueT result = 0;
|
18854 |
|
|
unsigned char * where = (unsigned char *) buf;
|
18855 |
|
|
|
18856 |
|
|
if (target_big_endian)
|
18857 |
|
|
{
|
18858 |
|
|
while (n--)
|
18859 |
|
|
{
|
18860 |
|
|
result <<= 8;
|
18861 |
|
|
result |= (*where++ & 255);
|
18862 |
|
|
}
|
18863 |
|
|
}
|
18864 |
|
|
else
|
18865 |
|
|
{
|
18866 |
|
|
while (n--)
|
18867 |
|
|
{
|
18868 |
|
|
result <<= 8;
|
18869 |
|
|
result |= (where[n] & 255);
|
18870 |
|
|
}
|
18871 |
|
|
}
|
18872 |
|
|
|
18873 |
|
|
return result;
|
18874 |
|
|
}
|
18875 |
|
|
|
18876 |
|
|
/* MD interface: Sections. */
|
18877 |
|
|
|
18878 |
|
|
/* Estimate the size of a frag before relaxing. Assume everything fits in
|
18879 |
|
|
2 bytes. */
|
18880 |
|
|
|
18881 |
|
|
int
|
18882 |
|
|
md_estimate_size_before_relax (fragS * fragp,
|
18883 |
|
|
segT segtype ATTRIBUTE_UNUSED)
|
18884 |
|
|
{
|
18885 |
|
|
fragp->fr_var = 2;
|
18886 |
|
|
return 2;
|
18887 |
|
|
}
|
18888 |
|
|
|
18889 |
|
|
/* Convert a machine dependent frag. */
|
18890 |
|
|
|
18891 |
|
|
void
|
18892 |
|
|
md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
|
18893 |
|
|
{
|
18894 |
|
|
unsigned long insn;
|
18895 |
|
|
unsigned long old_op;
|
18896 |
|
|
char *buf;
|
18897 |
|
|
expressionS exp;
|
18898 |
|
|
fixS *fixp;
|
18899 |
|
|
int reloc_type;
|
18900 |
|
|
int pc_rel;
|
18901 |
|
|
int opcode;
|
18902 |
|
|
|
18903 |
|
|
buf = fragp->fr_literal + fragp->fr_fix;
|
18904 |
|
|
|
18905 |
|
|
old_op = bfd_get_16(abfd, buf);
|
18906 |
|
|
if (fragp->fr_symbol)
|
18907 |
|
|
{
|
18908 |
|
|
exp.X_op = O_symbol;
|
18909 |
|
|
exp.X_add_symbol = fragp->fr_symbol;
|
18910 |
|
|
}
|
18911 |
|
|
else
|
18912 |
|
|
{
|
18913 |
|
|
exp.X_op = O_constant;
|
18914 |
|
|
}
|
18915 |
|
|
exp.X_add_number = fragp->fr_offset;
|
18916 |
|
|
opcode = fragp->fr_subtype;
|
18917 |
|
|
switch (opcode)
|
18918 |
|
|
{
|
18919 |
|
|
case T_MNEM_ldr_pc:
|
18920 |
|
|
case T_MNEM_ldr_pc2:
|
18921 |
|
|
case T_MNEM_ldr_sp:
|
18922 |
|
|
case T_MNEM_str_sp:
|
18923 |
|
|
case T_MNEM_ldr:
|
18924 |
|
|
case T_MNEM_ldrb:
|
18925 |
|
|
case T_MNEM_ldrh:
|
18926 |
|
|
case T_MNEM_str:
|
18927 |
|
|
case T_MNEM_strb:
|
18928 |
|
|
case T_MNEM_strh:
|
18929 |
|
|
if (fragp->fr_var == 4)
|
18930 |
|
|
{
|
18931 |
|
|
insn = THUMB_OP32 (opcode);
|
18932 |
|
|
if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
|
18933 |
|
|
{
|
18934 |
|
|
insn |= (old_op & 0x700) << 4;
|
18935 |
|
|
}
|
18936 |
|
|
else
|
18937 |
|
|
{
|
18938 |
|
|
insn |= (old_op & 7) << 12;
|
18939 |
|
|
insn |= (old_op & 0x38) << 13;
|
18940 |
|
|
}
|
18941 |
|
|
insn |= 0x00000c00;
|
18942 |
|
|
put_thumb32_insn (buf, insn);
|
18943 |
|
|
reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
|
18944 |
|
|
}
|
18945 |
|
|
else
|
18946 |
|
|
{
|
18947 |
|
|
reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
|
18948 |
|
|
}
|
18949 |
|
|
pc_rel = (opcode == T_MNEM_ldr_pc2);
|
18950 |
|
|
break;
|
18951 |
|
|
case T_MNEM_adr:
|
18952 |
|
|
if (fragp->fr_var == 4)
|
18953 |
|
|
{
|
18954 |
|
|
insn = THUMB_OP32 (opcode);
|
18955 |
|
|
insn |= (old_op & 0xf0) << 4;
|
18956 |
|
|
put_thumb32_insn (buf, insn);
|
18957 |
|
|
reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
|
18958 |
|
|
}
|
18959 |
|
|
else
|
18960 |
|
|
{
|
18961 |
|
|
reloc_type = BFD_RELOC_ARM_THUMB_ADD;
|
18962 |
|
|
exp.X_add_number -= 4;
|
18963 |
|
|
}
|
18964 |
|
|
pc_rel = 1;
|
18965 |
|
|
break;
|
18966 |
|
|
case T_MNEM_mov:
|
18967 |
|
|
case T_MNEM_movs:
|
18968 |
|
|
case T_MNEM_cmp:
|
18969 |
|
|
case T_MNEM_cmn:
|
18970 |
|
|
if (fragp->fr_var == 4)
|
18971 |
|
|
{
|
18972 |
|
|
int r0off = (opcode == T_MNEM_mov
|
18973 |
|
|
|| opcode == T_MNEM_movs) ? 0 : 8;
|
18974 |
|
|
insn = THUMB_OP32 (opcode);
|
18975 |
|
|
insn = (insn & 0xe1ffffff) | 0x10000000;
|
18976 |
|
|
insn |= (old_op & 0x700) << r0off;
|
18977 |
|
|
put_thumb32_insn (buf, insn);
|
18978 |
|
|
reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
|
18979 |
|
|
}
|
18980 |
|
|
else
|
18981 |
|
|
{
|
18982 |
|
|
reloc_type = BFD_RELOC_ARM_THUMB_IMM;
|
18983 |
|
|
}
|
18984 |
|
|
pc_rel = 0;
|
18985 |
|
|
break;
|
18986 |
|
|
case T_MNEM_b:
|
18987 |
|
|
if (fragp->fr_var == 4)
|
18988 |
|
|
{
|
18989 |
|
|
insn = THUMB_OP32(opcode);
|
18990 |
|
|
put_thumb32_insn (buf, insn);
|
18991 |
|
|
reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
|
18992 |
|
|
}
|
18993 |
|
|
else
|
18994 |
|
|
reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
|
18995 |
|
|
pc_rel = 1;
|
18996 |
|
|
break;
|
18997 |
|
|
case T_MNEM_bcond:
|
18998 |
|
|
if (fragp->fr_var == 4)
|
18999 |
|
|
{
|
19000 |
|
|
insn = THUMB_OP32(opcode);
|
19001 |
|
|
insn |= (old_op & 0xf00) << 14;
|
19002 |
|
|
put_thumb32_insn (buf, insn);
|
19003 |
|
|
reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
|
19004 |
|
|
}
|
19005 |
|
|
else
|
19006 |
|
|
reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
|
19007 |
|
|
pc_rel = 1;
|
19008 |
|
|
break;
|
19009 |
|
|
case T_MNEM_add_sp:
|
19010 |
|
|
case T_MNEM_add_pc:
|
19011 |
|
|
case T_MNEM_inc_sp:
|
19012 |
|
|
case T_MNEM_dec_sp:
|
19013 |
|
|
if (fragp->fr_var == 4)
|
19014 |
|
|
{
|
19015 |
|
|
/* ??? Choose between add and addw. */
|
19016 |
|
|
insn = THUMB_OP32 (opcode);
|
19017 |
|
|
insn |= (old_op & 0xf0) << 4;
|
19018 |
|
|
put_thumb32_insn (buf, insn);
|
19019 |
|
|
if (opcode == T_MNEM_add_pc)
|
19020 |
|
|
reloc_type = BFD_RELOC_ARM_T32_IMM12;
|
19021 |
|
|
else
|
19022 |
|
|
reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
|
19023 |
|
|
}
|
19024 |
|
|
else
|
19025 |
|
|
reloc_type = BFD_RELOC_ARM_THUMB_ADD;
|
19026 |
|
|
pc_rel = 0;
|
19027 |
|
|
break;
|
19028 |
|
|
|
19029 |
|
|
case T_MNEM_addi:
|
19030 |
|
|
case T_MNEM_addis:
|
19031 |
|
|
case T_MNEM_subi:
|
19032 |
|
|
case T_MNEM_subis:
|
19033 |
|
|
if (fragp->fr_var == 4)
|
19034 |
|
|
{
|
19035 |
|
|
insn = THUMB_OP32 (opcode);
|
19036 |
|
|
insn |= (old_op & 0xf0) << 4;
|
19037 |
|
|
insn |= (old_op & 0xf) << 16;
|
19038 |
|
|
put_thumb32_insn (buf, insn);
|
19039 |
|
|
if (insn & (1 << 20))
|
19040 |
|
|
reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
|
19041 |
|
|
else
|
19042 |
|
|
reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
|
19043 |
|
|
}
|
19044 |
|
|
else
|
19045 |
|
|
reloc_type = BFD_RELOC_ARM_THUMB_ADD;
|
19046 |
|
|
pc_rel = 0;
|
19047 |
|
|
break;
|
19048 |
|
|
default:
|
19049 |
|
|
abort ();
|
19050 |
|
|
}
|
19051 |
|
|
fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
|
19052 |
|
|
(enum bfd_reloc_code_real) reloc_type);
|
19053 |
|
|
fixp->fx_file = fragp->fr_file;
|
19054 |
|
|
fixp->fx_line = fragp->fr_line;
|
19055 |
|
|
fragp->fr_fix += fragp->fr_var;
|
19056 |
|
|
}
|
19057 |
|
|
|
19058 |
|
|
/* Return the size of a relaxable immediate operand instruction.
|
19059 |
|
|
SHIFT and SIZE specify the form of the allowable immediate. */
|
19060 |
|
|
static int
|
19061 |
|
|
relax_immediate (fragS *fragp, int size, int shift)
|
19062 |
|
|
{
|
19063 |
|
|
offsetT offset;
|
19064 |
|
|
offsetT mask;
|
19065 |
|
|
offsetT low;
|
19066 |
|
|
|
19067 |
|
|
/* ??? Should be able to do better than this. */
|
19068 |
|
|
if (fragp->fr_symbol)
|
19069 |
|
|
return 4;
|
19070 |
|
|
|
19071 |
|
|
low = (1 << shift) - 1;
|
19072 |
|
|
mask = (1 << (shift + size)) - (1 << shift);
|
19073 |
|
|
offset = fragp->fr_offset;
|
19074 |
|
|
/* Force misaligned offsets to 32-bit variant. */
|
19075 |
|
|
if (offset & low)
|
19076 |
|
|
return 4;
|
19077 |
|
|
if (offset & ~mask)
|
19078 |
|
|
return 4;
|
19079 |
|
|
return 2;
|
19080 |
|
|
}
|
19081 |
|
|
|
19082 |
|
|
/* Get the address of a symbol during relaxation. */
|
19083 |
|
|
static addressT
|
19084 |
|
|
relaxed_symbol_addr (fragS *fragp, long stretch)
|
19085 |
|
|
{
|
19086 |
|
|
fragS *sym_frag;
|
19087 |
|
|
addressT addr;
|
19088 |
|
|
symbolS *sym;
|
19089 |
|
|
|
19090 |
|
|
sym = fragp->fr_symbol;
|
19091 |
|
|
sym_frag = symbol_get_frag (sym);
|
19092 |
|
|
know (S_GET_SEGMENT (sym) != absolute_section
|
19093 |
|
|
|| sym_frag == &zero_address_frag);
|
19094 |
|
|
addr = S_GET_VALUE (sym) + fragp->fr_offset;
|
19095 |
|
|
|
19096 |
|
|
/* If frag has yet to be reached on this pass, assume it will
|
19097 |
|
|
move by STRETCH just as we did. If this is not so, it will
|
19098 |
|
|
be because some frag between grows, and that will force
|
19099 |
|
|
another pass. */
|
19100 |
|
|
|
19101 |
|
|
if (stretch != 0
|
19102 |
|
|
&& sym_frag->relax_marker != fragp->relax_marker)
|
19103 |
|
|
{
|
19104 |
|
|
fragS *f;
|
19105 |
|
|
|
19106 |
|
|
/* Adjust stretch for any alignment frag. Note that if have
|
19107 |
|
|
been expanding the earlier code, the symbol may be
|
19108 |
|
|
defined in what appears to be an earlier frag. FIXME:
|
19109 |
|
|
This doesn't handle the fr_subtype field, which specifies
|
19110 |
|
|
a maximum number of bytes to skip when doing an
|
19111 |
|
|
alignment. */
|
19112 |
|
|
for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
|
19113 |
|
|
{
|
19114 |
|
|
if (f->fr_type == rs_align || f->fr_type == rs_align_code)
|
19115 |
|
|
{
|
19116 |
|
|
if (stretch < 0)
|
19117 |
|
|
stretch = - ((- stretch)
|
19118 |
|
|
& ~ ((1 << (int) f->fr_offset) - 1));
|
19119 |
|
|
else
|
19120 |
|
|
stretch &= ~ ((1 << (int) f->fr_offset) - 1);
|
19121 |
|
|
if (stretch == 0)
|
19122 |
|
|
break;
|
19123 |
|
|
}
|
19124 |
|
|
}
|
19125 |
|
|
if (f != NULL)
|
19126 |
|
|
addr += stretch;
|
19127 |
|
|
}
|
19128 |
|
|
|
19129 |
|
|
return addr;
|
19130 |
|
|
}
|
19131 |
|
|
|
19132 |
|
|
/* Return the size of a relaxable adr pseudo-instruction or PC-relative
|
19133 |
|
|
load. */
|
19134 |
|
|
static int
|
19135 |
|
|
relax_adr (fragS *fragp, asection *sec, long stretch)
|
19136 |
|
|
{
|
19137 |
|
|
addressT addr;
|
19138 |
|
|
offsetT val;
|
19139 |
|
|
|
19140 |
|
|
/* Assume worst case for symbols not known to be in the same section. */
|
19141 |
|
|
if (fragp->fr_symbol == NULL
|
19142 |
|
|
|| !S_IS_DEFINED (fragp->fr_symbol)
|
19143 |
|
|
|| sec != S_GET_SEGMENT (fragp->fr_symbol)
|
19144 |
|
|
|| S_IS_WEAK (fragp->fr_symbol))
|
19145 |
|
|
return 4;
|
19146 |
|
|
|
19147 |
|
|
val = relaxed_symbol_addr (fragp, stretch);
|
19148 |
|
|
addr = fragp->fr_address + fragp->fr_fix;
|
19149 |
|
|
addr = (addr + 4) & ~3;
|
19150 |
|
|
/* Force misaligned targets to 32-bit variant. */
|
19151 |
|
|
if (val & 3)
|
19152 |
|
|
return 4;
|
19153 |
|
|
val -= addr;
|
19154 |
|
|
if (val < 0 || val > 1020)
|
19155 |
|
|
return 4;
|
19156 |
|
|
return 2;
|
19157 |
|
|
}
|
19158 |
|
|
|
19159 |
|
|
/* Return the size of a relaxable add/sub immediate instruction. */
|
19160 |
|
|
static int
|
19161 |
|
|
relax_addsub (fragS *fragp, asection *sec)
|
19162 |
|
|
{
|
19163 |
|
|
char *buf;
|
19164 |
|
|
int op;
|
19165 |
|
|
|
19166 |
|
|
buf = fragp->fr_literal + fragp->fr_fix;
|
19167 |
|
|
op = bfd_get_16(sec->owner, buf);
|
19168 |
|
|
if ((op & 0xf) == ((op >> 4) & 0xf))
|
19169 |
|
|
return relax_immediate (fragp, 8, 0);
|
19170 |
|
|
else
|
19171 |
|
|
return relax_immediate (fragp, 3, 0);
|
19172 |
|
|
}
|
19173 |
|
|
|
19174 |
|
|
|
19175 |
|
|
/* Return the size of a relaxable branch instruction. BITS is the
|
19176 |
|
|
size of the offset field in the narrow instruction. */
|
19177 |
|
|
|
19178 |
|
|
static int
|
19179 |
|
|
relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
|
19180 |
|
|
{
|
19181 |
|
|
addressT addr;
|
19182 |
|
|
offsetT val;
|
19183 |
|
|
offsetT limit;
|
19184 |
|
|
|
19185 |
|
|
/* Assume worst case for symbols not known to be in the same section. */
|
19186 |
|
|
if (!S_IS_DEFINED (fragp->fr_symbol)
|
19187 |
|
|
|| sec != S_GET_SEGMENT (fragp->fr_symbol)
|
19188 |
|
|
|| S_IS_WEAK (fragp->fr_symbol))
|
19189 |
|
|
return 4;
|
19190 |
|
|
|
19191 |
|
|
#ifdef OBJ_ELF
|
19192 |
|
|
if (S_IS_DEFINED (fragp->fr_symbol)
|
19193 |
|
|
&& ARM_IS_FUNC (fragp->fr_symbol))
|
19194 |
|
|
return 4;
|
19195 |
|
|
|
19196 |
|
|
/* PR 12532. Global symbols with default visibility might
|
19197 |
|
|
be preempted, so do not relax relocations to them. */
|
19198 |
|
|
if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
|
19199 |
|
|
&& (! S_IS_LOCAL (fragp->fr_symbol)))
|
19200 |
|
|
return 4;
|
19201 |
|
|
#endif
|
19202 |
|
|
|
19203 |
|
|
val = relaxed_symbol_addr (fragp, stretch);
|
19204 |
|
|
addr = fragp->fr_address + fragp->fr_fix + 4;
|
19205 |
|
|
val -= addr;
|
19206 |
|
|
|
19207 |
|
|
/* Offset is a signed value *2 */
|
19208 |
|
|
limit = 1 << bits;
|
19209 |
|
|
if (val >= limit || val < -limit)
|
19210 |
|
|
return 4;
|
19211 |
|
|
return 2;
|
19212 |
|
|
}
|
19213 |
|
|
|
19214 |
|
|
|
19215 |
|
|
/* Relax a machine dependent frag. This returns the amount by which
|
19216 |
|
|
the current size of the frag should change. */
|
19217 |
|
|
|
19218 |
|
|
int
|
19219 |
|
|
arm_relax_frag (asection *sec, fragS *fragp, long stretch)
|
19220 |
|
|
{
|
19221 |
|
|
int oldsize;
|
19222 |
|
|
int newsize;
|
19223 |
|
|
|
19224 |
|
|
oldsize = fragp->fr_var;
|
19225 |
|
|
switch (fragp->fr_subtype)
|
19226 |
|
|
{
|
19227 |
|
|
case T_MNEM_ldr_pc2:
|
19228 |
|
|
newsize = relax_adr (fragp, sec, stretch);
|
19229 |
|
|
break;
|
19230 |
|
|
case T_MNEM_ldr_pc:
|
19231 |
|
|
case T_MNEM_ldr_sp:
|
19232 |
|
|
case T_MNEM_str_sp:
|
19233 |
|
|
newsize = relax_immediate (fragp, 8, 2);
|
19234 |
|
|
break;
|
19235 |
|
|
case T_MNEM_ldr:
|
19236 |
|
|
case T_MNEM_str:
|
19237 |
|
|
newsize = relax_immediate (fragp, 5, 2);
|
19238 |
|
|
break;
|
19239 |
|
|
case T_MNEM_ldrh:
|
19240 |
|
|
case T_MNEM_strh:
|
19241 |
|
|
newsize = relax_immediate (fragp, 5, 1);
|
19242 |
|
|
break;
|
19243 |
|
|
case T_MNEM_ldrb:
|
19244 |
|
|
case T_MNEM_strb:
|
19245 |
|
|
newsize = relax_immediate (fragp, 5, 0);
|
19246 |
|
|
break;
|
19247 |
|
|
case T_MNEM_adr:
|
19248 |
|
|
newsize = relax_adr (fragp, sec, stretch);
|
19249 |
|
|
break;
|
19250 |
|
|
case T_MNEM_mov:
|
19251 |
|
|
case T_MNEM_movs:
|
19252 |
|
|
case T_MNEM_cmp:
|
19253 |
|
|
case T_MNEM_cmn:
|
19254 |
|
|
newsize = relax_immediate (fragp, 8, 0);
|
19255 |
|
|
break;
|
19256 |
|
|
case T_MNEM_b:
|
19257 |
|
|
newsize = relax_branch (fragp, sec, 11, stretch);
|
19258 |
|
|
break;
|
19259 |
|
|
case T_MNEM_bcond:
|
19260 |
|
|
newsize = relax_branch (fragp, sec, 8, stretch);
|
19261 |
|
|
break;
|
19262 |
|
|
case T_MNEM_add_sp:
|
19263 |
|
|
case T_MNEM_add_pc:
|
19264 |
|
|
newsize = relax_immediate (fragp, 8, 2);
|
19265 |
|
|
break;
|
19266 |
|
|
case T_MNEM_inc_sp:
|
19267 |
|
|
case T_MNEM_dec_sp:
|
19268 |
|
|
newsize = relax_immediate (fragp, 7, 2);
|
19269 |
|
|
break;
|
19270 |
|
|
case T_MNEM_addi:
|
19271 |
|
|
case T_MNEM_addis:
|
19272 |
|
|
case T_MNEM_subi:
|
19273 |
|
|
case T_MNEM_subis:
|
19274 |
|
|
newsize = relax_addsub (fragp, sec);
|
19275 |
|
|
break;
|
19276 |
|
|
default:
|
19277 |
|
|
abort ();
|
19278 |
|
|
}
|
19279 |
|
|
|
19280 |
|
|
fragp->fr_var = newsize;
|
19281 |
|
|
/* Freeze wide instructions that are at or before the same location as
|
19282 |
|
|
in the previous pass. This avoids infinite loops.
|
19283 |
|
|
Don't freeze them unconditionally because targets may be artificially
|
19284 |
|
|
misaligned by the expansion of preceding frags. */
|
19285 |
|
|
if (stretch <= 0 && newsize > 2)
|
19286 |
|
|
{
|
19287 |
|
|
md_convert_frag (sec->owner, sec, fragp);
|
19288 |
|
|
frag_wane (fragp);
|
19289 |
|
|
}
|
19290 |
|
|
|
19291 |
|
|
return newsize - oldsize;
|
19292 |
|
|
}
|
19293 |
|
|
|
19294 |
|
|
/* Round up a section size to the appropriate boundary. */
|
19295 |
|
|
|
19296 |
|
|
valueT
|
19297 |
|
|
md_section_align (segT segment ATTRIBUTE_UNUSED,
|
19298 |
|
|
valueT size)
|
19299 |
|
|
{
|
19300 |
|
|
#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
|
19301 |
|
|
if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
|
19302 |
|
|
{
|
19303 |
|
|
/* For a.out, force the section size to be aligned. If we don't do
|
19304 |
|
|
this, BFD will align it for us, but it will not write out the
|
19305 |
|
|
final bytes of the section. This may be a bug in BFD, but it is
|
19306 |
|
|
easier to fix it here since that is how the other a.out targets
|
19307 |
|
|
work. */
|
19308 |
|
|
int align;
|
19309 |
|
|
|
19310 |
|
|
align = bfd_get_section_alignment (stdoutput, segment);
|
19311 |
|
|
size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
|
19312 |
|
|
}
|
19313 |
|
|
#endif
|
19314 |
|
|
|
19315 |
|
|
return size;
|
19316 |
|
|
}
|
19317 |
|
|
|
19318 |
|
|
/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
|
19319 |
|
|
of an rs_align_code fragment. */
|
19320 |
|
|
|
19321 |
|
|
void
|
19322 |
|
|
arm_handle_align (fragS * fragP)
|
19323 |
|
|
{
|
19324 |
|
|
static char const arm_noop[2][2][4] =
|
19325 |
|
|
{
|
19326 |
|
|
{ /* ARMv1 */
|
19327 |
|
|
{0x00, 0x00, 0xa0, 0xe1}, /* LE */
|
19328 |
|
|
{0xe1, 0xa0, 0x00, 0x00}, /* BE */
|
19329 |
|
|
},
|
19330 |
|
|
{ /* ARMv6k */
|
19331 |
|
|
{0x00, 0xf0, 0x20, 0xe3}, /* LE */
|
19332 |
|
|
{0xe3, 0x20, 0xf0, 0x00}, /* BE */
|
19333 |
|
|
},
|
19334 |
|
|
};
|
19335 |
|
|
static char const thumb_noop[2][2][2] =
|
19336 |
|
|
{
|
19337 |
|
|
{ /* Thumb-1 */
|
19338 |
|
|
{0xc0, 0x46}, /* LE */
|
19339 |
|
|
{0x46, 0xc0}, /* BE */
|
19340 |
|
|
},
|
19341 |
|
|
{ /* Thumb-2 */
|
19342 |
|
|
{0x00, 0xbf}, /* LE */
|
19343 |
|
|
{0xbf, 0x00} /* BE */
|
19344 |
|
|
}
|
19345 |
|
|
};
|
19346 |
|
|
static char const wide_thumb_noop[2][4] =
|
19347 |
|
|
{ /* Wide Thumb-2 */
|
19348 |
|
|
{0xaf, 0xf3, 0x00, 0x80}, /* LE */
|
19349 |
|
|
{0xf3, 0xaf, 0x80, 0x00}, /* BE */
|
19350 |
|
|
};
|
19351 |
|
|
|
19352 |
|
|
unsigned bytes, fix, noop_size;
|
19353 |
|
|
char * p;
|
19354 |
|
|
const char * noop;
|
19355 |
|
|
const char *narrow_noop = NULL;
|
19356 |
|
|
#ifdef OBJ_ELF
|
19357 |
|
|
enum mstate state;
|
19358 |
|
|
#endif
|
19359 |
|
|
|
19360 |
|
|
if (fragP->fr_type != rs_align_code)
|
19361 |
|
|
return;
|
19362 |
|
|
|
19363 |
|
|
bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
|
19364 |
|
|
p = fragP->fr_literal + fragP->fr_fix;
|
19365 |
|
|
fix = 0;
|
19366 |
|
|
|
19367 |
|
|
if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
|
19368 |
|
|
bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
|
19369 |
|
|
|
19370 |
|
|
gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
|
19371 |
|
|
|
19372 |
|
|
if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
|
19373 |
|
|
{
|
19374 |
|
|
if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
|
19375 |
|
|
{
|
19376 |
|
|
narrow_noop = thumb_noop[1][target_big_endian];
|
19377 |
|
|
noop = wide_thumb_noop[target_big_endian];
|
19378 |
|
|
}
|
19379 |
|
|
else
|
19380 |
|
|
noop = thumb_noop[0][target_big_endian];
|
19381 |
|
|
noop_size = 2;
|
19382 |
|
|
#ifdef OBJ_ELF
|
19383 |
|
|
state = MAP_THUMB;
|
19384 |
|
|
#endif
|
19385 |
|
|
}
|
19386 |
|
|
else
|
19387 |
|
|
{
|
19388 |
|
|
noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
|
19389 |
|
|
[target_big_endian];
|
19390 |
|
|
noop_size = 4;
|
19391 |
|
|
#ifdef OBJ_ELF
|
19392 |
|
|
state = MAP_ARM;
|
19393 |
|
|
#endif
|
19394 |
|
|
}
|
19395 |
|
|
|
19396 |
|
|
fragP->fr_var = noop_size;
|
19397 |
|
|
|
19398 |
|
|
if (bytes & (noop_size - 1))
|
19399 |
|
|
{
|
19400 |
|
|
fix = bytes & (noop_size - 1);
|
19401 |
|
|
#ifdef OBJ_ELF
|
19402 |
|
|
insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
|
19403 |
|
|
#endif
|
19404 |
|
|
memset (p, 0, fix);
|
19405 |
|
|
p += fix;
|
19406 |
|
|
bytes -= fix;
|
19407 |
|
|
}
|
19408 |
|
|
|
19409 |
|
|
if (narrow_noop)
|
19410 |
|
|
{
|
19411 |
|
|
if (bytes & noop_size)
|
19412 |
|
|
{
|
19413 |
|
|
/* Insert a narrow noop. */
|
19414 |
|
|
memcpy (p, narrow_noop, noop_size);
|
19415 |
|
|
p += noop_size;
|
19416 |
|
|
bytes -= noop_size;
|
19417 |
|
|
fix += noop_size;
|
19418 |
|
|
}
|
19419 |
|
|
|
19420 |
|
|
/* Use wide noops for the remainder */
|
19421 |
|
|
noop_size = 4;
|
19422 |
|
|
}
|
19423 |
|
|
|
19424 |
|
|
while (bytes >= noop_size)
|
19425 |
|
|
{
|
19426 |
|
|
memcpy (p, noop, noop_size);
|
19427 |
|
|
p += noop_size;
|
19428 |
|
|
bytes -= noop_size;
|
19429 |
|
|
fix += noop_size;
|
19430 |
|
|
}
|
19431 |
|
|
|
19432 |
|
|
fragP->fr_fix += fix;
|
19433 |
|
|
}
|
19434 |
|
|
|
19435 |
|
|
/* Called from md_do_align. Used to create an alignment
|
19436 |
|
|
frag in a code section. */
|
19437 |
|
|
|
19438 |
|
|
void
|
19439 |
|
|
arm_frag_align_code (int n, int max)
|
19440 |
|
|
{
|
19441 |
|
|
char * p;
|
19442 |
|
|
|
19443 |
|
|
/* We assume that there will never be a requirement
|
19444 |
|
|
to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
|
19445 |
|
|
if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
|
19446 |
|
|
{
|
19447 |
|
|
char err_msg[128];
|
19448 |
|
|
|
19449 |
|
|
sprintf (err_msg,
|
19450 |
|
|
_("alignments greater than %d bytes not supported in .text sections."),
|
19451 |
|
|
MAX_MEM_FOR_RS_ALIGN_CODE + 1);
|
19452 |
|
|
as_fatal ("%s", err_msg);
|
19453 |
|
|
}
|
19454 |
|
|
|
19455 |
|
|
p = frag_var (rs_align_code,
|
19456 |
|
|
MAX_MEM_FOR_RS_ALIGN_CODE,
|
19457 |
|
|
1,
|
19458 |
|
|
(relax_substateT) max,
|
19459 |
|
|
(symbolS *) NULL,
|
19460 |
|
|
(offsetT) n,
|
19461 |
|
|
(char *) NULL);
|
19462 |
|
|
*p = 0;
|
19463 |
|
|
}
|
19464 |
|
|
|
19465 |
|
|
/* Perform target specific initialisation of a frag.
|
19466 |
|
|
Note - despite the name this initialisation is not done when the frag
|
19467 |
|
|
is created, but only when its type is assigned. A frag can be created
|
19468 |
|
|
and used a long time before its type is set, so beware of assuming that
|
19469 |
|
|
this initialisationis performed first. */
|
19470 |
|
|
|
19471 |
|
|
#ifndef OBJ_ELF
|
19472 |
|
|
void
|
19473 |
|
|
arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
|
19474 |
|
|
{
|
19475 |
|
|
/* Record whether this frag is in an ARM or a THUMB area. */
|
19476 |
|
|
fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
|
19477 |
|
|
}
|
19478 |
|
|
|
19479 |
|
|
#else /* OBJ_ELF is defined. */
|
19480 |
|
|
void
|
19481 |
|
|
arm_init_frag (fragS * fragP, int max_chars)
|
19482 |
|
|
{
|
19483 |
|
|
/* If the current ARM vs THUMB mode has not already
|
19484 |
|
|
been recorded into this frag then do so now. */
|
19485 |
|
|
if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
|
19486 |
|
|
{
|
19487 |
|
|
fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
|
19488 |
|
|
|
19489 |
|
|
/* Record a mapping symbol for alignment frags. We will delete this
|
19490 |
|
|
later if the alignment ends up empty. */
|
19491 |
|
|
switch (fragP->fr_type)
|
19492 |
|
|
{
|
19493 |
|
|
case rs_align:
|
19494 |
|
|
case rs_align_test:
|
19495 |
|
|
case rs_fill:
|
19496 |
|
|
mapping_state_2 (MAP_DATA, max_chars);
|
19497 |
|
|
break;
|
19498 |
|
|
case rs_align_code:
|
19499 |
|
|
mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
|
19500 |
|
|
break;
|
19501 |
|
|
default:
|
19502 |
|
|
break;
|
19503 |
|
|
}
|
19504 |
|
|
}
|
19505 |
|
|
}
|
19506 |
|
|
|
19507 |
|
|
/* When we change sections we need to issue a new mapping symbol. */
|
19508 |
|
|
|
19509 |
|
|
void
|
19510 |
|
|
arm_elf_change_section (void)
|
19511 |
|
|
{
|
19512 |
|
|
/* Link an unlinked unwind index table section to the .text section. */
|
19513 |
|
|
if (elf_section_type (now_seg) == SHT_ARM_EXIDX
|
19514 |
|
|
&& elf_linked_to_section (now_seg) == NULL)
|
19515 |
|
|
elf_linked_to_section (now_seg) = text_section;
|
19516 |
|
|
}
|
19517 |
|
|
|
19518 |
|
|
int
|
19519 |
|
|
arm_elf_section_type (const char * str, size_t len)
|
19520 |
|
|
{
|
19521 |
|
|
if (len == 5 && strncmp (str, "exidx", 5) == 0)
|
19522 |
|
|
return SHT_ARM_EXIDX;
|
19523 |
|
|
|
19524 |
|
|
return -1;
|
19525 |
|
|
}
|
19526 |
|
|
|
19527 |
|
|
/* Code to deal with unwinding tables. */
|
19528 |
|
|
|
19529 |
|
|
static void add_unwind_adjustsp (offsetT);
|
19530 |
|
|
|
19531 |
|
|
/* Generate any deferred unwind frame offset. */
|
19532 |
|
|
|
19533 |
|
|
static void
|
19534 |
|
|
flush_pending_unwind (void)
|
19535 |
|
|
{
|
19536 |
|
|
offsetT offset;
|
19537 |
|
|
|
19538 |
|
|
offset = unwind.pending_offset;
|
19539 |
|
|
unwind.pending_offset = 0;
|
19540 |
|
|
if (offset != 0)
|
19541 |
|
|
add_unwind_adjustsp (offset);
|
19542 |
|
|
}
|
19543 |
|
|
|
19544 |
|
|
/* Add an opcode to this list for this function. Two-byte opcodes should
|
19545 |
|
|
be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
|
19546 |
|
|
order. */
|
19547 |
|
|
|
19548 |
|
|
static void
|
19549 |
|
|
add_unwind_opcode (valueT op, int length)
|
19550 |
|
|
{
|
19551 |
|
|
/* Add any deferred stack adjustment. */
|
19552 |
|
|
if (unwind.pending_offset)
|
19553 |
|
|
flush_pending_unwind ();
|
19554 |
|
|
|
19555 |
|
|
unwind.sp_restored = 0;
|
19556 |
|
|
|
19557 |
|
|
if (unwind.opcode_count + length > unwind.opcode_alloc)
|
19558 |
|
|
{
|
19559 |
|
|
unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
|
19560 |
|
|
if (unwind.opcodes)
|
19561 |
|
|
unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
|
19562 |
|
|
unwind.opcode_alloc);
|
19563 |
|
|
else
|
19564 |
|
|
unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
|
19565 |
|
|
}
|
19566 |
|
|
while (length > 0)
|
19567 |
|
|
{
|
19568 |
|
|
length--;
|
19569 |
|
|
unwind.opcodes[unwind.opcode_count] = op & 0xff;
|
19570 |
|
|
op >>= 8;
|
19571 |
|
|
unwind.opcode_count++;
|
19572 |
|
|
}
|
19573 |
|
|
}
|
19574 |
|
|
|
19575 |
|
|
/* Add unwind opcodes to adjust the stack pointer. */
|
19576 |
|
|
|
19577 |
|
|
static void
|
19578 |
|
|
add_unwind_adjustsp (offsetT offset)
|
19579 |
|
|
{
|
19580 |
|
|
valueT op;
|
19581 |
|
|
|
19582 |
|
|
if (offset > 0x200)
|
19583 |
|
|
{
|
19584 |
|
|
/* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
|
19585 |
|
|
char bytes[5];
|
19586 |
|
|
int n;
|
19587 |
|
|
valueT o;
|
19588 |
|
|
|
19589 |
|
|
/* Long form: 0xb2, uleb128. */
|
19590 |
|
|
/* This might not fit in a word so add the individual bytes,
|
19591 |
|
|
remembering the list is built in reverse order. */
|
19592 |
|
|
o = (valueT) ((offset - 0x204) >> 2);
|
19593 |
|
|
if (o == 0)
|
19594 |
|
|
add_unwind_opcode (0, 1);
|
19595 |
|
|
|
19596 |
|
|
/* Calculate the uleb128 encoding of the offset. */
|
19597 |
|
|
n = 0;
|
19598 |
|
|
while (o)
|
19599 |
|
|
{
|
19600 |
|
|
bytes[n] = o & 0x7f;
|
19601 |
|
|
o >>= 7;
|
19602 |
|
|
if (o)
|
19603 |
|
|
bytes[n] |= 0x80;
|
19604 |
|
|
n++;
|
19605 |
|
|
}
|
19606 |
|
|
/* Add the insn. */
|
19607 |
|
|
for (; n; n--)
|
19608 |
|
|
add_unwind_opcode (bytes[n - 1], 1);
|
19609 |
|
|
add_unwind_opcode (0xb2, 1);
|
19610 |
|
|
}
|
19611 |
|
|
else if (offset > 0x100)
|
19612 |
|
|
{
|
19613 |
|
|
/* Two short opcodes. */
|
19614 |
|
|
add_unwind_opcode (0x3f, 1);
|
19615 |
|
|
op = (offset - 0x104) >> 2;
|
19616 |
|
|
add_unwind_opcode (op, 1);
|
19617 |
|
|
}
|
19618 |
|
|
else if (offset > 0)
|
19619 |
|
|
{
|
19620 |
|
|
/* Short opcode. */
|
19621 |
|
|
op = (offset - 4) >> 2;
|
19622 |
|
|
add_unwind_opcode (op, 1);
|
19623 |
|
|
}
|
19624 |
|
|
else if (offset < 0)
|
19625 |
|
|
{
|
19626 |
|
|
offset = -offset;
|
19627 |
|
|
while (offset > 0x100)
|
19628 |
|
|
{
|
19629 |
|
|
add_unwind_opcode (0x7f, 1);
|
19630 |
|
|
offset -= 0x100;
|
19631 |
|
|
}
|
19632 |
|
|
op = ((offset - 4) >> 2) | 0x40;
|
19633 |
|
|
add_unwind_opcode (op, 1);
|
19634 |
|
|
}
|
19635 |
|
|
}
|
19636 |
|
|
|
19637 |
|
|
/* Finish the list of unwind opcodes for this function. */
|
19638 |
|
|
static void
|
19639 |
|
|
finish_unwind_opcodes (void)
|
19640 |
|
|
{
|
19641 |
|
|
valueT op;
|
19642 |
|
|
|
19643 |
|
|
if (unwind.fp_used)
|
19644 |
|
|
{
|
19645 |
|
|
/* Adjust sp as necessary. */
|
19646 |
|
|
unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
|
19647 |
|
|
flush_pending_unwind ();
|
19648 |
|
|
|
19649 |
|
|
/* After restoring sp from the frame pointer. */
|
19650 |
|
|
op = 0x90 | unwind.fp_reg;
|
19651 |
|
|
add_unwind_opcode (op, 1);
|
19652 |
|
|
}
|
19653 |
|
|
else
|
19654 |
|
|
flush_pending_unwind ();
|
19655 |
|
|
}
|
19656 |
|
|
|
19657 |
|
|
|
19658 |
|
|
/* Start an exception table entry. If idx is nonzero this is an index table
|
19659 |
|
|
entry. */
|
19660 |
|
|
|
19661 |
|
|
static void
|
19662 |
|
|
start_unwind_section (const segT text_seg, int idx)
|
19663 |
|
|
{
|
19664 |
|
|
const char * text_name;
|
19665 |
|
|
const char * prefix;
|
19666 |
|
|
const char * prefix_once;
|
19667 |
|
|
const char * group_name;
|
19668 |
|
|
size_t prefix_len;
|
19669 |
|
|
size_t text_len;
|
19670 |
|
|
char * sec_name;
|
19671 |
|
|
size_t sec_name_len;
|
19672 |
|
|
int type;
|
19673 |
|
|
int flags;
|
19674 |
|
|
int linkonce;
|
19675 |
|
|
|
19676 |
|
|
if (idx)
|
19677 |
|
|
{
|
19678 |
|
|
prefix = ELF_STRING_ARM_unwind;
|
19679 |
|
|
prefix_once = ELF_STRING_ARM_unwind_once;
|
19680 |
|
|
type = SHT_ARM_EXIDX;
|
19681 |
|
|
}
|
19682 |
|
|
else
|
19683 |
|
|
{
|
19684 |
|
|
prefix = ELF_STRING_ARM_unwind_info;
|
19685 |
|
|
prefix_once = ELF_STRING_ARM_unwind_info_once;
|
19686 |
|
|
type = SHT_PROGBITS;
|
19687 |
|
|
}
|
19688 |
|
|
|
19689 |
|
|
text_name = segment_name (text_seg);
|
19690 |
|
|
if (streq (text_name, ".text"))
|
19691 |
|
|
text_name = "";
|
19692 |
|
|
|
19693 |
|
|
if (strncmp (text_name, ".gnu.linkonce.t.",
|
19694 |
|
|
strlen (".gnu.linkonce.t.")) == 0)
|
19695 |
|
|
{
|
19696 |
|
|
prefix = prefix_once;
|
19697 |
|
|
text_name += strlen (".gnu.linkonce.t.");
|
19698 |
|
|
}
|
19699 |
|
|
|
19700 |
|
|
prefix_len = strlen (prefix);
|
19701 |
|
|
text_len = strlen (text_name);
|
19702 |
|
|
sec_name_len = prefix_len + text_len;
|
19703 |
|
|
sec_name = (char *) xmalloc (sec_name_len + 1);
|
19704 |
|
|
memcpy (sec_name, prefix, prefix_len);
|
19705 |
|
|
memcpy (sec_name + prefix_len, text_name, text_len);
|
19706 |
|
|
sec_name[prefix_len + text_len] = '\0';
|
19707 |
|
|
|
19708 |
|
|
flags = SHF_ALLOC;
|
19709 |
|
|
linkonce = 0;
|
19710 |
|
|
group_name = 0;
|
19711 |
|
|
|
19712 |
|
|
/* Handle COMDAT group. */
|
19713 |
|
|
if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
|
19714 |
|
|
{
|
19715 |
|
|
group_name = elf_group_name (text_seg);
|
19716 |
|
|
if (group_name == NULL)
|
19717 |
|
|
{
|
19718 |
|
|
as_bad (_("Group section `%s' has no group signature"),
|
19719 |
|
|
segment_name (text_seg));
|
19720 |
|
|
ignore_rest_of_line ();
|
19721 |
|
|
return;
|
19722 |
|
|
}
|
19723 |
|
|
flags |= SHF_GROUP;
|
19724 |
|
|
linkonce = 1;
|
19725 |
|
|
}
|
19726 |
|
|
|
19727 |
|
|
obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
|
19728 |
|
|
|
19729 |
|
|
/* Set the section link for index tables. */
|
19730 |
|
|
if (idx)
|
19731 |
|
|
elf_linked_to_section (now_seg) = text_seg;
|
19732 |
|
|
}
|
19733 |
|
|
|
19734 |
|
|
|
19735 |
|
|
/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
|
19736 |
|
|
personality routine data. Returns zero, or the index table value for
|
19737 |
|
|
and inline entry. */
|
19738 |
|
|
|
19739 |
|
|
static valueT
|
19740 |
|
|
create_unwind_entry (int have_data)
|
19741 |
|
|
{
|
19742 |
|
|
int size;
|
19743 |
|
|
addressT where;
|
19744 |
|
|
char *ptr;
|
19745 |
|
|
/* The current word of data. */
|
19746 |
|
|
valueT data;
|
19747 |
|
|
/* The number of bytes left in this word. */
|
19748 |
|
|
int n;
|
19749 |
|
|
|
19750 |
|
|
finish_unwind_opcodes ();
|
19751 |
|
|
|
19752 |
|
|
/* Remember the current text section. */
|
19753 |
|
|
unwind.saved_seg = now_seg;
|
19754 |
|
|
unwind.saved_subseg = now_subseg;
|
19755 |
|
|
|
19756 |
|
|
start_unwind_section (now_seg, 0);
|
19757 |
|
|
|
19758 |
|
|
if (unwind.personality_routine == NULL)
|
19759 |
|
|
{
|
19760 |
|
|
if (unwind.personality_index == -2)
|
19761 |
|
|
{
|
19762 |
|
|
if (have_data)
|
19763 |
|
|
as_bad (_("handlerdata in cantunwind frame"));
|
19764 |
|
|
return 1; /* EXIDX_CANTUNWIND. */
|
19765 |
|
|
}
|
19766 |
|
|
|
19767 |
|
|
/* Use a default personality routine if none is specified. */
|
19768 |
|
|
if (unwind.personality_index == -1)
|
19769 |
|
|
{
|
19770 |
|
|
if (unwind.opcode_count > 3)
|
19771 |
|
|
unwind.personality_index = 1;
|
19772 |
|
|
else
|
19773 |
|
|
unwind.personality_index = 0;
|
19774 |
|
|
}
|
19775 |
|
|
|
19776 |
|
|
/* Space for the personality routine entry. */
|
19777 |
|
|
if (unwind.personality_index == 0)
|
19778 |
|
|
{
|
19779 |
|
|
if (unwind.opcode_count > 3)
|
19780 |
|
|
as_bad (_("too many unwind opcodes for personality routine 0"));
|
19781 |
|
|
|
19782 |
|
|
if (!have_data)
|
19783 |
|
|
{
|
19784 |
|
|
/* All the data is inline in the index table. */
|
19785 |
|
|
data = 0x80;
|
19786 |
|
|
n = 3;
|
19787 |
|
|
while (unwind.opcode_count > 0)
|
19788 |
|
|
{
|
19789 |
|
|
unwind.opcode_count--;
|
19790 |
|
|
data = (data << 8) | unwind.opcodes[unwind.opcode_count];
|
19791 |
|
|
n--;
|
19792 |
|
|
}
|
19793 |
|
|
|
19794 |
|
|
/* Pad with "finish" opcodes. */
|
19795 |
|
|
while (n--)
|
19796 |
|
|
data = (data << 8) | 0xb0;
|
19797 |
|
|
|
19798 |
|
|
return data;
|
19799 |
|
|
}
|
19800 |
|
|
size = 0;
|
19801 |
|
|
}
|
19802 |
|
|
else
|
19803 |
|
|
/* We get two opcodes "free" in the first word. */
|
19804 |
|
|
size = unwind.opcode_count - 2;
|
19805 |
|
|
}
|
19806 |
|
|
else
|
19807 |
|
|
/* An extra byte is required for the opcode count. */
|
19808 |
|
|
size = unwind.opcode_count + 1;
|
19809 |
|
|
|
19810 |
|
|
size = (size + 3) >> 2;
|
19811 |
|
|
if (size > 0xff)
|
19812 |
|
|
as_bad (_("too many unwind opcodes"));
|
19813 |
|
|
|
19814 |
|
|
frag_align (2, 0, 0);
|
19815 |
|
|
record_alignment (now_seg, 2);
|
19816 |
|
|
unwind.table_entry = expr_build_dot ();
|
19817 |
|
|
|
19818 |
|
|
/* Allocate the table entry. */
|
19819 |
|
|
ptr = frag_more ((size << 2) + 4);
|
19820 |
|
|
where = frag_now_fix () - ((size << 2) + 4);
|
19821 |
|
|
|
19822 |
|
|
switch (unwind.personality_index)
|
19823 |
|
|
{
|
19824 |
|
|
case -1:
|
19825 |
|
|
/* ??? Should this be a PLT generating relocation? */
|
19826 |
|
|
/* Custom personality routine. */
|
19827 |
|
|
fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
|
19828 |
|
|
BFD_RELOC_ARM_PREL31);
|
19829 |
|
|
|
19830 |
|
|
where += 4;
|
19831 |
|
|
ptr += 4;
|
19832 |
|
|
|
19833 |
|
|
/* Set the first byte to the number of additional words. */
|
19834 |
|
|
data = size - 1;
|
19835 |
|
|
n = 3;
|
19836 |
|
|
break;
|
19837 |
|
|
|
19838 |
|
|
/* ABI defined personality routines. */
|
19839 |
|
|
case 0:
|
19840 |
|
|
/* Three opcodes bytes are packed into the first word. */
|
19841 |
|
|
data = 0x80;
|
19842 |
|
|
n = 3;
|
19843 |
|
|
break;
|
19844 |
|
|
|
19845 |
|
|
case 1:
|
19846 |
|
|
case 2:
|
19847 |
|
|
/* The size and first two opcode bytes go in the first word. */
|
19848 |
|
|
data = ((0x80 + unwind.personality_index) << 8) | size;
|
19849 |
|
|
n = 2;
|
19850 |
|
|
break;
|
19851 |
|
|
|
19852 |
|
|
default:
|
19853 |
|
|
/* Should never happen. */
|
19854 |
|
|
abort ();
|
19855 |
|
|
}
|
19856 |
|
|
|
19857 |
|
|
/* Pack the opcodes into words (MSB first), reversing the list at the same
|
19858 |
|
|
time. */
|
19859 |
|
|
while (unwind.opcode_count > 0)
|
19860 |
|
|
{
|
19861 |
|
|
if (n == 0)
|
19862 |
|
|
{
|
19863 |
|
|
md_number_to_chars (ptr, data, 4);
|
19864 |
|
|
ptr += 4;
|
19865 |
|
|
n = 4;
|
19866 |
|
|
data = 0;
|
19867 |
|
|
}
|
19868 |
|
|
unwind.opcode_count--;
|
19869 |
|
|
n--;
|
19870 |
|
|
data = (data << 8) | unwind.opcodes[unwind.opcode_count];
|
19871 |
|
|
}
|
19872 |
|
|
|
19873 |
|
|
/* Finish off the last word. */
|
19874 |
|
|
if (n < 4)
|
19875 |
|
|
{
|
19876 |
|
|
/* Pad with "finish" opcodes. */
|
19877 |
|
|
while (n--)
|
19878 |
|
|
data = (data << 8) | 0xb0;
|
19879 |
|
|
|
19880 |
|
|
md_number_to_chars (ptr, data, 4);
|
19881 |
|
|
}
|
19882 |
|
|
|
19883 |
|
|
if (!have_data)
|
19884 |
|
|
{
|
19885 |
|
|
/* Add an empty descriptor if there is no user-specified data. */
|
19886 |
|
|
ptr = frag_more (4);
|
19887 |
|
|
md_number_to_chars (ptr, 0, 4);
|
19888 |
|
|
}
|
19889 |
|
|
|
19890 |
|
|
return 0;
|
19891 |
|
|
}
|
19892 |
|
|
|
19893 |
|
|
|
19894 |
|
|
/* Initialize the DWARF-2 unwind information for this procedure. */
|
19895 |
|
|
|
19896 |
|
|
void
|
19897 |
|
|
tc_arm_frame_initial_instructions (void)
|
19898 |
|
|
{
|
19899 |
|
|
cfi_add_CFA_def_cfa (REG_SP, 0);
|
19900 |
|
|
}
|
19901 |
|
|
#endif /* OBJ_ELF */
|
19902 |
|
|
|
19903 |
|
|
/* Convert REGNAME to a DWARF-2 register number. */
|
19904 |
|
|
|
19905 |
|
|
int
|
19906 |
|
|
tc_arm_regname_to_dw2regnum (char *regname)
|
19907 |
|
|
{
|
19908 |
|
|
int reg = arm_reg_parse (®name, REG_TYPE_RN);
|
19909 |
|
|
|
19910 |
|
|
if (reg == FAIL)
|
19911 |
|
|
return -1;
|
19912 |
|
|
|
19913 |
|
|
return reg;
|
19914 |
|
|
}
|
19915 |
|
|
|
19916 |
|
|
#ifdef TE_PE
|
19917 |
|
|
void
|
19918 |
|
|
tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
|
19919 |
|
|
{
|
19920 |
|
|
expressionS exp;
|
19921 |
|
|
|
19922 |
|
|
exp.X_op = O_secrel;
|
19923 |
|
|
exp.X_add_symbol = symbol;
|
19924 |
|
|
exp.X_add_number = 0;
|
19925 |
|
|
emit_expr (&exp, size);
|
19926 |
|
|
}
|
19927 |
|
|
#endif
|
19928 |
|
|
|
19929 |
|
|
/* MD interface: Symbol and relocation handling. */
|
19930 |
|
|
|
19931 |
|
|
/* Return the address within the segment that a PC-relative fixup is
|
19932 |
|
|
relative to. For ARM, PC-relative fixups applied to instructions
|
19933 |
|
|
are generally relative to the location of the fixup plus 8 bytes.
|
19934 |
|
|
Thumb branches are offset by 4, and Thumb loads relative to PC
|
19935 |
|
|
require special handling. */
|
19936 |
|
|
|
19937 |
|
|
long
|
19938 |
|
|
md_pcrel_from_section (fixS * fixP, segT seg)
|
19939 |
|
|
{
|
19940 |
|
|
offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
|
19941 |
|
|
|
19942 |
|
|
/* If this is pc-relative and we are going to emit a relocation
|
19943 |
|
|
then we just want to put out any pipeline compensation that the linker
|
19944 |
|
|
will need. Otherwise we want to use the calculated base.
|
19945 |
|
|
For WinCE we skip the bias for externals as well, since this
|
19946 |
|
|
is how the MS ARM-CE assembler behaves and we want to be compatible. */
|
19947 |
|
|
if (fixP->fx_pcrel
|
19948 |
|
|
&& ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
|
19949 |
|
|
|| (arm_force_relocation (fixP)
|
19950 |
|
|
#ifdef TE_WINCE
|
19951 |
|
|
&& !S_IS_EXTERNAL (fixP->fx_addsy)
|
19952 |
|
|
#endif
|
19953 |
|
|
)))
|
19954 |
|
|
base = 0;
|
19955 |
|
|
|
19956 |
|
|
|
19957 |
|
|
switch (fixP->fx_r_type)
|
19958 |
|
|
{
|
19959 |
|
|
/* PC relative addressing on the Thumb is slightly odd as the
|
19960 |
|
|
bottom two bits of the PC are forced to zero for the
|
19961 |
|
|
calculation. This happens *after* application of the
|
19962 |
|
|
pipeline offset. However, Thumb adrl already adjusts for
|
19963 |
|
|
this, so we need not do it again. */
|
19964 |
|
|
case BFD_RELOC_ARM_THUMB_ADD:
|
19965 |
|
|
return base & ~3;
|
19966 |
|
|
|
19967 |
|
|
case BFD_RELOC_ARM_THUMB_OFFSET:
|
19968 |
|
|
case BFD_RELOC_ARM_T32_OFFSET_IMM:
|
19969 |
|
|
case BFD_RELOC_ARM_T32_ADD_PC12:
|
19970 |
|
|
case BFD_RELOC_ARM_T32_CP_OFF_IMM:
|
19971 |
|
|
return (base + 4) & ~3;
|
19972 |
|
|
|
19973 |
|
|
/* Thumb branches are simply offset by +4. */
|
19974 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH7:
|
19975 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH9:
|
19976 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH12:
|
19977 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH20:
|
19978 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH25:
|
19979 |
|
|
return base + 4;
|
19980 |
|
|
|
19981 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH23:
|
19982 |
|
|
if (fixP->fx_addsy
|
19983 |
|
|
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
|
19984 |
|
|
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
|
19985 |
|
|
&& ARM_IS_FUNC (fixP->fx_addsy)
|
19986 |
|
|
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
|
19987 |
|
|
base = fixP->fx_where + fixP->fx_frag->fr_address;
|
19988 |
|
|
return base + 4;
|
19989 |
|
|
|
19990 |
|
|
/* BLX is like branches above, but forces the low two bits of PC to
|
19991 |
|
|
zero. */
|
19992 |
|
|
case BFD_RELOC_THUMB_PCREL_BLX:
|
19993 |
|
|
if (fixP->fx_addsy
|
19994 |
|
|
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
|
19995 |
|
|
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
|
19996 |
|
|
&& THUMB_IS_FUNC (fixP->fx_addsy)
|
19997 |
|
|
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
|
19998 |
|
|
base = fixP->fx_where + fixP->fx_frag->fr_address;
|
19999 |
|
|
return (base + 4) & ~3;
|
20000 |
|
|
|
20001 |
|
|
/* ARM mode branches are offset by +8. However, the Windows CE
|
20002 |
|
|
loader expects the relocation not to take this into account. */
|
20003 |
|
|
case BFD_RELOC_ARM_PCREL_BLX:
|
20004 |
|
|
if (fixP->fx_addsy
|
20005 |
|
|
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
|
20006 |
|
|
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
|
20007 |
|
|
&& ARM_IS_FUNC (fixP->fx_addsy)
|
20008 |
|
|
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
|
20009 |
|
|
base = fixP->fx_where + fixP->fx_frag->fr_address;
|
20010 |
|
|
return base + 8;
|
20011 |
|
|
|
20012 |
|
|
case BFD_RELOC_ARM_PCREL_CALL:
|
20013 |
|
|
if (fixP->fx_addsy
|
20014 |
|
|
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
|
20015 |
|
|
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
|
20016 |
|
|
&& THUMB_IS_FUNC (fixP->fx_addsy)
|
20017 |
|
|
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
|
20018 |
|
|
base = fixP->fx_where + fixP->fx_frag->fr_address;
|
20019 |
|
|
return base + 8;
|
20020 |
|
|
|
20021 |
|
|
case BFD_RELOC_ARM_PCREL_BRANCH:
|
20022 |
|
|
case BFD_RELOC_ARM_PCREL_JUMP:
|
20023 |
|
|
case BFD_RELOC_ARM_PLT32:
|
20024 |
|
|
#ifdef TE_WINCE
|
20025 |
|
|
/* When handling fixups immediately, because we have already
|
20026 |
|
|
discovered the value of a symbol, or the address of the frag involved
|
20027 |
|
|
we must account for the offset by +8, as the OS loader will never see the reloc.
|
20028 |
|
|
see fixup_segment() in write.c
|
20029 |
|
|
The S_IS_EXTERNAL test handles the case of global symbols.
|
20030 |
|
|
Those need the calculated base, not just the pipe compensation the linker will need. */
|
20031 |
|
|
if (fixP->fx_pcrel
|
20032 |
|
|
&& fixP->fx_addsy != NULL
|
20033 |
|
|
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
|
20034 |
|
|
&& (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
|
20035 |
|
|
return base + 8;
|
20036 |
|
|
return base;
|
20037 |
|
|
#else
|
20038 |
|
|
return base + 8;
|
20039 |
|
|
#endif
|
20040 |
|
|
|
20041 |
|
|
|
20042 |
|
|
/* ARM mode loads relative to PC are also offset by +8. Unlike
|
20043 |
|
|
branches, the Windows CE loader *does* expect the relocation
|
20044 |
|
|
to take this into account. */
|
20045 |
|
|
case BFD_RELOC_ARM_OFFSET_IMM:
|
20046 |
|
|
case BFD_RELOC_ARM_OFFSET_IMM8:
|
20047 |
|
|
case BFD_RELOC_ARM_HWLITERAL:
|
20048 |
|
|
case BFD_RELOC_ARM_LITERAL:
|
20049 |
|
|
case BFD_RELOC_ARM_CP_OFF_IMM:
|
20050 |
|
|
return base + 8;
|
20051 |
|
|
|
20052 |
|
|
|
20053 |
|
|
/* Other PC-relative relocations are un-offset. */
|
20054 |
|
|
default:
|
20055 |
|
|
return base;
|
20056 |
|
|
}
|
20057 |
|
|
}
|
20058 |
|
|
|
20059 |
|
|
/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
|
20060 |
|
|
Otherwise we have no need to default values of symbols. */
|
20061 |
|
|
|
20062 |
|
|
symbolS *
|
20063 |
|
|
md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
|
20064 |
|
|
{
|
20065 |
|
|
#ifdef OBJ_ELF
|
20066 |
|
|
if (name[0] == '_' && name[1] == 'G'
|
20067 |
|
|
&& streq (name, GLOBAL_OFFSET_TABLE_NAME))
|
20068 |
|
|
{
|
20069 |
|
|
if (!GOT_symbol)
|
20070 |
|
|
{
|
20071 |
|
|
if (symbol_find (name))
|
20072 |
|
|
as_bad (_("GOT already in the symbol table"));
|
20073 |
|
|
|
20074 |
|
|
GOT_symbol = symbol_new (name, undefined_section,
|
20075 |
|
|
(valueT) 0, & zero_address_frag);
|
20076 |
|
|
}
|
20077 |
|
|
|
20078 |
|
|
return GOT_symbol;
|
20079 |
|
|
}
|
20080 |
|
|
#endif
|
20081 |
|
|
|
20082 |
|
|
return NULL;
|
20083 |
|
|
}
|
20084 |
|
|
|
20085 |
|
|
/* Subroutine of md_apply_fix. Check to see if an immediate can be
|
20086 |
|
|
computed as two separate immediate values, added together. We
|
20087 |
|
|
already know that this value cannot be computed by just one ARM
|
20088 |
|
|
instruction. */
|
20089 |
|
|
|
20090 |
|
|
static unsigned int
|
20091 |
|
|
validate_immediate_twopart (unsigned int val,
|
20092 |
|
|
unsigned int * highpart)
|
20093 |
|
|
{
|
20094 |
|
|
unsigned int a;
|
20095 |
|
|
unsigned int i;
|
20096 |
|
|
|
20097 |
|
|
for (i = 0; i < 32; i += 2)
|
20098 |
|
|
if (((a = rotate_left (val, i)) & 0xff) != 0)
|
20099 |
|
|
{
|
20100 |
|
|
if (a & 0xff00)
|
20101 |
|
|
{
|
20102 |
|
|
if (a & ~ 0xffff)
|
20103 |
|
|
continue;
|
20104 |
|
|
* highpart = (a >> 8) | ((i + 24) << 7);
|
20105 |
|
|
}
|
20106 |
|
|
else if (a & 0xff0000)
|
20107 |
|
|
{
|
20108 |
|
|
if (a & 0xff000000)
|
20109 |
|
|
continue;
|
20110 |
|
|
* highpart = (a >> 16) | ((i + 16) << 7);
|
20111 |
|
|
}
|
20112 |
|
|
else
|
20113 |
|
|
{
|
20114 |
|
|
gas_assert (a & 0xff000000);
|
20115 |
|
|
* highpart = (a >> 24) | ((i + 8) << 7);
|
20116 |
|
|
}
|
20117 |
|
|
|
20118 |
|
|
return (a & 0xff) | (i << 7);
|
20119 |
|
|
}
|
20120 |
|
|
|
20121 |
|
|
return FAIL;
|
20122 |
|
|
}
|
20123 |
|
|
|
20124 |
|
|
static int
|
20125 |
|
|
validate_offset_imm (unsigned int val, int hwse)
|
20126 |
|
|
{
|
20127 |
|
|
if ((hwse && val > 255) || val > 4095)
|
20128 |
|
|
return FAIL;
|
20129 |
|
|
return val;
|
20130 |
|
|
}
|
20131 |
|
|
|
20132 |
|
|
/* Subroutine of md_apply_fix. Do those data_ops which can take a
|
20133 |
|
|
negative immediate constant by altering the instruction. A bit of
|
20134 |
|
|
a hack really.
|
20135 |
|
|
MOV <-> MVN
|
20136 |
|
|
AND <-> BIC
|
20137 |
|
|
ADC <-> SBC
|
20138 |
|
|
by inverting the second operand, and
|
20139 |
|
|
ADD <-> SUB
|
20140 |
|
|
CMP <-> CMN
|
20141 |
|
|
by negating the second operand. */
|
20142 |
|
|
|
20143 |
|
|
static int
|
20144 |
|
|
negate_data_op (unsigned long * instruction,
|
20145 |
|
|
unsigned long value)
|
20146 |
|
|
{
|
20147 |
|
|
int op, new_inst;
|
20148 |
|
|
unsigned long negated, inverted;
|
20149 |
|
|
|
20150 |
|
|
negated = encode_arm_immediate (-value);
|
20151 |
|
|
inverted = encode_arm_immediate (~value);
|
20152 |
|
|
|
20153 |
|
|
op = (*instruction >> DATA_OP_SHIFT) & 0xf;
|
20154 |
|
|
switch (op)
|
20155 |
|
|
{
|
20156 |
|
|
/* First negates. */
|
20157 |
|
|
case OPCODE_SUB: /* ADD <-> SUB */
|
20158 |
|
|
new_inst = OPCODE_ADD;
|
20159 |
|
|
value = negated;
|
20160 |
|
|
break;
|
20161 |
|
|
|
20162 |
|
|
case OPCODE_ADD:
|
20163 |
|
|
new_inst = OPCODE_SUB;
|
20164 |
|
|
value = negated;
|
20165 |
|
|
break;
|
20166 |
|
|
|
20167 |
|
|
case OPCODE_CMP: /* CMP <-> CMN */
|
20168 |
|
|
new_inst = OPCODE_CMN;
|
20169 |
|
|
value = negated;
|
20170 |
|
|
break;
|
20171 |
|
|
|
20172 |
|
|
case OPCODE_CMN:
|
20173 |
|
|
new_inst = OPCODE_CMP;
|
20174 |
|
|
value = negated;
|
20175 |
|
|
break;
|
20176 |
|
|
|
20177 |
|
|
/* Now Inverted ops. */
|
20178 |
|
|
case OPCODE_MOV: /* MOV <-> MVN */
|
20179 |
|
|
new_inst = OPCODE_MVN;
|
20180 |
|
|
value = inverted;
|
20181 |
|
|
break;
|
20182 |
|
|
|
20183 |
|
|
case OPCODE_MVN:
|
20184 |
|
|
new_inst = OPCODE_MOV;
|
20185 |
|
|
value = inverted;
|
20186 |
|
|
break;
|
20187 |
|
|
|
20188 |
|
|
case OPCODE_AND: /* AND <-> BIC */
|
20189 |
|
|
new_inst = OPCODE_BIC;
|
20190 |
|
|
value = inverted;
|
20191 |
|
|
break;
|
20192 |
|
|
|
20193 |
|
|
case OPCODE_BIC:
|
20194 |
|
|
new_inst = OPCODE_AND;
|
20195 |
|
|
value = inverted;
|
20196 |
|
|
break;
|
20197 |
|
|
|
20198 |
|
|
case OPCODE_ADC: /* ADC <-> SBC */
|
20199 |
|
|
new_inst = OPCODE_SBC;
|
20200 |
|
|
value = inverted;
|
20201 |
|
|
break;
|
20202 |
|
|
|
20203 |
|
|
case OPCODE_SBC:
|
20204 |
|
|
new_inst = OPCODE_ADC;
|
20205 |
|
|
value = inverted;
|
20206 |
|
|
break;
|
20207 |
|
|
|
20208 |
|
|
/* We cannot do anything. */
|
20209 |
|
|
default:
|
20210 |
|
|
return FAIL;
|
20211 |
|
|
}
|
20212 |
|
|
|
20213 |
|
|
if (value == (unsigned) FAIL)
|
20214 |
|
|
return FAIL;
|
20215 |
|
|
|
20216 |
|
|
*instruction &= OPCODE_MASK;
|
20217 |
|
|
*instruction |= new_inst << DATA_OP_SHIFT;
|
20218 |
|
|
return value;
|
20219 |
|
|
}
|
20220 |
|
|
|
20221 |
|
|
/* Like negate_data_op, but for Thumb-2. */
|
20222 |
|
|
|
20223 |
|
|
static unsigned int
|
20224 |
|
|
thumb32_negate_data_op (offsetT *instruction, unsigned int value)
|
20225 |
|
|
{
|
20226 |
|
|
int op, new_inst;
|
20227 |
|
|
int rd;
|
20228 |
|
|
unsigned int negated, inverted;
|
20229 |
|
|
|
20230 |
|
|
negated = encode_thumb32_immediate (-value);
|
20231 |
|
|
inverted = encode_thumb32_immediate (~value);
|
20232 |
|
|
|
20233 |
|
|
rd = (*instruction >> 8) & 0xf;
|
20234 |
|
|
op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
|
20235 |
|
|
switch (op)
|
20236 |
|
|
{
|
20237 |
|
|
/* ADD <-> SUB. Includes CMP <-> CMN. */
|
20238 |
|
|
case T2_OPCODE_SUB:
|
20239 |
|
|
new_inst = T2_OPCODE_ADD;
|
20240 |
|
|
value = negated;
|
20241 |
|
|
break;
|
20242 |
|
|
|
20243 |
|
|
case T2_OPCODE_ADD:
|
20244 |
|
|
new_inst = T2_OPCODE_SUB;
|
20245 |
|
|
value = negated;
|
20246 |
|
|
break;
|
20247 |
|
|
|
20248 |
|
|
/* ORR <-> ORN. Includes MOV <-> MVN. */
|
20249 |
|
|
case T2_OPCODE_ORR:
|
20250 |
|
|
new_inst = T2_OPCODE_ORN;
|
20251 |
|
|
value = inverted;
|
20252 |
|
|
break;
|
20253 |
|
|
|
20254 |
|
|
case T2_OPCODE_ORN:
|
20255 |
|
|
new_inst = T2_OPCODE_ORR;
|
20256 |
|
|
value = inverted;
|
20257 |
|
|
break;
|
20258 |
|
|
|
20259 |
|
|
/* AND <-> BIC. TST has no inverted equivalent. */
|
20260 |
|
|
case T2_OPCODE_AND:
|
20261 |
|
|
new_inst = T2_OPCODE_BIC;
|
20262 |
|
|
if (rd == 15)
|
20263 |
|
|
value = FAIL;
|
20264 |
|
|
else
|
20265 |
|
|
value = inverted;
|
20266 |
|
|
break;
|
20267 |
|
|
|
20268 |
|
|
case T2_OPCODE_BIC:
|
20269 |
|
|
new_inst = T2_OPCODE_AND;
|
20270 |
|
|
value = inverted;
|
20271 |
|
|
break;
|
20272 |
|
|
|
20273 |
|
|
/* ADC <-> SBC */
|
20274 |
|
|
case T2_OPCODE_ADC:
|
20275 |
|
|
new_inst = T2_OPCODE_SBC;
|
20276 |
|
|
value = inverted;
|
20277 |
|
|
break;
|
20278 |
|
|
|
20279 |
|
|
case T2_OPCODE_SBC:
|
20280 |
|
|
new_inst = T2_OPCODE_ADC;
|
20281 |
|
|
value = inverted;
|
20282 |
|
|
break;
|
20283 |
|
|
|
20284 |
|
|
/* We cannot do anything. */
|
20285 |
|
|
default:
|
20286 |
|
|
return FAIL;
|
20287 |
|
|
}
|
20288 |
|
|
|
20289 |
|
|
if (value == (unsigned int)FAIL)
|
20290 |
|
|
return FAIL;
|
20291 |
|
|
|
20292 |
|
|
*instruction &= T2_OPCODE_MASK;
|
20293 |
|
|
*instruction |= new_inst << T2_DATA_OP_SHIFT;
|
20294 |
|
|
return value;
|
20295 |
|
|
}
|
20296 |
|
|
|
20297 |
|
|
/* Read a 32-bit thumb instruction from buf. */
|
20298 |
|
|
static unsigned long
|
20299 |
|
|
get_thumb32_insn (char * buf)
|
20300 |
|
|
{
|
20301 |
|
|
unsigned long insn;
|
20302 |
|
|
insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
|
20303 |
|
|
insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
|
20304 |
|
|
|
20305 |
|
|
return insn;
|
20306 |
|
|
}
|
20307 |
|
|
|
20308 |
|
|
|
20309 |
|
|
/* We usually want to set the low bit on the address of thumb function
|
20310 |
|
|
symbols. In particular .word foo - . should have the low bit set.
|
20311 |
|
|
Generic code tries to fold the difference of two symbols to
|
20312 |
|
|
a constant. Prevent this and force a relocation when the first symbols
|
20313 |
|
|
is a thumb function. */
|
20314 |
|
|
|
20315 |
|
|
bfd_boolean
|
20316 |
|
|
arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
|
20317 |
|
|
{
|
20318 |
|
|
if (op == O_subtract
|
20319 |
|
|
&& l->X_op == O_symbol
|
20320 |
|
|
&& r->X_op == O_symbol
|
20321 |
|
|
&& THUMB_IS_FUNC (l->X_add_symbol))
|
20322 |
|
|
{
|
20323 |
|
|
l->X_op = O_subtract;
|
20324 |
|
|
l->X_op_symbol = r->X_add_symbol;
|
20325 |
|
|
l->X_add_number -= r->X_add_number;
|
20326 |
|
|
return TRUE;
|
20327 |
|
|
}
|
20328 |
|
|
|
20329 |
|
|
/* Process as normal. */
|
20330 |
|
|
return FALSE;
|
20331 |
|
|
}
|
20332 |
|
|
|
20333 |
|
|
/* Encode Thumb2 unconditional branches and calls. The encoding
|
20334 |
|
|
for the 2 are identical for the immediate values. */
|
20335 |
|
|
|
20336 |
|
|
static void
|
20337 |
|
|
encode_thumb2_b_bl_offset (char * buf, offsetT value)
|
20338 |
|
|
{
|
20339 |
|
|
#define T2I1I2MASK ((1 << 13) | (1 << 11))
|
20340 |
|
|
offsetT newval;
|
20341 |
|
|
offsetT newval2;
|
20342 |
|
|
addressT S, I1, I2, lo, hi;
|
20343 |
|
|
|
20344 |
|
|
S = (value >> 24) & 0x01;
|
20345 |
|
|
I1 = (value >> 23) & 0x01;
|
20346 |
|
|
I2 = (value >> 22) & 0x01;
|
20347 |
|
|
hi = (value >> 12) & 0x3ff;
|
20348 |
|
|
lo = (value >> 1) & 0x7ff;
|
20349 |
|
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
20350 |
|
|
newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
|
20351 |
|
|
newval |= (S << 10) | hi;
|
20352 |
|
|
newval2 &= ~T2I1I2MASK;
|
20353 |
|
|
newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
|
20354 |
|
|
md_number_to_chars (buf, newval, THUMB_SIZE);
|
20355 |
|
|
md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
|
20356 |
|
|
}
|
20357 |
|
|
|
20358 |
|
|
void
|
20359 |
|
|
md_apply_fix (fixS * fixP,
|
20360 |
|
|
valueT * valP,
|
20361 |
|
|
segT seg)
|
20362 |
|
|
{
|
20363 |
|
|
offsetT value = * valP;
|
20364 |
|
|
offsetT newval;
|
20365 |
|
|
unsigned int newimm;
|
20366 |
|
|
unsigned long temp;
|
20367 |
|
|
int sign;
|
20368 |
|
|
char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
|
20369 |
|
|
|
20370 |
|
|
gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
|
20371 |
|
|
|
20372 |
|
|
/* Note whether this will delete the relocation. */
|
20373 |
|
|
|
20374 |
|
|
if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
|
20375 |
|
|
fixP->fx_done = 1;
|
20376 |
|
|
|
20377 |
|
|
/* On a 64-bit host, silently truncate 'value' to 32 bits for
|
20378 |
|
|
consistency with the behaviour on 32-bit hosts. Remember value
|
20379 |
|
|
for emit_reloc. */
|
20380 |
|
|
value &= 0xffffffff;
|
20381 |
|
|
value ^= 0x80000000;
|
20382 |
|
|
value -= 0x80000000;
|
20383 |
|
|
|
20384 |
|
|
*valP = value;
|
20385 |
|
|
fixP->fx_addnumber = value;
|
20386 |
|
|
|
20387 |
|
|
/* Same treatment for fixP->fx_offset. */
|
20388 |
|
|
fixP->fx_offset &= 0xffffffff;
|
20389 |
|
|
fixP->fx_offset ^= 0x80000000;
|
20390 |
|
|
fixP->fx_offset -= 0x80000000;
|
20391 |
|
|
|
20392 |
|
|
switch (fixP->fx_r_type)
|
20393 |
|
|
{
|
20394 |
|
|
case BFD_RELOC_NONE:
|
20395 |
|
|
/* This will need to go in the object file. */
|
20396 |
|
|
fixP->fx_done = 0;
|
20397 |
|
|
break;
|
20398 |
|
|
|
20399 |
|
|
case BFD_RELOC_ARM_IMMEDIATE:
|
20400 |
|
|
/* We claim that this fixup has been processed here,
|
20401 |
|
|
even if in fact we generate an error because we do
|
20402 |
|
|
not have a reloc for it, so tc_gen_reloc will reject it. */
|
20403 |
|
|
fixP->fx_done = 1;
|
20404 |
|
|
|
20405 |
|
|
if (fixP->fx_addsy)
|
20406 |
|
|
{
|
20407 |
|
|
const char *msg = 0;
|
20408 |
|
|
|
20409 |
|
|
if (! S_IS_DEFINED (fixP->fx_addsy))
|
20410 |
|
|
msg = _("undefined symbol %s used as an immediate value");
|
20411 |
|
|
else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
|
20412 |
|
|
msg = _("symbol %s is in a different section");
|
20413 |
|
|
else if (S_IS_WEAK (fixP->fx_addsy))
|
20414 |
|
|
msg = _("symbol %s is weak and may be overridden later");
|
20415 |
|
|
|
20416 |
|
|
if (msg)
|
20417 |
|
|
{
|
20418 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20419 |
|
|
msg, S_GET_NAME (fixP->fx_addsy));
|
20420 |
|
|
break;
|
20421 |
|
|
}
|
20422 |
|
|
}
|
20423 |
|
|
|
20424 |
|
|
newimm = encode_arm_immediate (value);
|
20425 |
|
|
temp = md_chars_to_number (buf, INSN_SIZE);
|
20426 |
|
|
|
20427 |
|
|
/* If the instruction will fail, see if we can fix things up by
|
20428 |
|
|
changing the opcode. */
|
20429 |
|
|
if (newimm == (unsigned int) FAIL
|
20430 |
|
|
&& (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
|
20431 |
|
|
{
|
20432 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20433 |
|
|
_("invalid constant (%lx) after fixup"),
|
20434 |
|
|
(unsigned long) value);
|
20435 |
|
|
break;
|
20436 |
|
|
}
|
20437 |
|
|
|
20438 |
|
|
newimm |= (temp & 0xfffff000);
|
20439 |
|
|
md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
|
20440 |
|
|
break;
|
20441 |
|
|
|
20442 |
|
|
case BFD_RELOC_ARM_ADRL_IMMEDIATE:
|
20443 |
|
|
{
|
20444 |
|
|
unsigned int highpart = 0;
|
20445 |
|
|
unsigned int newinsn = 0xe1a00000; /* nop. */
|
20446 |
|
|
|
20447 |
|
|
if (fixP->fx_addsy)
|
20448 |
|
|
{
|
20449 |
|
|
const char *msg = 0;
|
20450 |
|
|
|
20451 |
|
|
if (! S_IS_DEFINED (fixP->fx_addsy))
|
20452 |
|
|
msg = _("undefined symbol %s used as an immediate value");
|
20453 |
|
|
else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
|
20454 |
|
|
msg = _("symbol %s is in a different section");
|
20455 |
|
|
else if (S_IS_WEAK (fixP->fx_addsy))
|
20456 |
|
|
msg = _("symbol %s is weak and may be overridden later");
|
20457 |
|
|
|
20458 |
|
|
if (msg)
|
20459 |
|
|
{
|
20460 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20461 |
|
|
msg, S_GET_NAME (fixP->fx_addsy));
|
20462 |
|
|
break;
|
20463 |
|
|
}
|
20464 |
|
|
}
|
20465 |
|
|
|
20466 |
|
|
newimm = encode_arm_immediate (value);
|
20467 |
|
|
temp = md_chars_to_number (buf, INSN_SIZE);
|
20468 |
|
|
|
20469 |
|
|
/* If the instruction will fail, see if we can fix things up by
|
20470 |
|
|
changing the opcode. */
|
20471 |
|
|
if (newimm == (unsigned int) FAIL
|
20472 |
|
|
&& (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
|
20473 |
|
|
{
|
20474 |
|
|
/* No ? OK - try using two ADD instructions to generate
|
20475 |
|
|
the value. */
|
20476 |
|
|
newimm = validate_immediate_twopart (value, & highpart);
|
20477 |
|
|
|
20478 |
|
|
/* Yes - then make sure that the second instruction is
|
20479 |
|
|
also an add. */
|
20480 |
|
|
if (newimm != (unsigned int) FAIL)
|
20481 |
|
|
newinsn = temp;
|
20482 |
|
|
/* Still No ? Try using a negated value. */
|
20483 |
|
|
else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
|
20484 |
|
|
temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
|
20485 |
|
|
/* Otherwise - give up. */
|
20486 |
|
|
else
|
20487 |
|
|
{
|
20488 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20489 |
|
|
_("unable to compute ADRL instructions for PC offset of 0x%lx"),
|
20490 |
|
|
(long) value);
|
20491 |
|
|
break;
|
20492 |
|
|
}
|
20493 |
|
|
|
20494 |
|
|
/* Replace the first operand in the 2nd instruction (which
|
20495 |
|
|
is the PC) with the destination register. We have
|
20496 |
|
|
already added in the PC in the first instruction and we
|
20497 |
|
|
do not want to do it again. */
|
20498 |
|
|
newinsn &= ~ 0xf0000;
|
20499 |
|
|
newinsn |= ((newinsn & 0x0f000) << 4);
|
20500 |
|
|
}
|
20501 |
|
|
|
20502 |
|
|
newimm |= (temp & 0xfffff000);
|
20503 |
|
|
md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
|
20504 |
|
|
|
20505 |
|
|
highpart |= (newinsn & 0xfffff000);
|
20506 |
|
|
md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
|
20507 |
|
|
}
|
20508 |
|
|
break;
|
20509 |
|
|
|
20510 |
|
|
case BFD_RELOC_ARM_OFFSET_IMM:
|
20511 |
|
|
if (!fixP->fx_done && seg->use_rela_p)
|
20512 |
|
|
value = 0;
|
20513 |
|
|
|
20514 |
|
|
case BFD_RELOC_ARM_LITERAL:
|
20515 |
|
|
sign = value > 0;
|
20516 |
|
|
|
20517 |
|
|
if (value < 0)
|
20518 |
|
|
value = - value;
|
20519 |
|
|
|
20520 |
|
|
if (validate_offset_imm (value, 0) == FAIL)
|
20521 |
|
|
{
|
20522 |
|
|
if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
|
20523 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20524 |
|
|
_("invalid literal constant: pool needs to be closer"));
|
20525 |
|
|
else
|
20526 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20527 |
|
|
_("bad immediate value for offset (%ld)"),
|
20528 |
|
|
(long) value);
|
20529 |
|
|
break;
|
20530 |
|
|
}
|
20531 |
|
|
|
20532 |
|
|
newval = md_chars_to_number (buf, INSN_SIZE);
|
20533 |
|
|
if (value == 0)
|
20534 |
|
|
newval &= 0xfffff000;
|
20535 |
|
|
else
|
20536 |
|
|
{
|
20537 |
|
|
newval &= 0xff7ff000;
|
20538 |
|
|
newval |= value | (sign ? INDEX_UP : 0);
|
20539 |
|
|
}
|
20540 |
|
|
md_number_to_chars (buf, newval, INSN_SIZE);
|
20541 |
|
|
break;
|
20542 |
|
|
|
20543 |
|
|
case BFD_RELOC_ARM_OFFSET_IMM8:
|
20544 |
|
|
case BFD_RELOC_ARM_HWLITERAL:
|
20545 |
|
|
sign = value > 0;
|
20546 |
|
|
|
20547 |
|
|
if (value < 0)
|
20548 |
|
|
value = - value;
|
20549 |
|
|
|
20550 |
|
|
if (validate_offset_imm (value, 1) == FAIL)
|
20551 |
|
|
{
|
20552 |
|
|
if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
|
20553 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20554 |
|
|
_("invalid literal constant: pool needs to be closer"));
|
20555 |
|
|
else
|
20556 |
|
|
as_bad (_("bad immediate value for 8-bit offset (%ld)"),
|
20557 |
|
|
(long) value);
|
20558 |
|
|
break;
|
20559 |
|
|
}
|
20560 |
|
|
|
20561 |
|
|
newval = md_chars_to_number (buf, INSN_SIZE);
|
20562 |
|
|
if (value == 0)
|
20563 |
|
|
newval &= 0xfffff0f0;
|
20564 |
|
|
else
|
20565 |
|
|
{
|
20566 |
|
|
newval &= 0xff7ff0f0;
|
20567 |
|
|
newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
|
20568 |
|
|
}
|
20569 |
|
|
md_number_to_chars (buf, newval, INSN_SIZE);
|
20570 |
|
|
break;
|
20571 |
|
|
|
20572 |
|
|
case BFD_RELOC_ARM_T32_OFFSET_U8:
|
20573 |
|
|
if (value < 0 || value > 1020 || value % 4 != 0)
|
20574 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20575 |
|
|
_("bad immediate value for offset (%ld)"), (long) value);
|
20576 |
|
|
value /= 4;
|
20577 |
|
|
|
20578 |
|
|
newval = md_chars_to_number (buf+2, THUMB_SIZE);
|
20579 |
|
|
newval |= value;
|
20580 |
|
|
md_number_to_chars (buf+2, newval, THUMB_SIZE);
|
20581 |
|
|
break;
|
20582 |
|
|
|
20583 |
|
|
case BFD_RELOC_ARM_T32_OFFSET_IMM:
|
20584 |
|
|
/* This is a complicated relocation used for all varieties of Thumb32
|
20585 |
|
|
load/store instruction with immediate offset:
|
20586 |
|
|
|
20587 |
|
|
1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
|
20588 |
|
|
*4, optional writeback(W)
|
20589 |
|
|
(doubleword load/store)
|
20590 |
|
|
|
20591 |
|
|
1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
|
20592 |
|
|
1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
|
20593 |
|
|
1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
|
20594 |
|
|
1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
|
20595 |
|
|
1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
|
20596 |
|
|
|
20597 |
|
|
Uppercase letters indicate bits that are already encoded at
|
20598 |
|
|
this point. Lowercase letters are our problem. For the
|
20599 |
|
|
second block of instructions, the secondary opcode nybble
|
20600 |
|
|
(bits 8..11) is present, and bit 23 is zero, even if this is
|
20601 |
|
|
a PC-relative operation. */
|
20602 |
|
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
20603 |
|
|
newval <<= 16;
|
20604 |
|
|
newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
|
20605 |
|
|
|
20606 |
|
|
if ((newval & 0xf0000000) == 0xe0000000)
|
20607 |
|
|
{
|
20608 |
|
|
/* Doubleword load/store: 8-bit offset, scaled by 4. */
|
20609 |
|
|
if (value >= 0)
|
20610 |
|
|
newval |= (1 << 23);
|
20611 |
|
|
else
|
20612 |
|
|
value = -value;
|
20613 |
|
|
if (value % 4 != 0)
|
20614 |
|
|
{
|
20615 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20616 |
|
|
_("offset not a multiple of 4"));
|
20617 |
|
|
break;
|
20618 |
|
|
}
|
20619 |
|
|
value /= 4;
|
20620 |
|
|
if (value > 0xff)
|
20621 |
|
|
{
|
20622 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20623 |
|
|
_("offset out of range"));
|
20624 |
|
|
break;
|
20625 |
|
|
}
|
20626 |
|
|
newval &= ~0xff;
|
20627 |
|
|
}
|
20628 |
|
|
else if ((newval & 0x000f0000) == 0x000f0000)
|
20629 |
|
|
{
|
20630 |
|
|
/* PC-relative, 12-bit offset. */
|
20631 |
|
|
if (value >= 0)
|
20632 |
|
|
newval |= (1 << 23);
|
20633 |
|
|
else
|
20634 |
|
|
value = -value;
|
20635 |
|
|
if (value > 0xfff)
|
20636 |
|
|
{
|
20637 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20638 |
|
|
_("offset out of range"));
|
20639 |
|
|
break;
|
20640 |
|
|
}
|
20641 |
|
|
newval &= ~0xfff;
|
20642 |
|
|
}
|
20643 |
|
|
else if ((newval & 0x00000100) == 0x00000100)
|
20644 |
|
|
{
|
20645 |
|
|
/* Writeback: 8-bit, +/- offset. */
|
20646 |
|
|
if (value >= 0)
|
20647 |
|
|
newval |= (1 << 9);
|
20648 |
|
|
else
|
20649 |
|
|
value = -value;
|
20650 |
|
|
if (value > 0xff)
|
20651 |
|
|
{
|
20652 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20653 |
|
|
_("offset out of range"));
|
20654 |
|
|
break;
|
20655 |
|
|
}
|
20656 |
|
|
newval &= ~0xff;
|
20657 |
|
|
}
|
20658 |
|
|
else if ((newval & 0x00000f00) == 0x00000e00)
|
20659 |
|
|
{
|
20660 |
|
|
/* T-instruction: positive 8-bit offset. */
|
20661 |
|
|
if (value < 0 || value > 0xff)
|
20662 |
|
|
{
|
20663 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20664 |
|
|
_("offset out of range"));
|
20665 |
|
|
break;
|
20666 |
|
|
}
|
20667 |
|
|
newval &= ~0xff;
|
20668 |
|
|
newval |= value;
|
20669 |
|
|
}
|
20670 |
|
|
else
|
20671 |
|
|
{
|
20672 |
|
|
/* Positive 12-bit or negative 8-bit offset. */
|
20673 |
|
|
int limit;
|
20674 |
|
|
if (value >= 0)
|
20675 |
|
|
{
|
20676 |
|
|
newval |= (1 << 23);
|
20677 |
|
|
limit = 0xfff;
|
20678 |
|
|
}
|
20679 |
|
|
else
|
20680 |
|
|
{
|
20681 |
|
|
value = -value;
|
20682 |
|
|
limit = 0xff;
|
20683 |
|
|
}
|
20684 |
|
|
if (value > limit)
|
20685 |
|
|
{
|
20686 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20687 |
|
|
_("offset out of range"));
|
20688 |
|
|
break;
|
20689 |
|
|
}
|
20690 |
|
|
newval &= ~limit;
|
20691 |
|
|
}
|
20692 |
|
|
|
20693 |
|
|
newval |= value;
|
20694 |
|
|
md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
|
20695 |
|
|
md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
|
20696 |
|
|
break;
|
20697 |
|
|
|
20698 |
|
|
case BFD_RELOC_ARM_SHIFT_IMM:
|
20699 |
|
|
newval = md_chars_to_number (buf, INSN_SIZE);
|
20700 |
|
|
if (((unsigned long) value) > 32
|
20701 |
|
|
|| (value == 32
|
20702 |
|
|
&& (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
|
20703 |
|
|
{
|
20704 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20705 |
|
|
_("shift expression is too large"));
|
20706 |
|
|
break;
|
20707 |
|
|
}
|
20708 |
|
|
|
20709 |
|
|
if (value == 0)
|
20710 |
|
|
/* Shifts of zero must be done as lsl. */
|
20711 |
|
|
newval &= ~0x60;
|
20712 |
|
|
else if (value == 32)
|
20713 |
|
|
value = 0;
|
20714 |
|
|
newval &= 0xfffff07f;
|
20715 |
|
|
newval |= (value & 0x1f) << 7;
|
20716 |
|
|
md_number_to_chars (buf, newval, INSN_SIZE);
|
20717 |
|
|
break;
|
20718 |
|
|
|
20719 |
|
|
case BFD_RELOC_ARM_T32_IMMEDIATE:
|
20720 |
|
|
case BFD_RELOC_ARM_T32_ADD_IMM:
|
20721 |
|
|
case BFD_RELOC_ARM_T32_IMM12:
|
20722 |
|
|
case BFD_RELOC_ARM_T32_ADD_PC12:
|
20723 |
|
|
/* We claim that this fixup has been processed here,
|
20724 |
|
|
even if in fact we generate an error because we do
|
20725 |
|
|
not have a reloc for it, so tc_gen_reloc will reject it. */
|
20726 |
|
|
fixP->fx_done = 1;
|
20727 |
|
|
|
20728 |
|
|
if (fixP->fx_addsy
|
20729 |
|
|
&& ! S_IS_DEFINED (fixP->fx_addsy))
|
20730 |
|
|
{
|
20731 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20732 |
|
|
_("undefined symbol %s used as an immediate value"),
|
20733 |
|
|
S_GET_NAME (fixP->fx_addsy));
|
20734 |
|
|
break;
|
20735 |
|
|
}
|
20736 |
|
|
|
20737 |
|
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
20738 |
|
|
newval <<= 16;
|
20739 |
|
|
newval |= md_chars_to_number (buf+2, THUMB_SIZE);
|
20740 |
|
|
|
20741 |
|
|
newimm = FAIL;
|
20742 |
|
|
if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
|
20743 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
|
20744 |
|
|
{
|
20745 |
|
|
newimm = encode_thumb32_immediate (value);
|
20746 |
|
|
if (newimm == (unsigned int) FAIL)
|
20747 |
|
|
newimm = thumb32_negate_data_op (&newval, value);
|
20748 |
|
|
}
|
20749 |
|
|
if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
|
20750 |
|
|
&& newimm == (unsigned int) FAIL)
|
20751 |
|
|
{
|
20752 |
|
|
/* Turn add/sum into addw/subw. */
|
20753 |
|
|
if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
|
20754 |
|
|
newval = (newval & 0xfeffffff) | 0x02000000;
|
20755 |
|
|
/* No flat 12-bit imm encoding for addsw/subsw. */
|
20756 |
|
|
if ((newval & 0x00100000) == 0)
|
20757 |
|
|
{
|
20758 |
|
|
/* 12 bit immediate for addw/subw. */
|
20759 |
|
|
if (value < 0)
|
20760 |
|
|
{
|
20761 |
|
|
value = -value;
|
20762 |
|
|
newval ^= 0x00a00000;
|
20763 |
|
|
}
|
20764 |
|
|
if (value > 0xfff)
|
20765 |
|
|
newimm = (unsigned int) FAIL;
|
20766 |
|
|
else
|
20767 |
|
|
newimm = value;
|
20768 |
|
|
}
|
20769 |
|
|
}
|
20770 |
|
|
|
20771 |
|
|
if (newimm == (unsigned int)FAIL)
|
20772 |
|
|
{
|
20773 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20774 |
|
|
_("invalid constant (%lx) after fixup"),
|
20775 |
|
|
(unsigned long) value);
|
20776 |
|
|
break;
|
20777 |
|
|
}
|
20778 |
|
|
|
20779 |
|
|
newval |= (newimm & 0x800) << 15;
|
20780 |
|
|
newval |= (newimm & 0x700) << 4;
|
20781 |
|
|
newval |= (newimm & 0x0ff);
|
20782 |
|
|
|
20783 |
|
|
md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
|
20784 |
|
|
md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
|
20785 |
|
|
break;
|
20786 |
|
|
|
20787 |
|
|
case BFD_RELOC_ARM_SMC:
|
20788 |
|
|
if (((unsigned long) value) > 0xffff)
|
20789 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20790 |
|
|
_("invalid smc expression"));
|
20791 |
|
|
newval = md_chars_to_number (buf, INSN_SIZE);
|
20792 |
|
|
newval |= (value & 0xf) | ((value & 0xfff0) << 4);
|
20793 |
|
|
md_number_to_chars (buf, newval, INSN_SIZE);
|
20794 |
|
|
break;
|
20795 |
|
|
|
20796 |
|
|
case BFD_RELOC_ARM_HVC:
|
20797 |
|
|
if (((unsigned long) value) > 0xffff)
|
20798 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20799 |
|
|
_("invalid hvc expression"));
|
20800 |
|
|
newval = md_chars_to_number (buf, INSN_SIZE);
|
20801 |
|
|
newval |= (value & 0xf) | ((value & 0xfff0) << 4);
|
20802 |
|
|
md_number_to_chars (buf, newval, INSN_SIZE);
|
20803 |
|
|
break;
|
20804 |
|
|
|
20805 |
|
|
case BFD_RELOC_ARM_SWI:
|
20806 |
|
|
if (fixP->tc_fix_data != 0)
|
20807 |
|
|
{
|
20808 |
|
|
if (((unsigned long) value) > 0xff)
|
20809 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20810 |
|
|
_("invalid swi expression"));
|
20811 |
|
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
20812 |
|
|
newval |= value;
|
20813 |
|
|
md_number_to_chars (buf, newval, THUMB_SIZE);
|
20814 |
|
|
}
|
20815 |
|
|
else
|
20816 |
|
|
{
|
20817 |
|
|
if (((unsigned long) value) > 0x00ffffff)
|
20818 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20819 |
|
|
_("invalid swi expression"));
|
20820 |
|
|
newval = md_chars_to_number (buf, INSN_SIZE);
|
20821 |
|
|
newval |= value;
|
20822 |
|
|
md_number_to_chars (buf, newval, INSN_SIZE);
|
20823 |
|
|
}
|
20824 |
|
|
break;
|
20825 |
|
|
|
20826 |
|
|
case BFD_RELOC_ARM_MULTI:
|
20827 |
|
|
if (((unsigned long) value) > 0xffff)
|
20828 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20829 |
|
|
_("invalid expression in load/store multiple"));
|
20830 |
|
|
newval = value | md_chars_to_number (buf, INSN_SIZE);
|
20831 |
|
|
md_number_to_chars (buf, newval, INSN_SIZE);
|
20832 |
|
|
break;
|
20833 |
|
|
|
20834 |
|
|
#ifdef OBJ_ELF
|
20835 |
|
|
case BFD_RELOC_ARM_PCREL_CALL:
|
20836 |
|
|
|
20837 |
|
|
if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
|
20838 |
|
|
&& fixP->fx_addsy
|
20839 |
|
|
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
|
20840 |
|
|
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
|
20841 |
|
|
&& THUMB_IS_FUNC (fixP->fx_addsy))
|
20842 |
|
|
/* Flip the bl to blx. This is a simple flip
|
20843 |
|
|
bit here because we generate PCREL_CALL for
|
20844 |
|
|
unconditional bls. */
|
20845 |
|
|
{
|
20846 |
|
|
newval = md_chars_to_number (buf, INSN_SIZE);
|
20847 |
|
|
newval = newval | 0x10000000;
|
20848 |
|
|
md_number_to_chars (buf, newval, INSN_SIZE);
|
20849 |
|
|
temp = 1;
|
20850 |
|
|
fixP->fx_done = 1;
|
20851 |
|
|
}
|
20852 |
|
|
else
|
20853 |
|
|
temp = 3;
|
20854 |
|
|
goto arm_branch_common;
|
20855 |
|
|
|
20856 |
|
|
case BFD_RELOC_ARM_PCREL_JUMP:
|
20857 |
|
|
if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
|
20858 |
|
|
&& fixP->fx_addsy
|
20859 |
|
|
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
|
20860 |
|
|
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
|
20861 |
|
|
&& THUMB_IS_FUNC (fixP->fx_addsy))
|
20862 |
|
|
{
|
20863 |
|
|
/* This would map to a bl<cond>, b<cond>,
|
20864 |
|
|
b<always> to a Thumb function. We
|
20865 |
|
|
need to force a relocation for this particular
|
20866 |
|
|
case. */
|
20867 |
|
|
newval = md_chars_to_number (buf, INSN_SIZE);
|
20868 |
|
|
fixP->fx_done = 0;
|
20869 |
|
|
}
|
20870 |
|
|
|
20871 |
|
|
case BFD_RELOC_ARM_PLT32:
|
20872 |
|
|
#endif
|
20873 |
|
|
case BFD_RELOC_ARM_PCREL_BRANCH:
|
20874 |
|
|
temp = 3;
|
20875 |
|
|
goto arm_branch_common;
|
20876 |
|
|
|
20877 |
|
|
case BFD_RELOC_ARM_PCREL_BLX:
|
20878 |
|
|
|
20879 |
|
|
temp = 1;
|
20880 |
|
|
if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
|
20881 |
|
|
&& fixP->fx_addsy
|
20882 |
|
|
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
|
20883 |
|
|
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
|
20884 |
|
|
&& ARM_IS_FUNC (fixP->fx_addsy))
|
20885 |
|
|
{
|
20886 |
|
|
/* Flip the blx to a bl and warn. */
|
20887 |
|
|
const char *name = S_GET_NAME (fixP->fx_addsy);
|
20888 |
|
|
newval = 0xeb000000;
|
20889 |
|
|
as_warn_where (fixP->fx_file, fixP->fx_line,
|
20890 |
|
|
_("blx to '%s' an ARM ISA state function changed to bl"),
|
20891 |
|
|
name);
|
20892 |
|
|
md_number_to_chars (buf, newval, INSN_SIZE);
|
20893 |
|
|
temp = 3;
|
20894 |
|
|
fixP->fx_done = 1;
|
20895 |
|
|
}
|
20896 |
|
|
|
20897 |
|
|
#ifdef OBJ_ELF
|
20898 |
|
|
if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
|
20899 |
|
|
fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
|
20900 |
|
|
#endif
|
20901 |
|
|
|
20902 |
|
|
arm_branch_common:
|
20903 |
|
|
/* We are going to store value (shifted right by two) in the
|
20904 |
|
|
instruction, in a 24 bit, signed field. Bits 26 through 32 either
|
20905 |
|
|
all clear or all set and bit 0 must be clear. For B/BL bit 1 must
|
20906 |
|
|
also be be clear. */
|
20907 |
|
|
if (value & temp)
|
20908 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20909 |
|
|
_("misaligned branch destination"));
|
20910 |
|
|
if ((value & (offsetT)0xfe000000) != (offsetT)0
|
20911 |
|
|
&& (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
|
20912 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20913 |
|
|
_("branch out of range"));
|
20914 |
|
|
|
20915 |
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
20916 |
|
|
{
|
20917 |
|
|
newval = md_chars_to_number (buf, INSN_SIZE);
|
20918 |
|
|
newval |= (value >> 2) & 0x00ffffff;
|
20919 |
|
|
/* Set the H bit on BLX instructions. */
|
20920 |
|
|
if (temp == 1)
|
20921 |
|
|
{
|
20922 |
|
|
if (value & 2)
|
20923 |
|
|
newval |= 0x01000000;
|
20924 |
|
|
else
|
20925 |
|
|
newval &= ~0x01000000;
|
20926 |
|
|
}
|
20927 |
|
|
md_number_to_chars (buf, newval, INSN_SIZE);
|
20928 |
|
|
}
|
20929 |
|
|
break;
|
20930 |
|
|
|
20931 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
|
20932 |
|
|
/* CBZ can only branch forward. */
|
20933 |
|
|
|
20934 |
|
|
/* Attempts to use CBZ to branch to the next instruction
|
20935 |
|
|
(which, strictly speaking, are prohibited) will be turned into
|
20936 |
|
|
no-ops.
|
20937 |
|
|
|
20938 |
|
|
FIXME: It may be better to remove the instruction completely and
|
20939 |
|
|
perform relaxation. */
|
20940 |
|
|
if (value == -2)
|
20941 |
|
|
{
|
20942 |
|
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
20943 |
|
|
newval = 0xbf00; /* NOP encoding T1 */
|
20944 |
|
|
md_number_to_chars (buf, newval, THUMB_SIZE);
|
20945 |
|
|
}
|
20946 |
|
|
else
|
20947 |
|
|
{
|
20948 |
|
|
if (value & ~0x7e)
|
20949 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20950 |
|
|
_("branch out of range"));
|
20951 |
|
|
|
20952 |
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
20953 |
|
|
{
|
20954 |
|
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
20955 |
|
|
newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
|
20956 |
|
|
md_number_to_chars (buf, newval, THUMB_SIZE);
|
20957 |
|
|
}
|
20958 |
|
|
}
|
20959 |
|
|
break;
|
20960 |
|
|
|
20961 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
|
20962 |
|
|
if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
|
20963 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20964 |
|
|
_("branch out of range"));
|
20965 |
|
|
|
20966 |
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
20967 |
|
|
{
|
20968 |
|
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
20969 |
|
|
newval |= (value & 0x1ff) >> 1;
|
20970 |
|
|
md_number_to_chars (buf, newval, THUMB_SIZE);
|
20971 |
|
|
}
|
20972 |
|
|
break;
|
20973 |
|
|
|
20974 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
|
20975 |
|
|
if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
|
20976 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20977 |
|
|
_("branch out of range"));
|
20978 |
|
|
|
20979 |
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
20980 |
|
|
{
|
20981 |
|
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
20982 |
|
|
newval |= (value & 0xfff) >> 1;
|
20983 |
|
|
md_number_to_chars (buf, newval, THUMB_SIZE);
|
20984 |
|
|
}
|
20985 |
|
|
break;
|
20986 |
|
|
|
20987 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH20:
|
20988 |
|
|
if (fixP->fx_addsy
|
20989 |
|
|
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
|
20990 |
|
|
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
|
20991 |
|
|
&& ARM_IS_FUNC (fixP->fx_addsy)
|
20992 |
|
|
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
|
20993 |
|
|
{
|
20994 |
|
|
/* Force a relocation for a branch 20 bits wide. */
|
20995 |
|
|
fixP->fx_done = 0;
|
20996 |
|
|
}
|
20997 |
|
|
if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
|
20998 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
20999 |
|
|
_("conditional branch out of range"));
|
21000 |
|
|
|
21001 |
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
21002 |
|
|
{
|
21003 |
|
|
offsetT newval2;
|
21004 |
|
|
addressT S, J1, J2, lo, hi;
|
21005 |
|
|
|
21006 |
|
|
S = (value & 0x00100000) >> 20;
|
21007 |
|
|
J2 = (value & 0x00080000) >> 19;
|
21008 |
|
|
J1 = (value & 0x00040000) >> 18;
|
21009 |
|
|
hi = (value & 0x0003f000) >> 12;
|
21010 |
|
|
lo = (value & 0x00000ffe) >> 1;
|
21011 |
|
|
|
21012 |
|
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
21013 |
|
|
newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
|
21014 |
|
|
newval |= (S << 10) | hi;
|
21015 |
|
|
newval2 |= (J1 << 13) | (J2 << 11) | lo;
|
21016 |
|
|
md_number_to_chars (buf, newval, THUMB_SIZE);
|
21017 |
|
|
md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
|
21018 |
|
|
}
|
21019 |
|
|
break;
|
21020 |
|
|
|
21021 |
|
|
case BFD_RELOC_THUMB_PCREL_BLX:
|
21022 |
|
|
|
21023 |
|
|
/* If there is a blx from a thumb state function to
|
21024 |
|
|
another thumb function flip this to a bl and warn
|
21025 |
|
|
about it. */
|
21026 |
|
|
|
21027 |
|
|
if (fixP->fx_addsy
|
21028 |
|
|
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
|
21029 |
|
|
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
|
21030 |
|
|
&& THUMB_IS_FUNC (fixP->fx_addsy))
|
21031 |
|
|
{
|
21032 |
|
|
const char *name = S_GET_NAME (fixP->fx_addsy);
|
21033 |
|
|
as_warn_where (fixP->fx_file, fixP->fx_line,
|
21034 |
|
|
_("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
|
21035 |
|
|
name);
|
21036 |
|
|
newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
|
21037 |
|
|
newval = newval | 0x1000;
|
21038 |
|
|
md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
|
21039 |
|
|
fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
|
21040 |
|
|
fixP->fx_done = 1;
|
21041 |
|
|
}
|
21042 |
|
|
|
21043 |
|
|
|
21044 |
|
|
goto thumb_bl_common;
|
21045 |
|
|
|
21046 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH23:
|
21047 |
|
|
|
21048 |
|
|
/* A bl from Thumb state ISA to an internal ARM state function
|
21049 |
|
|
is converted to a blx. */
|
21050 |
|
|
if (fixP->fx_addsy
|
21051 |
|
|
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
|
21052 |
|
|
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
|
21053 |
|
|
&& ARM_IS_FUNC (fixP->fx_addsy)
|
21054 |
|
|
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
|
21055 |
|
|
{
|
21056 |
|
|
newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
|
21057 |
|
|
newval = newval & ~0x1000;
|
21058 |
|
|
md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
|
21059 |
|
|
fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
|
21060 |
|
|
fixP->fx_done = 1;
|
21061 |
|
|
}
|
21062 |
|
|
|
21063 |
|
|
thumb_bl_common:
|
21064 |
|
|
|
21065 |
|
|
#ifdef OBJ_ELF
|
21066 |
|
|
if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 &&
|
21067 |
|
|
fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
|
21068 |
|
|
fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
|
21069 |
|
|
#endif
|
21070 |
|
|
|
21071 |
|
|
if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
|
21072 |
|
|
/* For a BLX instruction, make sure that the relocation is rounded up
|
21073 |
|
|
to a word boundary. This follows the semantics of the instruction
|
21074 |
|
|
which specifies that bit 1 of the target address will come from bit
|
21075 |
|
|
1 of the base address. */
|
21076 |
|
|
value = (value + 1) & ~ 1;
|
21077 |
|
|
|
21078 |
|
|
|
21079 |
|
|
if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
|
21080 |
|
|
{
|
21081 |
|
|
if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
|
21082 |
|
|
{
|
21083 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21084 |
|
|
_("branch out of range"));
|
21085 |
|
|
}
|
21086 |
|
|
else if ((value & ~0x1ffffff)
|
21087 |
|
|
&& ((value & ~0x1ffffff) != ~0x1ffffff))
|
21088 |
|
|
{
|
21089 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21090 |
|
|
_("Thumb2 branch out of range"));
|
21091 |
|
|
}
|
21092 |
|
|
}
|
21093 |
|
|
|
21094 |
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
21095 |
|
|
encode_thumb2_b_bl_offset (buf, value);
|
21096 |
|
|
|
21097 |
|
|
break;
|
21098 |
|
|
|
21099 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH25:
|
21100 |
|
|
if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
|
21101 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21102 |
|
|
_("branch out of range"));
|
21103 |
|
|
|
21104 |
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
21105 |
|
|
encode_thumb2_b_bl_offset (buf, value);
|
21106 |
|
|
|
21107 |
|
|
break;
|
21108 |
|
|
|
21109 |
|
|
case BFD_RELOC_8:
|
21110 |
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
21111 |
|
|
md_number_to_chars (buf, value, 1);
|
21112 |
|
|
break;
|
21113 |
|
|
|
21114 |
|
|
case BFD_RELOC_16:
|
21115 |
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
21116 |
|
|
md_number_to_chars (buf, value, 2);
|
21117 |
|
|
break;
|
21118 |
|
|
|
21119 |
|
|
#ifdef OBJ_ELF
|
21120 |
|
|
case BFD_RELOC_ARM_TLS_CALL:
|
21121 |
|
|
case BFD_RELOC_ARM_THM_TLS_CALL:
|
21122 |
|
|
case BFD_RELOC_ARM_TLS_DESCSEQ:
|
21123 |
|
|
case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
|
21124 |
|
|
S_SET_THREAD_LOCAL (fixP->fx_addsy);
|
21125 |
|
|
break;
|
21126 |
|
|
|
21127 |
|
|
case BFD_RELOC_ARM_TLS_GOTDESC:
|
21128 |
|
|
case BFD_RELOC_ARM_TLS_GD32:
|
21129 |
|
|
case BFD_RELOC_ARM_TLS_LE32:
|
21130 |
|
|
case BFD_RELOC_ARM_TLS_IE32:
|
21131 |
|
|
case BFD_RELOC_ARM_TLS_LDM32:
|
21132 |
|
|
case BFD_RELOC_ARM_TLS_LDO32:
|
21133 |
|
|
S_SET_THREAD_LOCAL (fixP->fx_addsy);
|
21134 |
|
|
/* fall through */
|
21135 |
|
|
|
21136 |
|
|
case BFD_RELOC_ARM_GOT32:
|
21137 |
|
|
case BFD_RELOC_ARM_GOTOFF:
|
21138 |
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
21139 |
|
|
md_number_to_chars (buf, 0, 4);
|
21140 |
|
|
break;
|
21141 |
|
|
|
21142 |
|
|
case BFD_RELOC_ARM_GOT_PREL:
|
21143 |
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
21144 |
|
|
md_number_to_chars (buf, value, 4);
|
21145 |
|
|
break;
|
21146 |
|
|
|
21147 |
|
|
case BFD_RELOC_ARM_TARGET2:
|
21148 |
|
|
/* TARGET2 is not partial-inplace, so we need to write the
|
21149 |
|
|
addend here for REL targets, because it won't be written out
|
21150 |
|
|
during reloc processing later. */
|
21151 |
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
21152 |
|
|
md_number_to_chars (buf, fixP->fx_offset, 4);
|
21153 |
|
|
break;
|
21154 |
|
|
#endif
|
21155 |
|
|
|
21156 |
|
|
case BFD_RELOC_RVA:
|
21157 |
|
|
case BFD_RELOC_32:
|
21158 |
|
|
case BFD_RELOC_ARM_TARGET1:
|
21159 |
|
|
case BFD_RELOC_ARM_ROSEGREL32:
|
21160 |
|
|
case BFD_RELOC_ARM_SBREL32:
|
21161 |
|
|
case BFD_RELOC_32_PCREL:
|
21162 |
|
|
#ifdef TE_PE
|
21163 |
|
|
case BFD_RELOC_32_SECREL:
|
21164 |
|
|
#endif
|
21165 |
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
21166 |
|
|
#ifdef TE_WINCE
|
21167 |
|
|
/* For WinCE we only do this for pcrel fixups. */
|
21168 |
|
|
if (fixP->fx_done || fixP->fx_pcrel)
|
21169 |
|
|
#endif
|
21170 |
|
|
md_number_to_chars (buf, value, 4);
|
21171 |
|
|
break;
|
21172 |
|
|
|
21173 |
|
|
#ifdef OBJ_ELF
|
21174 |
|
|
case BFD_RELOC_ARM_PREL31:
|
21175 |
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
21176 |
|
|
{
|
21177 |
|
|
newval = md_chars_to_number (buf, 4) & 0x80000000;
|
21178 |
|
|
if ((value ^ (value >> 1)) & 0x40000000)
|
21179 |
|
|
{
|
21180 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21181 |
|
|
_("rel31 relocation overflow"));
|
21182 |
|
|
}
|
21183 |
|
|
newval |= value & 0x7fffffff;
|
21184 |
|
|
md_number_to_chars (buf, newval, 4);
|
21185 |
|
|
}
|
21186 |
|
|
break;
|
21187 |
|
|
#endif
|
21188 |
|
|
|
21189 |
|
|
case BFD_RELOC_ARM_CP_OFF_IMM:
|
21190 |
|
|
case BFD_RELOC_ARM_T32_CP_OFF_IMM:
|
21191 |
|
|
if (value < -1023 || value > 1023 || (value & 3))
|
21192 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21193 |
|
|
_("co-processor offset out of range"));
|
21194 |
|
|
cp_off_common:
|
21195 |
|
|
sign = value > 0;
|
21196 |
|
|
if (value < 0)
|
21197 |
|
|
value = -value;
|
21198 |
|
|
if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
|
21199 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
|
21200 |
|
|
newval = md_chars_to_number (buf, INSN_SIZE);
|
21201 |
|
|
else
|
21202 |
|
|
newval = get_thumb32_insn (buf);
|
21203 |
|
|
if (value == 0)
|
21204 |
|
|
newval &= 0xffffff00;
|
21205 |
|
|
else
|
21206 |
|
|
{
|
21207 |
|
|
newval &= 0xff7fff00;
|
21208 |
|
|
newval |= (value >> 2) | (sign ? INDEX_UP : 0);
|
21209 |
|
|
}
|
21210 |
|
|
if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
|
21211 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
|
21212 |
|
|
md_number_to_chars (buf, newval, INSN_SIZE);
|
21213 |
|
|
else
|
21214 |
|
|
put_thumb32_insn (buf, newval);
|
21215 |
|
|
break;
|
21216 |
|
|
|
21217 |
|
|
case BFD_RELOC_ARM_CP_OFF_IMM_S2:
|
21218 |
|
|
case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
|
21219 |
|
|
if (value < -255 || value > 255)
|
21220 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21221 |
|
|
_("co-processor offset out of range"));
|
21222 |
|
|
value *= 4;
|
21223 |
|
|
goto cp_off_common;
|
21224 |
|
|
|
21225 |
|
|
case BFD_RELOC_ARM_THUMB_OFFSET:
|
21226 |
|
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
21227 |
|
|
/* Exactly what ranges, and where the offset is inserted depends
|
21228 |
|
|
on the type of instruction, we can establish this from the
|
21229 |
|
|
top 4 bits. */
|
21230 |
|
|
switch (newval >> 12)
|
21231 |
|
|
{
|
21232 |
|
|
case 4: /* PC load. */
|
21233 |
|
|
/* Thumb PC loads are somewhat odd, bit 1 of the PC is
|
21234 |
|
|
forced to zero for these loads; md_pcrel_from has already
|
21235 |
|
|
compensated for this. */
|
21236 |
|
|
if (value & 3)
|
21237 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21238 |
|
|
_("invalid offset, target not word aligned (0x%08lX)"),
|
21239 |
|
|
(((unsigned long) fixP->fx_frag->fr_address
|
21240 |
|
|
+ (unsigned long) fixP->fx_where) & ~3)
|
21241 |
|
|
+ (unsigned long) value);
|
21242 |
|
|
|
21243 |
|
|
if (value & ~0x3fc)
|
21244 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21245 |
|
|
_("invalid offset, value too big (0x%08lX)"),
|
21246 |
|
|
(long) value);
|
21247 |
|
|
|
21248 |
|
|
newval |= value >> 2;
|
21249 |
|
|
break;
|
21250 |
|
|
|
21251 |
|
|
case 9: /* SP load/store. */
|
21252 |
|
|
if (value & ~0x3fc)
|
21253 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21254 |
|
|
_("invalid offset, value too big (0x%08lX)"),
|
21255 |
|
|
(long) value);
|
21256 |
|
|
newval |= value >> 2;
|
21257 |
|
|
break;
|
21258 |
|
|
|
21259 |
|
|
case 6: /* Word load/store. */
|
21260 |
|
|
if (value & ~0x7c)
|
21261 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21262 |
|
|
_("invalid offset, value too big (0x%08lX)"),
|
21263 |
|
|
(long) value);
|
21264 |
|
|
newval |= value << 4; /* 6 - 2. */
|
21265 |
|
|
break;
|
21266 |
|
|
|
21267 |
|
|
case 7: /* Byte load/store. */
|
21268 |
|
|
if (value & ~0x1f)
|
21269 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21270 |
|
|
_("invalid offset, value too big (0x%08lX)"),
|
21271 |
|
|
(long) value);
|
21272 |
|
|
newval |= value << 6;
|
21273 |
|
|
break;
|
21274 |
|
|
|
21275 |
|
|
case 8: /* Halfword load/store. */
|
21276 |
|
|
if (value & ~0x3e)
|
21277 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21278 |
|
|
_("invalid offset, value too big (0x%08lX)"),
|
21279 |
|
|
(long) value);
|
21280 |
|
|
newval |= value << 5; /* 6 - 1. */
|
21281 |
|
|
break;
|
21282 |
|
|
|
21283 |
|
|
default:
|
21284 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21285 |
|
|
"Unable to process relocation for thumb opcode: %lx",
|
21286 |
|
|
(unsigned long) newval);
|
21287 |
|
|
break;
|
21288 |
|
|
}
|
21289 |
|
|
md_number_to_chars (buf, newval, THUMB_SIZE);
|
21290 |
|
|
break;
|
21291 |
|
|
|
21292 |
|
|
case BFD_RELOC_ARM_THUMB_ADD:
|
21293 |
|
|
/* This is a complicated relocation, since we use it for all of
|
21294 |
|
|
the following immediate relocations:
|
21295 |
|
|
|
21296 |
|
|
3bit ADD/SUB
|
21297 |
|
|
8bit ADD/SUB
|
21298 |
|
|
9bit ADD/SUB SP word-aligned
|
21299 |
|
|
10bit ADD PC/SP word-aligned
|
21300 |
|
|
|
21301 |
|
|
The type of instruction being processed is encoded in the
|
21302 |
|
|
instruction field:
|
21303 |
|
|
|
21304 |
|
|
0x8000 SUB
|
21305 |
|
|
0x00F0 Rd
|
21306 |
|
|
0x000F Rs
|
21307 |
|
|
*/
|
21308 |
|
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
21309 |
|
|
{
|
21310 |
|
|
int rd = (newval >> 4) & 0xf;
|
21311 |
|
|
int rs = newval & 0xf;
|
21312 |
|
|
int subtract = !!(newval & 0x8000);
|
21313 |
|
|
|
21314 |
|
|
/* Check for HI regs, only very restricted cases allowed:
|
21315 |
|
|
Adjusting SP, and using PC or SP to get an address. */
|
21316 |
|
|
if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
|
21317 |
|
|
|| (rs > 7 && rs != REG_SP && rs != REG_PC))
|
21318 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21319 |
|
|
_("invalid Hi register with immediate"));
|
21320 |
|
|
|
21321 |
|
|
/* If value is negative, choose the opposite instruction. */
|
21322 |
|
|
if (value < 0)
|
21323 |
|
|
{
|
21324 |
|
|
value = -value;
|
21325 |
|
|
subtract = !subtract;
|
21326 |
|
|
if (value < 0)
|
21327 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21328 |
|
|
_("immediate value out of range"));
|
21329 |
|
|
}
|
21330 |
|
|
|
21331 |
|
|
if (rd == REG_SP)
|
21332 |
|
|
{
|
21333 |
|
|
if (value & ~0x1fc)
|
21334 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21335 |
|
|
_("invalid immediate for stack address calculation"));
|
21336 |
|
|
newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
|
21337 |
|
|
newval |= value >> 2;
|
21338 |
|
|
}
|
21339 |
|
|
else if (rs == REG_PC || rs == REG_SP)
|
21340 |
|
|
{
|
21341 |
|
|
if (subtract || value & ~0x3fc)
|
21342 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21343 |
|
|
_("invalid immediate for address calculation (value = 0x%08lX)"),
|
21344 |
|
|
(unsigned long) value);
|
21345 |
|
|
newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
|
21346 |
|
|
newval |= rd << 8;
|
21347 |
|
|
newval |= value >> 2;
|
21348 |
|
|
}
|
21349 |
|
|
else if (rs == rd)
|
21350 |
|
|
{
|
21351 |
|
|
if (value & ~0xff)
|
21352 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21353 |
|
|
_("immediate value out of range"));
|
21354 |
|
|
newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
|
21355 |
|
|
newval |= (rd << 8) | value;
|
21356 |
|
|
}
|
21357 |
|
|
else
|
21358 |
|
|
{
|
21359 |
|
|
if (value & ~0x7)
|
21360 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21361 |
|
|
_("immediate value out of range"));
|
21362 |
|
|
newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
|
21363 |
|
|
newval |= rd | (rs << 3) | (value << 6);
|
21364 |
|
|
}
|
21365 |
|
|
}
|
21366 |
|
|
md_number_to_chars (buf, newval, THUMB_SIZE);
|
21367 |
|
|
break;
|
21368 |
|
|
|
21369 |
|
|
case BFD_RELOC_ARM_THUMB_IMM:
|
21370 |
|
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
21371 |
|
|
if (value < 0 || value > 255)
|
21372 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21373 |
|
|
_("invalid immediate: %ld is out of range"),
|
21374 |
|
|
(long) value);
|
21375 |
|
|
newval |= value;
|
21376 |
|
|
md_number_to_chars (buf, newval, THUMB_SIZE);
|
21377 |
|
|
break;
|
21378 |
|
|
|
21379 |
|
|
case BFD_RELOC_ARM_THUMB_SHIFT:
|
21380 |
|
|
/* 5bit shift value (0..32). LSL cannot take 32. */
|
21381 |
|
|
newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
|
21382 |
|
|
temp = newval & 0xf800;
|
21383 |
|
|
if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
|
21384 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21385 |
|
|
_("invalid shift value: %ld"), (long) value);
|
21386 |
|
|
/* Shifts of zero must be encoded as LSL. */
|
21387 |
|
|
if (value == 0)
|
21388 |
|
|
newval = (newval & 0x003f) | T_OPCODE_LSL_I;
|
21389 |
|
|
/* Shifts of 32 are encoded as zero. */
|
21390 |
|
|
else if (value == 32)
|
21391 |
|
|
value = 0;
|
21392 |
|
|
newval |= value << 6;
|
21393 |
|
|
md_number_to_chars (buf, newval, THUMB_SIZE);
|
21394 |
|
|
break;
|
21395 |
|
|
|
21396 |
|
|
case BFD_RELOC_VTABLE_INHERIT:
|
21397 |
|
|
case BFD_RELOC_VTABLE_ENTRY:
|
21398 |
|
|
fixP->fx_done = 0;
|
21399 |
|
|
return;
|
21400 |
|
|
|
21401 |
|
|
case BFD_RELOC_ARM_MOVW:
|
21402 |
|
|
case BFD_RELOC_ARM_MOVT:
|
21403 |
|
|
case BFD_RELOC_ARM_THUMB_MOVW:
|
21404 |
|
|
case BFD_RELOC_ARM_THUMB_MOVT:
|
21405 |
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
21406 |
|
|
{
|
21407 |
|
|
/* REL format relocations are limited to a 16-bit addend. */
|
21408 |
|
|
if (!fixP->fx_done)
|
21409 |
|
|
{
|
21410 |
|
|
if (value < -0x8000 || value > 0x7fff)
|
21411 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21412 |
|
|
_("offset out of range"));
|
21413 |
|
|
}
|
21414 |
|
|
else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
|
21415 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
|
21416 |
|
|
{
|
21417 |
|
|
value >>= 16;
|
21418 |
|
|
}
|
21419 |
|
|
|
21420 |
|
|
if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
|
21421 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
|
21422 |
|
|
{
|
21423 |
|
|
newval = get_thumb32_insn (buf);
|
21424 |
|
|
newval &= 0xfbf08f00;
|
21425 |
|
|
newval |= (value & 0xf000) << 4;
|
21426 |
|
|
newval |= (value & 0x0800) << 15;
|
21427 |
|
|
newval |= (value & 0x0700) << 4;
|
21428 |
|
|
newval |= (value & 0x00ff);
|
21429 |
|
|
put_thumb32_insn (buf, newval);
|
21430 |
|
|
}
|
21431 |
|
|
else
|
21432 |
|
|
{
|
21433 |
|
|
newval = md_chars_to_number (buf, 4);
|
21434 |
|
|
newval &= 0xfff0f000;
|
21435 |
|
|
newval |= value & 0x0fff;
|
21436 |
|
|
newval |= (value & 0xf000) << 4;
|
21437 |
|
|
md_number_to_chars (buf, newval, 4);
|
21438 |
|
|
}
|
21439 |
|
|
}
|
21440 |
|
|
return;
|
21441 |
|
|
|
21442 |
|
|
case BFD_RELOC_ARM_ALU_PC_G0_NC:
|
21443 |
|
|
case BFD_RELOC_ARM_ALU_PC_G0:
|
21444 |
|
|
case BFD_RELOC_ARM_ALU_PC_G1_NC:
|
21445 |
|
|
case BFD_RELOC_ARM_ALU_PC_G1:
|
21446 |
|
|
case BFD_RELOC_ARM_ALU_PC_G2:
|
21447 |
|
|
case BFD_RELOC_ARM_ALU_SB_G0_NC:
|
21448 |
|
|
case BFD_RELOC_ARM_ALU_SB_G0:
|
21449 |
|
|
case BFD_RELOC_ARM_ALU_SB_G1_NC:
|
21450 |
|
|
case BFD_RELOC_ARM_ALU_SB_G1:
|
21451 |
|
|
case BFD_RELOC_ARM_ALU_SB_G2:
|
21452 |
|
|
gas_assert (!fixP->fx_done);
|
21453 |
|
|
if (!seg->use_rela_p)
|
21454 |
|
|
{
|
21455 |
|
|
bfd_vma insn;
|
21456 |
|
|
bfd_vma encoded_addend;
|
21457 |
|
|
bfd_vma addend_abs = abs (value);
|
21458 |
|
|
|
21459 |
|
|
/* Check that the absolute value of the addend can be
|
21460 |
|
|
expressed as an 8-bit constant plus a rotation. */
|
21461 |
|
|
encoded_addend = encode_arm_immediate (addend_abs);
|
21462 |
|
|
if (encoded_addend == (unsigned int) FAIL)
|
21463 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21464 |
|
|
_("the offset 0x%08lX is not representable"),
|
21465 |
|
|
(unsigned long) addend_abs);
|
21466 |
|
|
|
21467 |
|
|
/* Extract the instruction. */
|
21468 |
|
|
insn = md_chars_to_number (buf, INSN_SIZE);
|
21469 |
|
|
|
21470 |
|
|
/* If the addend is positive, use an ADD instruction.
|
21471 |
|
|
Otherwise use a SUB. Take care not to destroy the S bit. */
|
21472 |
|
|
insn &= 0xff1fffff;
|
21473 |
|
|
if (value < 0)
|
21474 |
|
|
insn |= 1 << 22;
|
21475 |
|
|
else
|
21476 |
|
|
insn |= 1 << 23;
|
21477 |
|
|
|
21478 |
|
|
/* Place the encoded addend into the first 12 bits of the
|
21479 |
|
|
instruction. */
|
21480 |
|
|
insn &= 0xfffff000;
|
21481 |
|
|
insn |= encoded_addend;
|
21482 |
|
|
|
21483 |
|
|
/* Update the instruction. */
|
21484 |
|
|
md_number_to_chars (buf, insn, INSN_SIZE);
|
21485 |
|
|
}
|
21486 |
|
|
break;
|
21487 |
|
|
|
21488 |
|
|
case BFD_RELOC_ARM_LDR_PC_G0:
|
21489 |
|
|
case BFD_RELOC_ARM_LDR_PC_G1:
|
21490 |
|
|
case BFD_RELOC_ARM_LDR_PC_G2:
|
21491 |
|
|
case BFD_RELOC_ARM_LDR_SB_G0:
|
21492 |
|
|
case BFD_RELOC_ARM_LDR_SB_G1:
|
21493 |
|
|
case BFD_RELOC_ARM_LDR_SB_G2:
|
21494 |
|
|
gas_assert (!fixP->fx_done);
|
21495 |
|
|
if (!seg->use_rela_p)
|
21496 |
|
|
{
|
21497 |
|
|
bfd_vma insn;
|
21498 |
|
|
bfd_vma addend_abs = abs (value);
|
21499 |
|
|
|
21500 |
|
|
/* Check that the absolute value of the addend can be
|
21501 |
|
|
encoded in 12 bits. */
|
21502 |
|
|
if (addend_abs >= 0x1000)
|
21503 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21504 |
|
|
_("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
|
21505 |
|
|
(unsigned long) addend_abs);
|
21506 |
|
|
|
21507 |
|
|
/* Extract the instruction. */
|
21508 |
|
|
insn = md_chars_to_number (buf, INSN_SIZE);
|
21509 |
|
|
|
21510 |
|
|
/* If the addend is negative, clear bit 23 of the instruction.
|
21511 |
|
|
Otherwise set it. */
|
21512 |
|
|
if (value < 0)
|
21513 |
|
|
insn &= ~(1 << 23);
|
21514 |
|
|
else
|
21515 |
|
|
insn |= 1 << 23;
|
21516 |
|
|
|
21517 |
|
|
/* Place the absolute value of the addend into the first 12 bits
|
21518 |
|
|
of the instruction. */
|
21519 |
|
|
insn &= 0xfffff000;
|
21520 |
|
|
insn |= addend_abs;
|
21521 |
|
|
|
21522 |
|
|
/* Update the instruction. */
|
21523 |
|
|
md_number_to_chars (buf, insn, INSN_SIZE);
|
21524 |
|
|
}
|
21525 |
|
|
break;
|
21526 |
|
|
|
21527 |
|
|
case BFD_RELOC_ARM_LDRS_PC_G0:
|
21528 |
|
|
case BFD_RELOC_ARM_LDRS_PC_G1:
|
21529 |
|
|
case BFD_RELOC_ARM_LDRS_PC_G2:
|
21530 |
|
|
case BFD_RELOC_ARM_LDRS_SB_G0:
|
21531 |
|
|
case BFD_RELOC_ARM_LDRS_SB_G1:
|
21532 |
|
|
case BFD_RELOC_ARM_LDRS_SB_G2:
|
21533 |
|
|
gas_assert (!fixP->fx_done);
|
21534 |
|
|
if (!seg->use_rela_p)
|
21535 |
|
|
{
|
21536 |
|
|
bfd_vma insn;
|
21537 |
|
|
bfd_vma addend_abs = abs (value);
|
21538 |
|
|
|
21539 |
|
|
/* Check that the absolute value of the addend can be
|
21540 |
|
|
encoded in 8 bits. */
|
21541 |
|
|
if (addend_abs >= 0x100)
|
21542 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21543 |
|
|
_("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
|
21544 |
|
|
(unsigned long) addend_abs);
|
21545 |
|
|
|
21546 |
|
|
/* Extract the instruction. */
|
21547 |
|
|
insn = md_chars_to_number (buf, INSN_SIZE);
|
21548 |
|
|
|
21549 |
|
|
/* If the addend is negative, clear bit 23 of the instruction.
|
21550 |
|
|
Otherwise set it. */
|
21551 |
|
|
if (value < 0)
|
21552 |
|
|
insn &= ~(1 << 23);
|
21553 |
|
|
else
|
21554 |
|
|
insn |= 1 << 23;
|
21555 |
|
|
|
21556 |
|
|
/* Place the first four bits of the absolute value of the addend
|
21557 |
|
|
into the first 4 bits of the instruction, and the remaining
|
21558 |
|
|
four into bits 8 .. 11. */
|
21559 |
|
|
insn &= 0xfffff0f0;
|
21560 |
|
|
insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
|
21561 |
|
|
|
21562 |
|
|
/* Update the instruction. */
|
21563 |
|
|
md_number_to_chars (buf, insn, INSN_SIZE);
|
21564 |
|
|
}
|
21565 |
|
|
break;
|
21566 |
|
|
|
21567 |
|
|
case BFD_RELOC_ARM_LDC_PC_G0:
|
21568 |
|
|
case BFD_RELOC_ARM_LDC_PC_G1:
|
21569 |
|
|
case BFD_RELOC_ARM_LDC_PC_G2:
|
21570 |
|
|
case BFD_RELOC_ARM_LDC_SB_G0:
|
21571 |
|
|
case BFD_RELOC_ARM_LDC_SB_G1:
|
21572 |
|
|
case BFD_RELOC_ARM_LDC_SB_G2:
|
21573 |
|
|
gas_assert (!fixP->fx_done);
|
21574 |
|
|
if (!seg->use_rela_p)
|
21575 |
|
|
{
|
21576 |
|
|
bfd_vma insn;
|
21577 |
|
|
bfd_vma addend_abs = abs (value);
|
21578 |
|
|
|
21579 |
|
|
/* Check that the absolute value of the addend is a multiple of
|
21580 |
|
|
four and, when divided by four, fits in 8 bits. */
|
21581 |
|
|
if (addend_abs & 0x3)
|
21582 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21583 |
|
|
_("bad offset 0x%08lX (must be word-aligned)"),
|
21584 |
|
|
(unsigned long) addend_abs);
|
21585 |
|
|
|
21586 |
|
|
if ((addend_abs >> 2) > 0xff)
|
21587 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21588 |
|
|
_("bad offset 0x%08lX (must be an 8-bit number of words)"),
|
21589 |
|
|
(unsigned long) addend_abs);
|
21590 |
|
|
|
21591 |
|
|
/* Extract the instruction. */
|
21592 |
|
|
insn = md_chars_to_number (buf, INSN_SIZE);
|
21593 |
|
|
|
21594 |
|
|
/* If the addend is negative, clear bit 23 of the instruction.
|
21595 |
|
|
Otherwise set it. */
|
21596 |
|
|
if (value < 0)
|
21597 |
|
|
insn &= ~(1 << 23);
|
21598 |
|
|
else
|
21599 |
|
|
insn |= 1 << 23;
|
21600 |
|
|
|
21601 |
|
|
/* Place the addend (divided by four) into the first eight
|
21602 |
|
|
bits of the instruction. */
|
21603 |
|
|
insn &= 0xfffffff0;
|
21604 |
|
|
insn |= addend_abs >> 2;
|
21605 |
|
|
|
21606 |
|
|
/* Update the instruction. */
|
21607 |
|
|
md_number_to_chars (buf, insn, INSN_SIZE);
|
21608 |
|
|
}
|
21609 |
|
|
break;
|
21610 |
|
|
|
21611 |
|
|
case BFD_RELOC_ARM_V4BX:
|
21612 |
|
|
/* This will need to go in the object file. */
|
21613 |
|
|
fixP->fx_done = 0;
|
21614 |
|
|
break;
|
21615 |
|
|
|
21616 |
|
|
case BFD_RELOC_UNUSED:
|
21617 |
|
|
default:
|
21618 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
21619 |
|
|
_("bad relocation fixup type (%d)"), fixP->fx_r_type);
|
21620 |
|
|
}
|
21621 |
|
|
}
|
21622 |
|
|
|
21623 |
|
|
/* Translate internal representation of relocation info to BFD target
|
21624 |
|
|
format. */
|
21625 |
|
|
|
21626 |
|
|
arelent *
|
21627 |
|
|
tc_gen_reloc (asection *section, fixS *fixp)
|
21628 |
|
|
{
|
21629 |
|
|
arelent * reloc;
|
21630 |
|
|
bfd_reloc_code_real_type code;
|
21631 |
|
|
|
21632 |
|
|
reloc = (arelent *) xmalloc (sizeof (arelent));
|
21633 |
|
|
|
21634 |
|
|
reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
|
21635 |
|
|
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
|
21636 |
|
|
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
|
21637 |
|
|
|
21638 |
|
|
if (fixp->fx_pcrel)
|
21639 |
|
|
{
|
21640 |
|
|
if (section->use_rela_p)
|
21641 |
|
|
fixp->fx_offset -= md_pcrel_from_section (fixp, section);
|
21642 |
|
|
else
|
21643 |
|
|
fixp->fx_offset = reloc->address;
|
21644 |
|
|
}
|
21645 |
|
|
reloc->addend = fixp->fx_offset;
|
21646 |
|
|
|
21647 |
|
|
switch (fixp->fx_r_type)
|
21648 |
|
|
{
|
21649 |
|
|
case BFD_RELOC_8:
|
21650 |
|
|
if (fixp->fx_pcrel)
|
21651 |
|
|
{
|
21652 |
|
|
code = BFD_RELOC_8_PCREL;
|
21653 |
|
|
break;
|
21654 |
|
|
}
|
21655 |
|
|
|
21656 |
|
|
case BFD_RELOC_16:
|
21657 |
|
|
if (fixp->fx_pcrel)
|
21658 |
|
|
{
|
21659 |
|
|
code = BFD_RELOC_16_PCREL;
|
21660 |
|
|
break;
|
21661 |
|
|
}
|
21662 |
|
|
|
21663 |
|
|
case BFD_RELOC_32:
|
21664 |
|
|
if (fixp->fx_pcrel)
|
21665 |
|
|
{
|
21666 |
|
|
code = BFD_RELOC_32_PCREL;
|
21667 |
|
|
break;
|
21668 |
|
|
}
|
21669 |
|
|
|
21670 |
|
|
case BFD_RELOC_ARM_MOVW:
|
21671 |
|
|
if (fixp->fx_pcrel)
|
21672 |
|
|
{
|
21673 |
|
|
code = BFD_RELOC_ARM_MOVW_PCREL;
|
21674 |
|
|
break;
|
21675 |
|
|
}
|
21676 |
|
|
|
21677 |
|
|
case BFD_RELOC_ARM_MOVT:
|
21678 |
|
|
if (fixp->fx_pcrel)
|
21679 |
|
|
{
|
21680 |
|
|
code = BFD_RELOC_ARM_MOVT_PCREL;
|
21681 |
|
|
break;
|
21682 |
|
|
}
|
21683 |
|
|
|
21684 |
|
|
case BFD_RELOC_ARM_THUMB_MOVW:
|
21685 |
|
|
if (fixp->fx_pcrel)
|
21686 |
|
|
{
|
21687 |
|
|
code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
|
21688 |
|
|
break;
|
21689 |
|
|
}
|
21690 |
|
|
|
21691 |
|
|
case BFD_RELOC_ARM_THUMB_MOVT:
|
21692 |
|
|
if (fixp->fx_pcrel)
|
21693 |
|
|
{
|
21694 |
|
|
code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
|
21695 |
|
|
break;
|
21696 |
|
|
}
|
21697 |
|
|
|
21698 |
|
|
case BFD_RELOC_NONE:
|
21699 |
|
|
case BFD_RELOC_ARM_PCREL_BRANCH:
|
21700 |
|
|
case BFD_RELOC_ARM_PCREL_BLX:
|
21701 |
|
|
case BFD_RELOC_RVA:
|
21702 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH7:
|
21703 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH9:
|
21704 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH12:
|
21705 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH20:
|
21706 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH23:
|
21707 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH25:
|
21708 |
|
|
case BFD_RELOC_VTABLE_ENTRY:
|
21709 |
|
|
case BFD_RELOC_VTABLE_INHERIT:
|
21710 |
|
|
#ifdef TE_PE
|
21711 |
|
|
case BFD_RELOC_32_SECREL:
|
21712 |
|
|
#endif
|
21713 |
|
|
code = fixp->fx_r_type;
|
21714 |
|
|
break;
|
21715 |
|
|
|
21716 |
|
|
case BFD_RELOC_THUMB_PCREL_BLX:
|
21717 |
|
|
#ifdef OBJ_ELF
|
21718 |
|
|
if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
|
21719 |
|
|
code = BFD_RELOC_THUMB_PCREL_BRANCH23;
|
21720 |
|
|
else
|
21721 |
|
|
#endif
|
21722 |
|
|
code = BFD_RELOC_THUMB_PCREL_BLX;
|
21723 |
|
|
break;
|
21724 |
|
|
|
21725 |
|
|
case BFD_RELOC_ARM_LITERAL:
|
21726 |
|
|
case BFD_RELOC_ARM_HWLITERAL:
|
21727 |
|
|
/* If this is called then the a literal has
|
21728 |
|
|
been referenced across a section boundary. */
|
21729 |
|
|
as_bad_where (fixp->fx_file, fixp->fx_line,
|
21730 |
|
|
_("literal referenced across section boundary"));
|
21731 |
|
|
return NULL;
|
21732 |
|
|
|
21733 |
|
|
#ifdef OBJ_ELF
|
21734 |
|
|
case BFD_RELOC_ARM_TLS_CALL:
|
21735 |
|
|
case BFD_RELOC_ARM_THM_TLS_CALL:
|
21736 |
|
|
case BFD_RELOC_ARM_TLS_DESCSEQ:
|
21737 |
|
|
case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
|
21738 |
|
|
case BFD_RELOC_ARM_GOT32:
|
21739 |
|
|
case BFD_RELOC_ARM_GOTOFF:
|
21740 |
|
|
case BFD_RELOC_ARM_GOT_PREL:
|
21741 |
|
|
case BFD_RELOC_ARM_PLT32:
|
21742 |
|
|
case BFD_RELOC_ARM_TARGET1:
|
21743 |
|
|
case BFD_RELOC_ARM_ROSEGREL32:
|
21744 |
|
|
case BFD_RELOC_ARM_SBREL32:
|
21745 |
|
|
case BFD_RELOC_ARM_PREL31:
|
21746 |
|
|
case BFD_RELOC_ARM_TARGET2:
|
21747 |
|
|
case BFD_RELOC_ARM_TLS_LE32:
|
21748 |
|
|
case BFD_RELOC_ARM_TLS_LDO32:
|
21749 |
|
|
case BFD_RELOC_ARM_PCREL_CALL:
|
21750 |
|
|
case BFD_RELOC_ARM_PCREL_JUMP:
|
21751 |
|
|
case BFD_RELOC_ARM_ALU_PC_G0_NC:
|
21752 |
|
|
case BFD_RELOC_ARM_ALU_PC_G0:
|
21753 |
|
|
case BFD_RELOC_ARM_ALU_PC_G1_NC:
|
21754 |
|
|
case BFD_RELOC_ARM_ALU_PC_G1:
|
21755 |
|
|
case BFD_RELOC_ARM_ALU_PC_G2:
|
21756 |
|
|
case BFD_RELOC_ARM_LDR_PC_G0:
|
21757 |
|
|
case BFD_RELOC_ARM_LDR_PC_G1:
|
21758 |
|
|
case BFD_RELOC_ARM_LDR_PC_G2:
|
21759 |
|
|
case BFD_RELOC_ARM_LDRS_PC_G0:
|
21760 |
|
|
case BFD_RELOC_ARM_LDRS_PC_G1:
|
21761 |
|
|
case BFD_RELOC_ARM_LDRS_PC_G2:
|
21762 |
|
|
case BFD_RELOC_ARM_LDC_PC_G0:
|
21763 |
|
|
case BFD_RELOC_ARM_LDC_PC_G1:
|
21764 |
|
|
case BFD_RELOC_ARM_LDC_PC_G2:
|
21765 |
|
|
case BFD_RELOC_ARM_ALU_SB_G0_NC:
|
21766 |
|
|
case BFD_RELOC_ARM_ALU_SB_G0:
|
21767 |
|
|
case BFD_RELOC_ARM_ALU_SB_G1_NC:
|
21768 |
|
|
case BFD_RELOC_ARM_ALU_SB_G1:
|
21769 |
|
|
case BFD_RELOC_ARM_ALU_SB_G2:
|
21770 |
|
|
case BFD_RELOC_ARM_LDR_SB_G0:
|
21771 |
|
|
case BFD_RELOC_ARM_LDR_SB_G1:
|
21772 |
|
|
case BFD_RELOC_ARM_LDR_SB_G2:
|
21773 |
|
|
case BFD_RELOC_ARM_LDRS_SB_G0:
|
21774 |
|
|
case BFD_RELOC_ARM_LDRS_SB_G1:
|
21775 |
|
|
case BFD_RELOC_ARM_LDRS_SB_G2:
|
21776 |
|
|
case BFD_RELOC_ARM_LDC_SB_G0:
|
21777 |
|
|
case BFD_RELOC_ARM_LDC_SB_G1:
|
21778 |
|
|
case BFD_RELOC_ARM_LDC_SB_G2:
|
21779 |
|
|
case BFD_RELOC_ARM_V4BX:
|
21780 |
|
|
code = fixp->fx_r_type;
|
21781 |
|
|
break;
|
21782 |
|
|
|
21783 |
|
|
case BFD_RELOC_ARM_TLS_GOTDESC:
|
21784 |
|
|
case BFD_RELOC_ARM_TLS_GD32:
|
21785 |
|
|
case BFD_RELOC_ARM_TLS_IE32:
|
21786 |
|
|
case BFD_RELOC_ARM_TLS_LDM32:
|
21787 |
|
|
/* BFD will include the symbol's address in the addend.
|
21788 |
|
|
But we don't want that, so subtract it out again here. */
|
21789 |
|
|
if (!S_IS_COMMON (fixp->fx_addsy))
|
21790 |
|
|
reloc->addend -= (*reloc->sym_ptr_ptr)->value;
|
21791 |
|
|
code = fixp->fx_r_type;
|
21792 |
|
|
break;
|
21793 |
|
|
#endif
|
21794 |
|
|
|
21795 |
|
|
case BFD_RELOC_ARM_IMMEDIATE:
|
21796 |
|
|
as_bad_where (fixp->fx_file, fixp->fx_line,
|
21797 |
|
|
_("internal relocation (type: IMMEDIATE) not fixed up"));
|
21798 |
|
|
return NULL;
|
21799 |
|
|
|
21800 |
|
|
case BFD_RELOC_ARM_ADRL_IMMEDIATE:
|
21801 |
|
|
as_bad_where (fixp->fx_file, fixp->fx_line,
|
21802 |
|
|
_("ADRL used for a symbol not defined in the same file"));
|
21803 |
|
|
return NULL;
|
21804 |
|
|
|
21805 |
|
|
case BFD_RELOC_ARM_OFFSET_IMM:
|
21806 |
|
|
if (section->use_rela_p)
|
21807 |
|
|
{
|
21808 |
|
|
code = fixp->fx_r_type;
|
21809 |
|
|
break;
|
21810 |
|
|
}
|
21811 |
|
|
|
21812 |
|
|
if (fixp->fx_addsy != NULL
|
21813 |
|
|
&& !S_IS_DEFINED (fixp->fx_addsy)
|
21814 |
|
|
&& S_IS_LOCAL (fixp->fx_addsy))
|
21815 |
|
|
{
|
21816 |
|
|
as_bad_where (fixp->fx_file, fixp->fx_line,
|
21817 |
|
|
_("undefined local label `%s'"),
|
21818 |
|
|
S_GET_NAME (fixp->fx_addsy));
|
21819 |
|
|
return NULL;
|
21820 |
|
|
}
|
21821 |
|
|
|
21822 |
|
|
as_bad_where (fixp->fx_file, fixp->fx_line,
|
21823 |
|
|
_("internal_relocation (type: OFFSET_IMM) not fixed up"));
|
21824 |
|
|
return NULL;
|
21825 |
|
|
|
21826 |
|
|
default:
|
21827 |
|
|
{
|
21828 |
|
|
char * type;
|
21829 |
|
|
|
21830 |
|
|
switch (fixp->fx_r_type)
|
21831 |
|
|
{
|
21832 |
|
|
case BFD_RELOC_NONE: type = "NONE"; break;
|
21833 |
|
|
case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
|
21834 |
|
|
case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
|
21835 |
|
|
case BFD_RELOC_ARM_SMC: type = "SMC"; break;
|
21836 |
|
|
case BFD_RELOC_ARM_SWI: type = "SWI"; break;
|
21837 |
|
|
case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
|
21838 |
|
|
case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
|
21839 |
|
|
case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
|
21840 |
|
|
case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
|
21841 |
|
|
case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
|
21842 |
|
|
case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
|
21843 |
|
|
case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
|
21844 |
|
|
case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
|
21845 |
|
|
default: type = _("<unknown>"); break;
|
21846 |
|
|
}
|
21847 |
|
|
as_bad_where (fixp->fx_file, fixp->fx_line,
|
21848 |
|
|
_("cannot represent %s relocation in this object file format"),
|
21849 |
|
|
type);
|
21850 |
|
|
return NULL;
|
21851 |
|
|
}
|
21852 |
|
|
}
|
21853 |
|
|
|
21854 |
|
|
#ifdef OBJ_ELF
|
21855 |
|
|
if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
|
21856 |
|
|
&& GOT_symbol
|
21857 |
|
|
&& fixp->fx_addsy == GOT_symbol)
|
21858 |
|
|
{
|
21859 |
|
|
code = BFD_RELOC_ARM_GOTPC;
|
21860 |
|
|
reloc->addend = fixp->fx_offset = reloc->address;
|
21861 |
|
|
}
|
21862 |
|
|
#endif
|
21863 |
|
|
|
21864 |
|
|
reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
|
21865 |
|
|
|
21866 |
|
|
if (reloc->howto == NULL)
|
21867 |
|
|
{
|
21868 |
|
|
as_bad_where (fixp->fx_file, fixp->fx_line,
|
21869 |
|
|
_("cannot represent %s relocation in this object file format"),
|
21870 |
|
|
bfd_get_reloc_code_name (code));
|
21871 |
|
|
return NULL;
|
21872 |
|
|
}
|
21873 |
|
|
|
21874 |
|
|
/* HACK: Since arm ELF uses Rel instead of Rela, encode the
|
21875 |
|
|
vtable entry to be used in the relocation's section offset. */
|
21876 |
|
|
if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
|
21877 |
|
|
reloc->address = fixp->fx_offset;
|
21878 |
|
|
|
21879 |
|
|
return reloc;
|
21880 |
|
|
}
|
21881 |
|
|
|
21882 |
|
|
/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
|
21883 |
|
|
|
21884 |
|
|
void
|
21885 |
|
|
cons_fix_new_arm (fragS * frag,
|
21886 |
|
|
int where,
|
21887 |
|
|
int size,
|
21888 |
|
|
expressionS * exp)
|
21889 |
|
|
{
|
21890 |
|
|
bfd_reloc_code_real_type type;
|
21891 |
|
|
int pcrel = 0;
|
21892 |
|
|
|
21893 |
|
|
/* Pick a reloc.
|
21894 |
|
|
FIXME: @@ Should look at CPU word size. */
|
21895 |
|
|
switch (size)
|
21896 |
|
|
{
|
21897 |
|
|
case 1:
|
21898 |
|
|
type = BFD_RELOC_8;
|
21899 |
|
|
break;
|
21900 |
|
|
case 2:
|
21901 |
|
|
type = BFD_RELOC_16;
|
21902 |
|
|
break;
|
21903 |
|
|
case 4:
|
21904 |
|
|
default:
|
21905 |
|
|
type = BFD_RELOC_32;
|
21906 |
|
|
break;
|
21907 |
|
|
case 8:
|
21908 |
|
|
type = BFD_RELOC_64;
|
21909 |
|
|
break;
|
21910 |
|
|
}
|
21911 |
|
|
|
21912 |
|
|
#ifdef TE_PE
|
21913 |
|
|
if (exp->X_op == O_secrel)
|
21914 |
|
|
{
|
21915 |
|
|
exp->X_op = O_symbol;
|
21916 |
|
|
type = BFD_RELOC_32_SECREL;
|
21917 |
|
|
}
|
21918 |
|
|
#endif
|
21919 |
|
|
|
21920 |
|
|
fix_new_exp (frag, where, (int) size, exp, pcrel, type);
|
21921 |
|
|
}
|
21922 |
|
|
|
21923 |
|
|
#if defined (OBJ_COFF)
|
21924 |
|
|
void
|
21925 |
|
|
arm_validate_fix (fixS * fixP)
|
21926 |
|
|
{
|
21927 |
|
|
/* If the destination of the branch is a defined symbol which does not have
|
21928 |
|
|
the THUMB_FUNC attribute, then we must be calling a function which has
|
21929 |
|
|
the (interfacearm) attribute. We look for the Thumb entry point to that
|
21930 |
|
|
function and change the branch to refer to that function instead. */
|
21931 |
|
|
if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
|
21932 |
|
|
&& fixP->fx_addsy != NULL
|
21933 |
|
|
&& S_IS_DEFINED (fixP->fx_addsy)
|
21934 |
|
|
&& ! THUMB_IS_FUNC (fixP->fx_addsy))
|
21935 |
|
|
{
|
21936 |
|
|
fixP->fx_addsy = find_real_start (fixP->fx_addsy);
|
21937 |
|
|
}
|
21938 |
|
|
}
|
21939 |
|
|
#endif
|
21940 |
|
|
|
21941 |
|
|
|
21942 |
|
|
int
|
21943 |
|
|
arm_force_relocation (struct fix * fixp)
|
21944 |
|
|
{
|
21945 |
|
|
#if defined (OBJ_COFF) && defined (TE_PE)
|
21946 |
|
|
if (fixp->fx_r_type == BFD_RELOC_RVA)
|
21947 |
|
|
return 1;
|
21948 |
|
|
#endif
|
21949 |
|
|
|
21950 |
|
|
/* In case we have a call or a branch to a function in ARM ISA mode from
|
21951 |
|
|
a thumb function or vice-versa force the relocation. These relocations
|
21952 |
|
|
are cleared off for some cores that might have blx and simple transformations
|
21953 |
|
|
are possible. */
|
21954 |
|
|
|
21955 |
|
|
#ifdef OBJ_ELF
|
21956 |
|
|
switch (fixp->fx_r_type)
|
21957 |
|
|
{
|
21958 |
|
|
case BFD_RELOC_ARM_PCREL_JUMP:
|
21959 |
|
|
case BFD_RELOC_ARM_PCREL_CALL:
|
21960 |
|
|
case BFD_RELOC_THUMB_PCREL_BLX:
|
21961 |
|
|
if (THUMB_IS_FUNC (fixp->fx_addsy))
|
21962 |
|
|
return 1;
|
21963 |
|
|
break;
|
21964 |
|
|
|
21965 |
|
|
case BFD_RELOC_ARM_PCREL_BLX:
|
21966 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH25:
|
21967 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH20:
|
21968 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH23:
|
21969 |
|
|
if (ARM_IS_FUNC (fixp->fx_addsy))
|
21970 |
|
|
return 1;
|
21971 |
|
|
break;
|
21972 |
|
|
|
21973 |
|
|
default:
|
21974 |
|
|
break;
|
21975 |
|
|
}
|
21976 |
|
|
#endif
|
21977 |
|
|
|
21978 |
|
|
/* Resolve these relocations even if the symbol is extern or weak.
|
21979 |
|
|
Technically this is probably wrong due to symbol preemption.
|
21980 |
|
|
In practice these relocations do not have enough range to be useful
|
21981 |
|
|
at dynamic link time, and some code (e.g. in the Linux kernel)
|
21982 |
|
|
expects these references to be resolved. */
|
21983 |
|
|
if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
|
21984 |
|
|
|| fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
|
21985 |
|
|
|| fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
|
21986 |
|
|
|| fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
|
21987 |
|
|
|| fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
|
21988 |
|
|
|| fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
|
21989 |
|
|
|| fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
|
21990 |
|
|
|| fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
|
21991 |
|
|
|| fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
|
21992 |
|
|
|| fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
|
21993 |
|
|
|| fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
|
21994 |
|
|
|| fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
|
21995 |
|
|
|| fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
|
21996 |
|
|
|| fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
|
21997 |
|
|
return 0;
|
21998 |
|
|
|
21999 |
|
|
/* Always leave these relocations for the linker. */
|
22000 |
|
|
if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
|
22001 |
|
|
&& fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
|
22002 |
|
|
|| fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
|
22003 |
|
|
return 1;
|
22004 |
|
|
|
22005 |
|
|
/* Always generate relocations against function symbols. */
|
22006 |
|
|
if (fixp->fx_r_type == BFD_RELOC_32
|
22007 |
|
|
&& fixp->fx_addsy
|
22008 |
|
|
&& (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
|
22009 |
|
|
return 1;
|
22010 |
|
|
|
22011 |
|
|
return generic_force_reloc (fixp);
|
22012 |
|
|
}
|
22013 |
|
|
|
22014 |
|
|
#if defined (OBJ_ELF) || defined (OBJ_COFF)
|
22015 |
|
|
/* Relocations against function names must be left unadjusted,
|
22016 |
|
|
so that the linker can use this information to generate interworking
|
22017 |
|
|
stubs. The MIPS version of this function
|
22018 |
|
|
also prevents relocations that are mips-16 specific, but I do not
|
22019 |
|
|
know why it does this.
|
22020 |
|
|
|
22021 |
|
|
FIXME:
|
22022 |
|
|
There is one other problem that ought to be addressed here, but
|
22023 |
|
|
which currently is not: Taking the address of a label (rather
|
22024 |
|
|
than a function) and then later jumping to that address. Such
|
22025 |
|
|
addresses also ought to have their bottom bit set (assuming that
|
22026 |
|
|
they reside in Thumb code), but at the moment they will not. */
|
22027 |
|
|
|
22028 |
|
|
bfd_boolean
|
22029 |
|
|
arm_fix_adjustable (fixS * fixP)
|
22030 |
|
|
{
|
22031 |
|
|
if (fixP->fx_addsy == NULL)
|
22032 |
|
|
return 1;
|
22033 |
|
|
|
22034 |
|
|
/* Preserve relocations against symbols with function type. */
|
22035 |
|
|
if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
|
22036 |
|
|
return FALSE;
|
22037 |
|
|
|
22038 |
|
|
if (THUMB_IS_FUNC (fixP->fx_addsy)
|
22039 |
|
|
&& fixP->fx_subsy == NULL)
|
22040 |
|
|
return FALSE;
|
22041 |
|
|
|
22042 |
|
|
/* We need the symbol name for the VTABLE entries. */
|
22043 |
|
|
if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|
22044 |
|
|
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
|
22045 |
|
|
return FALSE;
|
22046 |
|
|
|
22047 |
|
|
/* Don't allow symbols to be discarded on GOT related relocs. */
|
22048 |
|
|
if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
|
22049 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_GOT32
|
22050 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
|
22051 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
|
22052 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
|
22053 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
|
22054 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
|
22055 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
|
22056 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
|
22057 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
|
22058 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
|
22059 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
|
22060 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
|
22061 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
|
22062 |
|
|
return FALSE;
|
22063 |
|
|
|
22064 |
|
|
/* Similarly for group relocations. */
|
22065 |
|
|
if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
|
22066 |
|
|
&& fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
|
22067 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
|
22068 |
|
|
return FALSE;
|
22069 |
|
|
|
22070 |
|
|
/* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
|
22071 |
|
|
if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
|
22072 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_MOVT
|
22073 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
|
22074 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
|
22075 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
|
22076 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
|
22077 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
|
22078 |
|
|
|| fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
|
22079 |
|
|
return FALSE;
|
22080 |
|
|
|
22081 |
|
|
return TRUE;
|
22082 |
|
|
}
|
22083 |
|
|
#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
|
22084 |
|
|
|
22085 |
|
|
#ifdef OBJ_ELF
|
22086 |
|
|
|
22087 |
|
|
const char *
|
22088 |
|
|
elf32_arm_target_format (void)
|
22089 |
|
|
{
|
22090 |
|
|
#ifdef TE_SYMBIAN
|
22091 |
|
|
return (target_big_endian
|
22092 |
|
|
? "elf32-bigarm-symbian"
|
22093 |
|
|
: "elf32-littlearm-symbian");
|
22094 |
|
|
#elif defined (TE_VXWORKS)
|
22095 |
|
|
return (target_big_endian
|
22096 |
|
|
? "elf32-bigarm-vxworks"
|
22097 |
|
|
: "elf32-littlearm-vxworks");
|
22098 |
|
|
#else
|
22099 |
|
|
if (target_big_endian)
|
22100 |
|
|
return "elf32-bigarm";
|
22101 |
|
|
else
|
22102 |
|
|
return "elf32-littlearm";
|
22103 |
|
|
#endif
|
22104 |
|
|
}
|
22105 |
|
|
|
22106 |
|
|
void
|
22107 |
|
|
armelf_frob_symbol (symbolS * symp,
|
22108 |
|
|
int * puntp)
|
22109 |
|
|
{
|
22110 |
|
|
elf_frob_symbol (symp, puntp);
|
22111 |
|
|
}
|
22112 |
|
|
#endif
|
22113 |
|
|
|
22114 |
|
|
/* MD interface: Finalization. */
|
22115 |
|
|
|
22116 |
|
|
void
|
22117 |
|
|
arm_cleanup (void)
|
22118 |
|
|
{
|
22119 |
|
|
literal_pool * pool;
|
22120 |
|
|
|
22121 |
|
|
/* Ensure that all the IT blocks are properly closed. */
|
22122 |
|
|
check_it_blocks_finished ();
|
22123 |
|
|
|
22124 |
|
|
for (pool = list_of_pools; pool; pool = pool->next)
|
22125 |
|
|
{
|
22126 |
|
|
/* Put it at the end of the relevant section. */
|
22127 |
|
|
subseg_set (pool->section, pool->sub_section);
|
22128 |
|
|
#ifdef OBJ_ELF
|
22129 |
|
|
arm_elf_change_section ();
|
22130 |
|
|
#endif
|
22131 |
|
|
s_ltorg (0);
|
22132 |
|
|
}
|
22133 |
|
|
}
|
22134 |
|
|
|
22135 |
|
|
#ifdef OBJ_ELF
|
22136 |
|
|
/* Remove any excess mapping symbols generated for alignment frags in
|
22137 |
|
|
SEC. We may have created a mapping symbol before a zero byte
|
22138 |
|
|
alignment; remove it if there's a mapping symbol after the
|
22139 |
|
|
alignment. */
|
22140 |
|
|
static void
|
22141 |
|
|
check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
|
22142 |
|
|
void *dummy ATTRIBUTE_UNUSED)
|
22143 |
|
|
{
|
22144 |
|
|
segment_info_type *seginfo = seg_info (sec);
|
22145 |
|
|
fragS *fragp;
|
22146 |
|
|
|
22147 |
|
|
if (seginfo == NULL || seginfo->frchainP == NULL)
|
22148 |
|
|
return;
|
22149 |
|
|
|
22150 |
|
|
for (fragp = seginfo->frchainP->frch_root;
|
22151 |
|
|
fragp != NULL;
|
22152 |
|
|
fragp = fragp->fr_next)
|
22153 |
|
|
{
|
22154 |
|
|
symbolS *sym = fragp->tc_frag_data.last_map;
|
22155 |
|
|
fragS *next = fragp->fr_next;
|
22156 |
|
|
|
22157 |
|
|
/* Variable-sized frags have been converted to fixed size by
|
22158 |
|
|
this point. But if this was variable-sized to start with,
|
22159 |
|
|
there will be a fixed-size frag after it. So don't handle
|
22160 |
|
|
next == NULL. */
|
22161 |
|
|
if (sym == NULL || next == NULL)
|
22162 |
|
|
continue;
|
22163 |
|
|
|
22164 |
|
|
if (S_GET_VALUE (sym) < next->fr_address)
|
22165 |
|
|
/* Not at the end of this frag. */
|
22166 |
|
|
continue;
|
22167 |
|
|
know (S_GET_VALUE (sym) == next->fr_address);
|
22168 |
|
|
|
22169 |
|
|
do
|
22170 |
|
|
{
|
22171 |
|
|
if (next->tc_frag_data.first_map != NULL)
|
22172 |
|
|
{
|
22173 |
|
|
/* Next frag starts with a mapping symbol. Discard this
|
22174 |
|
|
one. */
|
22175 |
|
|
symbol_remove (sym, &symbol_rootP, &symbol_lastP);
|
22176 |
|
|
break;
|
22177 |
|
|
}
|
22178 |
|
|
|
22179 |
|
|
if (next->fr_next == NULL)
|
22180 |
|
|
{
|
22181 |
|
|
/* This mapping symbol is at the end of the section. Discard
|
22182 |
|
|
it. */
|
22183 |
|
|
know (next->fr_fix == 0 && next->fr_var == 0);
|
22184 |
|
|
symbol_remove (sym, &symbol_rootP, &symbol_lastP);
|
22185 |
|
|
break;
|
22186 |
|
|
}
|
22187 |
|
|
|
22188 |
|
|
/* As long as we have empty frags without any mapping symbols,
|
22189 |
|
|
keep looking. */
|
22190 |
|
|
/* If the next frag is non-empty and does not start with a
|
22191 |
|
|
mapping symbol, then this mapping symbol is required. */
|
22192 |
|
|
if (next->fr_address != next->fr_next->fr_address)
|
22193 |
|
|
break;
|
22194 |
|
|
|
22195 |
|
|
next = next->fr_next;
|
22196 |
|
|
}
|
22197 |
|
|
while (next != NULL);
|
22198 |
|
|
}
|
22199 |
|
|
}
|
22200 |
|
|
#endif
|
22201 |
|
|
|
22202 |
|
|
/* Adjust the symbol table. This marks Thumb symbols as distinct from
|
22203 |
|
|
ARM ones. */
|
22204 |
|
|
|
22205 |
|
|
void
|
22206 |
|
|
arm_adjust_symtab (void)
|
22207 |
|
|
{
|
22208 |
|
|
#ifdef OBJ_COFF
|
22209 |
|
|
symbolS * sym;
|
22210 |
|
|
|
22211 |
|
|
for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
|
22212 |
|
|
{
|
22213 |
|
|
if (ARM_IS_THUMB (sym))
|
22214 |
|
|
{
|
22215 |
|
|
if (THUMB_IS_FUNC (sym))
|
22216 |
|
|
{
|
22217 |
|
|
/* Mark the symbol as a Thumb function. */
|
22218 |
|
|
if ( S_GET_STORAGE_CLASS (sym) == C_STAT
|
22219 |
|
|
|| S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
|
22220 |
|
|
S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
|
22221 |
|
|
|
22222 |
|
|
else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
|
22223 |
|
|
S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
|
22224 |
|
|
else
|
22225 |
|
|
as_bad (_("%s: unexpected function type: %d"),
|
22226 |
|
|
S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
|
22227 |
|
|
}
|
22228 |
|
|
else switch (S_GET_STORAGE_CLASS (sym))
|
22229 |
|
|
{
|
22230 |
|
|
case C_EXT:
|
22231 |
|
|
S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
|
22232 |
|
|
break;
|
22233 |
|
|
case C_STAT:
|
22234 |
|
|
S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
|
22235 |
|
|
break;
|
22236 |
|
|
case C_LABEL:
|
22237 |
|
|
S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
|
22238 |
|
|
break;
|
22239 |
|
|
default:
|
22240 |
|
|
/* Do nothing. */
|
22241 |
|
|
break;
|
22242 |
|
|
}
|
22243 |
|
|
}
|
22244 |
|
|
|
22245 |
|
|
if (ARM_IS_INTERWORK (sym))
|
22246 |
|
|
coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
|
22247 |
|
|
}
|
22248 |
|
|
#endif
|
22249 |
|
|
#ifdef OBJ_ELF
|
22250 |
|
|
symbolS * sym;
|
22251 |
|
|
char bind;
|
22252 |
|
|
|
22253 |
|
|
for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
|
22254 |
|
|
{
|
22255 |
|
|
if (ARM_IS_THUMB (sym))
|
22256 |
|
|
{
|
22257 |
|
|
elf_symbol_type * elf_sym;
|
22258 |
|
|
|
22259 |
|
|
elf_sym = elf_symbol (symbol_get_bfdsym (sym));
|
22260 |
|
|
bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
|
22261 |
|
|
|
22262 |
|
|
if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
|
22263 |
|
|
BFD_ARM_SPECIAL_SYM_TYPE_ANY))
|
22264 |
|
|
{
|
22265 |
|
|
/* If it's a .thumb_func, declare it as so,
|
22266 |
|
|
otherwise tag label as .code 16. */
|
22267 |
|
|
if (THUMB_IS_FUNC (sym))
|
22268 |
|
|
elf_sym->internal_elf_sym.st_target_internal
|
22269 |
|
|
= ST_BRANCH_TO_THUMB;
|
22270 |
|
|
else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
|
22271 |
|
|
elf_sym->internal_elf_sym.st_info =
|
22272 |
|
|
ELF_ST_INFO (bind, STT_ARM_16BIT);
|
22273 |
|
|
}
|
22274 |
|
|
}
|
22275 |
|
|
}
|
22276 |
|
|
|
22277 |
|
|
/* Remove any overlapping mapping symbols generated by alignment frags. */
|
22278 |
|
|
bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
|
22279 |
|
|
/* Now do generic ELF adjustments. */
|
22280 |
|
|
elf_adjust_symtab ();
|
22281 |
|
|
#endif
|
22282 |
|
|
}
|
22283 |
|
|
|
22284 |
|
|
/* MD interface: Initialization. */
|
22285 |
|
|
|
22286 |
|
|
static void
|
22287 |
|
|
set_constant_flonums (void)
|
22288 |
|
|
{
|
22289 |
|
|
int i;
|
22290 |
|
|
|
22291 |
|
|
for (i = 0; i < NUM_FLOAT_VALS; i++)
|
22292 |
|
|
if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
|
22293 |
|
|
abort ();
|
22294 |
|
|
}
|
22295 |
|
|
|
22296 |
|
|
/* Auto-select Thumb mode if it's the only available instruction set for the
|
22297 |
|
|
given architecture. */
|
22298 |
|
|
|
22299 |
|
|
static void
|
22300 |
|
|
autoselect_thumb_from_cpu_variant (void)
|
22301 |
|
|
{
|
22302 |
|
|
if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
|
22303 |
|
|
opcode_select (16);
|
22304 |
|
|
}
|
22305 |
|
|
|
22306 |
|
|
void
|
22307 |
|
|
md_begin (void)
|
22308 |
|
|
{
|
22309 |
|
|
unsigned mach;
|
22310 |
|
|
unsigned int i;
|
22311 |
|
|
|
22312 |
|
|
if ( (arm_ops_hsh = hash_new ()) == NULL
|
22313 |
|
|
|| (arm_cond_hsh = hash_new ()) == NULL
|
22314 |
|
|
|| (arm_shift_hsh = hash_new ()) == NULL
|
22315 |
|
|
|| (arm_psr_hsh = hash_new ()) == NULL
|
22316 |
|
|
|| (arm_v7m_psr_hsh = hash_new ()) == NULL
|
22317 |
|
|
|| (arm_reg_hsh = hash_new ()) == NULL
|
22318 |
|
|
|| (arm_reloc_hsh = hash_new ()) == NULL
|
22319 |
|
|
|| (arm_barrier_opt_hsh = hash_new ()) == NULL)
|
22320 |
|
|
as_fatal (_("virtual memory exhausted"));
|
22321 |
|
|
|
22322 |
|
|
for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
|
22323 |
|
|
hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
|
22324 |
|
|
for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
|
22325 |
|
|
hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
|
22326 |
|
|
for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
|
22327 |
|
|
hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
|
22328 |
|
|
for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
|
22329 |
|
|
hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
|
22330 |
|
|
for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
|
22331 |
|
|
hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
|
22332 |
|
|
(void *) (v7m_psrs + i));
|
22333 |
|
|
for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
|
22334 |
|
|
hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
|
22335 |
|
|
for (i = 0;
|
22336 |
|
|
i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
|
22337 |
|
|
i++)
|
22338 |
|
|
hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
|
22339 |
|
|
(void *) (barrier_opt_names + i));
|
22340 |
|
|
#ifdef OBJ_ELF
|
22341 |
|
|
for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
|
22342 |
|
|
hash_insert (arm_reloc_hsh, reloc_names[i].name, (void *) (reloc_names + i));
|
22343 |
|
|
#endif
|
22344 |
|
|
|
22345 |
|
|
set_constant_flonums ();
|
22346 |
|
|
|
22347 |
|
|
/* Set the cpu variant based on the command-line options. We prefer
|
22348 |
|
|
-mcpu= over -march= if both are set (as for GCC); and we prefer
|
22349 |
|
|
-mfpu= over any other way of setting the floating point unit.
|
22350 |
|
|
Use of legacy options with new options are faulted. */
|
22351 |
|
|
if (legacy_cpu)
|
22352 |
|
|
{
|
22353 |
|
|
if (mcpu_cpu_opt || march_cpu_opt)
|
22354 |
|
|
as_bad (_("use of old and new-style options to set CPU type"));
|
22355 |
|
|
|
22356 |
|
|
mcpu_cpu_opt = legacy_cpu;
|
22357 |
|
|
}
|
22358 |
|
|
else if (!mcpu_cpu_opt)
|
22359 |
|
|
mcpu_cpu_opt = march_cpu_opt;
|
22360 |
|
|
|
22361 |
|
|
if (legacy_fpu)
|
22362 |
|
|
{
|
22363 |
|
|
if (mfpu_opt)
|
22364 |
|
|
as_bad (_("use of old and new-style options to set FPU type"));
|
22365 |
|
|
|
22366 |
|
|
mfpu_opt = legacy_fpu;
|
22367 |
|
|
}
|
22368 |
|
|
else if (!mfpu_opt)
|
22369 |
|
|
{
|
22370 |
|
|
#if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
|
22371 |
|
|
|| defined (TE_NetBSD) || defined (TE_VXWORKS))
|
22372 |
|
|
/* Some environments specify a default FPU. If they don't, infer it
|
22373 |
|
|
from the processor. */
|
22374 |
|
|
if (mcpu_fpu_opt)
|
22375 |
|
|
mfpu_opt = mcpu_fpu_opt;
|
22376 |
|
|
else
|
22377 |
|
|
mfpu_opt = march_fpu_opt;
|
22378 |
|
|
#else
|
22379 |
|
|
mfpu_opt = &fpu_default;
|
22380 |
|
|
#endif
|
22381 |
|
|
}
|
22382 |
|
|
|
22383 |
|
|
if (!mfpu_opt)
|
22384 |
|
|
{
|
22385 |
|
|
if (mcpu_cpu_opt != NULL)
|
22386 |
|
|
mfpu_opt = &fpu_default;
|
22387 |
|
|
else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
|
22388 |
|
|
mfpu_opt = &fpu_arch_vfp_v2;
|
22389 |
|
|
else
|
22390 |
|
|
mfpu_opt = &fpu_arch_fpa;
|
22391 |
|
|
}
|
22392 |
|
|
|
22393 |
|
|
#ifdef CPU_DEFAULT
|
22394 |
|
|
if (!mcpu_cpu_opt)
|
22395 |
|
|
{
|
22396 |
|
|
mcpu_cpu_opt = &cpu_default;
|
22397 |
|
|
selected_cpu = cpu_default;
|
22398 |
|
|
}
|
22399 |
|
|
#else
|
22400 |
|
|
if (mcpu_cpu_opt)
|
22401 |
|
|
selected_cpu = *mcpu_cpu_opt;
|
22402 |
|
|
else
|
22403 |
|
|
mcpu_cpu_opt = &arm_arch_any;
|
22404 |
|
|
#endif
|
22405 |
|
|
|
22406 |
|
|
ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
|
22407 |
|
|
|
22408 |
|
|
autoselect_thumb_from_cpu_variant ();
|
22409 |
|
|
|
22410 |
|
|
arm_arch_used = thumb_arch_used = arm_arch_none;
|
22411 |
|
|
|
22412 |
|
|
#if defined OBJ_COFF || defined OBJ_ELF
|
22413 |
|
|
{
|
22414 |
|
|
unsigned int flags = 0;
|
22415 |
|
|
|
22416 |
|
|
#if defined OBJ_ELF
|
22417 |
|
|
flags = meabi_flags;
|
22418 |
|
|
|
22419 |
|
|
switch (meabi_flags)
|
22420 |
|
|
{
|
22421 |
|
|
case EF_ARM_EABI_UNKNOWN:
|
22422 |
|
|
#endif
|
22423 |
|
|
/* Set the flags in the private structure. */
|
22424 |
|
|
if (uses_apcs_26) flags |= F_APCS26;
|
22425 |
|
|
if (support_interwork) flags |= F_INTERWORK;
|
22426 |
|
|
if (uses_apcs_float) flags |= F_APCS_FLOAT;
|
22427 |
|
|
if (pic_code) flags |= F_PIC;
|
22428 |
|
|
if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
|
22429 |
|
|
flags |= F_SOFT_FLOAT;
|
22430 |
|
|
|
22431 |
|
|
switch (mfloat_abi_opt)
|
22432 |
|
|
{
|
22433 |
|
|
case ARM_FLOAT_ABI_SOFT:
|
22434 |
|
|
case ARM_FLOAT_ABI_SOFTFP:
|
22435 |
|
|
flags |= F_SOFT_FLOAT;
|
22436 |
|
|
break;
|
22437 |
|
|
|
22438 |
|
|
case ARM_FLOAT_ABI_HARD:
|
22439 |
|
|
if (flags & F_SOFT_FLOAT)
|
22440 |
|
|
as_bad (_("hard-float conflicts with specified fpu"));
|
22441 |
|
|
break;
|
22442 |
|
|
}
|
22443 |
|
|
|
22444 |
|
|
/* Using pure-endian doubles (even if soft-float). */
|
22445 |
|
|
if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
|
22446 |
|
|
flags |= F_VFP_FLOAT;
|
22447 |
|
|
|
22448 |
|
|
#if defined OBJ_ELF
|
22449 |
|
|
if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
|
22450 |
|
|
flags |= EF_ARM_MAVERICK_FLOAT;
|
22451 |
|
|
break;
|
22452 |
|
|
|
22453 |
|
|
case EF_ARM_EABI_VER4:
|
22454 |
|
|
case EF_ARM_EABI_VER5:
|
22455 |
|
|
/* No additional flags to set. */
|
22456 |
|
|
break;
|
22457 |
|
|
|
22458 |
|
|
default:
|
22459 |
|
|
abort ();
|
22460 |
|
|
}
|
22461 |
|
|
#endif
|
22462 |
|
|
bfd_set_private_flags (stdoutput, flags);
|
22463 |
|
|
|
22464 |
|
|
/* We have run out flags in the COFF header to encode the
|
22465 |
|
|
status of ATPCS support, so instead we create a dummy,
|
22466 |
|
|
empty, debug section called .arm.atpcs. */
|
22467 |
|
|
if (atpcs)
|
22468 |
|
|
{
|
22469 |
|
|
asection * sec;
|
22470 |
|
|
|
22471 |
|
|
sec = bfd_make_section (stdoutput, ".arm.atpcs");
|
22472 |
|
|
|
22473 |
|
|
if (sec != NULL)
|
22474 |
|
|
{
|
22475 |
|
|
bfd_set_section_flags
|
22476 |
|
|
(stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
|
22477 |
|
|
bfd_set_section_size (stdoutput, sec, 0);
|
22478 |
|
|
bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
|
22479 |
|
|
}
|
22480 |
|
|
}
|
22481 |
|
|
}
|
22482 |
|
|
#endif
|
22483 |
|
|
|
22484 |
|
|
/* Record the CPU type as well. */
|
22485 |
|
|
if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
|
22486 |
|
|
mach = bfd_mach_arm_iWMMXt2;
|
22487 |
|
|
else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
|
22488 |
|
|
mach = bfd_mach_arm_iWMMXt;
|
22489 |
|
|
else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
|
22490 |
|
|
mach = bfd_mach_arm_XScale;
|
22491 |
|
|
else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
|
22492 |
|
|
mach = bfd_mach_arm_ep9312;
|
22493 |
|
|
else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
|
22494 |
|
|
mach = bfd_mach_arm_5TE;
|
22495 |
|
|
else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
|
22496 |
|
|
{
|
22497 |
|
|
if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
|
22498 |
|
|
mach = bfd_mach_arm_5T;
|
22499 |
|
|
else
|
22500 |
|
|
mach = bfd_mach_arm_5;
|
22501 |
|
|
}
|
22502 |
|
|
else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
|
22503 |
|
|
{
|
22504 |
|
|
if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
|
22505 |
|
|
mach = bfd_mach_arm_4T;
|
22506 |
|
|
else
|
22507 |
|
|
mach = bfd_mach_arm_4;
|
22508 |
|
|
}
|
22509 |
|
|
else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
|
22510 |
|
|
mach = bfd_mach_arm_3M;
|
22511 |
|
|
else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
|
22512 |
|
|
mach = bfd_mach_arm_3;
|
22513 |
|
|
else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
|
22514 |
|
|
mach = bfd_mach_arm_2a;
|
22515 |
|
|
else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
|
22516 |
|
|
mach = bfd_mach_arm_2;
|
22517 |
|
|
else
|
22518 |
|
|
mach = bfd_mach_arm_unknown;
|
22519 |
|
|
|
22520 |
|
|
bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
|
22521 |
|
|
}
|
22522 |
|
|
|
22523 |
|
|
/* Command line processing. */
|
22524 |
|
|
|
22525 |
|
|
/* md_parse_option
|
22526 |
|
|
Invocation line includes a switch not recognized by the base assembler.
|
22527 |
|
|
See if it's a processor-specific option.
|
22528 |
|
|
|
22529 |
|
|
This routine is somewhat complicated by the need for backwards
|
22530 |
|
|
compatibility (since older releases of gcc can't be changed).
|
22531 |
|
|
The new options try to make the interface as compatible as
|
22532 |
|
|
possible with GCC.
|
22533 |
|
|
|
22534 |
|
|
New options (supported) are:
|
22535 |
|
|
|
22536 |
|
|
-mcpu=<cpu name> Assemble for selected processor
|
22537 |
|
|
-march=<architecture name> Assemble for selected architecture
|
22538 |
|
|
-mfpu=<fpu architecture> Assemble for selected FPU.
|
22539 |
|
|
-EB/-mbig-endian Big-endian
|
22540 |
|
|
-EL/-mlittle-endian Little-endian
|
22541 |
|
|
-k Generate PIC code
|
22542 |
|
|
-mthumb Start in Thumb mode
|
22543 |
|
|
-mthumb-interwork Code supports ARM/Thumb interworking
|
22544 |
|
|
|
22545 |
|
|
-m[no-]warn-deprecated Warn about deprecated features
|
22546 |
|
|
|
22547 |
|
|
For now we will also provide support for:
|
22548 |
|
|
|
22549 |
|
|
-mapcs-32 32-bit Program counter
|
22550 |
|
|
-mapcs-26 26-bit Program counter
|
22551 |
|
|
-macps-float Floats passed in FP registers
|
22552 |
|
|
-mapcs-reentrant Reentrant code
|
22553 |
|
|
-matpcs
|
22554 |
|
|
(sometime these will probably be replaced with -mapcs=<list of options>
|
22555 |
|
|
and -matpcs=<list of options>)
|
22556 |
|
|
|
22557 |
|
|
The remaining options are only supported for back-wards compatibility.
|
22558 |
|
|
Cpu variants, the arm part is optional:
|
22559 |
|
|
-m[arm]1 Currently not supported.
|
22560 |
|
|
-m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
|
22561 |
|
|
-m[arm]3 Arm 3 processor
|
22562 |
|
|
-m[arm]6[xx], Arm 6 processors
|
22563 |
|
|
-m[arm]7[xx][t][[d]m] Arm 7 processors
|
22564 |
|
|
-m[arm]8[10] Arm 8 processors
|
22565 |
|
|
-m[arm]9[20][tdmi] Arm 9 processors
|
22566 |
|
|
-mstrongarm[110[0]] StrongARM processors
|
22567 |
|
|
-mxscale XScale processors
|
22568 |
|
|
-m[arm]v[2345[t[e]]] Arm architectures
|
22569 |
|
|
-mall All (except the ARM1)
|
22570 |
|
|
FP variants:
|
22571 |
|
|
-mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
|
22572 |
|
|
-mfpe-old (No float load/store multiples)
|
22573 |
|
|
-mvfpxd VFP Single precision
|
22574 |
|
|
-mvfp All VFP
|
22575 |
|
|
-mno-fpu Disable all floating point instructions
|
22576 |
|
|
|
22577 |
|
|
The following CPU names are recognized:
|
22578 |
|
|
arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
|
22579 |
|
|
arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
|
22580 |
|
|
arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
|
22581 |
|
|
arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
|
22582 |
|
|
arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
|
22583 |
|
|
arm10t arm10e, arm1020t, arm1020e, arm10200e,
|
22584 |
|
|
strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
|
22585 |
|
|
|
22586 |
|
|
*/
|
22587 |
|
|
|
22588 |
|
|
const char * md_shortopts = "m:k";
|
22589 |
|
|
|
22590 |
|
|
#ifdef ARM_BI_ENDIAN
|
22591 |
|
|
#define OPTION_EB (OPTION_MD_BASE + 0)
|
22592 |
|
|
#define OPTION_EL (OPTION_MD_BASE + 1)
|
22593 |
|
|
#else
|
22594 |
|
|
#if TARGET_BYTES_BIG_ENDIAN
|
22595 |
|
|
#define OPTION_EB (OPTION_MD_BASE + 0)
|
22596 |
|
|
#else
|
22597 |
|
|
#define OPTION_EL (OPTION_MD_BASE + 1)
|
22598 |
|
|
#endif
|
22599 |
|
|
#endif
|
22600 |
|
|
#define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
|
22601 |
|
|
|
22602 |
|
|
struct option md_longopts[] =
|
22603 |
|
|
{
|
22604 |
|
|
#ifdef OPTION_EB
|
22605 |
|
|
{"EB", no_argument, NULL, OPTION_EB},
|
22606 |
|
|
#endif
|
22607 |
|
|
#ifdef OPTION_EL
|
22608 |
|
|
{"EL", no_argument, NULL, OPTION_EL},
|
22609 |
|
|
#endif
|
22610 |
|
|
{"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
|
22611 |
|
|
{NULL, no_argument, NULL, 0}
|
22612 |
|
|
};
|
22613 |
|
|
|
22614 |
|
|
size_t md_longopts_size = sizeof (md_longopts);
|
22615 |
|
|
|
22616 |
|
|
struct arm_option_table
|
22617 |
|
|
{
|
22618 |
|
|
char *option; /* Option name to match. */
|
22619 |
|
|
char *help; /* Help information. */
|
22620 |
|
|
int *var; /* Variable to change. */
|
22621 |
|
|
int value; /* What to change it to. */
|
22622 |
|
|
char *deprecated; /* If non-null, print this message. */
|
22623 |
|
|
};
|
22624 |
|
|
|
22625 |
|
|
struct arm_option_table arm_opts[] =
|
22626 |
|
|
{
|
22627 |
|
|
{"k", N_("generate PIC code"), &pic_code, 1, NULL},
|
22628 |
|
|
{"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
|
22629 |
|
|
{"mthumb-interwork", N_("support ARM/Thumb interworking"),
|
22630 |
|
|
&support_interwork, 1, NULL},
|
22631 |
|
|
{"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
|
22632 |
|
|
{"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
|
22633 |
|
|
{"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
|
22634 |
|
|
1, NULL},
|
22635 |
|
|
{"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
|
22636 |
|
|
{"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
|
22637 |
|
|
{"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
|
22638 |
|
|
{"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
|
22639 |
|
|
NULL},
|
22640 |
|
|
|
22641 |
|
|
/* These are recognized by the assembler, but have no affect on code. */
|
22642 |
|
|
{"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
|
22643 |
|
|
{"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
|
22644 |
|
|
|
22645 |
|
|
{"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
|
22646 |
|
|
{"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
|
22647 |
|
|
&warn_on_deprecated, 0, NULL},
|
22648 |
|
|
{NULL, NULL, NULL, 0, NULL}
|
22649 |
|
|
};
|
22650 |
|
|
|
22651 |
|
|
struct arm_legacy_option_table
|
22652 |
|
|
{
|
22653 |
|
|
char *option; /* Option name to match. */
|
22654 |
|
|
const arm_feature_set **var; /* Variable to change. */
|
22655 |
|
|
const arm_feature_set value; /* What to change it to. */
|
22656 |
|
|
char *deprecated; /* If non-null, print this message. */
|
22657 |
|
|
};
|
22658 |
|
|
|
22659 |
|
|
const struct arm_legacy_option_table arm_legacy_opts[] =
|
22660 |
|
|
{
|
22661 |
|
|
/* DON'T add any new processors to this list -- we want the whole list
|
22662 |
|
|
to go away... Add them to the processors table instead. */
|
22663 |
|
|
{"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
|
22664 |
|
|
{"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
|
22665 |
|
|
{"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
|
22666 |
|
|
{"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
|
22667 |
|
|
{"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
|
22668 |
|
|
{"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
|
22669 |
|
|
{"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
|
22670 |
|
|
{"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
|
22671 |
|
|
{"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
|
22672 |
|
|
{"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
|
22673 |
|
|
{"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
|
22674 |
|
|
{"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
|
22675 |
|
|
{"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
|
22676 |
|
|
{"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
|
22677 |
|
|
{"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
|
22678 |
|
|
{"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
|
22679 |
|
|
{"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
|
22680 |
|
|
{"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
|
22681 |
|
|
{"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
|
22682 |
|
|
{"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
|
22683 |
|
|
{"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
|
22684 |
|
|
{"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
|
22685 |
|
|
{"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
|
22686 |
|
|
{"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
|
22687 |
|
|
{"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
|
22688 |
|
|
{"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
|
22689 |
|
|
{"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
|
22690 |
|
|
{"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
|
22691 |
|
|
{"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
|
22692 |
|
|
{"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
|
22693 |
|
|
{"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
|
22694 |
|
|
{"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
|
22695 |
|
|
{"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
|
22696 |
|
|
{"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
|
22697 |
|
|
{"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
|
22698 |
|
|
{"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
|
22699 |
|
|
{"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
|
22700 |
|
|
{"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
|
22701 |
|
|
{"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
|
22702 |
|
|
{"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
|
22703 |
|
|
{"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
|
22704 |
|
|
{"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
|
22705 |
|
|
{"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
|
22706 |
|
|
{"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
|
22707 |
|
|
{"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
|
22708 |
|
|
{"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
|
22709 |
|
|
{"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
|
22710 |
|
|
{"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
|
22711 |
|
|
{"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
|
22712 |
|
|
{"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
|
22713 |
|
|
{"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
|
22714 |
|
|
{"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
|
22715 |
|
|
{"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
|
22716 |
|
|
{"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
|
22717 |
|
|
{"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
|
22718 |
|
|
{"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
|
22719 |
|
|
{"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
|
22720 |
|
|
{"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
|
22721 |
|
|
{"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
|
22722 |
|
|
{"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
|
22723 |
|
|
{"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
|
22724 |
|
|
{"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
|
22725 |
|
|
{"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
|
22726 |
|
|
{"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
|
22727 |
|
|
{"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
|
22728 |
|
|
{"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
|
22729 |
|
|
{"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
|
22730 |
|
|
{"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
|
22731 |
|
|
{"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
|
22732 |
|
|
{"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
|
22733 |
|
|
N_("use -mcpu=strongarm110")},
|
22734 |
|
|
{"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
|
22735 |
|
|
N_("use -mcpu=strongarm1100")},
|
22736 |
|
|
{"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
|
22737 |
|
|
N_("use -mcpu=strongarm1110")},
|
22738 |
|
|
{"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
|
22739 |
|
|
{"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
|
22740 |
|
|
{"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
|
22741 |
|
|
|
22742 |
|
|
/* Architecture variants -- don't add any more to this list either. */
|
22743 |
|
|
{"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
|
22744 |
|
|
{"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
|
22745 |
|
|
{"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
|
22746 |
|
|
{"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
|
22747 |
|
|
{"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
|
22748 |
|
|
{"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
|
22749 |
|
|
{"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
|
22750 |
|
|
{"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
|
22751 |
|
|
{"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
|
22752 |
|
|
{"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
|
22753 |
|
|
{"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
|
22754 |
|
|
{"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
|
22755 |
|
|
{"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
|
22756 |
|
|
{"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
|
22757 |
|
|
{"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
|
22758 |
|
|
{"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
|
22759 |
|
|
{"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
|
22760 |
|
|
{"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
|
22761 |
|
|
|
22762 |
|
|
/* Floating point variants -- don't add any more to this list either. */
|
22763 |
|
|
{"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
|
22764 |
|
|
{"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
|
22765 |
|
|
{"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
|
22766 |
|
|
{"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
|
22767 |
|
|
N_("use either -mfpu=softfpa or -mfpu=softvfp")},
|
22768 |
|
|
|
22769 |
|
|
{NULL, NULL, ARM_ARCH_NONE, NULL}
|
22770 |
|
|
};
|
22771 |
|
|
|
22772 |
|
|
struct arm_cpu_option_table
|
22773 |
|
|
{
|
22774 |
|
|
char *name;
|
22775 |
|
|
const arm_feature_set value;
|
22776 |
|
|
/* For some CPUs we assume an FPU unless the user explicitly sets
|
22777 |
|
|
-mfpu=... */
|
22778 |
|
|
const arm_feature_set default_fpu;
|
22779 |
|
|
/* The canonical name of the CPU, or NULL to use NAME converted to upper
|
22780 |
|
|
case. */
|
22781 |
|
|
const char *canonical_name;
|
22782 |
|
|
};
|
22783 |
|
|
|
22784 |
|
|
/* This list should, at a minimum, contain all the cpu names
|
22785 |
|
|
recognized by GCC. */
|
22786 |
|
|
static const struct arm_cpu_option_table arm_cpus[] =
|
22787 |
|
|
{
|
22788 |
|
|
{"all", ARM_ANY, FPU_ARCH_FPA, NULL},
|
22789 |
|
|
{"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
|
22790 |
|
|
{"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
|
22791 |
|
|
{"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
|
22792 |
|
|
{"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
|
22793 |
|
|
{"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
|
22794 |
|
|
{"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
|
22795 |
|
|
{"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
|
22796 |
|
|
{"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
|
22797 |
|
|
{"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
|
22798 |
|
|
{"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
|
22799 |
|
|
{"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
|
22800 |
|
|
{"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
|
22801 |
|
|
{"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
|
22802 |
|
|
{"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
|
22803 |
|
|
{"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
|
22804 |
|
|
{"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
|
22805 |
|
|
{"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
|
22806 |
|
|
{"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
|
22807 |
|
|
{"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
|
22808 |
|
|
{"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
|
22809 |
|
|
{"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
|
22810 |
|
|
{"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
|
22811 |
|
|
{"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
|
22812 |
|
|
{"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
|
22813 |
|
|
{"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
|
22814 |
|
|
{"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
|
22815 |
|
|
{"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
|
22816 |
|
|
{"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
|
22817 |
|
|
{"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
|
22818 |
|
|
{"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
|
22819 |
|
|
{"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
|
22820 |
|
|
{"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
|
22821 |
|
|
{"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
|
22822 |
|
|
{"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
|
22823 |
|
|
{"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
|
22824 |
|
|
{"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
|
22825 |
|
|
{"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
|
22826 |
|
|
{"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
|
22827 |
|
|
{"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
|
22828 |
|
|
{"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
|
22829 |
|
|
{"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
|
22830 |
|
|
{"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
|
22831 |
|
|
{"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
|
22832 |
|
|
{"fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
|
22833 |
|
|
{"fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
|
22834 |
|
|
/* For V5 or later processors we default to using VFP; but the user
|
22835 |
|
|
should really set the FPU type explicitly. */
|
22836 |
|
|
{"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
|
22837 |
|
|
{"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
|
22838 |
|
|
{"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
|
22839 |
|
|
{"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
|
22840 |
|
|
{"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
|
22841 |
|
|
{"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
|
22842 |
|
|
{"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
|
22843 |
|
|
{"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
|
22844 |
|
|
{"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
|
22845 |
|
|
{"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
|
22846 |
|
|
{"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
|
22847 |
|
|
{"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
|
22848 |
|
|
{"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
|
22849 |
|
|
{"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
|
22850 |
|
|
{"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
|
22851 |
|
|
{"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
|
22852 |
|
|
{"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
|
22853 |
|
|
{"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
|
22854 |
|
|
{"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
|
22855 |
|
|
{"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
|
22856 |
|
|
{"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
|
22857 |
|
|
{"fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
|
22858 |
|
|
{"fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
|
22859 |
|
|
{"fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
|
22860 |
|
|
{"fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
|
22861 |
|
|
{"fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
|
22862 |
|
|
{"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
|
22863 |
|
|
{"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
|
22864 |
|
|
{"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
|
22865 |
|
|
{"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
|
22866 |
|
|
{"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"},
|
22867 |
|
|
{"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"},
|
22868 |
|
|
{"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
|
22869 |
|
|
{"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
|
22870 |
|
|
{"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
|
22871 |
|
|
{"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
|
22872 |
|
|
{"cortex-a5", ARM_ARCH_V7A_MP_SEC,
|
22873 |
|
|
FPU_NONE, "Cortex-A5"},
|
22874 |
|
|
{"cortex-a8", ARM_ARCH_V7A_SEC,
|
22875 |
|
|
ARM_FEATURE (0, FPU_VFP_V3
|
22876 |
|
|
| FPU_NEON_EXT_V1),
|
22877 |
|
|
"Cortex-A8"},
|
22878 |
|
|
{"cortex-a9", ARM_ARCH_V7A_MP_SEC,
|
22879 |
|
|
ARM_FEATURE (0, FPU_VFP_V3
|
22880 |
|
|
| FPU_NEON_EXT_V1),
|
22881 |
|
|
"Cortex-A9"},
|
22882 |
|
|
{"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
|
22883 |
|
|
FPU_ARCH_NEON_VFP_V4,
|
22884 |
|
|
"Cortex-A15"},
|
22885 |
|
|
{"cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"},
|
22886 |
|
|
{"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
|
22887 |
|
|
"Cortex-R4F"},
|
22888 |
|
|
{"cortex-r5", ARM_ARCH_V7R_IDIV,
|
22889 |
|
|
FPU_NONE, "Cortex-R5"},
|
22890 |
|
|
{"cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"},
|
22891 |
|
|
{"cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"},
|
22892 |
|
|
{"cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"},
|
22893 |
|
|
{"cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"},
|
22894 |
|
|
/* ??? XSCALE is really an architecture. */
|
22895 |
|
|
{"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
|
22896 |
|
|
/* ??? iwmmxt is not a processor. */
|
22897 |
|
|
{"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
|
22898 |
|
|
{"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL},
|
22899 |
|
|
{"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
|
22900 |
|
|
/* Maverick */
|
22901 |
|
|
{"ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
|
22902 |
|
|
{NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL}
|
22903 |
|
|
};
|
22904 |
|
|
|
22905 |
|
|
struct arm_arch_option_table
|
22906 |
|
|
{
|
22907 |
|
|
char *name;
|
22908 |
|
|
const arm_feature_set value;
|
22909 |
|
|
const arm_feature_set default_fpu;
|
22910 |
|
|
};
|
22911 |
|
|
|
22912 |
|
|
/* This list should, at a minimum, contain all the architecture names
|
22913 |
|
|
recognized by GCC. */
|
22914 |
|
|
static const struct arm_arch_option_table arm_archs[] =
|
22915 |
|
|
{
|
22916 |
|
|
{"all", ARM_ANY, FPU_ARCH_FPA},
|
22917 |
|
|
{"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
|
22918 |
|
|
{"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
|
22919 |
|
|
{"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
|
22920 |
|
|
{"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
|
22921 |
|
|
{"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
|
22922 |
|
|
{"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
|
22923 |
|
|
{"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
|
22924 |
|
|
{"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
|
22925 |
|
|
{"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
|
22926 |
|
|
{"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
|
22927 |
|
|
{"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
|
22928 |
|
|
{"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
|
22929 |
|
|
{"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
|
22930 |
|
|
{"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
|
22931 |
|
|
{"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
|
22932 |
|
|
{"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
|
22933 |
|
|
{"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
|
22934 |
|
|
{"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
|
22935 |
|
|
{"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
|
22936 |
|
|
{"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
|
22937 |
|
|
{"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
|
22938 |
|
|
{"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
|
22939 |
|
|
{"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
|
22940 |
|
|
{"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
|
22941 |
|
|
{"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
|
22942 |
|
|
{"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP},
|
22943 |
|
|
{"armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP},
|
22944 |
|
|
{"armv7", ARM_ARCH_V7, FPU_ARCH_VFP},
|
22945 |
|
|
/* The official spelling of the ARMv7 profile variants is the dashed form.
|
22946 |
|
|
Accept the non-dashed form for compatibility with old toolchains. */
|
22947 |
|
|
{"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP},
|
22948 |
|
|
{"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP},
|
22949 |
|
|
{"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP},
|
22950 |
|
|
{"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP},
|
22951 |
|
|
{"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP},
|
22952 |
|
|
{"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP},
|
22953 |
|
|
{"armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP},
|
22954 |
|
|
{"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
|
22955 |
|
|
{"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
|
22956 |
|
|
{"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP},
|
22957 |
|
|
{NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
|
22958 |
|
|
};
|
22959 |
|
|
|
22960 |
|
|
/* ISA extensions in the co-processor and main instruction set space. */
|
22961 |
|
|
struct arm_option_extension_value_table
|
22962 |
|
|
{
|
22963 |
|
|
char *name;
|
22964 |
|
|
const arm_feature_set value;
|
22965 |
|
|
const arm_feature_set allowed_archs;
|
22966 |
|
|
};
|
22967 |
|
|
|
22968 |
|
|
/* The following table must be in alphabetical order with a NULL last entry.
|
22969 |
|
|
*/
|
22970 |
|
|
static const struct arm_option_extension_value_table arm_extensions[] =
|
22971 |
|
|
{
|
22972 |
|
|
{"idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
|
22973 |
|
|
ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)},
|
22974 |
|
|
{"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY},
|
22975 |
|
|
{"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY},
|
22976 |
|
|
{"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY},
|
22977 |
|
|
{"mp", ARM_FEATURE (ARM_EXT_MP, 0),
|
22978 |
|
|
ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)},
|
22979 |
|
|
{"os", ARM_FEATURE (ARM_EXT_OS, 0),
|
22980 |
|
|
ARM_FEATURE (ARM_EXT_V6M, 0)},
|
22981 |
|
|
{"sec", ARM_FEATURE (ARM_EXT_SEC, 0),
|
22982 |
|
|
ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)},
|
22983 |
|
|
{"virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV | ARM_EXT_DIV, 0),
|
22984 |
|
|
ARM_FEATURE (ARM_EXT_V7A, 0)},
|
22985 |
|
|
{"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY},
|
22986 |
|
|
{NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
|
22987 |
|
|
};
|
22988 |
|
|
|
22989 |
|
|
/* ISA floating-point and Advanced SIMD extensions. */
|
22990 |
|
|
struct arm_option_fpu_value_table
|
22991 |
|
|
{
|
22992 |
|
|
char *name;
|
22993 |
|
|
const arm_feature_set value;
|
22994 |
|
|
};
|
22995 |
|
|
|
22996 |
|
|
/* This list should, at a minimum, contain all the fpu names
|
22997 |
|
|
recognized by GCC. */
|
22998 |
|
|
static const struct arm_option_fpu_value_table arm_fpus[] =
|
22999 |
|
|
{
|
23000 |
|
|
{"softfpa", FPU_NONE},
|
23001 |
|
|
{"fpe", FPU_ARCH_FPE},
|
23002 |
|
|
{"fpe2", FPU_ARCH_FPE},
|
23003 |
|
|
{"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
|
23004 |
|
|
{"fpa", FPU_ARCH_FPA},
|
23005 |
|
|
{"fpa10", FPU_ARCH_FPA},
|
23006 |
|
|
{"fpa11", FPU_ARCH_FPA},
|
23007 |
|
|
{"arm7500fe", FPU_ARCH_FPA},
|
23008 |
|
|
{"softvfp", FPU_ARCH_VFP},
|
23009 |
|
|
{"softvfp+vfp", FPU_ARCH_VFP_V2},
|
23010 |
|
|
{"vfp", FPU_ARCH_VFP_V2},
|
23011 |
|
|
{"vfp9", FPU_ARCH_VFP_V2},
|
23012 |
|
|
{"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
|
23013 |
|
|
{"vfp10", FPU_ARCH_VFP_V2},
|
23014 |
|
|
{"vfp10-r0", FPU_ARCH_VFP_V1},
|
23015 |
|
|
{"vfpxd", FPU_ARCH_VFP_V1xD},
|
23016 |
|
|
{"vfpv2", FPU_ARCH_VFP_V2},
|
23017 |
|
|
{"vfpv3", FPU_ARCH_VFP_V3},
|
23018 |
|
|
{"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
|
23019 |
|
|
{"vfpv3-d16", FPU_ARCH_VFP_V3D16},
|
23020 |
|
|
{"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
|
23021 |
|
|
{"vfpv3xd", FPU_ARCH_VFP_V3xD},
|
23022 |
|
|
{"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
|
23023 |
|
|
{"arm1020t", FPU_ARCH_VFP_V1},
|
23024 |
|
|
{"arm1020e", FPU_ARCH_VFP_V2},
|
23025 |
|
|
{"arm1136jfs", FPU_ARCH_VFP_V2},
|
23026 |
|
|
{"arm1136jf-s", FPU_ARCH_VFP_V2},
|
23027 |
|
|
{"maverick", FPU_ARCH_MAVERICK},
|
23028 |
|
|
{"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
|
23029 |
|
|
{"neon-fp16", FPU_ARCH_NEON_FP16},
|
23030 |
|
|
{"vfpv4", FPU_ARCH_VFP_V4},
|
23031 |
|
|
{"vfpv4-d16", FPU_ARCH_VFP_V4D16},
|
23032 |
|
|
{"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
|
23033 |
|
|
{"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
|
23034 |
|
|
{NULL, ARM_ARCH_NONE}
|
23035 |
|
|
};
|
23036 |
|
|
|
23037 |
|
|
struct arm_option_value_table
|
23038 |
|
|
{
|
23039 |
|
|
char *name;
|
23040 |
|
|
long value;
|
23041 |
|
|
};
|
23042 |
|
|
|
23043 |
|
|
static const struct arm_option_value_table arm_float_abis[] =
|
23044 |
|
|
{
|
23045 |
|
|
{"hard", ARM_FLOAT_ABI_HARD},
|
23046 |
|
|
{"softfp", ARM_FLOAT_ABI_SOFTFP},
|
23047 |
|
|
{"soft", ARM_FLOAT_ABI_SOFT},
|
23048 |
|
|
{NULL, 0}
|
23049 |
|
|
};
|
23050 |
|
|
|
23051 |
|
|
#ifdef OBJ_ELF
|
23052 |
|
|
/* We only know how to output GNU and ver 4/5 (AAELF) formats. */
|
23053 |
|
|
static const struct arm_option_value_table arm_eabis[] =
|
23054 |
|
|
{
|
23055 |
|
|
{"gnu", EF_ARM_EABI_UNKNOWN},
|
23056 |
|
|
{"4", EF_ARM_EABI_VER4},
|
23057 |
|
|
{"5", EF_ARM_EABI_VER5},
|
23058 |
|
|
{NULL, 0}
|
23059 |
|
|
};
|
23060 |
|
|
#endif
|
23061 |
|
|
|
23062 |
|
|
struct arm_long_option_table
|
23063 |
|
|
{
|
23064 |
|
|
char * option; /* Substring to match. */
|
23065 |
|
|
char * help; /* Help information. */
|
23066 |
|
|
int (* func) (char * subopt); /* Function to decode sub-option. */
|
23067 |
|
|
char * deprecated; /* If non-null, print this message. */
|
23068 |
|
|
};
|
23069 |
|
|
|
23070 |
|
|
static bfd_boolean
|
23071 |
|
|
arm_parse_extension (char * str, const arm_feature_set **opt_p)
|
23072 |
|
|
{
|
23073 |
|
|
arm_feature_set *ext_set = (arm_feature_set *)
|
23074 |
|
|
xmalloc (sizeof (arm_feature_set));
|
23075 |
|
|
|
23076 |
|
|
/* We insist on extensions being specified in alphabetical order, and with
|
23077 |
|
|
extensions being added before being removed. We achieve this by having
|
23078 |
|
|
the global ARM_EXTENSIONS table in alphabetical order, and using the
|
23079 |
|
|
ADDING_VALUE variable to indicate whether we are adding an extension (1)
|
23080 |
|
|
or removing it (0) and only allowing it to change in the order
|
23081 |
|
|
-1 -> 1 -> 0. */
|
23082 |
|
|
const struct arm_option_extension_value_table * opt = NULL;
|
23083 |
|
|
int adding_value = -1;
|
23084 |
|
|
|
23085 |
|
|
/* Copy the feature set, so that we can modify it. */
|
23086 |
|
|
*ext_set = **opt_p;
|
23087 |
|
|
*opt_p = ext_set;
|
23088 |
|
|
|
23089 |
|
|
while (str != NULL && *str != 0)
|
23090 |
|
|
{
|
23091 |
|
|
char * ext;
|
23092 |
|
|
size_t optlen;
|
23093 |
|
|
|
23094 |
|
|
if (*str != '+')
|
23095 |
|
|
{
|
23096 |
|
|
as_bad (_("invalid architectural extension"));
|
23097 |
|
|
return FALSE;
|
23098 |
|
|
}
|
23099 |
|
|
|
23100 |
|
|
str++;
|
23101 |
|
|
ext = strchr (str, '+');
|
23102 |
|
|
|
23103 |
|
|
if (ext != NULL)
|
23104 |
|
|
optlen = ext - str;
|
23105 |
|
|
else
|
23106 |
|
|
optlen = strlen (str);
|
23107 |
|
|
|
23108 |
|
|
if (optlen >= 2
|
23109 |
|
|
&& strncmp (str, "no", 2) == 0)
|
23110 |
|
|
{
|
23111 |
|
|
if (adding_value != 0)
|
23112 |
|
|
{
|
23113 |
|
|
adding_value = 0;
|
23114 |
|
|
opt = arm_extensions;
|
23115 |
|
|
}
|
23116 |
|
|
|
23117 |
|
|
optlen -= 2;
|
23118 |
|
|
str += 2;
|
23119 |
|
|
}
|
23120 |
|
|
else if (optlen > 0)
|
23121 |
|
|
{
|
23122 |
|
|
if (adding_value == -1)
|
23123 |
|
|
{
|
23124 |
|
|
adding_value = 1;
|
23125 |
|
|
opt = arm_extensions;
|
23126 |
|
|
}
|
23127 |
|
|
else if (adding_value != 1)
|
23128 |
|
|
{
|
23129 |
|
|
as_bad (_("must specify extensions to add before specifying "
|
23130 |
|
|
"those to remove"));
|
23131 |
|
|
return FALSE;
|
23132 |
|
|
}
|
23133 |
|
|
}
|
23134 |
|
|
|
23135 |
|
|
if (optlen == 0)
|
23136 |
|
|
{
|
23137 |
|
|
as_bad (_("missing architectural extension"));
|
23138 |
|
|
return FALSE;
|
23139 |
|
|
}
|
23140 |
|
|
|
23141 |
|
|
gas_assert (adding_value != -1);
|
23142 |
|
|
gas_assert (opt != NULL);
|
23143 |
|
|
|
23144 |
|
|
/* Scan over the options table trying to find an exact match. */
|
23145 |
|
|
for (; opt->name != NULL; opt++)
|
23146 |
|
|
if (strncmp (opt->name, str, optlen) == 0
|
23147 |
|
|
&& strlen (opt->name) == optlen)
|
23148 |
|
|
{
|
23149 |
|
|
/* Check we can apply the extension to this architecture. */
|
23150 |
|
|
if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
|
23151 |
|
|
{
|
23152 |
|
|
as_bad (_("extension does not apply to the base architecture"));
|
23153 |
|
|
return FALSE;
|
23154 |
|
|
}
|
23155 |
|
|
|
23156 |
|
|
/* Add or remove the extension. */
|
23157 |
|
|
if (adding_value)
|
23158 |
|
|
ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
|
23159 |
|
|
else
|
23160 |
|
|
ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
|
23161 |
|
|
|
23162 |
|
|
break;
|
23163 |
|
|
}
|
23164 |
|
|
|
23165 |
|
|
if (opt->name == NULL)
|
23166 |
|
|
{
|
23167 |
|
|
/* Did we fail to find an extension because it wasn't specified in
|
23168 |
|
|
alphabetical order, or because it does not exist? */
|
23169 |
|
|
|
23170 |
|
|
for (opt = arm_extensions; opt->name != NULL; opt++)
|
23171 |
|
|
if (strncmp (opt->name, str, optlen) == 0)
|
23172 |
|
|
break;
|
23173 |
|
|
|
23174 |
|
|
if (opt->name == NULL)
|
23175 |
|
|
as_bad (_("unknown architectural extension `%s'"), str);
|
23176 |
|
|
else
|
23177 |
|
|
as_bad (_("architectural extensions must be specified in "
|
23178 |
|
|
"alphabetical order"));
|
23179 |
|
|
|
23180 |
|
|
return FALSE;
|
23181 |
|
|
}
|
23182 |
|
|
else
|
23183 |
|
|
{
|
23184 |
|
|
/* We should skip the extension we've just matched the next time
|
23185 |
|
|
round. */
|
23186 |
|
|
opt++;
|
23187 |
|
|
}
|
23188 |
|
|
|
23189 |
|
|
str = ext;
|
23190 |
|
|
};
|
23191 |
|
|
|
23192 |
|
|
return TRUE;
|
23193 |
|
|
}
|
23194 |
|
|
|
23195 |
|
|
static bfd_boolean
|
23196 |
|
|
arm_parse_cpu (char * str)
|
23197 |
|
|
{
|
23198 |
|
|
const struct arm_cpu_option_table * opt;
|
23199 |
|
|
char * ext = strchr (str, '+');
|
23200 |
|
|
int optlen;
|
23201 |
|
|
|
23202 |
|
|
if (ext != NULL)
|
23203 |
|
|
optlen = ext - str;
|
23204 |
|
|
else
|
23205 |
|
|
optlen = strlen (str);
|
23206 |
|
|
|
23207 |
|
|
if (optlen == 0)
|
23208 |
|
|
{
|
23209 |
|
|
as_bad (_("missing cpu name `%s'"), str);
|
23210 |
|
|
return FALSE;
|
23211 |
|
|
}
|
23212 |
|
|
|
23213 |
|
|
for (opt = arm_cpus; opt->name != NULL; opt++)
|
23214 |
|
|
if (strncmp (opt->name, str, optlen) == 0)
|
23215 |
|
|
{
|
23216 |
|
|
mcpu_cpu_opt = &opt->value;
|
23217 |
|
|
mcpu_fpu_opt = &opt->default_fpu;
|
23218 |
|
|
if (opt->canonical_name)
|
23219 |
|
|
strcpy (selected_cpu_name, opt->canonical_name);
|
23220 |
|
|
else
|
23221 |
|
|
{
|
23222 |
|
|
int i;
|
23223 |
|
|
|
23224 |
|
|
for (i = 0; i < optlen; i++)
|
23225 |
|
|
selected_cpu_name[i] = TOUPPER (opt->name[i]);
|
23226 |
|
|
selected_cpu_name[i] = 0;
|
23227 |
|
|
}
|
23228 |
|
|
|
23229 |
|
|
if (ext != NULL)
|
23230 |
|
|
return arm_parse_extension (ext, &mcpu_cpu_opt);
|
23231 |
|
|
|
23232 |
|
|
return TRUE;
|
23233 |
|
|
}
|
23234 |
|
|
|
23235 |
|
|
as_bad (_("unknown cpu `%s'"), str);
|
23236 |
|
|
return FALSE;
|
23237 |
|
|
}
|
23238 |
|
|
|
23239 |
|
|
static bfd_boolean
|
23240 |
|
|
arm_parse_arch (char * str)
|
23241 |
|
|
{
|
23242 |
|
|
const struct arm_arch_option_table *opt;
|
23243 |
|
|
char *ext = strchr (str, '+');
|
23244 |
|
|
int optlen;
|
23245 |
|
|
|
23246 |
|
|
if (ext != NULL)
|
23247 |
|
|
optlen = ext - str;
|
23248 |
|
|
else
|
23249 |
|
|
optlen = strlen (str);
|
23250 |
|
|
|
23251 |
|
|
if (optlen == 0)
|
23252 |
|
|
{
|
23253 |
|
|
as_bad (_("missing architecture name `%s'"), str);
|
23254 |
|
|
return FALSE;
|
23255 |
|
|
}
|
23256 |
|
|
|
23257 |
|
|
for (opt = arm_archs; opt->name != NULL; opt++)
|
23258 |
|
|
if (strncmp (opt->name, str, optlen) == 0)
|
23259 |
|
|
{
|
23260 |
|
|
march_cpu_opt = &opt->value;
|
23261 |
|
|
march_fpu_opt = &opt->default_fpu;
|
23262 |
|
|
strcpy (selected_cpu_name, opt->name);
|
23263 |
|
|
|
23264 |
|
|
if (ext != NULL)
|
23265 |
|
|
return arm_parse_extension (ext, &march_cpu_opt);
|
23266 |
|
|
|
23267 |
|
|
return TRUE;
|
23268 |
|
|
}
|
23269 |
|
|
|
23270 |
|
|
as_bad (_("unknown architecture `%s'\n"), str);
|
23271 |
|
|
return FALSE;
|
23272 |
|
|
}
|
23273 |
|
|
|
23274 |
|
|
static bfd_boolean
|
23275 |
|
|
arm_parse_fpu (char * str)
|
23276 |
|
|
{
|
23277 |
|
|
const struct arm_option_fpu_value_table * opt;
|
23278 |
|
|
|
23279 |
|
|
for (opt = arm_fpus; opt->name != NULL; opt++)
|
23280 |
|
|
if (streq (opt->name, str))
|
23281 |
|
|
{
|
23282 |
|
|
mfpu_opt = &opt->value;
|
23283 |
|
|
return TRUE;
|
23284 |
|
|
}
|
23285 |
|
|
|
23286 |
|
|
as_bad (_("unknown floating point format `%s'\n"), str);
|
23287 |
|
|
return FALSE;
|
23288 |
|
|
}
|
23289 |
|
|
|
23290 |
|
|
static bfd_boolean
|
23291 |
|
|
arm_parse_float_abi (char * str)
|
23292 |
|
|
{
|
23293 |
|
|
const struct arm_option_value_table * opt;
|
23294 |
|
|
|
23295 |
|
|
for (opt = arm_float_abis; opt->name != NULL; opt++)
|
23296 |
|
|
if (streq (opt->name, str))
|
23297 |
|
|
{
|
23298 |
|
|
mfloat_abi_opt = opt->value;
|
23299 |
|
|
return TRUE;
|
23300 |
|
|
}
|
23301 |
|
|
|
23302 |
|
|
as_bad (_("unknown floating point abi `%s'\n"), str);
|
23303 |
|
|
return FALSE;
|
23304 |
|
|
}
|
23305 |
|
|
|
23306 |
|
|
#ifdef OBJ_ELF
|
23307 |
|
|
static bfd_boolean
|
23308 |
|
|
arm_parse_eabi (char * str)
|
23309 |
|
|
{
|
23310 |
|
|
const struct arm_option_value_table *opt;
|
23311 |
|
|
|
23312 |
|
|
for (opt = arm_eabis; opt->name != NULL; opt++)
|
23313 |
|
|
if (streq (opt->name, str))
|
23314 |
|
|
{
|
23315 |
|
|
meabi_flags = opt->value;
|
23316 |
|
|
return TRUE;
|
23317 |
|
|
}
|
23318 |
|
|
as_bad (_("unknown EABI `%s'\n"), str);
|
23319 |
|
|
return FALSE;
|
23320 |
|
|
}
|
23321 |
|
|
#endif
|
23322 |
|
|
|
23323 |
|
|
static bfd_boolean
|
23324 |
|
|
arm_parse_it_mode (char * str)
|
23325 |
|
|
{
|
23326 |
|
|
bfd_boolean ret = TRUE;
|
23327 |
|
|
|
23328 |
|
|
if (streq ("arm", str))
|
23329 |
|
|
implicit_it_mode = IMPLICIT_IT_MODE_ARM;
|
23330 |
|
|
else if (streq ("thumb", str))
|
23331 |
|
|
implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
|
23332 |
|
|
else if (streq ("always", str))
|
23333 |
|
|
implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
|
23334 |
|
|
else if (streq ("never", str))
|
23335 |
|
|
implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
|
23336 |
|
|
else
|
23337 |
|
|
{
|
23338 |
|
|
as_bad (_("unknown implicit IT mode `%s', should be "\
|
23339 |
|
|
"arm, thumb, always, or never."), str);
|
23340 |
|
|
ret = FALSE;
|
23341 |
|
|
}
|
23342 |
|
|
|
23343 |
|
|
return ret;
|
23344 |
|
|
}
|
23345 |
|
|
|
23346 |
|
|
struct arm_long_option_table arm_long_opts[] =
|
23347 |
|
|
{
|
23348 |
|
|
{"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
|
23349 |
|
|
arm_parse_cpu, NULL},
|
23350 |
|
|
{"march=", N_("<arch name>\t assemble for architecture <arch name>"),
|
23351 |
|
|
arm_parse_arch, NULL},
|
23352 |
|
|
{"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
|
23353 |
|
|
arm_parse_fpu, NULL},
|
23354 |
|
|
{"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
|
23355 |
|
|
arm_parse_float_abi, NULL},
|
23356 |
|
|
#ifdef OBJ_ELF
|
23357 |
|
|
{"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
|
23358 |
|
|
arm_parse_eabi, NULL},
|
23359 |
|
|
#endif
|
23360 |
|
|
{"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
|
23361 |
|
|
arm_parse_it_mode, NULL},
|
23362 |
|
|
{NULL, NULL, 0, NULL}
|
23363 |
|
|
};
|
23364 |
|
|
|
23365 |
|
|
int
|
23366 |
|
|
md_parse_option (int c, char * arg)
|
23367 |
|
|
{
|
23368 |
|
|
struct arm_option_table *opt;
|
23369 |
|
|
const struct arm_legacy_option_table *fopt;
|
23370 |
|
|
struct arm_long_option_table *lopt;
|
23371 |
|
|
|
23372 |
|
|
switch (c)
|
23373 |
|
|
{
|
23374 |
|
|
#ifdef OPTION_EB
|
23375 |
|
|
case OPTION_EB:
|
23376 |
|
|
target_big_endian = 1;
|
23377 |
|
|
break;
|
23378 |
|
|
#endif
|
23379 |
|
|
|
23380 |
|
|
#ifdef OPTION_EL
|
23381 |
|
|
case OPTION_EL:
|
23382 |
|
|
target_big_endian = 0;
|
23383 |
|
|
break;
|
23384 |
|
|
#endif
|
23385 |
|
|
|
23386 |
|
|
case OPTION_FIX_V4BX:
|
23387 |
|
|
fix_v4bx = TRUE;
|
23388 |
|
|
break;
|
23389 |
|
|
|
23390 |
|
|
case 'a':
|
23391 |
|
|
/* Listing option. Just ignore these, we don't support additional
|
23392 |
|
|
ones. */
|
23393 |
|
|
return 0;
|
23394 |
|
|
|
23395 |
|
|
default:
|
23396 |
|
|
for (opt = arm_opts; opt->option != NULL; opt++)
|
23397 |
|
|
{
|
23398 |
|
|
if (c == opt->option[0]
|
23399 |
|
|
&& ((arg == NULL && opt->option[1] == 0)
|
23400 |
|
|
|| streq (arg, opt->option + 1)))
|
23401 |
|
|
{
|
23402 |
|
|
/* If the option is deprecated, tell the user. */
|
23403 |
|
|
if (warn_on_deprecated && opt->deprecated != NULL)
|
23404 |
|
|
as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
|
23405 |
|
|
arg ? arg : "", _(opt->deprecated));
|
23406 |
|
|
|
23407 |
|
|
if (opt->var != NULL)
|
23408 |
|
|
*opt->var = opt->value;
|
23409 |
|
|
|
23410 |
|
|
return 1;
|
23411 |
|
|
}
|
23412 |
|
|
}
|
23413 |
|
|
|
23414 |
|
|
for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
|
23415 |
|
|
{
|
23416 |
|
|
if (c == fopt->option[0]
|
23417 |
|
|
&& ((arg == NULL && fopt->option[1] == 0)
|
23418 |
|
|
|| streq (arg, fopt->option + 1)))
|
23419 |
|
|
{
|
23420 |
|
|
/* If the option is deprecated, tell the user. */
|
23421 |
|
|
if (warn_on_deprecated && fopt->deprecated != NULL)
|
23422 |
|
|
as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
|
23423 |
|
|
arg ? arg : "", _(fopt->deprecated));
|
23424 |
|
|
|
23425 |
|
|
if (fopt->var != NULL)
|
23426 |
|
|
*fopt->var = &fopt->value;
|
23427 |
|
|
|
23428 |
|
|
return 1;
|
23429 |
|
|
}
|
23430 |
|
|
}
|
23431 |
|
|
|
23432 |
|
|
for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
|
23433 |
|
|
{
|
23434 |
|
|
/* These options are expected to have an argument. */
|
23435 |
|
|
if (c == lopt->option[0]
|
23436 |
|
|
&& arg != NULL
|
23437 |
|
|
&& strncmp (arg, lopt->option + 1,
|
23438 |
|
|
strlen (lopt->option + 1)) == 0)
|
23439 |
|
|
{
|
23440 |
|
|
/* If the option is deprecated, tell the user. */
|
23441 |
|
|
if (warn_on_deprecated && lopt->deprecated != NULL)
|
23442 |
|
|
as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
|
23443 |
|
|
_(lopt->deprecated));
|
23444 |
|
|
|
23445 |
|
|
/* Call the sup-option parser. */
|
23446 |
|
|
return lopt->func (arg + strlen (lopt->option) - 1);
|
23447 |
|
|
}
|
23448 |
|
|
}
|
23449 |
|
|
|
23450 |
|
|
return 0;
|
23451 |
|
|
}
|
23452 |
|
|
|
23453 |
|
|
return 1;
|
23454 |
|
|
}
|
23455 |
|
|
|
23456 |
|
|
void
|
23457 |
|
|
md_show_usage (FILE * fp)
|
23458 |
|
|
{
|
23459 |
|
|
struct arm_option_table *opt;
|
23460 |
|
|
struct arm_long_option_table *lopt;
|
23461 |
|
|
|
23462 |
|
|
fprintf (fp, _(" ARM-specific assembler options:\n"));
|
23463 |
|
|
|
23464 |
|
|
for (opt = arm_opts; opt->option != NULL; opt++)
|
23465 |
|
|
if (opt->help != NULL)
|
23466 |
|
|
fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
|
23467 |
|
|
|
23468 |
|
|
for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
|
23469 |
|
|
if (lopt->help != NULL)
|
23470 |
|
|
fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
|
23471 |
|
|
|
23472 |
|
|
#ifdef OPTION_EB
|
23473 |
|
|
fprintf (fp, _("\
|
23474 |
|
|
-EB assemble code for a big-endian cpu\n"));
|
23475 |
|
|
#endif
|
23476 |
|
|
|
23477 |
|
|
#ifdef OPTION_EL
|
23478 |
|
|
fprintf (fp, _("\
|
23479 |
|
|
-EL assemble code for a little-endian cpu\n"));
|
23480 |
|
|
#endif
|
23481 |
|
|
|
23482 |
|
|
fprintf (fp, _("\
|
23483 |
|
|
--fix-v4bx Allow BX in ARMv4 code\n"));
|
23484 |
|
|
}
|
23485 |
|
|
|
23486 |
|
|
|
23487 |
|
|
#ifdef OBJ_ELF
|
23488 |
|
|
typedef struct
|
23489 |
|
|
{
|
23490 |
|
|
int val;
|
23491 |
|
|
arm_feature_set flags;
|
23492 |
|
|
} cpu_arch_ver_table;
|
23493 |
|
|
|
23494 |
|
|
/* Mapping from CPU features to EABI CPU arch values. Table must be sorted
|
23495 |
|
|
least features first. */
|
23496 |
|
|
static const cpu_arch_ver_table cpu_arch_ver[] =
|
23497 |
|
|
{
|
23498 |
|
|
{1, ARM_ARCH_V4},
|
23499 |
|
|
{2, ARM_ARCH_V4T},
|
23500 |
|
|
{3, ARM_ARCH_V5},
|
23501 |
|
|
{3, ARM_ARCH_V5T},
|
23502 |
|
|
{4, ARM_ARCH_V5TE},
|
23503 |
|
|
{5, ARM_ARCH_V5TEJ},
|
23504 |
|
|
{6, ARM_ARCH_V6},
|
23505 |
|
|
{9, ARM_ARCH_V6K},
|
23506 |
|
|
{7, ARM_ARCH_V6Z},
|
23507 |
|
|
{11, ARM_ARCH_V6M},
|
23508 |
|
|
{12, ARM_ARCH_V6SM},
|
23509 |
|
|
{8, ARM_ARCH_V6T2},
|
23510 |
|
|
{10, ARM_ARCH_V7A},
|
23511 |
|
|
{10, ARM_ARCH_V7R},
|
23512 |
|
|
{10, ARM_ARCH_V7M},
|
23513 |
|
|
{0, ARM_ARCH_NONE}
|
23514 |
|
|
};
|
23515 |
|
|
|
23516 |
|
|
/* Set an attribute if it has not already been set by the user. */
|
23517 |
|
|
static void
|
23518 |
|
|
aeabi_set_attribute_int (int tag, int value)
|
23519 |
|
|
{
|
23520 |
|
|
if (tag < 1
|
23521 |
|
|
|| tag >= NUM_KNOWN_OBJ_ATTRIBUTES
|
23522 |
|
|
|| !attributes_set_explicitly[tag])
|
23523 |
|
|
bfd_elf_add_proc_attr_int (stdoutput, tag, value);
|
23524 |
|
|
}
|
23525 |
|
|
|
23526 |
|
|
static void
|
23527 |
|
|
aeabi_set_attribute_string (int tag, const char *value)
|
23528 |
|
|
{
|
23529 |
|
|
if (tag < 1
|
23530 |
|
|
|| tag >= NUM_KNOWN_OBJ_ATTRIBUTES
|
23531 |
|
|
|| !attributes_set_explicitly[tag])
|
23532 |
|
|
bfd_elf_add_proc_attr_string (stdoutput, tag, value);
|
23533 |
|
|
}
|
23534 |
|
|
|
23535 |
|
|
/* Set the public EABI object attributes. */
|
23536 |
|
|
static void
|
23537 |
|
|
aeabi_set_public_attributes (void)
|
23538 |
|
|
{
|
23539 |
|
|
int arch;
|
23540 |
|
|
int virt_sec = 0;
|
23541 |
|
|
arm_feature_set flags;
|
23542 |
|
|
arm_feature_set tmp;
|
23543 |
|
|
const cpu_arch_ver_table *p;
|
23544 |
|
|
|
23545 |
|
|
/* Choose the architecture based on the capabilities of the requested cpu
|
23546 |
|
|
(if any) and/or the instructions actually used. */
|
23547 |
|
|
ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
|
23548 |
|
|
ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
|
23549 |
|
|
ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
|
23550 |
|
|
/*Allow the user to override the reported architecture. */
|
23551 |
|
|
if (object_arch)
|
23552 |
|
|
{
|
23553 |
|
|
ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
|
23554 |
|
|
ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
|
23555 |
|
|
}
|
23556 |
|
|
|
23557 |
|
|
/* We need to make sure that the attributes do not identify us as v6S-M
|
23558 |
|
|
when the only v6S-M feature in use is the Operating System Extensions. */
|
23559 |
|
|
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
|
23560 |
|
|
if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
|
23561 |
|
|
ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
|
23562 |
|
|
|
23563 |
|
|
tmp = flags;
|
23564 |
|
|
arch = 0;
|
23565 |
|
|
for (p = cpu_arch_ver; p->val; p++)
|
23566 |
|
|
{
|
23567 |
|
|
if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
|
23568 |
|
|
{
|
23569 |
|
|
arch = p->val;
|
23570 |
|
|
ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
|
23571 |
|
|
}
|
23572 |
|
|
}
|
23573 |
|
|
|
23574 |
|
|
/* The table lookup above finds the last architecture to contribute
|
23575 |
|
|
a new feature. Unfortunately, Tag13 is a subset of the union of
|
23576 |
|
|
v6T2 and v7-M, so it is never seen as contributing a new feature.
|
23577 |
|
|
We can not search for the last entry which is entirely used,
|
23578 |
|
|
because if no CPU is specified we build up only those flags
|
23579 |
|
|
actually used. Perhaps we should separate out the specified
|
23580 |
|
|
and implicit cases. Avoid taking this path for -march=all by
|
23581 |
|
|
checking for contradictory v7-A / v7-M features. */
|
23582 |
|
|
if (arch == 10
|
23583 |
|
|
&& !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
|
23584 |
|
|
&& ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
|
23585 |
|
|
&& ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
|
23586 |
|
|
arch = 13;
|
23587 |
|
|
|
23588 |
|
|
/* Tag_CPU_name. */
|
23589 |
|
|
if (selected_cpu_name[0])
|
23590 |
|
|
{
|
23591 |
|
|
char *q;
|
23592 |
|
|
|
23593 |
|
|
q = selected_cpu_name;
|
23594 |
|
|
if (strncmp (q, "armv", 4) == 0)
|
23595 |
|
|
{
|
23596 |
|
|
int i;
|
23597 |
|
|
|
23598 |
|
|
q += 4;
|
23599 |
|
|
for (i = 0; q[i]; i++)
|
23600 |
|
|
q[i] = TOUPPER (q[i]);
|
23601 |
|
|
}
|
23602 |
|
|
aeabi_set_attribute_string (Tag_CPU_name, q);
|
23603 |
|
|
}
|
23604 |
|
|
|
23605 |
|
|
/* Tag_CPU_arch. */
|
23606 |
|
|
aeabi_set_attribute_int (Tag_CPU_arch, arch);
|
23607 |
|
|
|
23608 |
|
|
/* Tag_CPU_arch_profile. */
|
23609 |
|
|
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
|
23610 |
|
|
aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A');
|
23611 |
|
|
else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
|
23612 |
|
|
aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R');
|
23613 |
|
|
else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
|
23614 |
|
|
aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M');
|
23615 |
|
|
|
23616 |
|
|
/* Tag_ARM_ISA_use. */
|
23617 |
|
|
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
|
23618 |
|
|
|| arch == 0)
|
23619 |
|
|
aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
|
23620 |
|
|
|
23621 |
|
|
/* Tag_THUMB_ISA_use. */
|
23622 |
|
|
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
|
23623 |
|
|
|| arch == 0)
|
23624 |
|
|
aeabi_set_attribute_int (Tag_THUMB_ISA_use,
|
23625 |
|
|
ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
|
23626 |
|
|
|
23627 |
|
|
/* Tag_VFP_arch. */
|
23628 |
|
|
if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
|
23629 |
|
|
aeabi_set_attribute_int (Tag_VFP_arch,
|
23630 |
|
|
ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
|
23631 |
|
|
? 5 : 6);
|
23632 |
|
|
else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
|
23633 |
|
|
aeabi_set_attribute_int (Tag_VFP_arch, 3);
|
23634 |
|
|
else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
|
23635 |
|
|
aeabi_set_attribute_int (Tag_VFP_arch, 4);
|
23636 |
|
|
else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
|
23637 |
|
|
aeabi_set_attribute_int (Tag_VFP_arch, 2);
|
23638 |
|
|
else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
|
23639 |
|
|
|| ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
|
23640 |
|
|
aeabi_set_attribute_int (Tag_VFP_arch, 1);
|
23641 |
|
|
|
23642 |
|
|
/* Tag_ABI_HardFP_use. */
|
23643 |
|
|
if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
|
23644 |
|
|
&& !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
|
23645 |
|
|
aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
|
23646 |
|
|
|
23647 |
|
|
/* Tag_WMMX_arch. */
|
23648 |
|
|
if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
|
23649 |
|
|
aeabi_set_attribute_int (Tag_WMMX_arch, 2);
|
23650 |
|
|
else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
|
23651 |
|
|
aeabi_set_attribute_int (Tag_WMMX_arch, 1);
|
23652 |
|
|
|
23653 |
|
|
/* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
|
23654 |
|
|
if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
|
23655 |
|
|
aeabi_set_attribute_int
|
23656 |
|
|
(Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)
|
23657 |
|
|
? 2 : 1));
|
23658 |
|
|
|
23659 |
|
|
/* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
|
23660 |
|
|
if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16))
|
23661 |
|
|
aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
|
23662 |
|
|
|
23663 |
|
|
/* Tag_DIV_use. */
|
23664 |
|
|
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv))
|
23665 |
|
|
aeabi_set_attribute_int (Tag_DIV_use, 2);
|
23666 |
|
|
else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div))
|
23667 |
|
|
aeabi_set_attribute_int (Tag_DIV_use, 0);
|
23668 |
|
|
else
|
23669 |
|
|
aeabi_set_attribute_int (Tag_DIV_use, 1);
|
23670 |
|
|
|
23671 |
|
|
/* Tag_MP_extension_use. */
|
23672 |
|
|
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
|
23673 |
|
|
aeabi_set_attribute_int (Tag_MPextension_use, 1);
|
23674 |
|
|
|
23675 |
|
|
/* Tag Virtualization_use. */
|
23676 |
|
|
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
|
23677 |
|
|
virt_sec |= 1;
|
23678 |
|
|
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
|
23679 |
|
|
virt_sec |= 2;
|
23680 |
|
|
if (virt_sec != 0)
|
23681 |
|
|
aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
|
23682 |
|
|
}
|
23683 |
|
|
|
23684 |
|
|
/* Add the default contents for the .ARM.attributes section. */
|
23685 |
|
|
void
|
23686 |
|
|
arm_md_end (void)
|
23687 |
|
|
{
|
23688 |
|
|
if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
|
23689 |
|
|
return;
|
23690 |
|
|
|
23691 |
|
|
aeabi_set_public_attributes ();
|
23692 |
|
|
}
|
23693 |
|
|
#endif /* OBJ_ELF */
|
23694 |
|
|
|
23695 |
|
|
|
23696 |
|
|
/* Parse a .cpu directive. */
|
23697 |
|
|
|
23698 |
|
|
static void
|
23699 |
|
|
s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
|
23700 |
|
|
{
|
23701 |
|
|
const struct arm_cpu_option_table *opt;
|
23702 |
|
|
char *name;
|
23703 |
|
|
char saved_char;
|
23704 |
|
|
|
23705 |
|
|
name = input_line_pointer;
|
23706 |
|
|
while (*input_line_pointer && !ISSPACE (*input_line_pointer))
|
23707 |
|
|
input_line_pointer++;
|
23708 |
|
|
saved_char = *input_line_pointer;
|
23709 |
|
|
*input_line_pointer = 0;
|
23710 |
|
|
|
23711 |
|
|
/* Skip the first "all" entry. */
|
23712 |
|
|
for (opt = arm_cpus + 1; opt->name != NULL; opt++)
|
23713 |
|
|
if (streq (opt->name, name))
|
23714 |
|
|
{
|
23715 |
|
|
mcpu_cpu_opt = &opt->value;
|
23716 |
|
|
selected_cpu = opt->value;
|
23717 |
|
|
if (opt->canonical_name)
|
23718 |
|
|
strcpy (selected_cpu_name, opt->canonical_name);
|
23719 |
|
|
else
|
23720 |
|
|
{
|
23721 |
|
|
int i;
|
23722 |
|
|
for (i = 0; opt->name[i]; i++)
|
23723 |
|
|
selected_cpu_name[i] = TOUPPER (opt->name[i]);
|
23724 |
|
|
selected_cpu_name[i] = 0;
|
23725 |
|
|
}
|
23726 |
|
|
ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
|
23727 |
|
|
*input_line_pointer = saved_char;
|
23728 |
|
|
demand_empty_rest_of_line ();
|
23729 |
|
|
return;
|
23730 |
|
|
}
|
23731 |
|
|
as_bad (_("unknown cpu `%s'"), name);
|
23732 |
|
|
*input_line_pointer = saved_char;
|
23733 |
|
|
ignore_rest_of_line ();
|
23734 |
|
|
}
|
23735 |
|
|
|
23736 |
|
|
|
23737 |
|
|
/* Parse a .arch directive. */
|
23738 |
|
|
|
23739 |
|
|
static void
|
23740 |
|
|
s_arm_arch (int ignored ATTRIBUTE_UNUSED)
|
23741 |
|
|
{
|
23742 |
|
|
const struct arm_arch_option_table *opt;
|
23743 |
|
|
char saved_char;
|
23744 |
|
|
char *name;
|
23745 |
|
|
|
23746 |
|
|
name = input_line_pointer;
|
23747 |
|
|
while (*input_line_pointer && !ISSPACE (*input_line_pointer))
|
23748 |
|
|
input_line_pointer++;
|
23749 |
|
|
saved_char = *input_line_pointer;
|
23750 |
|
|
*input_line_pointer = 0;
|
23751 |
|
|
|
23752 |
|
|
/* Skip the first "all" entry. */
|
23753 |
|
|
for (opt = arm_archs + 1; opt->name != NULL; opt++)
|
23754 |
|
|
if (streq (opt->name, name))
|
23755 |
|
|
{
|
23756 |
|
|
mcpu_cpu_opt = &opt->value;
|
23757 |
|
|
selected_cpu = opt->value;
|
23758 |
|
|
strcpy (selected_cpu_name, opt->name);
|
23759 |
|
|
ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
|
23760 |
|
|
*input_line_pointer = saved_char;
|
23761 |
|
|
demand_empty_rest_of_line ();
|
23762 |
|
|
return;
|
23763 |
|
|
}
|
23764 |
|
|
|
23765 |
|
|
as_bad (_("unknown architecture `%s'\n"), name);
|
23766 |
|
|
*input_line_pointer = saved_char;
|
23767 |
|
|
ignore_rest_of_line ();
|
23768 |
|
|
}
|
23769 |
|
|
|
23770 |
|
|
|
23771 |
|
|
/* Parse a .object_arch directive. */
|
23772 |
|
|
|
23773 |
|
|
static void
|
23774 |
|
|
s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
|
23775 |
|
|
{
|
23776 |
|
|
const struct arm_arch_option_table *opt;
|
23777 |
|
|
char saved_char;
|
23778 |
|
|
char *name;
|
23779 |
|
|
|
23780 |
|
|
name = input_line_pointer;
|
23781 |
|
|
while (*input_line_pointer && !ISSPACE (*input_line_pointer))
|
23782 |
|
|
input_line_pointer++;
|
23783 |
|
|
saved_char = *input_line_pointer;
|
23784 |
|
|
*input_line_pointer = 0;
|
23785 |
|
|
|
23786 |
|
|
/* Skip the first "all" entry. */
|
23787 |
|
|
for (opt = arm_archs + 1; opt->name != NULL; opt++)
|
23788 |
|
|
if (streq (opt->name, name))
|
23789 |
|
|
{
|
23790 |
|
|
object_arch = &opt->value;
|
23791 |
|
|
*input_line_pointer = saved_char;
|
23792 |
|
|
demand_empty_rest_of_line ();
|
23793 |
|
|
return;
|
23794 |
|
|
}
|
23795 |
|
|
|
23796 |
|
|
as_bad (_("unknown architecture `%s'\n"), name);
|
23797 |
|
|
*input_line_pointer = saved_char;
|
23798 |
|
|
ignore_rest_of_line ();
|
23799 |
|
|
}
|
23800 |
|
|
|
23801 |
|
|
/* Parse a .arch_extension directive. */
|
23802 |
|
|
|
23803 |
|
|
static void
|
23804 |
|
|
s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
|
23805 |
|
|
{
|
23806 |
|
|
const struct arm_option_extension_value_table *opt;
|
23807 |
|
|
char saved_char;
|
23808 |
|
|
char *name;
|
23809 |
|
|
int adding_value = 1;
|
23810 |
|
|
|
23811 |
|
|
name = input_line_pointer;
|
23812 |
|
|
while (*input_line_pointer && !ISSPACE (*input_line_pointer))
|
23813 |
|
|
input_line_pointer++;
|
23814 |
|
|
saved_char = *input_line_pointer;
|
23815 |
|
|
*input_line_pointer = 0;
|
23816 |
|
|
|
23817 |
|
|
if (strlen (name) >= 2
|
23818 |
|
|
&& strncmp (name, "no", 2) == 0)
|
23819 |
|
|
{
|
23820 |
|
|
adding_value = 0;
|
23821 |
|
|
name += 2;
|
23822 |
|
|
}
|
23823 |
|
|
|
23824 |
|
|
for (opt = arm_extensions; opt->name != NULL; opt++)
|
23825 |
|
|
if (streq (opt->name, name))
|
23826 |
|
|
{
|
23827 |
|
|
if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
|
23828 |
|
|
{
|
23829 |
|
|
as_bad (_("architectural extension `%s' is not allowed for the "
|
23830 |
|
|
"current base architecture"), name);
|
23831 |
|
|
break;
|
23832 |
|
|
}
|
23833 |
|
|
|
23834 |
|
|
if (adding_value)
|
23835 |
|
|
ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
|
23836 |
|
|
else
|
23837 |
|
|
ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
|
23838 |
|
|
|
23839 |
|
|
mcpu_cpu_opt = &selected_cpu;
|
23840 |
|
|
ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
|
23841 |
|
|
*input_line_pointer = saved_char;
|
23842 |
|
|
demand_empty_rest_of_line ();
|
23843 |
|
|
return;
|
23844 |
|
|
}
|
23845 |
|
|
|
23846 |
|
|
if (opt->name == NULL)
|
23847 |
|
|
as_bad (_("unknown architecture `%s'\n"), name);
|
23848 |
|
|
|
23849 |
|
|
*input_line_pointer = saved_char;
|
23850 |
|
|
ignore_rest_of_line ();
|
23851 |
|
|
}
|
23852 |
|
|
|
23853 |
|
|
/* Parse a .fpu directive. */
|
23854 |
|
|
|
23855 |
|
|
static void
|
23856 |
|
|
s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
|
23857 |
|
|
{
|
23858 |
|
|
const struct arm_option_fpu_value_table *opt;
|
23859 |
|
|
char saved_char;
|
23860 |
|
|
char *name;
|
23861 |
|
|
|
23862 |
|
|
name = input_line_pointer;
|
23863 |
|
|
while (*input_line_pointer && !ISSPACE (*input_line_pointer))
|
23864 |
|
|
input_line_pointer++;
|
23865 |
|
|
saved_char = *input_line_pointer;
|
23866 |
|
|
*input_line_pointer = 0;
|
23867 |
|
|
|
23868 |
|
|
for (opt = arm_fpus; opt->name != NULL; opt++)
|
23869 |
|
|
if (streq (opt->name, name))
|
23870 |
|
|
{
|
23871 |
|
|
mfpu_opt = &opt->value;
|
23872 |
|
|
ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
|
23873 |
|
|
*input_line_pointer = saved_char;
|
23874 |
|
|
demand_empty_rest_of_line ();
|
23875 |
|
|
return;
|
23876 |
|
|
}
|
23877 |
|
|
|
23878 |
|
|
as_bad (_("unknown floating point format `%s'\n"), name);
|
23879 |
|
|
*input_line_pointer = saved_char;
|
23880 |
|
|
ignore_rest_of_line ();
|
23881 |
|
|
}
|
23882 |
|
|
|
23883 |
|
|
/* Copy symbol information. */
|
23884 |
|
|
|
23885 |
|
|
void
|
23886 |
|
|
arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
|
23887 |
|
|
{
|
23888 |
|
|
ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
|
23889 |
|
|
}
|
23890 |
|
|
|
23891 |
|
|
#ifdef OBJ_ELF
|
23892 |
|
|
/* Given a symbolic attribute NAME, return the proper integer value.
|
23893 |
|
|
Returns -1 if the attribute is not known. */
|
23894 |
|
|
|
23895 |
|
|
int
|
23896 |
|
|
arm_convert_symbolic_attribute (const char *name)
|
23897 |
|
|
{
|
23898 |
|
|
static const struct
|
23899 |
|
|
{
|
23900 |
|
|
const char * name;
|
23901 |
|
|
const int tag;
|
23902 |
|
|
}
|
23903 |
|
|
attribute_table[] =
|
23904 |
|
|
{
|
23905 |
|
|
/* When you modify this table you should
|
23906 |
|
|
also modify the list in doc/c-arm.texi. */
|
23907 |
|
|
#define T(tag) {#tag, tag}
|
23908 |
|
|
T (Tag_CPU_raw_name),
|
23909 |
|
|
T (Tag_CPU_name),
|
23910 |
|
|
T (Tag_CPU_arch),
|
23911 |
|
|
T (Tag_CPU_arch_profile),
|
23912 |
|
|
T (Tag_ARM_ISA_use),
|
23913 |
|
|
T (Tag_THUMB_ISA_use),
|
23914 |
|
|
T (Tag_FP_arch),
|
23915 |
|
|
T (Tag_VFP_arch),
|
23916 |
|
|
T (Tag_WMMX_arch),
|
23917 |
|
|
T (Tag_Advanced_SIMD_arch),
|
23918 |
|
|
T (Tag_PCS_config),
|
23919 |
|
|
T (Tag_ABI_PCS_R9_use),
|
23920 |
|
|
T (Tag_ABI_PCS_RW_data),
|
23921 |
|
|
T (Tag_ABI_PCS_RO_data),
|
23922 |
|
|
T (Tag_ABI_PCS_GOT_use),
|
23923 |
|
|
T (Tag_ABI_PCS_wchar_t),
|
23924 |
|
|
T (Tag_ABI_FP_rounding),
|
23925 |
|
|
T (Tag_ABI_FP_denormal),
|
23926 |
|
|
T (Tag_ABI_FP_exceptions),
|
23927 |
|
|
T (Tag_ABI_FP_user_exceptions),
|
23928 |
|
|
T (Tag_ABI_FP_number_model),
|
23929 |
|
|
T (Tag_ABI_align_needed),
|
23930 |
|
|
T (Tag_ABI_align8_needed),
|
23931 |
|
|
T (Tag_ABI_align_preserved),
|
23932 |
|
|
T (Tag_ABI_align8_preserved),
|
23933 |
|
|
T (Tag_ABI_enum_size),
|
23934 |
|
|
T (Tag_ABI_HardFP_use),
|
23935 |
|
|
T (Tag_ABI_VFP_args),
|
23936 |
|
|
T (Tag_ABI_WMMX_args),
|
23937 |
|
|
T (Tag_ABI_optimization_goals),
|
23938 |
|
|
T (Tag_ABI_FP_optimization_goals),
|
23939 |
|
|
T (Tag_compatibility),
|
23940 |
|
|
T (Tag_CPU_unaligned_access),
|
23941 |
|
|
T (Tag_FP_HP_extension),
|
23942 |
|
|
T (Tag_VFP_HP_extension),
|
23943 |
|
|
T (Tag_ABI_FP_16bit_format),
|
23944 |
|
|
T (Tag_MPextension_use),
|
23945 |
|
|
T (Tag_DIV_use),
|
23946 |
|
|
T (Tag_nodefaults),
|
23947 |
|
|
T (Tag_also_compatible_with),
|
23948 |
|
|
T (Tag_conformance),
|
23949 |
|
|
T (Tag_T2EE_use),
|
23950 |
|
|
T (Tag_Virtualization_use),
|
23951 |
|
|
/* We deliberately do not include Tag_MPextension_use_legacy. */
|
23952 |
|
|
#undef T
|
23953 |
|
|
};
|
23954 |
|
|
unsigned int i;
|
23955 |
|
|
|
23956 |
|
|
if (name == NULL)
|
23957 |
|
|
return -1;
|
23958 |
|
|
|
23959 |
|
|
for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
|
23960 |
|
|
if (streq (name, attribute_table[i].name))
|
23961 |
|
|
return attribute_table[i].tag;
|
23962 |
|
|
|
23963 |
|
|
return -1;
|
23964 |
|
|
}
|
23965 |
|
|
|
23966 |
|
|
|
23967 |
|
|
/* Apply sym value for relocations only in the case that
|
23968 |
|
|
they are for local symbols and you have the respective
|
23969 |
|
|
architectural feature for blx and simple switches. */
|
23970 |
|
|
int
|
23971 |
|
|
arm_apply_sym_value (struct fix * fixP)
|
23972 |
|
|
{
|
23973 |
|
|
if (fixP->fx_addsy
|
23974 |
|
|
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
|
23975 |
|
|
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
|
23976 |
|
|
{
|
23977 |
|
|
switch (fixP->fx_r_type)
|
23978 |
|
|
{
|
23979 |
|
|
case BFD_RELOC_ARM_PCREL_BLX:
|
23980 |
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH23:
|
23981 |
|
|
if (ARM_IS_FUNC (fixP->fx_addsy))
|
23982 |
|
|
return 1;
|
23983 |
|
|
break;
|
23984 |
|
|
|
23985 |
|
|
case BFD_RELOC_ARM_PCREL_CALL:
|
23986 |
|
|
case BFD_RELOC_THUMB_PCREL_BLX:
|
23987 |
|
|
if (THUMB_IS_FUNC (fixP->fx_addsy))
|
23988 |
|
|
return 1;
|
23989 |
|
|
break;
|
23990 |
|
|
|
23991 |
|
|
default:
|
23992 |
|
|
break;
|
23993 |
|
|
}
|
23994 |
|
|
|
23995 |
|
|
}
|
23996 |
|
|
return 0;
|
23997 |
|
|
}
|
23998 |
|
|
#endif /* OBJ_ELF */
|