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[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [gas/] [config/] [tc-d10v.c] - Blame information for rev 16

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/* tc-d10v.c -- Assembler code for the Mitsubishi D10V
2
   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006,
3
   2007, 2009, 2010
4
   Free Software Foundation, Inc.
5
 
6
   This file is part of GAS, the GNU Assembler.
7
 
8
   GAS is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3, or (at your option)
11
   any later version.
12
 
13
   GAS is distributed in the hope that it will be useful,
14
   but WITHOUT ANY WARRANTY; without even the implied warranty of
15
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
   GNU General Public License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with GAS; see the file COPYING.  If not, write to
20
   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21
   Boston, MA 02110-1301, USA.  */
22
 
23
#include "as.h"
24
#include "safe-ctype.h"
25
#include "subsegs.h"
26
#include "opcode/d10v.h"
27
#include "elf/ppc.h"
28
#include "dwarf2dbg.h"
29
 
30
const char comment_chars[]        = ";";
31
const char line_comment_chars[]   = "#";
32
const char line_separator_chars[] = "";
33
const char *md_shortopts          = "O";
34
const char EXP_CHARS[]            = "eE";
35
const char FLT_CHARS[]            = "dD";
36
 
37
int Optimizing = 0;
38
 
39
#define AT_WORD_P(X) ((X)->X_op == O_right_shift \
40
                      && (X)->X_op_symbol != NULL \
41
                      && symbol_constant_p ((X)->X_op_symbol) \
42
                      && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT)
43
#define AT_WORD_RIGHT_SHIFT 2
44
 
45
/* Fixups.  */
46
#define MAX_INSN_FIXUPS  5
47
 
48
struct d10v_fixup
49
{
50
  expressionS exp;
51
  int operand;
52
  int pcrel;
53
  int size;
54
  bfd_reloc_code_real_type reloc;
55
};
56
 
57
typedef struct _fixups
58
{
59
  int fc;
60
  struct d10v_fixup fix[MAX_INSN_FIXUPS];
61
  struct _fixups *next;
62
} Fixups;
63
 
64
static Fixups FixUps[2];
65
static Fixups *fixups;
66
 
67
static int do_not_ignore_hash = 0;
68
 
69
typedef int packing_type;
70
#define PACK_UNSPEC     (0)     /* Packing order not specified.  */
71
#define PACK_PARALLEL   (1)     /* "||"  */
72
#define PACK_LEFT_RIGHT (2)     /* "->"  */
73
#define PACK_RIGHT_LEFT (3)     /* "<-"  */
74
static packing_type etype = PACK_UNSPEC; /* Used by d10v_cleanup.  */
75
 
76
/* TRUE if instruction swapping warnings should be inhibited.
77
   --nowarnswap.  */
78
static bfd_boolean flag_warn_suppress_instructionswap;
79
 
80
/* TRUE if instruction packing should be performed when --gstabs is specified.
81
   --gstabs-packing, --no-gstabs-packing.  */
82
static bfd_boolean flag_allow_gstabs_packing = 1;
83
 
84
/* Local functions.  */
85
 
86
enum options
87
{
88
  OPTION_NOWARNSWAP = OPTION_MD_BASE,
89
  OPTION_GSTABSPACKING,
90
  OPTION_NOGSTABSPACKING
91
};
92
 
93
struct option md_longopts[] =
94
{
95
  {"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP},
96
  {"gstabspacking",  no_argument, NULL, OPTION_GSTABSPACKING},
97
  {"gstabs-packing", no_argument, NULL, OPTION_GSTABSPACKING},
98
  {"nogstabspacking",   no_argument, NULL, OPTION_NOGSTABSPACKING},
99
  {"no-gstabs-packing", no_argument, NULL, OPTION_NOGSTABSPACKING},
100
  {NULL, no_argument, NULL, 0}
101
};
102
 
103
size_t md_longopts_size = sizeof (md_longopts);
104
 
105
/* Opcode hash table.  */
106
static struct hash_control *d10v_hash;
107
 
108
/* Do a binary search of the d10v_predefined_registers array to see if
109
   NAME is a valid regiter name.  Return the register number from the
110
   array on success, or -1 on failure.  */
111
 
112
static int
113
reg_name_search (char *name)
114
{
115
  int middle, low, high;
116
  int cmp;
117
 
118
  low = 0;
119
  high = d10v_reg_name_cnt () - 1;
120
 
121
  do
122
    {
123
      middle = (low + high) / 2;
124
      cmp = strcasecmp (name, d10v_predefined_registers[middle].name);
125
      if (cmp < 0)
126
        high = middle - 1;
127
      else if (cmp > 0)
128
        low = middle + 1;
129
      else
130
        return d10v_predefined_registers[middle].value;
131
    }
132
  while (low <= high);
133
  return -1;
134
}
135
 
136
/* Check the string at input_line_pointer
137
   to see if it is a valid register name.  */
138
 
139
static int
140
register_name (expressionS *expressionP)
141
{
142
  int reg_number;
143
  char c, *p = input_line_pointer;
144
 
145
  while (*p
146
         && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')')
147
    p++;
148
 
149
  c = *p;
150
  if (c)
151
    *p++ = 0;
152
 
153
  /* Look to see if it's in the register table.  */
154
  reg_number = reg_name_search (input_line_pointer);
155
  if (reg_number >= 0)
156
    {
157
      expressionP->X_op = O_register;
158
      /* Temporarily store a pointer to the string here.  */
159
      expressionP->X_op_symbol = (symbolS *) input_line_pointer;
160
      expressionP->X_add_number = reg_number;
161
      input_line_pointer = p;
162
      return 1;
163
    }
164
  if (c)
165
    *(p - 1) = c;
166
  return 0;
167
}
168
 
169
static int
170
check_range (unsigned long num, int bits, int flags)
171
{
172
  long min, max;
173
  int retval = 0;
174
 
175
  /* Don't bother checking 16-bit values.  */
176
  if (bits == 16)
177
    return 0;
178
 
179
  if (flags & OPERAND_SHIFT)
180
    {
181
      /* All special shift operands are unsigned and <= 16.
182
         We allow 0 for now.  */
183
      if (num > 16)
184
        return 1;
185
      else
186
        return 0;
187
    }
188
 
189
  if (flags & OPERAND_SIGNED)
190
    {
191
      /* Signed 3-bit integers are restricted to the (-2, 3) range.  */
192
      if (flags & RESTRICTED_NUM3)
193
        {
194
          if ((long) num < -2 || (long) num > 3)
195
            retval = 1;
196
        }
197
      else
198
        {
199
          max = (1 << (bits - 1)) - 1;
200
          min = - (1 << (bits - 1));
201
          if (((long) num > max) || ((long) num < min))
202
            retval = 1;
203
        }
204
    }
205
  else
206
    {
207
      max = (1 << bits) - 1;
208
      min = 0;
209
      if (((long) num > max) || ((long) num < min))
210
        retval = 1;
211
    }
212
  return retval;
213
}
214
 
215
void
216
md_show_usage (FILE *stream)
217
{
218
  fprintf (stream, _("D10V options:\n\
219
-O                      Optimize.  Will do some operations in parallel.\n\
220
--gstabs-packing        Pack adjacent short instructions together even\n\
221
                        when --gstabs is specified.  On by default.\n\
222
--no-gstabs-packing     If --gstabs is specified, do not pack adjacent\n\
223
                        instructions together.\n"));
224
}
225
 
226
int
227
md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
228
{
229
  switch (c)
230
    {
231
    case 'O':
232
      /* Optimize. Will attempt to parallelize operations.  */
233
      Optimizing = 1;
234
      break;
235
    case OPTION_NOWARNSWAP:
236
      flag_warn_suppress_instructionswap = 1;
237
      break;
238
    case OPTION_GSTABSPACKING:
239
      flag_allow_gstabs_packing = 1;
240
      break;
241
    case OPTION_NOGSTABSPACKING:
242
      flag_allow_gstabs_packing = 0;
243
      break;
244
    default:
245
      return 0;
246
    }
247
  return 1;
248
}
249
 
250
symbolS *
251
md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252
{
253
  return 0;
254
}
255
 
256
char *
257
md_atof (int type, char *litP, int *sizeP)
258
{
259
  return ieee_md_atof (type, litP, sizeP, TRUE);
260
}
261
 
262
void
263
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
264
                 asection *sec ATTRIBUTE_UNUSED,
265
                 fragS *fragP ATTRIBUTE_UNUSED)
266
{
267
  abort ();
268
}
269
 
270
valueT
271
md_section_align (asection *seg, valueT addr)
272
{
273
  int align = bfd_get_section_alignment (stdoutput, seg);
274
  return ((addr + (1 << align) - 1) & (-1 << align));
275
}
276
 
277
void
278
md_begin (void)
279
{
280
  char *prev_name = "";
281
  struct d10v_opcode *opcode;
282
  d10v_hash = hash_new ();
283
 
284
  /* Insert unique names into hash table.  The D10v instruction set
285
     has many identical opcode names that have different opcodes based
286
     on the operands.  This hash table then provides a quick index to
287
     the first opcode with a particular name in the opcode table.  */
288
 
289
  for (opcode = (struct d10v_opcode *) d10v_opcodes; opcode->name; opcode++)
290
    {
291
      if (strcmp (prev_name, opcode->name))
292
        {
293
          prev_name = (char *) opcode->name;
294
          hash_insert (d10v_hash, opcode->name, (char *) opcode);
295
        }
296
    }
297
 
298
  fixups = &FixUps[0];
299
  FixUps[0].next = &FixUps[1];
300
  FixUps[1].next = &FixUps[0];
301
}
302
 
303
/* Remove the postincrement or postdecrement operator ( '+' or '-' )
304
   from an expression.  */
305
 
306
static int
307
postfix (char *p)
308
{
309
  while (*p != '-' && *p != '+')
310
    {
311
      if (*p == 0 || *p == '\n' || *p == '\r')
312
        break;
313
      p++;
314
    }
315
 
316
  if (*p == '-')
317
    {
318
      *p = ' ';
319
      return -1;
320
    }
321
  if (*p == '+')
322
    {
323
      *p = ' ';
324
      return 1;
325
    }
326
 
327
  return 0;
328
}
329
 
330
static bfd_reloc_code_real_type
331
get_reloc (struct d10v_operand *op)
332
{
333
  int bits = op->bits;
334
 
335
  if (bits <= 4)
336
    return 0;
337
 
338
  if (op->flags & OPERAND_ADDR)
339
    {
340
      if (bits == 8)
341
        return BFD_RELOC_D10V_10_PCREL_R;
342
      else
343
        return BFD_RELOC_D10V_18_PCREL;
344
    }
345
 
346
  return BFD_RELOC_16;
347
}
348
 
349
/* Parse a string of operands.  Return an array of expressions.  */
350
 
351
static int
352
get_operands (expressionS exp[])
353
{
354
  char *p = input_line_pointer;
355
  int numops = 0;
356
  int post = 0;
357
  int uses_at = 0;
358
 
359
  while (*p)
360
    {
361
      while (*p == ' ' || *p == '\t' || *p == ',')
362
        p++;
363
      if (*p == 0 || *p == '\n' || *p == '\r')
364
        break;
365
 
366
      if (*p == '@')
367
        {
368
          uses_at = 1;
369
 
370
          p++;
371
          exp[numops].X_op = O_absent;
372
          if (*p == '(')
373
            {
374
              p++;
375
              exp[numops].X_add_number = OPERAND_ATPAR;
376
            }
377
          else if (*p == '-')
378
            {
379
              p++;
380
              exp[numops].X_add_number = OPERAND_ATMINUS;
381
            }
382
          else
383
            {
384
              exp[numops].X_add_number = OPERAND_ATSIGN;
385
              if (*p == '+')
386
                {
387
                  numops++;
388
                  exp[numops].X_op = O_absent;
389
                  exp[numops].X_add_number = OPERAND_PLUS;
390
                  p++;
391
                }
392
              post = postfix (p);
393
            }
394
          numops++;
395
          continue;
396
        }
397
 
398
      if (*p == ')')
399
        {
400
          /* Just skip the trailing paren.  */
401
          p++;
402
          continue;
403
        }
404
 
405
      input_line_pointer = p;
406
 
407
      /* Check to see if it might be a register name.  */
408
      if (!register_name (&exp[numops]))
409
        {
410
          /* Parse as an expression.  */
411
          if (uses_at)
412
            {
413
              /* Any expression that involves the indirect addressing
414
                 cannot also involve immediate addressing.  Therefore
415
                 the use of the hash character is illegal.  */
416
              int save = do_not_ignore_hash;
417
              do_not_ignore_hash = 1;
418
 
419
              expression (&exp[numops]);
420
 
421
              do_not_ignore_hash = save;
422
            }
423
          else
424
            expression (&exp[numops]);
425
        }
426
 
427
      if (strncasecmp (input_line_pointer, "@word", 5) == 0)
428
        {
429
          input_line_pointer += 5;
430
          if (exp[numops].X_op == O_register)
431
            {
432
              /* If it looked like a register name but was followed by
433
                 "@word" then it was really a symbol, so change it to
434
                 one.  */
435
              exp[numops].X_op = O_symbol;
436
              exp[numops].X_add_symbol =
437
                symbol_find_or_make ((char *) exp[numops].X_op_symbol);
438
            }
439
 
440
          /* Check for identifier@word+constant.  */
441
          if (*input_line_pointer == '-' || *input_line_pointer == '+')
442
            {
443
              expressionS new_exp;
444
              expression (&new_exp);
445
              exp[numops].X_add_number = new_exp.X_add_number;
446
            }
447
 
448
          /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT.  */
449
          {
450
            expressionS new_exp;
451
            memset (&new_exp, 0, sizeof new_exp);
452
            new_exp.X_add_number = AT_WORD_RIGHT_SHIFT;
453
            new_exp.X_op = O_constant;
454
            new_exp.X_unsigned = 1;
455
            exp[numops].X_op_symbol = make_expr_symbol (&new_exp);
456
            exp[numops].X_op = O_right_shift;
457
          }
458
 
459
          know (AT_WORD_P (&exp[numops]));
460
        }
461
 
462
      if (exp[numops].X_op == O_illegal)
463
        as_bad (_("illegal operand"));
464
      else if (exp[numops].X_op == O_absent)
465
        as_bad (_("missing operand"));
466
 
467
      numops++;
468
      p = input_line_pointer;
469
    }
470
 
471
  switch (post)
472
    {
473
    case -1:    /* Postdecrement mode.  */
474
      exp[numops].X_op = O_absent;
475
      exp[numops++].X_add_number = OPERAND_MINUS;
476
      break;
477
    case 1:     /* Postincrement mode.  */
478
      exp[numops].X_op = O_absent;
479
      exp[numops++].X_add_number = OPERAND_PLUS;
480
      break;
481
    }
482
 
483
  exp[numops].X_op = 0;
484
  return numops;
485
}
486
 
487
static unsigned long
488
d10v_insert_operand (unsigned long insn,
489
                     int op_type,
490
                     offsetT value,
491
                     int left,
492
                     fixS *fix)
493
{
494
  int shift, bits;
495
 
496
  shift = d10v_operands[op_type].shift;
497
  if (left)
498
    shift += 15;
499
 
500
  bits = d10v_operands[op_type].bits;
501
 
502
  /* Truncate to the proper number of bits.  */
503
  if (check_range (value, bits, d10v_operands[op_type].flags))
504
    as_bad_where (fix->fx_file, fix->fx_line,
505
                  _("operand out of range: %ld"), (long) value);
506
 
507
  value &= 0x7FFFFFFF >> (31 - bits);
508
  insn |= (value << shift);
509
 
510
  return insn;
511
}
512
 
513
/* Take a pointer to the opcode entry in the opcode table and the
514
   array of operand expressions.  Return the instruction.  */
515
 
516
static unsigned long
517
build_insn (struct d10v_opcode *opcode,
518
            expressionS *opers,
519
            unsigned long insn)
520
{
521
  int i, bits, shift, flags, format;
522
  unsigned long number;
523
 
524
  /* The insn argument is only used for the DIVS kludge.  */
525
  if (insn)
526
    format = LONG_R;
527
  else
528
    {
529
      insn = opcode->opcode;
530
      format = opcode->format;
531
    }
532
 
533
  for (i = 0; opcode->operands[i]; i++)
534
    {
535
      flags = d10v_operands[opcode->operands[i]].flags;
536
      bits = d10v_operands[opcode->operands[i]].bits;
537
      shift = d10v_operands[opcode->operands[i]].shift;
538
      number = opers[i].X_add_number;
539
 
540
      if (flags & OPERAND_REG)
541
        {
542
          number &= REGISTER_MASK;
543
          if (format == LONG_L)
544
            shift += 15;
545
        }
546
 
547
      if (opers[i].X_op != O_register && opers[i].X_op != O_constant)
548
        {
549
          /* Now create a fixup.  */
550
 
551
          if (fixups->fc >= MAX_INSN_FIXUPS)
552
            as_fatal (_("too many fixups"));
553
 
554
          if (AT_WORD_P (&opers[i]))
555
            {
556
              /* Recognize XXX>>1+N aka XXX@word+N as special (AT_WORD).  */
557
              fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18;
558
              opers[i].X_op = O_symbol;
559
              opers[i].X_op_symbol = NULL; /* Should free it.  */
560
              /* number is left shifted by AT_WORD_RIGHT_SHIFT so
561
                 that, it is aligned with the symbol's value.  Later,
562
                 BFD_RELOC_D10V_18 will right shift (symbol_value +
563
                 X_add_number).  */
564
              number <<= AT_WORD_RIGHT_SHIFT;
565
              opers[i].X_add_number = number;
566
            }
567
          else
568
            {
569
              fixups->fix[fixups->fc].reloc =
570
                get_reloc ((struct d10v_operand *) &d10v_operands[opcode->operands[i]]);
571
 
572
              /* Check that an immediate was passed to ops that expect one.  */
573
              if ((flags & OPERAND_NUM)
574
                  && (fixups->fix[fixups->fc].reloc == 0))
575
                as_bad (_("operand is not an immediate"));
576
            }
577
 
578
          if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 ||
579
              fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18)
580
            fixups->fix[fixups->fc].size = 2;
581
          else
582
            fixups->fix[fixups->fc].size = 4;
583
 
584
          fixups->fix[fixups->fc].exp = opers[i];
585
          fixups->fix[fixups->fc].operand = opcode->operands[i];
586
          fixups->fix[fixups->fc].pcrel =
587
            (flags & OPERAND_ADDR) ? TRUE : FALSE;
588
          (fixups->fc)++;
589
        }
590
 
591
      /* Truncate to the proper number of bits.  */
592
      if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
593
        as_bad (_("operand out of range: %lu"), number);
594
      number &= 0x7FFFFFFF >> (31 - bits);
595
      insn = insn | (number << shift);
596
    }
597
 
598
  /* kludge: for DIVS, we need to put the operands in twice on the second
599
     pass, format is changed to LONG_R to force the second set of operands
600
     to not be shifted over 15.  */
601
  if ((opcode->opcode == OPCODE_DIVS) && (format == LONG_L))
602
    insn = build_insn (opcode, opers, insn);
603
 
604
  return insn;
605
}
606
 
607
/* Write out a long form instruction.  */
608
 
609
static void
610
write_long (unsigned long insn, Fixups *fx)
611
{
612
  int i, where;
613
  char *f = frag_more (4);
614
 
615
  dwarf2_emit_insn (4);
616
  insn |= FM11;
617
  number_to_chars_bigendian (f, insn, 4);
618
 
619
  for (i = 0; i < fx->fc; i++)
620
    {
621
      if (fx->fix[i].reloc)
622
        {
623
          where = f - frag_now->fr_literal;
624
          if (fx->fix[i].size == 2)
625
            where += 2;
626
 
627
          if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
628
            fx->fix[i].operand |= 4096;
629
 
630
          fix_new_exp (frag_now,
631
                       where,
632
                       fx->fix[i].size,
633
                       &(fx->fix[i].exp),
634
                       fx->fix[i].pcrel,
635
                       fx->fix[i].operand|2048);
636
        }
637
    }
638
  fx->fc = 0;
639
}
640
 
641
/* Write out a short form instruction by itself.  */
642
 
643
static void
644
write_1_short (struct d10v_opcode *opcode,
645
               unsigned long insn,
646
               Fixups *fx)
647
{
648
  char *f = frag_more (4);
649
  int i, where;
650
 
651
  dwarf2_emit_insn (4);
652
  if (opcode->exec_type & PARONLY)
653
    as_fatal (_("Instruction must be executed in parallel with another instruction."));
654
 
655
  /* The other container needs to be NOP.
656
     According to 4.3.1: for FM=00, sub-instructions performed only by IU
657
     cannot be encoded in L-container.  */
658
  if (opcode->unit == IU)
659
    insn |= FM00 | (NOP << 15);         /* Right container.  */
660
  else
661
    insn = FM00 | (insn << 15) | NOP;   /* Left container.  */
662
 
663
  number_to_chars_bigendian (f, insn, 4);
664
  for (i = 0; i < fx->fc; i++)
665
    {
666
      if (fx->fix[i].reloc)
667
        {
668
          where = f - frag_now->fr_literal;
669
          if (fx->fix[i].size == 2)
670
            where += 2;
671
 
672
          if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
673
            fx->fix[i].operand |= 4096;
674
 
675
          /* If it's an R reloc, we may have to switch it to L.  */
676
          if ((fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R)
677
              && (opcode->unit != IU))
678
            fx->fix[i].operand |= 1024;
679
 
680
          fix_new_exp (frag_now,
681
                       where,
682
                       fx->fix[i].size,
683
                       &(fx->fix[i].exp),
684
                       fx->fix[i].pcrel,
685
                       fx->fix[i].operand|2048);
686
        }
687
    }
688
  fx->fc = 0;
689
}
690
 
691
/* Determine if there are any resource conflicts among two manually
692
   parallelized instructions.  Some of this was lifted from parallel_ok.  */
693
 
694
static void
695
check_resource_conflict (struct d10v_opcode *op1,
696
                         unsigned long insn1,
697
                         struct d10v_opcode *op2,
698
                         unsigned long insn2)
699
{
700
  int i, j, flags, mask, shift, regno;
701
  unsigned long ins, mod[2];
702
  struct d10v_opcode *op;
703
 
704
  if ((op1->exec_type & SEQ)
705
      || ! ((op1->exec_type & PAR) || (op1->exec_type & PARONLY)))
706
    {
707
      as_warn (_("packing conflict: %s must dispatch sequentially"),
708
              op1->name);
709
      return;
710
    }
711
 
712
  if ((op2->exec_type & SEQ)
713
      || ! ((op2->exec_type & PAR) || (op2->exec_type & PARONLY)))
714
    {
715
      as_warn (_("packing conflict: %s must dispatch sequentially"),
716
              op2->name);
717
      return;
718
    }
719
 
720
   /* See if both instructions write to the same resource.
721
 
722
      The idea here is to create two sets of bitmasks (mod and used) which
723
      indicate which registers are modified or used by each instruction.
724
      The operation can only be done in parallel if neither instruction
725
      modifies the same register. Accesses to control registers and memory
726
      are treated as accesses to a single register. So if both instructions
727
      write memory or if the first instruction writes memory and the second
728
      reads, then they cannot be done in parallel. We treat reads to the PSW
729
      (which includes C, F0, and F1) in isolation. So simultaneously writing
730
      C and F0 in two different sub-instructions is permitted.  */
731
 
732
  /* The bitmasks (mod and used) look like this (bit 31 = MSB).
733
     r0-r15       0-15
734
     a0-a1        16-17
735
     cr (not psw) 18
736
     psw(other)   19
737
     mem          20
738
     psw(C flag)  21
739
     psw(F0 flag) 22  */
740
 
741
  for (j = 0; j < 2; j++)
742
    {
743
      if (j == 0)
744
        {
745
          op = op1;
746
          ins = insn1;
747
        }
748
      else
749
        {
750
          op = op2;
751
          ins = insn2;
752
        }
753
      mod[j] = 0;
754
      if (op->exec_type & BRANCH_LINK)
755
        mod[j] |= 1 << 13;
756
 
757
      for (i = 0; op->operands[i]; i++)
758
        {
759
          flags = d10v_operands[op->operands[i]].flags;
760
          shift = d10v_operands[op->operands[i]].shift;
761
          mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
762
          if (flags & OPERAND_REG)
763
            {
764
              regno = (ins >> shift) & mask;
765
              if (flags & (OPERAND_ACC0 | OPERAND_ACC1))
766
                regno += 16;
767
              else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */
768
                {
769
                  if (regno == 0)
770
                    regno = 19;
771
                  else
772
                    regno = 18;
773
                }
774
              else if (flags & OPERAND_FFLAG)
775
                regno = 22;
776
              else if (flags & OPERAND_CFLAG)
777
                regno = 21;
778
 
779
              if (flags & OPERAND_DEST
780
                  /* Auto inc/dec also modifies the register.  */
781
                  || (op->operands[i + 1] != 0
782
                      && (d10v_operands[op->operands[i + 1]].flags
783
                          & (OPERAND_PLUS | OPERAND_MINUS)) != 0))
784
                {
785
                  mod[j] |= 1 << regno;
786
                  if (flags & OPERAND_EVEN)
787
                    mod[j] |= 1 << (regno + 1);
788
                }
789
            }
790
          else if (flags & OPERAND_ATMINUS)
791
            {
792
              /* SP implicitly used/modified.  */
793
              mod[j] |= 1 << 15;
794
            }
795
        }
796
 
797
      if (op->exec_type & WMEM)
798
        mod[j] |= 1 << 20;
799
      else if (op->exec_type & WF0)
800
        mod[j] |= 1 << 22;
801
      else if (op->exec_type & WCAR)
802
        mod[j] |= 1 << 21;
803
    }
804
 
805
  if ((mod[0] & mod[1]) == 0)
806
    return;
807
  else
808
    {
809
      unsigned long x;
810
      x = mod[0] & mod[1];
811
 
812
      for (j = 0; j <= 15; j++)
813
        if (x & (1 << j))
814
          as_warn (_("resource conflict (R%d)"), j);
815
      for (j = 16; j <= 17; j++)
816
        if (x & (1 << j))
817
          as_warn (_("resource conflict (A%d)"), j - 16);
818
      if (x & (1 << 19))
819
        as_warn (_("resource conflict (PSW)"));
820
      if (x & (1 << 21))
821
        as_warn (_("resource conflict (C flag)"));
822
      if (x & (1 << 22))
823
        as_warn (_("resource conflict (F flag)"));
824
    }
825
}
826
 
827
/* Check 2 instructions and determine if they can be safely
828
   executed in parallel.  Return 1 if they can be.  */
829
 
830
static int
831
parallel_ok (struct d10v_opcode *op1,
832
             unsigned long insn1,
833
             struct d10v_opcode *op2,
834
             unsigned long insn2,
835
             packing_type exec_type)
836
{
837
  int i, j, flags, mask, shift, regno;
838
  unsigned long ins, mod[2], used[2];
839
  struct d10v_opcode *op;
840
 
841
  if ((op1->exec_type & SEQ) != 0 || (op2->exec_type & SEQ) != 0
842
      || (op1->exec_type & PAR) == 0 || (op2->exec_type & PAR) == 0
843
      || (op1->unit == BOTH) || (op2->unit == BOTH)
844
      || (op1->unit == IU && op2->unit == IU)
845
      || (op1->unit == MU && op2->unit == MU))
846
    return 0;
847
 
848
  /* If this is auto parallelization, and the first instruction is a
849
     branch or should not be packed, then don't parallelize.  */
850
  if (exec_type == PACK_UNSPEC
851
      && (op1->exec_type & (ALONE | BRANCH)))
852
    return 0;
853
 
854
  /* The idea here is to create two sets of bitmasks (mod and used)
855
     which indicate which registers are modified or used by each
856
     instruction.  The operation can only be done in parallel if
857
     instruction 1 and instruction 2 modify different registers, and
858
     the first instruction does not modify registers that the second
859
     is using (The second instruction can modify registers that the
860
     first is using as they are only written back after the first
861
     instruction has completed).  Accesses to control registers, PSW,
862
     and memory are treated as accesses to a single register.  So if
863
     both instructions write memory or if the first instruction writes
864
     memory and the second reads, then they cannot be done in
865
     parallel.  Likewise, if the first instruction mucks with the psw
866
     and the second reads the PSW (which includes C, F0, and F1), then
867
     they cannot operate safely in parallel.  */
868
 
869
  /* The bitmasks (mod and used) look like this (bit 31 = MSB).
870
     r0-r15       0-15
871
     a0-a1        16-17
872
     cr (not psw) 18
873
     psw          19
874
     mem          20  */
875
 
876
  for (j = 0; j < 2; j++)
877
    {
878
      if (j == 0)
879
        {
880
          op = op1;
881
          ins = insn1;
882
        }
883
      else
884
        {
885
          op = op2;
886
          ins = insn2;
887
        }
888
      mod[j] = used[j] = 0;
889
      if (op->exec_type & BRANCH_LINK)
890
        mod[j] |= 1 << 13;
891
 
892
      for (i = 0; op->operands[i]; i++)
893
        {
894
          flags = d10v_operands[op->operands[i]].flags;
895
          shift = d10v_operands[op->operands[i]].shift;
896
          mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
897
          if (flags & OPERAND_REG)
898
            {
899
              regno = (ins >> shift) & mask;
900
              if (flags & (OPERAND_ACC0 | OPERAND_ACC1))
901
                regno += 16;
902
              else if (flags & OPERAND_CONTROL) /* mvtc or mvfc.  */
903
                {
904
                  if (regno == 0)
905
                    regno = 19;
906
                  else
907
                    regno = 18;
908
                }
909
              else if (flags & (OPERAND_FFLAG | OPERAND_CFLAG))
910
                regno = 19;
911
 
912
              if (flags & OPERAND_DEST)
913
                {
914
                  mod[j] |= 1 << regno;
915
                  if (flags & OPERAND_EVEN)
916
                    mod[j] |= 1 << (regno + 1);
917
                }
918
              else
919
                {
920
                  used[j] |= 1 << regno;
921
                  if (flags & OPERAND_EVEN)
922
                    used[j] |= 1 << (regno + 1);
923
 
924
                  /* Auto inc/dec also modifies the register.  */
925
                  if (op->operands[i + 1] != 0
926
                      && (d10v_operands[op->operands[i + 1]].flags
927
                          & (OPERAND_PLUS | OPERAND_MINUS)) != 0)
928
                    mod[j] |= 1 << regno;
929
                }
930
            }
931
          else if (flags & OPERAND_ATMINUS)
932
            {
933
              /* SP implicitly used/modified.  */
934
              mod[j] |= 1 << 15;
935
              used[j] |= 1 << 15;
936
            }
937
        }
938
      if (op->exec_type & RMEM)
939
        used[j] |= 1 << 20;
940
      else if (op->exec_type & WMEM)
941
        mod[j] |= 1 << 20;
942
      else if (op->exec_type & RF0)
943
        used[j] |= 1 << 19;
944
      else if (op->exec_type & WF0)
945
        mod[j] |= 1 << 19;
946
      else if (op->exec_type & WCAR)
947
        mod[j] |= 1 << 19;
948
    }
949
  if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0)
950
    return 1;
951
  return 0;
952
}
953
 
954
/* Expects two short instructions.
955
   If possible, writes out both as a single packed instruction.
956
   Otherwise, writes out the first one, packed with a NOP.
957
   Returns number of instructions not written out.  */
958
 
959
static int
960
write_2_short (struct d10v_opcode *opcode1,
961
               unsigned long insn1,
962
               struct d10v_opcode *opcode2,
963
               unsigned long insn2,
964
               packing_type exec_type,
965
               Fixups *fx)
966
{
967
  unsigned long insn;
968
  char *f;
969
  int i, j, where;
970
 
971
  if ((exec_type != PACK_PARALLEL)
972
      && ((opcode1->exec_type & PARONLY) || (opcode2->exec_type & PARONLY)))
973
    as_fatal (_("Instruction must be executed in parallel"));
974
 
975
  if ((opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
976
    as_fatal (_("Long instructions may not be combined."));
977
 
978
  switch (exec_type)
979
    {
980
    case PACK_UNSPEC:   /* Order not specified.  */
981
      if (opcode1->exec_type & ALONE)
982
        {
983
          /* Case of a short branch on a separate GAS line.  Pack with NOP.  */
984
          write_1_short (opcode1, insn1, fx->next);
985
          return 1;
986
        }
987
      if (Optimizing
988
          && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
989
        {
990
          /* Parallel.  */
991
          if (opcode1->unit == IU)
992
            insn = FM00 | (insn2 << 15) | insn1;
993
          else if (opcode2->unit == MU)
994
            insn = FM00 | (insn2 << 15) | insn1;
995
          else
996
            insn = FM00 | (insn1 << 15) | insn2;
997
        }
998
      else if (opcode1->unit == IU)
999
        /* Reverse sequential with IU opcode1 on right and done first.  */
1000
        insn = FM10 | (insn2 << 15) | insn1;
1001
      else
1002
        /* Sequential with non-IU opcode1 on left and done first.  */
1003
        insn = FM01 | (insn1 << 15) | insn2;
1004
      break;
1005
 
1006
    case PACK_PARALLEL:
1007
      if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ)
1008
        as_fatal
1009
          (_("One of these instructions may not be executed in parallel."));
1010
      if (opcode1->unit == IU)
1011
        {
1012
          if (opcode2->unit == IU)
1013
            as_fatal (_("Two IU instructions may not be executed in parallel"));
1014
          if (!flag_warn_suppress_instructionswap)
1015
            as_warn (_("Swapping instruction order"));
1016
          insn = FM00 | (insn2 << 15) | insn1;
1017
        }
1018
      else if (opcode2->unit == MU)
1019
        {
1020
          if (opcode1->unit == MU)
1021
            as_fatal (_("Two MU instructions may not be executed in parallel"));
1022
          if (!flag_warn_suppress_instructionswap)
1023
            as_warn (_("Swapping instruction order"));
1024
          insn = FM00 | (insn2 << 15) | insn1;
1025
        }
1026
      else
1027
        insn = FM00 | (insn1 << 15) | insn2;
1028
      check_resource_conflict (opcode1, insn1, opcode2, insn2);
1029
      break;
1030
 
1031
    case PACK_LEFT_RIGHT:
1032
      if (opcode1->unit != IU)
1033
        insn = FM01 | (insn1 << 15) | insn2;
1034
      else if (opcode2->unit == MU || opcode2->unit == EITHER)
1035
        {
1036
          if (!flag_warn_suppress_instructionswap)
1037
            as_warn (_("Swapping instruction order"));
1038
          insn = FM10 | (insn2 << 15) | insn1;
1039
        }
1040
      else
1041
        as_fatal (_("IU instruction may not be in the left container"));
1042
      if (opcode1->exec_type & ALONE)
1043
        as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
1044
      break;
1045
 
1046
    case PACK_RIGHT_LEFT:
1047
      if (opcode2->unit != MU)
1048
        insn = FM10 | (insn1 << 15) | insn2;
1049
      else if (opcode1->unit == IU || opcode1->unit == EITHER)
1050
        {
1051
          if (!flag_warn_suppress_instructionswap)
1052
            as_warn (_("Swapping instruction order"));
1053
          insn = FM01 | (insn2 << 15) | insn1;
1054
        }
1055
      else
1056
        as_fatal (_("MU instruction may not be in the right container"));
1057
      if (opcode2->exec_type & ALONE)
1058
        as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
1059
      break;
1060
 
1061
    default:
1062
      as_fatal (_("unknown execution type passed to write_2_short()"));
1063
    }
1064
 
1065
  f = frag_more (4);
1066
  dwarf2_emit_insn (4);
1067
  number_to_chars_bigendian (f, insn, 4);
1068
 
1069
  /* Process fixup chains.  fx refers to insn2 when j == 0, and to
1070
     insn1 when j == 1.  Yes, it's reversed.  */
1071
 
1072
  for (j = 0; j < 2; j++)
1073
    {
1074
      for (i = 0; i < fx->fc; i++)
1075
        {
1076
          if (fx->fix[i].reloc)
1077
            {
1078
              where = f - frag_now->fr_literal;
1079
              if (fx->fix[i].size == 2)
1080
                where += 2;
1081
 
1082
              if (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R
1083
                  /* A BFD_RELOC_D10V_10_PCREL_R relocation applied to
1084
                     the instruction in the L container has to be
1085
                     adjusted to BDF_RELOC_D10V_10_PCREL_L.  When
1086
                     j==0, we're processing insn2's operands, so we
1087
                     want to mark the operand if insn2 is *not* in the
1088
                     R container.  When j==1, we're processing insn1's
1089
                     operands, so we want to mark the operand if insn2
1090
                     *is* in the R container.  Note that, if two
1091
                     instructions are identical, we're never going to
1092
                     swap them, so the test is safe.  */
1093
                  && j == ((insn & 0x7fff) == insn2))
1094
                fx->fix[i].operand |= 1024;
1095
 
1096
              if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
1097
                fx->fix[i].operand |= 4096;
1098
 
1099
              fix_new_exp (frag_now,
1100
                           where,
1101
                           fx->fix[i].size,
1102
                           &(fx->fix[i].exp),
1103
                           fx->fix[i].pcrel,
1104
                           fx->fix[i].operand|2048);
1105
            }
1106
        }
1107
      fx->fc = 0;
1108
      fx = fx->next;
1109
    }
1110
  return 0;
1111
}
1112
 
1113
/* This is the main entry point for the machine-dependent assembler.
1114
   str points to a machine-dependent instruction.  This function is
1115
   supposed to emit the frags/bytes it assembles to.  For the D10V, it
1116
   mostly handles the special VLIW parsing and packing and leaves the
1117
   difficult stuff to do_assemble().  */
1118
 
1119
static unsigned long prev_insn;
1120
static struct d10v_opcode *prev_opcode = 0;
1121
static subsegT prev_subseg;
1122
static segT prev_seg = 0;;
1123
 
1124
/* Find the symbol which has the same name as the register in exp.  */
1125
 
1126
static symbolS *
1127
find_symbol_matching_register (expressionS *exp)
1128
{
1129
  int i;
1130
 
1131
  if (exp->X_op != O_register)
1132
    return NULL;
1133
 
1134
  /* Find the name of the register.  */
1135
  for (i = d10v_reg_name_cnt (); i--;)
1136
    if (d10v_predefined_registers[i].value == exp->X_add_number)
1137
      break;
1138
 
1139
  if (i < 0)
1140
    abort ();
1141
 
1142
  /* Now see if a symbol has been defined with the same name.  */
1143
  return symbol_find (d10v_predefined_registers[i].name);
1144
}
1145
 
1146
/* Get a pointer to an entry in the opcode table.
1147
   The function must look at all opcodes with the same name and use
1148
   the operands to choose the correct opcode.  */
1149
 
1150
static struct d10v_opcode *
1151
find_opcode (struct d10v_opcode *opcode, expressionS myops[])
1152
{
1153
  int i, match;
1154
  struct d10v_opcode *next_opcode;
1155
 
1156
  /* Get all the operands and save them as expressions.  */
1157
  get_operands (myops);
1158
 
1159
  /* Now see if the operand is a fake.  If so, find the correct size
1160
     instruction, if possible.  */
1161
  if (opcode->format == OPCODE_FAKE)
1162
    {
1163
      int opnum = opcode->operands[0];
1164
      int flags;
1165
 
1166
      if (myops[opnum].X_op == O_register)
1167
        {
1168
          myops[opnum].X_op = O_symbol;
1169
          myops[opnum].X_add_symbol =
1170
            symbol_find_or_make ((char *) myops[opnum].X_op_symbol);
1171
          myops[opnum].X_add_number = 0;
1172
          myops[opnum].X_op_symbol = NULL;
1173
        }
1174
 
1175
      next_opcode = opcode + 1;
1176
 
1177
      /* If the first operand is supposed to be a register, make sure
1178
         we got a valid one.  */
1179
      flags = d10v_operands[next_opcode->operands[0]].flags;
1180
      if (flags & OPERAND_REG)
1181
        {
1182
          int X_op = myops[0].X_op;
1183
          int num = myops[0].X_add_number;
1184
 
1185
          if (X_op != O_register
1186
              || (num & ~flags
1187
                  & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1
1188
                     | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL))
1189
              || ((flags & OPERAND_SP) && ! (num & OPERAND_SP)))
1190
            {
1191
              as_bad (_("bad opcode or operands"));
1192
              return 0;
1193
            }
1194
        }
1195
 
1196
      if (myops[opnum].X_op == O_constant
1197
          || (myops[opnum].X_op == O_symbol
1198
              && S_IS_DEFINED (myops[opnum].X_add_symbol)
1199
              && (S_GET_SEGMENT (myops[opnum].X_add_symbol) == now_seg)))
1200
        {
1201
          for (i = 0; opcode->operands[i + 1]; i++)
1202
            {
1203
              int bits = d10v_operands[next_opcode->operands[opnum]].bits;
1204
 
1205
              flags = d10v_operands[next_opcode->operands[opnum]].flags;
1206
 
1207
              if (flags & OPERAND_ADDR)
1208
                bits += 2;
1209
 
1210
              if (myops[opnum].X_op == O_constant)
1211
                {
1212
                  if (!check_range (myops[opnum].X_add_number, bits, flags))
1213
                    break;
1214
                }
1215
              else
1216
                {
1217
                  fragS *sym_frag;
1218
                  fragS *f;
1219
                  unsigned long current_position;
1220
                  unsigned long symbol_position;
1221
                  unsigned long value;
1222
                  bfd_boolean found_symbol;
1223
 
1224
                  /* Calculate the address of the current instruction
1225
                     and the address of the symbol.  Do this by summing
1226
                     the offsets of previous frags until we reach the
1227
                     frag containing the symbol, and the current frag.  */
1228
                  sym_frag = symbol_get_frag (myops[opnum].X_add_symbol);
1229
                  found_symbol = FALSE;
1230
 
1231
                  current_position =
1232
                    obstack_next_free (&frchain_now->frch_obstack)
1233
                    - frag_now->fr_literal;
1234
                  symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol);
1235
 
1236
                  for (f = frchain_now->frch_root; f; f = f->fr_next)
1237
                    {
1238
                      current_position += f->fr_fix + f->fr_offset;
1239
 
1240
                      if (f == sym_frag)
1241
                        found_symbol = TRUE;
1242
 
1243
                      if (! found_symbol)
1244
                        symbol_position += f->fr_fix + f->fr_offset;
1245
                    }
1246
 
1247
                  value = symbol_position;
1248
 
1249
                  if (flags & OPERAND_ADDR)
1250
                    value -= current_position;
1251
 
1252
                  if (AT_WORD_P (&myops[opnum]))
1253
                    {
1254
                      if (bits > 4)
1255
                        {
1256
                          bits += 2;
1257
                          if (!check_range (value, bits, flags))
1258
                            break;
1259
                        }
1260
                    }
1261
                  else if (!check_range (value, bits, flags))
1262
                    break;
1263
                }
1264
              next_opcode++;
1265
            }
1266
 
1267
          if (opcode->operands [i + 1] == 0)
1268
            as_fatal (_("value out of range"));
1269
          else
1270
            opcode = next_opcode;
1271
        }
1272
      else
1273
        /* Not a constant, so use a long instruction.  */
1274
        opcode += 2;
1275
    }
1276
 
1277
  match = 0;
1278
 
1279
  /* Now search the opcode table table for one with operands
1280
     that matches what we've got.  */
1281
  while (!match)
1282
    {
1283
      match = 1;
1284
      for (i = 0; opcode->operands[i]; i++)
1285
        {
1286
          int flags = d10v_operands[opcode->operands[i]].flags;
1287
          int X_op = myops[i].X_op;
1288
          int num = myops[i].X_add_number;
1289
 
1290
          if (X_op == 0)
1291
            {
1292
              match = 0;
1293
              break;
1294
            }
1295
 
1296
          if (flags & OPERAND_REG)
1297
            {
1298
              if ((X_op != O_register)
1299
                  || (num & ~flags
1300
                      & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1
1301
                         | OPERAND_FFLAG | OPERAND_CFLAG
1302
                         | OPERAND_CONTROL))
1303
                  || ((flags & OPERAND_SP) && ! (num & OPERAND_SP)))
1304
                {
1305
                  match = 0;
1306
                  break;
1307
                }
1308
            }
1309
 
1310
          if (((flags & OPERAND_MINUS)   && ((X_op != O_absent) || (num != OPERAND_MINUS))) ||
1311
              ((flags & OPERAND_PLUS)    && ((X_op != O_absent) || (num != OPERAND_PLUS))) ||
1312
              ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) ||
1313
              ((flags & OPERAND_ATPAR)   && ((X_op != O_absent) || (num != OPERAND_ATPAR))) ||
1314
              ((flags & OPERAND_ATSIGN)  && ((X_op != O_absent) || ((num != OPERAND_ATSIGN) && (num != OPERAND_ATPAR)))))
1315
            {
1316
              match = 0;
1317
              break;
1318
            }
1319
 
1320
          /* Unfortunately, for the indirect operand in instructions such
1321
             as ``ldb r1, @(c,r14)'' this function can be passed
1322
             X_op == O_register (because 'c' is a valid register name).
1323
             However we cannot just ignore the case when X_op == O_register
1324
             but flags & OPERAND_REG is null, so we check to see if a symbol
1325
             of the same name as the register exists.  If the symbol does
1326
             exist, then the parser was unable to distinguish the two cases
1327
             and we fix things here. (Ref: PR14826)  */
1328
 
1329
          if (!(flags & OPERAND_REG) && (X_op == O_register))
1330
            {
1331
              symbolS * sym;
1332
 
1333
              sym = find_symbol_matching_register (& myops[i]);
1334
 
1335
              if (sym != NULL)
1336
                {
1337
                  myops[i].X_op = X_op = O_symbol;
1338
                  myops[i].X_add_symbol = sym;
1339
                }
1340
              else
1341
                as_bad
1342
                  (_("illegal operand - register name found where none expected"));
1343
            }
1344
        }
1345
 
1346
      /* We're only done if the operands matched so far AND there
1347
             are no more to check.  */
1348
      if (match && myops[i].X_op == 0)
1349
        break;
1350
      else
1351
        match = 0;
1352
 
1353
      next_opcode = opcode + 1;
1354
 
1355
      if (next_opcode->opcode == 0)
1356
        break;
1357
 
1358
      if (strcmp (next_opcode->name, opcode->name))
1359
        break;
1360
 
1361
      opcode = next_opcode;
1362
    }
1363
 
1364
  if (!match)
1365
    {
1366
      as_bad (_("bad opcode or operands"));
1367
      return 0;
1368
    }
1369
 
1370
  /* Check that all registers that are required to be even are.
1371
     Also, if any operands were marked as registers, but were really symbols,
1372
     fix that here.  */
1373
  for (i = 0; opcode->operands[i]; i++)
1374
    {
1375
      if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) &&
1376
          (myops[i].X_add_number & 1))
1377
        as_fatal (_("Register number must be EVEN"));
1378
      if ((d10v_operands[opcode->operands[i]].flags & OPERAND_NOSP)
1379
          && (myops[i].X_add_number & OPERAND_SP))
1380
        as_bad (_("Unsupported use of sp"));
1381
      if (myops[i].X_op == O_register)
1382
        {
1383
          if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG))
1384
            {
1385
              myops[i].X_op = O_symbol;
1386
              myops[i].X_add_symbol =
1387
                symbol_find_or_make ((char *) myops[i].X_op_symbol);
1388
              myops[i].X_add_number = 0;
1389
              myops[i].X_op_symbol = NULL;
1390
            }
1391
        }
1392
      if ((d10v_operands[opcode->operands[i]].flags & OPERAND_CONTROL)
1393
          && (myops[i].X_add_number == OPERAND_CONTROL + 4
1394
              || myops[i].X_add_number == OPERAND_CONTROL + 5
1395
              || myops[i].X_add_number == OPERAND_CONTROL + 6
1396
              || myops[i].X_add_number == OPERAND_CONTROL + 12
1397
              || myops[i].X_add_number == OPERAND_CONTROL + 13
1398
              || myops[i].X_add_number == OPERAND_CONTROL + 15))
1399
        as_warn (_("cr%ld is a reserved control register"),
1400
                 myops[i].X_add_number - OPERAND_CONTROL);
1401
    }
1402
  return opcode;
1403
}
1404
 
1405
/* Assemble a single instruction.
1406
   Return an opcode, or -1 (an invalid opcode) on error.  */
1407
 
1408
static unsigned long
1409
do_assemble (char *str, struct d10v_opcode **opcode)
1410
{
1411
  unsigned char *op_start, *op_end;
1412
  char *save;
1413
  char name[20];
1414
  int nlen = 0;
1415
  expressionS myops[6];
1416
 
1417
  /* Drop leading whitespace.  */
1418
  while (*str == ' ')
1419
    str++;
1420
 
1421
  /* Find the opcode end.  */
1422
  for (op_start = op_end = (unsigned char *) str;
1423
       *op_end && !is_end_of_line[*op_end] && *op_end != ' ';
1424
       op_end++)
1425
    {
1426
      name[nlen] = TOLOWER (op_start[nlen]);
1427
      nlen++;
1428
      if (nlen == sizeof (name) - 1)
1429
        break;
1430
    }
1431
  name[nlen] = 0;
1432
 
1433
  if (nlen == 0)
1434
    return -1;
1435
 
1436
  /* Find the first opcode with the proper name.  */
1437
  *opcode = (struct d10v_opcode *) hash_find (d10v_hash, name);
1438
  if (*opcode == NULL)
1439
    return -1;
1440
 
1441
  save = input_line_pointer;
1442
  input_line_pointer = (char *) op_end;
1443
  *opcode = find_opcode (*opcode, myops);
1444
  if (*opcode == 0)
1445
    return -1;
1446
  input_line_pointer = save;
1447
 
1448
  return build_insn ((*opcode), myops, 0);
1449
}
1450
 
1451
/* If while processing a fixup, a reloc really needs to be created.
1452
   Then it is done here.  */
1453
 
1454
arelent *
1455
tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
1456
{
1457
  arelent *reloc;
1458
  reloc = xmalloc (sizeof (arelent));
1459
  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
1460
  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1461
  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1462
  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1463
  if (reloc->howto == (reloc_howto_type *) NULL)
1464
    {
1465
      as_bad_where (fixp->fx_file, fixp->fx_line,
1466
                    _("reloc %d not supported by object file format"),
1467
                    (int) fixp->fx_r_type);
1468
      return NULL;
1469
    }
1470
 
1471
  if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1472
    reloc->address = fixp->fx_offset;
1473
 
1474
  reloc->addend = 0;
1475
 
1476
  return reloc;
1477
}
1478
 
1479
int
1480
md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
1481
                               asection *seg ATTRIBUTE_UNUSED)
1482
{
1483
  abort ();
1484
  return 0;
1485
}
1486
 
1487
long
1488
md_pcrel_from_section (fixS *fixp, segT sec)
1489
{
1490
  if (fixp->fx_addsy != (symbolS *) NULL
1491
      && (!S_IS_DEFINED (fixp->fx_addsy)
1492
          || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
1493
    return 0;
1494
  return fixp->fx_frag->fr_address + fixp->fx_where;
1495
}
1496
 
1497
void
1498
md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
1499
{
1500
  char *where;
1501
  unsigned long insn;
1502
  long value = *valP;
1503
  int op_type;
1504
  int left = 0;
1505
 
1506
  if (fixP->fx_addsy == (symbolS *) NULL)
1507
    fixP->fx_done = 1;
1508
 
1509
  /* We don't actually support subtracting a symbol.  */
1510
  if (fixP->fx_subsy != (symbolS *) NULL)
1511
    as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1512
 
1513
  op_type = fixP->fx_r_type;
1514
  if (op_type & 2048)
1515
    {
1516
      op_type -= 2048;
1517
      if (op_type & 1024)
1518
        {
1519
          op_type -= 1024;
1520
          fixP->fx_r_type = BFD_RELOC_D10V_10_PCREL_L;
1521
          left = 1;
1522
        }
1523
      else if (op_type & 4096)
1524
        {
1525
          op_type -= 4096;
1526
          fixP->fx_r_type = BFD_RELOC_D10V_18;
1527
        }
1528
      else
1529
        fixP->fx_r_type =
1530
          get_reloc ((struct d10v_operand *) &d10v_operands[op_type]);
1531
    }
1532
 
1533
  /* Fetch the instruction, insert the fully resolved operand
1534
     value, and stuff the instruction back again.  */
1535
  where = fixP->fx_frag->fr_literal + fixP->fx_where;
1536
  insn = bfd_getb32 ((unsigned char *) where);
1537
 
1538
  switch (fixP->fx_r_type)
1539
    {
1540
    case BFD_RELOC_D10V_10_PCREL_L:
1541
    case BFD_RELOC_D10V_10_PCREL_R:
1542
    case BFD_RELOC_D10V_18_PCREL:
1543
      /* If the fix is relative to a global symbol, not a section
1544
         symbol, then ignore the offset.
1545
         XXX - Do we have to worry about branches to a symbol + offset ?  */
1546
      if (fixP->fx_addsy != NULL
1547
          && S_IS_EXTERNAL (fixP->fx_addsy) )
1548
        {
1549
          segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
1550
          segment_info_type *segf = seg_info(fseg);
1551
 
1552
          if ( segf && segf->sym != fixP->fx_addsy)
1553
            value = 0;
1554
        }
1555
      /* Drop through.  */
1556
    case BFD_RELOC_D10V_18:
1557
      /* Instruction addresses are always right-shifted by 2.  */
1558
      value >>= AT_WORD_RIGHT_SHIFT;
1559
      if (fixP->fx_size == 2)
1560
        bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
1561
      else
1562
        {
1563
          struct d10v_opcode *rep, *repi;
1564
 
1565
          rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep");
1566
          repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi");
1567
          if ((insn & FM11) == FM11
1568
              && ((repi != NULL
1569
                   && (insn & repi->mask) == (unsigned) repi->opcode)
1570
                  || (rep != NULL
1571
                      && (insn & rep->mask) == (unsigned) rep->opcode))
1572
              && value < 4)
1573
            as_fatal
1574
              (_("line %d: rep or repi must include at least 4 instructions"),
1575
               fixP->fx_line);
1576
          insn =
1577
            d10v_insert_operand (insn, op_type, (offsetT) value, left, fixP);
1578
          bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1579
        }
1580
      break;
1581
    case BFD_RELOC_32:
1582
      bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
1583
      break;
1584
    case BFD_RELOC_16:
1585
      bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
1586
      break;
1587
 
1588
    case BFD_RELOC_VTABLE_INHERIT:
1589
    case BFD_RELOC_VTABLE_ENTRY:
1590
      fixP->fx_done = 0;
1591
      return;
1592
 
1593
    default:
1594
      as_fatal (_("line %d: unknown relocation type: 0x%x"),
1595
                fixP->fx_line, fixP->fx_r_type);
1596
    }
1597
}
1598
 
1599
/* d10v_cleanup() is called after the assembler has finished parsing
1600
   the input file, when a label is read from the input file, or when a
1601
   stab directive is output.  Because the D10V assembler sometimes
1602
   saves short instructions to see if it can package them with the
1603
   next instruction, there may be a short instruction that still needs
1604
   to be written.
1605
 
1606
   NOTE: accesses a global, etype.
1607
   NOTE: invoked by various macros such as md_cleanup: see.  */
1608
 
1609
int
1610
d10v_cleanup (void)
1611
{
1612
  segT seg;
1613
  subsegT subseg;
1614
 
1615
  /* If cleanup was invoked because the assembler encountered, e.g., a
1616
     user label, we write out the pending instruction, if any.  If it
1617
     was invoked because the assembler is outputting a piece of line
1618
     debugging information, though, we write out the pending
1619
     instruction only if the --no-gstabs-packing command line switch
1620
     has been specified.  */
1621
  if (prev_opcode
1622
      && etype == PACK_UNSPEC
1623
      && (! outputting_stabs_line_debug || ! flag_allow_gstabs_packing))
1624
    {
1625
      seg = now_seg;
1626
      subseg = now_subseg;
1627
 
1628
      if (prev_seg)
1629
        subseg_set (prev_seg, prev_subseg);
1630
 
1631
      write_1_short (prev_opcode, prev_insn, fixups->next);
1632
      subseg_set (seg, subseg);
1633
      prev_opcode = NULL;
1634
    }
1635
  return 1;
1636
}
1637
 
1638
void
1639
d10v_frob_label (symbolS *lab)
1640
{
1641
  d10v_cleanup ();
1642
  symbol_set_frag (lab, frag_now);
1643
  S_SET_VALUE (lab, (valueT) frag_now_fix ());
1644
  dwarf2_emit_label (lab);
1645
}
1646
 
1647
/* Like normal .word, except support @word.
1648
   Clobbers input_line_pointer, checks end-of-line.  */
1649
 
1650
static void
1651
d10v_dot_word (int dummy ATTRIBUTE_UNUSED)
1652
{
1653
  expressionS exp;
1654
  char *p;
1655
 
1656
  if (is_it_end_of_statement ())
1657
    {
1658
      demand_empty_rest_of_line ();
1659
      return;
1660
    }
1661
 
1662
  do
1663
    {
1664
      expression (&exp);
1665
      if (!strncasecmp (input_line_pointer, "@word", 5))
1666
        {
1667
          exp.X_add_number = 0;
1668
          input_line_pointer += 5;
1669
 
1670
          p = frag_more (2);
1671
          fix_new_exp (frag_now, p - frag_now->fr_literal, 2,
1672
                       &exp, 0, BFD_RELOC_D10V_18);
1673
        }
1674
      else
1675
        emit_expr (&exp, 2);
1676
    }
1677
  while (*input_line_pointer++ == ',');
1678
 
1679
  input_line_pointer--;         /* Put terminator back into stream.  */
1680
  demand_empty_rest_of_line ();
1681
}
1682
 
1683
/* Mitsubishi asked that we support some old syntax that apparently
1684
   had immediate operands starting with '#'.  This is in some of their
1685
   sample code but is not documented (although it appears in some
1686
   examples in their assembler manual). For now, we'll solve this
1687
   compatibility problem by simply ignoring any '#' at the beginning
1688
   of an operand.  */
1689
 
1690
/* Operands that begin with '#' should fall through to here.
1691
   From expr.c.  */
1692
 
1693
void
1694
md_operand (expressionS *expressionP)
1695
{
1696
  if (*input_line_pointer == '#' && ! do_not_ignore_hash)
1697
    {
1698
      input_line_pointer++;
1699
      expression (expressionP);
1700
    }
1701
}
1702
 
1703
bfd_boolean
1704
d10v_fix_adjustable (fixS *fixP)
1705
{
1706
  /* We need the symbol name for the VTABLE entries.  */
1707
  if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1708
      || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1709
    return 0;
1710
 
1711
  return 1;
1712
}
1713
 
1714
/* The target specific pseudo-ops which we support.  */
1715
const pseudo_typeS md_pseudo_table[] =
1716
{
1717
  { "word",     d10v_dot_word,  2 },
1718
  { NULL,       NULL,           0 }
1719
};
1720
 
1721
void
1722
md_assemble (char *str)
1723
{
1724
  /* etype is saved extype.  For multi-line instructions.  */
1725
  packing_type extype = PACK_UNSPEC;            /* Parallel, etc.  */
1726
  struct d10v_opcode *opcode;
1727
  unsigned long insn;
1728
  char *str2;
1729
 
1730
  if (etype == PACK_UNSPEC)
1731
    {
1732
      /* Look for the special multiple instruction separators.  */
1733
      str2 = strstr (str, "||");
1734
      if (str2)
1735
        extype = PACK_PARALLEL;
1736
      else
1737
        {
1738
          str2 = strstr (str, "->");
1739
          if (str2)
1740
            extype = PACK_LEFT_RIGHT;
1741
          else
1742
            {
1743
              str2 = strstr (str, "<-");
1744
              if (str2)
1745
                extype = PACK_RIGHT_LEFT;
1746
            }
1747
        }
1748
 
1749
      /* str2 points to the separator, if there is one.  */
1750
      if (str2)
1751
        {
1752
          *str2 = 0;
1753
 
1754
          /* If two instructions are present and we already have one saved,
1755
             then first write out the saved one.  */
1756
          d10v_cleanup ();
1757
 
1758
          /* Assemble first instruction and save it.  */
1759
          prev_insn = do_assemble (str, &prev_opcode);
1760
          prev_seg = now_seg;
1761
          prev_subseg = now_subseg;
1762
          if (prev_insn == (unsigned long) -1)
1763
            as_fatal (_("can't find previous opcode "));
1764
          fixups = fixups->next;
1765
          str = str2 + 2;
1766
        }
1767
    }
1768
 
1769
  insn = do_assemble (str, &opcode);
1770
  if (insn == (unsigned long) -1)
1771
    {
1772
      if (extype != PACK_UNSPEC)
1773
        etype = extype;
1774
      else
1775
        as_bad (_("could not assemble: %s"), str);
1776
      return;
1777
    }
1778
 
1779
  if (etype != PACK_UNSPEC)
1780
    {
1781
      extype = etype;
1782
      etype = PACK_UNSPEC;
1783
    }
1784
 
1785
  /* If this is a long instruction, write it and any previous short
1786
     instruction.  */
1787
  if (opcode->format & LONG_OPCODE)
1788
    {
1789
      if (extype != PACK_UNSPEC)
1790
        as_fatal (_("Unable to mix instructions as specified"));
1791
      d10v_cleanup ();
1792
      write_long (insn, fixups);
1793
      prev_opcode = NULL;
1794
      return;
1795
    }
1796
 
1797
  if (prev_opcode
1798
      && prev_seg
1799
      && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
1800
    d10v_cleanup ();
1801
 
1802
  if (prev_opcode
1803
      && (0 == write_2_short (prev_opcode, prev_insn, opcode, insn, extype,
1804
                              fixups)))
1805
    {
1806
      /* No instructions saved.  */
1807
      prev_opcode = NULL;
1808
    }
1809
  else
1810
    {
1811
      if (extype != PACK_UNSPEC)
1812
        as_fatal (_("Unable to mix instructions as specified"));
1813
      /* Save last instruction so it may be packed on next pass.  */
1814
      prev_opcode = opcode;
1815
      prev_insn = insn;
1816
      prev_seg = now_seg;
1817
      prev_subseg = now_subseg;
1818
      fixups = fixups->next;
1819
    }
1820
}
1821
 

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