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[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [gas/] [config/] [tc-sparc.c] - Blame information for rev 299

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1 16 khays
/* tc-sparc.c -- Assemble for the SPARC
2
   Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 163 khays
   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4
   2011
5 16 khays
   Free Software Foundation, Inc.
6
   This file is part of GAS, the GNU Assembler.
7
 
8
   GAS is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3, or (at your option)
11
   any later version.
12
 
13
   GAS is distributed in the hope that it will be useful,
14
   but WITHOUT ANY WARRANTY; without even the implied warranty of
15
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
   GNU General Public License for more details.
17
 
18
   You should have received a copy of the GNU General Public
19
   License along with GAS; see the file COPYING.  If not, write
20
   to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21
   Boston, MA 02110-1301, USA.  */
22
 
23
#include "as.h"
24
#include "safe-ctype.h"
25
#include "subsegs.h"
26
 
27
#include "opcode/sparc.h"
28
#include "dw2gencfi.h"
29
 
30
#ifdef OBJ_ELF
31
#include "elf/sparc.h"
32
#include "dwarf2dbg.h"
33
#endif
34
 
35
/* Some ancient Sun C compilers would not take such hex constants as
36
   unsigned, and would end up sign-extending them to form an offsetT,
37
   so use these constants instead.  */
38
#define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
39
#define U0x80000000 ((((unsigned long) 1 << 16) << 15))
40
 
41
static int sparc_ip (char *, const struct sparc_opcode **);
42
static int parse_keyword_arg (int (*) (const char *), char **, int *);
43
static int parse_const_expr_arg (char **, int *);
44
static int get_expression (char *);
45
 
46
/* Default architecture.  */
47
/* ??? The default value should be V8, but sparclite support was added
48
   by making it the default.  GCC now passes -Asparclite, so maybe sometime in
49
   the future we can set this to V8.  */
50
#ifndef DEFAULT_ARCH
51
#define DEFAULT_ARCH "sparclite"
52
#endif
53
static char *default_arch = DEFAULT_ARCH;
54
 
55
/* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
56
   have been set.  */
57
static int default_init_p;
58
 
59
/* Current architecture.  We don't bump up unless necessary.  */
60
static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
61
 
62
/* The maximum architecture level we can bump up to.
63
   In a 32 bit environment, don't allow bumping up to v9 by default.
64
   The native assembler works this way.  The user is required to pass
65
   an explicit argument before we'll create v9 object files.  However, if
66
   we don't see any v9 insns, a v8plus object file is not created.  */
67
static enum sparc_opcode_arch_val max_architecture;
68
 
69
/* Either 32 or 64, selects file format.  */
70
static int sparc_arch_size;
71
/* Initial (default) value, recorded separately in case a user option
72
   changes the value before md_show_usage is called.  */
73
static int default_arch_size;
74
 
75
#ifdef OBJ_ELF
76
/* The currently selected v9 memory model.  Currently only used for
77
   ELF.  */
78
static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
79 163 khays
 
80
#ifndef TE_SOLARIS
81
/* Bitmask of instruction types seen so far, used to populate the
82
   GNU attributes section with hwcap information.  */
83
static int hwcap_seen;
84 16 khays
#endif
85 163 khays
#endif
86 16 khays
 
87 163 khays
static int hwcap_allowed;
88
 
89 16 khays
static int architecture_requested;
90
static int warn_on_bump;
91
 
92
/* If warn_on_bump and the needed architecture is higher than this
93
   architecture, issue a warning.  */
94
static enum sparc_opcode_arch_val warn_after_architecture;
95
 
96
/* Non-zero if as should generate error if an undeclared g[23] register
97
   has been used in -64.  */
98
static int no_undeclared_regs;
99
 
100
/* Non-zero if we should try to relax jumps and calls.  */
101
static int sparc_relax;
102
 
103
/* Non-zero if we are generating PIC code.  */
104
int sparc_pic_code;
105
 
106
/* Non-zero if we should give an error when misaligned data is seen.  */
107
static int enforce_aligned_data;
108
 
109
extern int target_big_endian;
110
 
111
static int target_little_endian_data;
112
 
113
/* Symbols for global registers on v9.  */
114
static symbolS *globals[8];
115
 
116
/* The dwarf2 data alignment, adjusted for 32 or 64 bit.  */
117
int sparc_cie_data_alignment;
118
 
119
/* V9 and 86x have big and little endian data, but instructions are always big
120
   endian.  The sparclet has bi-endian support but both data and insns have
121
   the same endianness.  Global `target_big_endian' is used for data.
122
   The following macro is used for instructions.  */
123
#ifndef INSN_BIG_ENDIAN
124
#define INSN_BIG_ENDIAN (target_big_endian \
125
                         || default_arch_type == sparc86x \
126
                         || SPARC_OPCODE_ARCH_V9_P (max_architecture))
127
#endif
128
 
129
/* Handle of the OPCODE hash table.  */
130
static struct hash_control *op_hash;
131
 
132
static void s_data1 (void);
133
static void s_seg (int);
134
static void s_proc (int);
135
static void s_reserve (int);
136
static void s_common (int);
137
static void s_empty (int);
138
static void s_uacons (int);
139
static void s_ncons (int);
140
#ifdef OBJ_ELF
141
static void s_register (int);
142
#endif
143
 
144
const pseudo_typeS md_pseudo_table[] =
145
{
146
  {"align", s_align_bytes, 0},   /* Defaulting is invalid (0).  */
147
  {"common", s_common, 0},
148
  {"empty", s_empty, 0},
149
  {"global", s_globl, 0},
150
  {"half", cons, 2},
151
  {"nword", s_ncons, 0},
152
  {"optim", s_ignore, 0},
153
  {"proc", s_proc, 0},
154
  {"reserve", s_reserve, 0},
155
  {"seg", s_seg, 0},
156
  {"skip", s_space, 0},
157
  {"word", cons, 4},
158
  {"xword", cons, 8},
159
  {"uahalf", s_uacons, 2},
160
  {"uaword", s_uacons, 4},
161
  {"uaxword", s_uacons, 8},
162
#ifdef OBJ_ELF
163
  /* These are specific to sparc/svr4.  */
164
  {"2byte", s_uacons, 2},
165
  {"4byte", s_uacons, 4},
166
  {"8byte", s_uacons, 8},
167
  {"register", s_register, 0},
168
#endif
169
  {NULL, 0, 0},
170
};
171
 
172
/* This array holds the chars that always start a comment.  If the
173
   pre-processor is disabled, these aren't very useful.  */
174
const char comment_chars[] = "!";       /* JF removed '|' from
175
                                           comment_chars.  */
176
 
177
/* This array holds the chars that only start a comment at the beginning of
178
   a line.  If the line seems to have the form '# 123 filename'
179
   .line and .file directives will appear in the pre-processed output.  */
180
/* Note that input_file.c hand checks for '#' at the beginning of the
181
   first line of the input file.  This is because the compiler outputs
182
   #NO_APP at the beginning of its output.  */
183
/* Also note that comments started like this one will always
184
   work if '/' isn't otherwise defined.  */
185
const char line_comment_chars[] = "#";
186
 
187
const char line_separator_chars[] = ";";
188
 
189
/* Chars that can be used to separate mant from exp in floating point
190
   nums.  */
191
const char EXP_CHARS[] = "eE";
192
 
193
/* Chars that mean this number is a floating point constant.
194
   As in 0f12.456
195
   or    0d1.2345e12  */
196
const char FLT_CHARS[] = "rRsSfFdDxXpP";
197
 
198
/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
199
   changed in read.c.  Ideally it shouldn't have to know about it at all,
200
   but nothing is ideal around here.  */
201
 
202
#define isoctal(c)  ((unsigned) ((c) - '0') < 8)
203
 
204
struct sparc_it
205
  {
206
    char *error;
207
    unsigned long opcode;
208
    struct nlist *nlistp;
209
    expressionS exp;
210
    expressionS exp2;
211
    int pcrel;
212
    bfd_reloc_code_real_type reloc;
213
  };
214
 
215
struct sparc_it the_insn, set_insn;
216
 
217
static void output_insn (const struct sparc_opcode *, struct sparc_it *);
218
 
219
/* Table of arguments to -A.
220
   The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
221
   for this use.  That table is for opcodes only.  This table is for opcodes
222
   and file formats.  */
223
 
224
enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
225
                       v8plusa, v9, v9a, v9b, v9_64};
226
 
227
static struct sparc_arch {
228
  char *name;
229
  char *opcode_arch;
230
  enum sparc_arch_types arch_type;
231
  /* Default word size, as specified during configuration.
232
     A value of zero means can't be used to specify default architecture.  */
233
  int default_arch_size;
234
  /* Allowable arg to -A?  */
235
  int user_option_p;
236 163 khays
  int hwcap_allowed;
237 16 khays
} sparc_arch_table[] = {
238 163 khays
  { "v6", "v6", v6, 0, 1, 0 },
239
  { "v7", "v7", v7, 0, 1, 0 },
240
  { "v8", "v8", v8, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
241
  { "v8a", "v8", v8, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
242
  { "sparc", "v9", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS },
243
  { "sparcvis", "v9a", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS },
244
  { "sparcvis2", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2 },
245
  { "sparcfmaf", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF },
246
  { "sparcima", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF|F_IMA },
247
  { "sparcvis3", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF|F_VIS3|F_HPC },
248
  { "sparcvis3r", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF|F_VIS3|F_HPC|F_RANDOM|F_TRANS|F_FJFMAU },
249
  { "sparclet", "sparclet", sparclet, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
250
  { "sparclite", "sparclite", sparclite, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
251
  { "sparc86x", "sparclite", sparc86x, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
252
  { "v8plus", "v9", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS },
253
  { "v8plusa", "v9a", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS },
254
  { "v8plusb", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS|F_VIS2 },
255
  { "v8plusc", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS|F_VIS2|F_ASI_BLK_INIT },
256
  { "v8plusd", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS|F_VIS2|F_ASI_BLK_INIT|F_FMAF|F_VIS3|F_HPC },
257
  { "v8plusv", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS|F_VIS2|F_ASI_BLK_INIT|F_FMAF|F_VIS3|F_HPC|F_RANDOM|F_TRANS|F_FJFMAU|F_IMA|F_ASI_CACHE_SPARING },
258
  { "v9", "v9", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC },
259
  { "v9a", "v9a", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS },
260
  { "v9b", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2 },
261
  { "v9c", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_ASI_BLK_INIT },
262
  { "v9d", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_ASI_BLK_INIT|F_FMAF|F_VIS3|F_HPC },
263
  { "v9v", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_ASI_BLK_INIT|F_FMAF|F_VIS3|F_HPC|F_RANDOM|F_TRANS|F_FJFMAU|F_IMA|F_ASI_CACHE_SPARING },
264 16 khays
  /* This exists to allow configure.in/Makefile.in to pass one
265
     value to specify both the default machine and default word size.  */
266 163 khays
  { "v9-64", "v9", v9, 64, 0, F_MUL32|F_DIV32|F_FSMULD|F_POPC },
267
  { NULL, NULL, v8, 0, 0, 0 }
268 16 khays
};
269
 
270
/* Variant of default_arch */
271
static enum sparc_arch_types default_arch_type;
272
 
273
static struct sparc_arch *
274
lookup_arch (char *name)
275
{
276
  struct sparc_arch *sa;
277
 
278
  for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
279
    if (strcmp (sa->name, name) == 0)
280
      break;
281
  if (sa->name == NULL)
282
    return NULL;
283
  return sa;
284
}
285
 
286
/* Initialize the default opcode arch and word size from the default
287
   architecture name.  */
288
 
289
static void
290
init_default_arch (void)
291
{
292
  struct sparc_arch *sa = lookup_arch (default_arch);
293
 
294
  if (sa == NULL
295
      || sa->default_arch_size == 0)
296
    as_fatal (_("Invalid default architecture, broken assembler."));
297
 
298
  max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
299
  if (max_architecture == SPARC_OPCODE_ARCH_BAD)
300
    as_fatal (_("Bad opcode table, broken assembler."));
301
  default_arch_size = sparc_arch_size = sa->default_arch_size;
302
  default_init_p = 1;
303
  default_arch_type = sa->arch_type;
304
}
305
 
306
/* Called by TARGET_FORMAT.  */
307
 
308
const char *
309
sparc_target_format (void)
310
{
311
  /* We don't get a chance to initialize anything before we're called,
312
     so handle that now.  */
313
  if (! default_init_p)
314
    init_default_arch ();
315
 
316
#ifdef OBJ_AOUT
317
#ifdef TE_NetBSD
318
  return "a.out-sparc-netbsd";
319
#else
320
#ifdef TE_SPARCAOUT
321
  if (target_big_endian)
322
    return "a.out-sunos-big";
323
  else if (default_arch_type == sparc86x && target_little_endian_data)
324
    return "a.out-sunos-big";
325
  else
326
    return "a.out-sparc-little";
327
#else
328
  return "a.out-sunos-big";
329
#endif
330
#endif
331
#endif
332
 
333
#ifdef OBJ_BOUT
334
  return "b.out.big";
335
#endif
336
 
337
#ifdef OBJ_COFF
338
#ifdef TE_LYNX
339
  return "coff-sparc-lynx";
340
#else
341
  return "coff-sparc";
342
#endif
343
#endif
344
 
345
#ifdef TE_VXWORKS
346
  return "elf32-sparc-vxworks";
347
#endif
348
 
349
#ifdef OBJ_ELF
350
  return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
351
#endif
352
 
353
  abort ();
354
}
355
 
356
/* md_parse_option
357
 *      Invocation line includes a switch not recognized by the base assembler.
358
 *      See if it's a processor-specific option.  These are:
359
 *
360
 *      -bump
361
 *              Warn on architecture bumps.  See also -A.
362
 *
363
 *      -Av6, -Av7, -Av8, -Asparclite, -Asparclet
364
 *              Standard 32 bit architectures.
365
 *      -Av9, -Av9a, -Av9b
366
 *              Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
367
 *              This used to only mean 64 bits, but properly specifying it
368
 *              complicated gcc's ASM_SPECs, so now opcode selection is
369
 *              specified orthogonally to word size (except when specifying
370
 *              the default, but that is an internal implementation detail).
371
 *      -Av8plus, -Av8plusa, -Av8plusb
372
 *              Same as -Av9{,a,b}.
373
 *      -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
374
 *              Same as -Av8plus{,a,b} -32, for compatibility with Sun's
375
 *              assembler.
376
 *      -xarch=v9, -xarch=v9a, -xarch=v9b
377
 *              Same as -Av9{,a,b} -64, for compatibility with Sun's
378
 *              assembler.
379
 *
380
 *              Select the architecture and possibly the file format.
381
 *              Instructions or features not supported by the selected
382
 *              architecture cause fatal errors.
383
 *
384
 *              The default is to start at v6, and bump the architecture up
385
 *              whenever an instruction is seen at a higher level.  In 32 bit
386
 *              environments, v9 is not bumped up to, the user must pass
387
 *              -Av8plus{,a,b}.
388
 *
389
 *              If -bump is specified, a warning is printing when bumping to
390
 *              higher levels.
391
 *
392
 *              If an architecture is specified, all instructions must match
393
 *              that architecture.  Any higher level instructions are flagged
394
 *              as errors.  Note that in the 32 bit environment specifying
395
 *              -Av8plus does not automatically create a v8plus object file, a
396
 *              v9 insn must be seen.
397
 *
398
 *              If both an architecture and -bump are specified, the
399
 *              architecture starts at the specified level, but bumps are
400
 *              warnings.  Note that we can't set `current_architecture' to
401
 *              the requested level in this case: in the 32 bit environment,
402
 *              we still must avoid creating v8plus object files unless v9
403
 *              insns are seen.
404
 *
405
 * Note:
406
 *              Bumping between incompatible architectures is always an
407
 *              error.  For example, from sparclite to v9.
408
 */
409
 
410
#ifdef OBJ_ELF
411
const char *md_shortopts = "A:K:VQ:sq";
412
#else
413
#ifdef OBJ_AOUT
414
const char *md_shortopts = "A:k";
415
#else
416
const char *md_shortopts = "A:";
417
#endif
418
#endif
419
struct option md_longopts[] = {
420
#define OPTION_BUMP (OPTION_MD_BASE)
421
  {"bump", no_argument, NULL, OPTION_BUMP},
422
#define OPTION_SPARC (OPTION_MD_BASE + 1)
423
  {"sparc", no_argument, NULL, OPTION_SPARC},
424
#define OPTION_XARCH (OPTION_MD_BASE + 2)
425
  {"xarch", required_argument, NULL, OPTION_XARCH},
426
#ifdef OBJ_ELF
427
#define OPTION_32 (OPTION_MD_BASE + 3)
428
  {"32", no_argument, NULL, OPTION_32},
429
#define OPTION_64 (OPTION_MD_BASE + 4)
430
  {"64", no_argument, NULL, OPTION_64},
431
#define OPTION_TSO (OPTION_MD_BASE + 5)
432
  {"TSO", no_argument, NULL, OPTION_TSO},
433
#define OPTION_PSO (OPTION_MD_BASE + 6)
434
  {"PSO", no_argument, NULL, OPTION_PSO},
435
#define OPTION_RMO (OPTION_MD_BASE + 7)
436
  {"RMO", no_argument, NULL, OPTION_RMO},
437
#endif
438
#ifdef SPARC_BIENDIAN
439
#define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
440
  {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
441
#define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
442
  {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
443
#endif
444
#define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
445
  {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
446
#define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
447
  {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
448
#ifdef OBJ_ELF
449
#define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
450
  {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
451
#define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
452
  {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
453
#endif
454
#define OPTION_RELAX (OPTION_MD_BASE + 14)
455
  {"relax", no_argument, NULL, OPTION_RELAX},
456
#define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
457
  {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
458
  {NULL, no_argument, NULL, 0}
459
};
460
 
461
size_t md_longopts_size = sizeof (md_longopts);
462
 
463
int
464
md_parse_option (int c, char *arg)
465
{
466
  /* We don't get a chance to initialize anything before we're called,
467
     so handle that now.  */
468
  if (! default_init_p)
469
    init_default_arch ();
470
 
471
  switch (c)
472
    {
473
    case OPTION_BUMP:
474
      warn_on_bump = 1;
475
      warn_after_architecture = SPARC_OPCODE_ARCH_V6;
476
      break;
477
 
478
    case OPTION_XARCH:
479
#ifdef OBJ_ELF
480
      if (strncmp (arg, "v9", 2) != 0)
481
        md_parse_option (OPTION_32, NULL);
482
      else
483
        md_parse_option (OPTION_64, NULL);
484
#endif
485
      /* Fall through.  */
486
 
487
    case 'A':
488
      {
489
        struct sparc_arch *sa;
490
        enum sparc_opcode_arch_val opcode_arch;
491
 
492
        sa = lookup_arch (arg);
493
        if (sa == NULL
494
            || ! sa->user_option_p)
495
          {
496
            if (c == OPTION_XARCH)
497
              as_bad (_("invalid architecture -xarch=%s"), arg);
498
            else
499
              as_bad (_("invalid architecture -A%s"), arg);
500
            return 0;
501
          }
502
 
503
        opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
504
        if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
505
          as_fatal (_("Bad opcode table, broken assembler."));
506
 
507 163 khays
        if (!architecture_requested
508
            || opcode_arch > max_architecture)
509
          max_architecture = opcode_arch;
510
        hwcap_allowed |= sa->hwcap_allowed;
511 16 khays
        architecture_requested = 1;
512
      }
513
      break;
514
 
515
    case OPTION_SPARC:
516
      /* Ignore -sparc, used by SunOS make default .s.o rule.  */
517
      break;
518
 
519
    case OPTION_ENFORCE_ALIGNED_DATA:
520
      enforce_aligned_data = 1;
521
      break;
522
 
523
#ifdef SPARC_BIENDIAN
524
    case OPTION_LITTLE_ENDIAN:
525
      target_big_endian = 0;
526
      if (default_arch_type != sparclet)
527
        as_fatal ("This target does not support -EL");
528
      break;
529
    case OPTION_LITTLE_ENDIAN_DATA:
530
      target_little_endian_data = 1;
531
      target_big_endian = 0;
532
      if (default_arch_type != sparc86x
533
          && default_arch_type != v9)
534
        as_fatal ("This target does not support --little-endian-data");
535
      break;
536
    case OPTION_BIG_ENDIAN:
537
      target_big_endian = 1;
538
      break;
539
#endif
540
 
541
#ifdef OBJ_AOUT
542
    case 'k':
543
      sparc_pic_code = 1;
544
      break;
545
#endif
546
 
547
#ifdef OBJ_ELF
548
    case OPTION_32:
549
    case OPTION_64:
550
      {
551
        const char **list, **l;
552
 
553
        sparc_arch_size = c == OPTION_32 ? 32 : 64;
554
        list = bfd_target_list ();
555
        for (l = list; *l != NULL; l++)
556
          {
557
            if (sparc_arch_size == 32)
558
              {
559
                if (CONST_STRNEQ (*l, "elf32-sparc"))
560
                  break;
561
              }
562
            else
563
              {
564
                if (CONST_STRNEQ (*l, "elf64-sparc"))
565
                  break;
566
              }
567
          }
568
        if (*l == NULL)
569
          as_fatal (_("No compiled in support for %d bit object file format"),
570
                    sparc_arch_size);
571
        free (list);
572
 
573
        if (sparc_arch_size == 64
574
            && max_architecture < SPARC_OPCODE_ARCH_V9)
575
          max_architecture = SPARC_OPCODE_ARCH_V9;
576
      }
577
      break;
578
 
579
    case OPTION_TSO:
580
      sparc_memory_model = MM_TSO;
581
      break;
582
 
583
    case OPTION_PSO:
584
      sparc_memory_model = MM_PSO;
585
      break;
586
 
587
    case OPTION_RMO:
588
      sparc_memory_model = MM_RMO;
589
      break;
590
 
591
    case 'V':
592
      print_version_id ();
593
      break;
594
 
595
    case 'Q':
596
      /* Qy - do emit .comment
597
         Qn - do not emit .comment.  */
598
      break;
599
 
600
    case 's':
601
      /* Use .stab instead of .stab.excl.  */
602
      break;
603
 
604
    case 'q':
605
      /* quick -- Native assembler does fewer checks.  */
606
      break;
607
 
608
    case 'K':
609
      if (strcmp (arg, "PIC") != 0)
610
        as_warn (_("Unrecognized option following -K"));
611
      else
612
        sparc_pic_code = 1;
613
      break;
614
 
615
    case OPTION_NO_UNDECLARED_REGS:
616
      no_undeclared_regs = 1;
617
      break;
618
 
619
    case OPTION_UNDECLARED_REGS:
620
      no_undeclared_regs = 0;
621
      break;
622
#endif
623
 
624
    case OPTION_RELAX:
625
      sparc_relax = 1;
626
      break;
627
 
628
    case OPTION_NO_RELAX:
629
      sparc_relax = 0;
630
      break;
631
 
632
    default:
633
      return 0;
634
    }
635
 
636
  return 1;
637
}
638
 
639
void
640
md_show_usage (FILE *stream)
641
{
642
  const struct sparc_arch *arch;
643
  int column;
644
 
645
  /* We don't get a chance to initialize anything before we're called,
646
     so handle that now.  */
647
  if (! default_init_p)
648
    init_default_arch ();
649
 
650
  fprintf (stream, _("SPARC options:\n"));
651
  column = 0;
652
  for (arch = &sparc_arch_table[0]; arch->name; arch++)
653
    {
654
      if (!arch->user_option_p)
655
        continue;
656
      if (arch != &sparc_arch_table[0])
657
        fprintf (stream, " | ");
658
      if (column + strlen (arch->name) > 70)
659
        {
660
          column = 0;
661
          fputc ('\n', stream);
662
        }
663
      column += 5 + 2 + strlen (arch->name);
664
      fprintf (stream, "-A%s", arch->name);
665
    }
666
  for (arch = &sparc_arch_table[0]; arch->name; arch++)
667
    {
668
      if (!arch->user_option_p)
669
        continue;
670
      fprintf (stream, " | ");
671
      if (column + strlen (arch->name) > 65)
672
        {
673
          column = 0;
674
          fputc ('\n', stream);
675
        }
676
      column += 5 + 7 + strlen (arch->name);
677
      fprintf (stream, "-xarch=%s", arch->name);
678
    }
679
  fprintf (stream, _("\n\
680
                        specify variant of SPARC architecture\n\
681
-bump                   warn when assembler switches architectures\n\
682
-sparc                  ignored\n\
683
--enforce-aligned-data  force .long, etc., to be aligned correctly\n\
684
-relax                  relax jumps and branches (default)\n\
685
-no-relax               avoid changing any jumps and branches\n"));
686
#ifdef OBJ_AOUT
687
  fprintf (stream, _("\
688
-k                      generate PIC\n"));
689
#endif
690
#ifdef OBJ_ELF
691
  fprintf (stream, _("\
692
-32                     create 32 bit object file\n\
693
-64                     create 64 bit object file\n"));
694
  fprintf (stream, _("\
695
                        [default is %d]\n"), default_arch_size);
696
  fprintf (stream, _("\
697
-TSO                    use Total Store Ordering\n\
698
-PSO                    use Partial Store Ordering\n\
699
-RMO                    use Relaxed Memory Ordering\n"));
700
  fprintf (stream, _("\
701
                        [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
702
  fprintf (stream, _("\
703
-KPIC                   generate PIC\n\
704
-V                      print assembler version number\n\
705
-undeclared-regs        ignore application global register usage without\n\
706
                        appropriate .register directive (default)\n\
707
-no-undeclared-regs     force error on application global register usage\n\
708
                        without appropriate .register directive\n\
709
-q                      ignored\n\
710
-Qy, -Qn                ignored\n\
711
-s                      ignored\n"));
712
#endif
713
#ifdef SPARC_BIENDIAN
714
  fprintf (stream, _("\
715
-EL                     generate code for a little endian machine\n\
716
-EB                     generate code for a big endian machine\n\
717
--little-endian-data    generate code for a machine having big endian\n\
718
                        instructions and little endian data.\n"));
719
#endif
720
}
721
 
722
/* Native operand size opcode translation.  */
723
struct
724
  {
725
    char *name;
726
    char *name32;
727
    char *name64;
728
  } native_op_table[] =
729
{
730
  {"ldn", "ld", "ldx"},
731
  {"ldna", "lda", "ldxa"},
732
  {"stn", "st", "stx"},
733
  {"stna", "sta", "stxa"},
734
  {"slln", "sll", "sllx"},
735
  {"srln", "srl", "srlx"},
736
  {"sran", "sra", "srax"},
737
  {"casn", "cas", "casx"},
738
  {"casna", "casa", "casxa"},
739
  {"clrn", "clr", "clrx"},
740
  {NULL, NULL, NULL},
741
};
742
 
743
/* sparc64 privileged and hyperprivileged registers.  */
744
 
745
struct priv_reg_entry
746
{
747
  char *name;
748
  int regnum;
749
};
750
 
751
struct priv_reg_entry priv_reg_table[] =
752
{
753
  {"tpc", 0},
754
  {"tnpc", 1},
755
  {"tstate", 2},
756
  {"tt", 3},
757
  {"tick", 4},
758
  {"tba", 5},
759
  {"pstate", 6},
760
  {"tl", 7},
761
  {"pil", 8},
762
  {"cwp", 9},
763
  {"cansave", 10},
764
  {"canrestore", 11},
765
  {"cleanwin", 12},
766
  {"otherwin", 13},
767
  {"wstate", 14},
768
  {"fq", 15},
769
  {"gl", 16},
770
  {"ver", 31},
771
  {"", -1},                     /* End marker.  */
772
};
773
 
774
struct priv_reg_entry hpriv_reg_table[] =
775
{
776
  {"hpstate", 0},
777
  {"htstate", 1},
778
  {"hintp", 3},
779
  {"htba", 5},
780
  {"hver", 6},
781
  {"hstick_cmpr", 31},
782
  {"", -1},                     /* End marker.  */
783
};
784
 
785
/* v9a specific asrs.  This table is ordered by initial
786
   letter, in reverse.  */
787
 
788
struct priv_reg_entry v9a_asr_table[] =
789
{
790
  {"tick_cmpr", 23},
791
  {"sys_tick_cmpr", 25},
792
  {"sys_tick", 24},
793
  {"stick_cmpr", 25},
794
  {"stick", 24},
795
  {"softint_clear", 21},
796
  {"softint_set", 20},
797
  {"softint", 22},
798
  {"set_softint", 20},
799
  {"pic", 17},
800
  {"pcr", 16},
801
  {"gsr", 19},
802
  {"dcr", 18},
803 160 khays
  {"cps", 28},
804 16 khays
  {"clear_softint", 21},
805
  {"", -1},                     /* End marker.  */
806
};
807
 
808
static int
809
cmp_reg_entry (const void *parg, const void *qarg)
810
{
811
  const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
812
  const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
813
 
814
  return strcmp (q->name, p->name);
815
}
816
 
817
/* This function is called once, at assembler startup time.  It should
818
   set up all the tables, etc. that the MD part of the assembler will
819
   need.  */
820
 
821
void
822
md_begin (void)
823
{
824
  register const char *retval = NULL;
825
  int lose = 0;
826
  register unsigned int i = 0;
827
 
828
  /* We don't get a chance to initialize anything before md_parse_option
829
     is called, and it may not be called, so handle default initialization
830
     now if not already done.  */
831
  if (! default_init_p)
832
    init_default_arch ();
833
 
834
  sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
835
  op_hash = hash_new ();
836
 
837
  while (i < (unsigned int) sparc_num_opcodes)
838
    {
839
      const char *name = sparc_opcodes[i].name;
840
      retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]);
841
      if (retval != NULL)
842
        {
843
          as_bad (_("Internal error: can't hash `%s': %s\n"),
844
                  sparc_opcodes[i].name, retval);
845
          lose = 1;
846
        }
847
      do
848
        {
849
          if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
850
            {
851
              as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
852
                      sparc_opcodes[i].name, sparc_opcodes[i].args);
853
              lose = 1;
854
            }
855
          ++i;
856
        }
857
      while (i < (unsigned int) sparc_num_opcodes
858
             && !strcmp (sparc_opcodes[i].name, name));
859
    }
860
 
861
  for (i = 0; native_op_table[i].name; i++)
862
    {
863
      const struct sparc_opcode *insn;
864
      char *name = ((sparc_arch_size == 32)
865
                    ? native_op_table[i].name32
866
                    : native_op_table[i].name64);
867
      insn = (struct sparc_opcode *) hash_find (op_hash, name);
868
      if (insn == NULL)
869
        {
870
          as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
871
                  name, native_op_table[i].name);
872
          lose = 1;
873
        }
874
      else
875
        {
876
          retval = hash_insert (op_hash, native_op_table[i].name,
877
                                (void *) insn);
878
          if (retval != NULL)
879
            {
880
              as_bad (_("Internal error: can't hash `%s': %s\n"),
881
                      sparc_opcodes[i].name, retval);
882
              lose = 1;
883
            }
884
        }
885
    }
886
 
887
  if (lose)
888
    as_fatal (_("Broken assembler.  No assembly attempted."));
889
 
890
  qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
891
         sizeof (priv_reg_table[0]), cmp_reg_entry);
892
 
893
  /* If -bump, record the architecture level at which we start issuing
894
     warnings.  The behaviour is different depending upon whether an
895
     architecture was explicitly specified.  If it wasn't, we issue warnings
896
     for all upwards bumps.  If it was, we don't start issuing warnings until
897
     we need to bump beyond the requested architecture or when we bump between
898
     conflicting architectures.  */
899
 
900
  if (warn_on_bump
901
      && architecture_requested)
902
    {
903
      /* `max_architecture' records the requested architecture.
904
         Issue warnings if we go above it.  */
905
      warn_after_architecture = max_architecture;
906
 
907
      /* Find the highest architecture level that doesn't conflict with
908
         the requested one.  */
909
      for (max_architecture = SPARC_OPCODE_ARCH_MAX;
910
           max_architecture > warn_after_architecture;
911
           --max_architecture)
912
        if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
913
                                       warn_after_architecture))
914
          break;
915
    }
916
}
917
 
918
/* Called after all assembly has been done.  */
919
 
920
void
921
sparc_md_end (void)
922
{
923
  unsigned long mach = bfd_mach_sparc;
924
 
925
  if (sparc_arch_size == 64)
926
    switch (current_architecture)
927
      {
928
      case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
929
      case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
930
      default: mach = bfd_mach_sparc_v9; break;
931
      }
932
  else
933
    switch (current_architecture)
934
      {
935
      case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
936
      case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
937
      case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
938
      case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
939
      /* The sparclite is treated like a normal sparc.  Perhaps it shouldn't
940
         be but for now it is (since that's the way it's always been
941
         treated).  */
942
      default: break;
943
      }
944
  bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
945 163 khays
 
946
#if defined(OBJ_ELF) && !defined(TE_SOLARIS)
947
  if (hwcap_seen)
948
    {
949
      int bits = 0;
950
 
951
      if (hwcap_seen & F_MUL32)
952
        bits |= ELF_SPARC_HWCAP_MUL32;
953
      if (hwcap_seen & F_DIV32)
954
        bits |= ELF_SPARC_HWCAP_DIV32;
955
      if (hwcap_seen & F_FSMULD)
956
        bits |= ELF_SPARC_HWCAP_FSMULD;
957
      if (hwcap_seen & F_V8PLUS)
958
        bits |= ELF_SPARC_HWCAP_V8PLUS;
959
      if (hwcap_seen & F_POPC)
960
        bits |= ELF_SPARC_HWCAP_POPC;
961
      if (hwcap_seen & F_VIS)
962
        bits |= ELF_SPARC_HWCAP_VIS;
963
      if (hwcap_seen & F_VIS2)
964
        bits |= ELF_SPARC_HWCAP_VIS2;
965
      if (hwcap_seen & F_ASI_BLK_INIT)
966
        bits |= ELF_SPARC_HWCAP_ASI_BLK_INIT;
967
      if (hwcap_seen & F_FMAF)
968
        bits |= ELF_SPARC_HWCAP_FMAF;
969
      if (hwcap_seen & F_VIS3)
970
        bits |= ELF_SPARC_HWCAP_VIS3;
971
      if (hwcap_seen & F_HPC)
972
        bits |= ELF_SPARC_HWCAP_HPC;
973
      if (hwcap_seen & F_RANDOM)
974
        bits |= ELF_SPARC_HWCAP_RANDOM;
975
      if (hwcap_seen & F_TRANS)
976
        bits |= ELF_SPARC_HWCAP_TRANS;
977
      if (hwcap_seen & F_FJFMAU)
978
        bits |= ELF_SPARC_HWCAP_FJFMAU;
979
      if (hwcap_seen & F_IMA)
980
        bits |= ELF_SPARC_HWCAP_IMA;
981
      if (hwcap_seen & F_ASI_CACHE_SPARING)
982
        bits |= ELF_SPARC_HWCAP_ASI_CACHE_SPARING;
983
 
984
      bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, bits);
985
    }
986
#endif
987 16 khays
}
988
 
989
/* Return non-zero if VAL is in the range -(MAX+1) to MAX.  */
990
 
991
static inline int
992
in_signed_range (bfd_signed_vma val, bfd_signed_vma max)
993
{
994
  if (max <= 0)
995
    abort ();
996
  /* Sign-extend the value from the architecture word size, so that
997
     0xffffffff is always considered -1 on sparc32.  */
998
  if (sparc_arch_size == 32)
999
    {
1000
      bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
1001
      val = ((val & U0xffffffff) ^ sign) - sign;
1002
    }
1003
  if (val > max)
1004
    return 0;
1005
  if (val < ~max)
1006
    return 0;
1007
  return 1;
1008
}
1009
 
1010
/* Return non-zero if VAL is in the range 0 to MAX.  */
1011
 
1012
static inline int
1013
in_unsigned_range (bfd_vma val, bfd_vma max)
1014
{
1015
  if (val > max)
1016
    return 0;
1017
  return 1;
1018
}
1019
 
1020
/* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
1021
   (e.g. -15 to +31).  */
1022
 
1023
static inline int
1024
in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max)
1025
{
1026
  if (max <= 0)
1027
    abort ();
1028
  if (val > max)
1029
    return 0;
1030
  if (val < ~(max >> 1))
1031
    return 0;
1032
  return 1;
1033
}
1034
 
1035
static int
1036
sparc_ffs (unsigned int mask)
1037
{
1038
  int i;
1039
 
1040
  if (mask == 0)
1041
    return -1;
1042
 
1043
  for (i = 0; (mask & 1) == 0; ++i)
1044
    mask >>= 1;
1045
  return i;
1046
}
1047
 
1048
/* Implement big shift right.  */
1049
static bfd_vma
1050
BSR (bfd_vma val, int amount)
1051
{
1052
  if (sizeof (bfd_vma) <= 4 && amount >= 32)
1053
    as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1054
  return val >> amount;
1055
}
1056
 
1057
/* For communication between sparc_ip and get_expression.  */
1058
static char *expr_end;
1059
 
1060
/* Values for `special_case'.
1061
   Instructions that require wierd handling because they're longer than
1062
   4 bytes.  */
1063
#define SPECIAL_CASE_NONE       0
1064
#define SPECIAL_CASE_SET        1
1065
#define SPECIAL_CASE_SETSW      2
1066
#define SPECIAL_CASE_SETX       3
1067
/* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this.  */
1068
#define SPECIAL_CASE_FDIV       4
1069
 
1070
/* Bit masks of various insns.  */
1071
#define NOP_INSN 0x01000000
1072
#define OR_INSN 0x80100000
1073
#define XOR_INSN 0x80180000
1074
#define FMOVS_INSN 0x81A00020
1075
#define SETHI_INSN 0x01000000
1076
#define SLLX_INSN 0x81281000
1077
#define SRA_INSN 0x81380000
1078
 
1079
/* The last instruction to be assembled.  */
1080
static const struct sparc_opcode *last_insn;
1081
/* The assembled opcode of `last_insn'.  */
1082
static unsigned long last_opcode;
1083
 
1084
/* Handle the set and setuw synthetic instructions.  */
1085
 
1086
static void
1087
synthetize_setuw (const struct sparc_opcode *insn)
1088
{
1089
  int need_hi22_p = 0;
1090
  int rd = (the_insn.opcode & RD (~0)) >> 25;
1091
 
1092
  if (the_insn.exp.X_op == O_constant)
1093
    {
1094
      if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1095
        {
1096
          if (sizeof (offsetT) > 4
1097
              && (the_insn.exp.X_add_number < 0
1098
                  || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1099
            as_warn (_("set: number not in 0..4294967295 range"));
1100
        }
1101
      else
1102
        {
1103
          if (sizeof (offsetT) > 4
1104
              && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1105
                  || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1106
            as_warn (_("set: number not in -2147483648..4294967295 range"));
1107
          the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1108
        }
1109
    }
1110
 
1111
  /* See if operand is absolute and small; skip sethi if so.  */
1112
  if (the_insn.exp.X_op != O_constant
1113
      || the_insn.exp.X_add_number >= (1 << 12)
1114
      || the_insn.exp.X_add_number < -(1 << 12))
1115
    {
1116
      the_insn.opcode = (SETHI_INSN | RD (rd)
1117
                         | ((the_insn.exp.X_add_number >> 10)
1118
                            & (the_insn.exp.X_op == O_constant
1119
                               ? 0x3fffff : 0)));
1120
      the_insn.reloc = (the_insn.exp.X_op != O_constant
1121
                        ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1122
      output_insn (insn, &the_insn);
1123
      need_hi22_p = 1;
1124
    }
1125
 
1126
  /* See if operand has no low-order bits; skip OR if so.  */
1127
  if (the_insn.exp.X_op != O_constant
1128
      || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1129
      || ! need_hi22_p)
1130
    {
1131
      the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1132
                         | RD (rd) | IMMED
1133
                         | (the_insn.exp.X_add_number
1134
                            & (the_insn.exp.X_op != O_constant
1135
                               ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1136
      the_insn.reloc = (the_insn.exp.X_op != O_constant
1137
                        ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1138
      output_insn (insn, &the_insn);
1139
    }
1140
}
1141
 
1142
/* Handle the setsw synthetic instruction.  */
1143
 
1144
static void
1145
synthetize_setsw (const struct sparc_opcode *insn)
1146
{
1147
  int low32, rd, opc;
1148
 
1149
  rd = (the_insn.opcode & RD (~0)) >> 25;
1150
 
1151
  if (the_insn.exp.X_op != O_constant)
1152
    {
1153
      synthetize_setuw (insn);
1154
 
1155
      /* Need to sign extend it.  */
1156
      the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1157
      the_insn.reloc = BFD_RELOC_NONE;
1158
      output_insn (insn, &the_insn);
1159
      return;
1160
    }
1161
 
1162
  if (sizeof (offsetT) > 4
1163
      && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1164
          || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1165
    as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1166
 
1167
  low32 = the_insn.exp.X_add_number;
1168
 
1169
  if (low32 >= 0)
1170
    {
1171
      synthetize_setuw (insn);
1172
      return;
1173
    }
1174
 
1175
  opc = OR_INSN;
1176
 
1177
  the_insn.reloc = BFD_RELOC_NONE;
1178
  /* See if operand is absolute and small; skip sethi if so.  */
1179
  if (low32 < -(1 << 12))
1180
    {
1181
      the_insn.opcode = (SETHI_INSN | RD (rd)
1182
                         | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1183
      output_insn (insn, &the_insn);
1184
      low32 = 0x1c00 | (low32 & 0x3ff);
1185
      opc = RS1 (rd) | XOR_INSN;
1186
    }
1187
 
1188
  the_insn.opcode = (opc | RD (rd) | IMMED
1189
                     | (low32 & 0x1fff));
1190
  output_insn (insn, &the_insn);
1191
}
1192
 
1193
/* Handle the setsw synthetic instruction.  */
1194
 
1195
static void
1196
synthetize_setx (const struct sparc_opcode *insn)
1197
{
1198
  int upper32, lower32;
1199
  int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1200
  int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1201
  int upper_dstreg;
1202
  int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1203
  int need_xor10_p = 0;
1204
 
1205
#define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1206
  lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1207
  upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1208
#undef SIGNEXT32
1209
 
1210
  upper_dstreg = tmpreg;
1211
  /* The tmp reg should not be the dst reg.  */
1212
  if (tmpreg == dstreg)
1213
    as_warn (_("setx: temporary register same as destination register"));
1214
 
1215
  /* ??? Obviously there are other optimizations we can do
1216
     (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1217
     doing some of these.  Later.  If you do change things, try to
1218
     change all of this to be table driven as well.  */
1219
  /* What to output depends on the number if it's constant.
1220
     Compute that first, then output what we've decided upon.  */
1221
  if (the_insn.exp.X_op != O_constant)
1222
    {
1223
      if (sparc_arch_size == 32)
1224
        {
1225
          /* When arch size is 32, we want setx to be equivalent
1226
             to setuw for anything but constants.  */
1227
          the_insn.exp.X_add_number &= 0xffffffff;
1228
          synthetize_setuw (insn);
1229
          return;
1230
        }
1231
      need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1232
      lower32 = 0;
1233
      upper32 = 0;
1234
    }
1235
  else
1236
    {
1237
      /* Reset X_add_number, we've extracted it as upper32/lower32.
1238
         Otherwise fixup_segment will complain about not being able to
1239
         write an 8 byte number in a 4 byte field.  */
1240
      the_insn.exp.X_add_number = 0;
1241
 
1242
      /* Only need hh22 if `or' insn can't handle constant.  */
1243
      if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1244
        need_hh22_p = 1;
1245
 
1246
      /* Does bottom part (after sethi) have bits?  */
1247
      if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1248
          /* No hh22, but does upper32 still have bits we can't set
1249
             from lower32?  */
1250
          || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1251
        need_hm10_p = 1;
1252
 
1253
      /* If the lower half is all zero, we build the upper half directly
1254
         into the dst reg.  */
1255
      if (lower32 != 0
1256
          /* Need lower half if number is zero or 0xffffffff00000000.  */
1257
          || (! need_hh22_p && ! need_hm10_p))
1258
        {
1259
          /* No need for sethi if `or' insn can handle constant.  */
1260
          if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1261
              /* Note that we can't use a negative constant in the `or'
1262
                 insn unless the upper 32 bits are all ones.  */
1263
              || (lower32 < 0 && upper32 != -1)
1264
              || (lower32 >= 0 && upper32 == -1))
1265
            need_hi22_p = 1;
1266
 
1267
          if (need_hi22_p && upper32 == -1)
1268
            need_xor10_p = 1;
1269
 
1270
          /* Does bottom part (after sethi) have bits?  */
1271
          else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1272
                   /* No sethi.  */
1273
                   || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1274
                   /* Need `or' if we didn't set anything else.  */
1275
                   || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1276
            need_lo10_p = 1;
1277
        }
1278
      else
1279
        /* Output directly to dst reg if lower 32 bits are all zero.  */
1280
        upper_dstreg = dstreg;
1281
    }
1282
 
1283
  if (!upper_dstreg && dstreg)
1284
    as_warn (_("setx: illegal temporary register g0"));
1285
 
1286
  if (need_hh22_p)
1287
    {
1288
      the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1289
                         | ((upper32 >> 10) & 0x3fffff));
1290
      the_insn.reloc = (the_insn.exp.X_op != O_constant
1291
                        ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1292
      output_insn (insn, &the_insn);
1293
    }
1294
 
1295
  if (need_hi22_p)
1296
    {
1297
      the_insn.opcode = (SETHI_INSN | RD (dstreg)
1298
                         | (((need_xor10_p ? ~lower32 : lower32)
1299
                             >> 10) & 0x3fffff));
1300
      the_insn.reloc = (the_insn.exp.X_op != O_constant
1301
                        ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1302
      output_insn (insn, &the_insn);
1303
    }
1304
 
1305
  if (need_hm10_p)
1306
    {
1307
      the_insn.opcode = (OR_INSN
1308
                         | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1309
                         | RD (upper_dstreg)
1310
                         | IMMED
1311
                         | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1312
      the_insn.reloc = (the_insn.exp.X_op != O_constant
1313
                        ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1314
      output_insn (insn, &the_insn);
1315
    }
1316
 
1317
  if (need_lo10_p)
1318
    {
1319
      /* FIXME: One nice optimization to do here is to OR the low part
1320
         with the highpart if hi22 isn't needed and the low part is
1321
         positive.  */
1322
      the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1323
                         | RD (dstreg)
1324
                         | IMMED
1325
                         | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1326
      the_insn.reloc = (the_insn.exp.X_op != O_constant
1327
                        ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1328
      output_insn (insn, &the_insn);
1329
    }
1330
 
1331
  /* If we needed to build the upper part, shift it into place.  */
1332
  if (need_hh22_p || need_hm10_p)
1333
    {
1334
      the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1335
                         | IMMED | 32);
1336
      the_insn.reloc = BFD_RELOC_NONE;
1337
      output_insn (insn, &the_insn);
1338
    }
1339
 
1340
  /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r.  */
1341
  if (need_xor10_p)
1342
    {
1343
      the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1344
                         | 0x1c00 | (lower32 & 0x3ff));
1345
      the_insn.reloc = BFD_RELOC_NONE;
1346
      output_insn (insn, &the_insn);
1347
    }
1348
 
1349
  /* If we needed to build both upper and lower parts, OR them together.  */
1350
  else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1351
    {
1352
      the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1353
                         | RD (dstreg));
1354
      the_insn.reloc = BFD_RELOC_NONE;
1355
      output_insn (insn, &the_insn);
1356
    }
1357
}
1358
 
1359
/* Main entry point to assemble one instruction.  */
1360
 
1361
void
1362
md_assemble (char *str)
1363
{
1364
  const struct sparc_opcode *insn;
1365
  int special_case;
1366
 
1367
  know (str);
1368
  special_case = sparc_ip (str, &insn);
1369
  if (insn == NULL)
1370
    return;
1371
 
1372
  /* We warn about attempts to put a floating point branch in a delay slot,
1373
     unless the delay slot has been annulled.  */
1374
  if (last_insn != NULL
1375
      && (insn->flags & F_FBR) != 0
1376
      && (last_insn->flags & F_DELAYED) != 0
1377
      /* ??? This test isn't completely accurate.  We assume anything with
1378
         F_{UNBR,CONDBR,FBR} set is annullable.  */
1379
      && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1380
          || (last_opcode & ANNUL) == 0))
1381
    as_warn (_("FP branch in delay slot"));
1382
 
1383
  /* SPARC before v9 requires a nop instruction between a floating
1384
     point instruction and a floating point branch.  We insert one
1385
     automatically, with a warning.  */
1386
  if (max_architecture < SPARC_OPCODE_ARCH_V9
1387
      && last_insn != NULL
1388
      && (insn->flags & F_FBR) != 0
1389
      && (last_insn->flags & F_FLOAT) != 0)
1390
    {
1391
      struct sparc_it nop_insn;
1392
 
1393
      nop_insn.opcode = NOP_INSN;
1394
      nop_insn.reloc = BFD_RELOC_NONE;
1395
      output_insn (insn, &nop_insn);
1396
      as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1397
    }
1398
 
1399
  switch (special_case)
1400
    {
1401
    case SPECIAL_CASE_NONE:
1402
      /* Normal insn.  */
1403
      output_insn (insn, &the_insn);
1404
      break;
1405
 
1406
    case SPECIAL_CASE_SETSW:
1407
      synthetize_setsw (insn);
1408
      break;
1409
 
1410
    case SPECIAL_CASE_SET:
1411
      synthetize_setuw (insn);
1412
      break;
1413
 
1414
    case SPECIAL_CASE_SETX:
1415
      synthetize_setx (insn);
1416
      break;
1417
 
1418
    case SPECIAL_CASE_FDIV:
1419
      {
1420
        int rd = (the_insn.opcode >> 25) & 0x1f;
1421
 
1422
        output_insn (insn, &the_insn);
1423
 
1424
        /* According to information leaked from Sun, the "fdiv" instructions
1425
           on early SPARC machines would produce incorrect results sometimes.
1426
           The workaround is to add an fmovs of the destination register to
1427
           itself just after the instruction.  This was true on machines
1428
           with Weitek 1165 float chips, such as the Sun-4/260 and /280.  */
1429
        gas_assert (the_insn.reloc == BFD_RELOC_NONE);
1430
        the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1431
        output_insn (insn, &the_insn);
1432
        return;
1433
      }
1434
 
1435
    default:
1436
      as_fatal (_("failed special case insn sanity check"));
1437
    }
1438
}
1439
 
1440 163 khays
static const char *
1441
get_hwcap_name (int mask)
1442
{
1443
  if (mask & F_MUL32)
1444
    return "mul32";
1445
  if (mask & F_DIV32)
1446
    return "div32";
1447
  if (mask & F_FSMULD)
1448
    return "fsmuld";
1449
  if (mask & F_V8PLUS)
1450
    return "v8plus";
1451
  if (mask & F_POPC)
1452
    return "popc";
1453
  if (mask & F_VIS)
1454
    return "vis";
1455
  if (mask & F_VIS2)
1456
    return "vis2";
1457
  if (mask & F_ASI_BLK_INIT)
1458
    return "ASIBlkInit";
1459
  if (mask & F_FMAF)
1460
    return "fmaf";
1461
  if (mask & F_VIS3)
1462
    return "vis3";
1463
  if (mask & F_HPC)
1464
    return "hpc";
1465
  if (mask & F_RANDOM)
1466
    return "random";
1467
  if (mask & F_TRANS)
1468
    return "trans";
1469
  if (mask & F_FJFMAU)
1470
    return "fjfmau";
1471
  if (mask & F_IMA)
1472
    return "ima";
1473
  if (mask & F_ASI_CACHE_SPARING)
1474
    return "cspare";
1475
  return "UNKNOWN";
1476
}
1477
 
1478 16 khays
/* Subroutine of md_assemble to do the actual parsing.  */
1479
 
1480
static int
1481
sparc_ip (char *str, const struct sparc_opcode **pinsn)
1482
{
1483
  char *error_message = "";
1484
  char *s;
1485
  const char *args;
1486
  char c;
1487
  const struct sparc_opcode *insn;
1488
  char *argsStart;
1489
  unsigned long opcode;
1490
  unsigned int mask = 0;
1491
  int match = 0;
1492
  int comma = 0;
1493
  int v9_arg_p;
1494
  int special_case = SPECIAL_CASE_NONE;
1495
 
1496
  s = str;
1497
  if (ISLOWER (*s))
1498
    {
1499
      do
1500
        ++s;
1501
      while (ISLOWER (*s) || ISDIGIT (*s));
1502
    }
1503
 
1504
  switch (*s)
1505
    {
1506
    case '\0':
1507
      break;
1508
 
1509
    case ',':
1510
      comma = 1;
1511
      /* Fall through.  */
1512
 
1513
    case ' ':
1514
      *s++ = '\0';
1515
      break;
1516
 
1517
    default:
1518
      as_bad (_("Unknown opcode: `%s'"), str);
1519
      *pinsn = NULL;
1520
      return special_case;
1521
    }
1522
  insn = (struct sparc_opcode *) hash_find (op_hash, str);
1523
  *pinsn = insn;
1524
  if (insn == NULL)
1525
    {
1526
      as_bad (_("Unknown opcode: `%s'"), str);
1527
      return special_case;
1528
    }
1529
  if (comma)
1530
    {
1531
      *--s = ',';
1532
    }
1533
 
1534
  argsStart = s;
1535
  for (;;)
1536
    {
1537
      opcode = insn->match;
1538
      memset (&the_insn, '\0', sizeof (the_insn));
1539
      the_insn.reloc = BFD_RELOC_NONE;
1540
      v9_arg_p = 0;
1541
 
1542
      /* Build the opcode, checking as we go to make sure that the
1543
         operands match.  */
1544
      for (args = insn->args;; ++args)
1545
        {
1546
          switch (*args)
1547
            {
1548
            case 'K':
1549
              {
1550
                int kmask = 0;
1551
 
1552
                /* Parse a series of masks.  */
1553
                if (*s == '#')
1554
                  {
1555
                    while (*s == '#')
1556
                      {
1557
                        int jmask;
1558
 
1559
                        if (! parse_keyword_arg (sparc_encode_membar, &s,
1560
                                                 &jmask))
1561
                          {
1562
                            error_message = _(": invalid membar mask name");
1563
                            goto error;
1564
                          }
1565
                        kmask |= jmask;
1566
                        while (*s == ' ')
1567
                          ++s;
1568
                        if (*s == '|' || *s == '+')
1569
                          ++s;
1570
                        while (*s == ' ')
1571
                          ++s;
1572
                      }
1573
                  }
1574
                else
1575
                  {
1576
                    if (! parse_const_expr_arg (&s, &kmask))
1577
                      {
1578
                        error_message = _(": invalid membar mask expression");
1579
                        goto error;
1580
                      }
1581
                    if (kmask < 0 || kmask > 127)
1582
                      {
1583
                        error_message = _(": invalid membar mask number");
1584
                        goto error;
1585
                      }
1586
                  }
1587
 
1588
                opcode |= MEMBAR (kmask);
1589
                continue;
1590
              }
1591
 
1592
            case '3':
1593
              {
1594
                int smask = 0;
1595
 
1596
                if (! parse_const_expr_arg (&s, &smask))
1597
                  {
1598
                    error_message = _(": invalid siam mode expression");
1599
                    goto error;
1600
                  }
1601
                if (smask < 0 || smask > 7)
1602
                  {
1603
                    error_message = _(": invalid siam mode number");
1604
                    goto error;
1605
                  }
1606
                opcode |= smask;
1607
                continue;
1608
              }
1609
 
1610
            case '*':
1611
              {
1612
                int fcn = 0;
1613
 
1614
                /* Parse a prefetch function.  */
1615
                if (*s == '#')
1616
                  {
1617
                    if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1618
                      {
1619
                        error_message = _(": invalid prefetch function name");
1620
                        goto error;
1621
                      }
1622
                  }
1623
                else
1624
                  {
1625
                    if (! parse_const_expr_arg (&s, &fcn))
1626
                      {
1627
                        error_message = _(": invalid prefetch function expression");
1628
                        goto error;
1629
                      }
1630
                    if (fcn < 0 || fcn > 31)
1631
                      {
1632
                        error_message = _(": invalid prefetch function number");
1633
                        goto error;
1634
                      }
1635
                  }
1636
                opcode |= RD (fcn);
1637
                continue;
1638
              }
1639
 
1640
            case '!':
1641
            case '?':
1642
              /* Parse a sparc64 privileged register.  */
1643
              if (*s == '%')
1644
                {
1645
                  struct priv_reg_entry *p = priv_reg_table;
1646
                  unsigned int len = 9999999; /* Init to make gcc happy.  */
1647
 
1648
                  s += 1;
1649
                  while (p->name[0] > s[0])
1650
                    p++;
1651
                  while (p->name[0] == s[0])
1652
                    {
1653
                      len = strlen (p->name);
1654
                      if (strncmp (p->name, s, len) == 0)
1655
                        break;
1656
                      p++;
1657
                    }
1658
                  if (p->name[0] != s[0])
1659
                    {
1660
                      error_message = _(": unrecognizable privileged register");
1661
                      goto error;
1662
                    }
1663
                  if (*args == '?')
1664
                    opcode |= (p->regnum << 14);
1665
                  else
1666
                    opcode |= (p->regnum << 25);
1667
                  s += len;
1668
                  continue;
1669
                }
1670
              else
1671
                {
1672
                  error_message = _(": unrecognizable privileged register");
1673
                  goto error;
1674
                }
1675
 
1676
            case '$':
1677
            case '%':
1678
              /* Parse a sparc64 hyperprivileged register.  */
1679
              if (*s == '%')
1680
                {
1681
                  struct priv_reg_entry *p = hpriv_reg_table;
1682
                  unsigned int len = 9999999; /* Init to make gcc happy.  */
1683
 
1684
                  s += 1;
1685
                  while (p->name[0] > s[0])
1686
                    p++;
1687
                  while (p->name[0] == s[0])
1688
                    {
1689
                      len = strlen (p->name);
1690
                      if (strncmp (p->name, s, len) == 0)
1691
                        break;
1692
                      p++;
1693
                    }
1694
                  if (p->name[0] != s[0])
1695
                    {
1696
                      error_message = _(": unrecognizable hyperprivileged register");
1697
                      goto error;
1698
                    }
1699
                  if (*args == '$')
1700
                    opcode |= (p->regnum << 14);
1701
                  else
1702
                    opcode |= (p->regnum << 25);
1703
                  s += len;
1704
                  continue;
1705
                }
1706
              else
1707
                {
1708
                  error_message = _(": unrecognizable hyperprivileged register");
1709
                  goto error;
1710
                }
1711
 
1712
            case '_':
1713
            case '/':
1714
              /* Parse a v9a/v9b ancillary state register.  */
1715
              if (*s == '%')
1716
                {
1717
                  struct priv_reg_entry *p = v9a_asr_table;
1718
                  unsigned int len = 9999999; /* Init to make gcc happy.  */
1719
 
1720
                  s += 1;
1721
                  while (p->name[0] > s[0])
1722
                    p++;
1723
                  while (p->name[0] == s[0])
1724
                    {
1725
                      len = strlen (p->name);
1726
                      if (strncmp (p->name, s, len) == 0)
1727
                        break;
1728
                      p++;
1729
                    }
1730
                  if (p->name[0] != s[0])
1731
                    {
1732
                      error_message = _(": unrecognizable v9a or v9b ancillary state register");
1733
                      goto error;
1734
                    }
1735
                  if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1736
                    {
1737
                      error_message = _(": rd on write only ancillary state register");
1738
                      goto error;
1739
                    }
1740
                  if (p->regnum >= 24
1741
                      && (insn->architecture
1742
                          & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1743
                    {
1744
                      /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1745
                      error_message = _(": unrecognizable v9a ancillary state register");
1746
                      goto error;
1747
                    }
1748
                  if (*args == '/')
1749
                    opcode |= (p->regnum << 14);
1750
                  else
1751
                    opcode |= (p->regnum << 25);
1752
                  s += len;
1753
                  continue;
1754
                }
1755
              else
1756
                {
1757
                  error_message = _(": unrecognizable v9a or v9b ancillary state register");
1758
                  goto error;
1759
                }
1760
 
1761
            case 'M':
1762
            case 'm':
1763
              if (strncmp (s, "%asr", 4) == 0)
1764
                {
1765
                  s += 4;
1766
 
1767
                  if (ISDIGIT (*s))
1768
                    {
1769
                      long num = 0;
1770
 
1771
                      while (ISDIGIT (*s))
1772
                        {
1773
                          num = num * 10 + *s - '0';
1774
                          ++s;
1775
                        }
1776
 
1777
                      if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1778
                        {
1779
                          if (num < 16 || 31 < num)
1780
                            {
1781
                              error_message = _(": asr number must be between 16 and 31");
1782
                              goto error;
1783
                            }
1784
                        }
1785
                      else
1786
                        {
1787
                          if (num < 0 || 31 < num)
1788
                            {
1789
                              error_message = _(": asr number must be between 0 and 31");
1790
                              goto error;
1791
                            }
1792
                        }
1793
 
1794
                      opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1795
                      continue;
1796
                    }
1797
                  else
1798
                    {
1799
                      error_message = _(": expecting %asrN");
1800
                      goto error;
1801
                    }
1802
                } /* if %asr  */
1803
              break;
1804
 
1805
            case 'I':
1806
              the_insn.reloc = BFD_RELOC_SPARC_11;
1807
              goto immediate;
1808
 
1809
            case 'j':
1810
              the_insn.reloc = BFD_RELOC_SPARC_10;
1811
              goto immediate;
1812
 
1813
            case 'X':
1814
              /* V8 systems don't understand BFD_RELOC_SPARC_5.  */
1815
              if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1816
                the_insn.reloc = BFD_RELOC_SPARC_5;
1817
              else
1818
                the_insn.reloc = BFD_RELOC_SPARC13;
1819
              /* These fields are unsigned, but for upward compatibility,
1820
                 allow negative values as well.  */
1821
              goto immediate;
1822
 
1823
            case 'Y':
1824
              /* V8 systems don't understand BFD_RELOC_SPARC_6.  */
1825
              if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1826
                the_insn.reloc = BFD_RELOC_SPARC_6;
1827
              else
1828
                the_insn.reloc = BFD_RELOC_SPARC13;
1829
              /* These fields are unsigned, but for upward compatibility,
1830
                 allow negative values as well.  */
1831
              goto immediate;
1832
 
1833
            case 'k':
1834
              the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1835
              the_insn.pcrel = 1;
1836
              goto immediate;
1837
 
1838
            case 'G':
1839
              the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1840
              the_insn.pcrel = 1;
1841
              goto immediate;
1842
 
1843
            case 'N':
1844
              if (*s == 'p' && s[1] == 'n')
1845
                {
1846
                  s += 2;
1847
                  continue;
1848
                }
1849
              break;
1850
 
1851
            case 'T':
1852
              if (*s == 'p' && s[1] == 't')
1853
                {
1854
                  s += 2;
1855
                  continue;
1856
                }
1857
              break;
1858
 
1859
            case 'z':
1860
              if (*s == ' ')
1861
                {
1862
                  ++s;
1863
                }
1864
              if (strncmp (s, "%icc", 4) == 0)
1865
                {
1866
                  s += 4;
1867
                  continue;
1868
                }
1869
              break;
1870
 
1871
            case 'Z':
1872
              if (*s == ' ')
1873
                {
1874
                  ++s;
1875
                }
1876
              if (strncmp (s, "%xcc", 4) == 0)
1877
                {
1878
                  s += 4;
1879
                  continue;
1880
                }
1881
              break;
1882
 
1883
            case '6':
1884
              if (*s == ' ')
1885
                {
1886
                  ++s;
1887
                }
1888
              if (strncmp (s, "%fcc0", 5) == 0)
1889
                {
1890
                  s += 5;
1891
                  continue;
1892
                }
1893
              break;
1894
 
1895
            case '7':
1896
              if (*s == ' ')
1897
                {
1898
                  ++s;
1899
                }
1900
              if (strncmp (s, "%fcc1", 5) == 0)
1901
                {
1902
                  s += 5;
1903
                  continue;
1904
                }
1905
              break;
1906
 
1907
            case '8':
1908
              if (*s == ' ')
1909
                {
1910
                  ++s;
1911
                }
1912
              if (strncmp (s, "%fcc2", 5) == 0)
1913
                {
1914
                  s += 5;
1915
                  continue;
1916
                }
1917
              break;
1918
 
1919
            case '9':
1920
              if (*s == ' ')
1921
                {
1922
                  ++s;
1923
                }
1924
              if (strncmp (s, "%fcc3", 5) == 0)
1925
                {
1926
                  s += 5;
1927
                  continue;
1928
                }
1929
              break;
1930
 
1931
            case 'P':
1932
              if (strncmp (s, "%pc", 3) == 0)
1933
                {
1934
                  s += 3;
1935
                  continue;
1936
                }
1937
              break;
1938
 
1939
            case 'W':
1940
              if (strncmp (s, "%tick", 5) == 0)
1941
                {
1942
                  s += 5;
1943
                  continue;
1944
                }
1945
              break;
1946
 
1947
            case '\0':          /* End of args.  */
1948
              if (s[0] == ',' && s[1] == '%')
1949
                {
1950
                  static const struct ops
1951
                  {
1952
                    /* The name as it appears in assembler.  */
1953
                    char *name;
1954
                    /* strlen (name), precomputed for speed */
1955
                    int len;
1956
                    /* The reloc this pseudo-op translates to.  */
1957
                    int reloc;
1958
                    /* 1 if tls call.  */
1959
                    int tls_call;
1960
                  }
1961
                  ops[] =
1962
                  {
1963
                    { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
1964
                    { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
1965
                    { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
1966
                    { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
1967
                    { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
1968
                    { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
1969
                    { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
1970
                    { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 },
1971
                    { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 },
1972
                    { NULL, 0, 0, 0 }
1973
                  };
1974
                  const struct ops *o;
1975
                  char *s1;
1976
                  int npar = 0;
1977
 
1978
                  for (o = ops; o->name; o++)
1979
                    if (strncmp (s + 2, o->name, o->len) == 0)
1980
                      break;
1981
                  if (o->name == NULL)
1982
                    break;
1983
 
1984
                  if (s[o->len + 2] != '(')
1985
                    {
1986
                      as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1987
                      return special_case;
1988
                    }
1989
 
1990
                  if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE)
1991
                    {
1992
                      as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
1993
                              o->name);
1994
                      return special_case;
1995
                    }
1996
 
1997
                  if (o->tls_call
1998
                      && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
1999
                          || the_insn.exp.X_add_number != 0
2000
                          || the_insn.exp.X_add_symbol
2001
                             != symbol_find_or_make ("__tls_get_addr")))
2002
                    {
2003
                      as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2004
                              o->name);
2005
                      return special_case;
2006
                    }
2007
 
2008
                  the_insn.reloc = o->reloc;
2009
                  memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2010
                  s += o->len + 3;
2011
 
2012
                  for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2013
                    if (*s1 == '(')
2014
                      npar++;
2015
                    else if (*s1 == ')')
2016
                      {
2017
                        if (!npar)
2018
                          break;
2019
                        npar--;
2020
                      }
2021
 
2022
                  if (*s1 != ')')
2023
                    {
2024
                      as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2025
                      return special_case;
2026
                    }
2027
 
2028
                  *s1 = '\0';
2029
                  (void) get_expression (s);
2030
                  *s1 = ')';
2031
                  s = s1 + 1;
2032
                }
2033
              if (*s == '\0')
2034
                match = 1;
2035
              break;
2036
 
2037
            case '+':
2038
              if (*s == '+')
2039
                {
2040
                  ++s;
2041
                  continue;
2042
                }
2043
              if (*s == '-')
2044
                {
2045
                  continue;
2046
                }
2047
              break;
2048
 
2049
            case '[':           /* These must match exactly.  */
2050
            case ']':
2051
            case ',':
2052
            case ' ':
2053
              if (*s++ == *args)
2054
                continue;
2055
              break;
2056
 
2057
            case '#':           /* Must be at least one digit.  */
2058
              if (ISDIGIT (*s++))
2059
                {
2060
                  while (ISDIGIT (*s))
2061
                    {
2062
                      ++s;
2063
                    }
2064
                  continue;
2065
                }
2066
              break;
2067
 
2068
            case 'C':           /* Coprocessor state register.  */
2069
              if (strncmp (s, "%csr", 4) == 0)
2070
                {
2071
                  s += 4;
2072
                  continue;
2073
                }
2074
              break;
2075
 
2076
            case 'b':           /* Next operand is a coprocessor register.  */
2077
            case 'c':
2078
            case 'D':
2079
              if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
2080
                {
2081
                  mask = *s++;
2082
                  if (ISDIGIT (*s))
2083
                    {
2084
                      mask = 10 * (mask - '0') + (*s++ - '0');
2085
                      if (mask >= 32)
2086
                        {
2087
                          break;
2088
                        }
2089
                    }
2090
                  else
2091
                    {
2092
                      mask -= '0';
2093
                    }
2094
                  switch (*args)
2095
                    {
2096
 
2097
                    case 'b':
2098
                      opcode |= mask << 14;
2099
                      continue;
2100
 
2101
                    case 'c':
2102
                      opcode |= mask;
2103
                      continue;
2104
 
2105
                    case 'D':
2106
                      opcode |= mask << 25;
2107
                      continue;
2108
                    }
2109
                }
2110
              break;
2111
 
2112
            case 'r':           /* next operand must be a register */
2113
            case 'O':
2114
            case '1':
2115
            case '2':
2116
            case 'd':
2117
              if (*s++ == '%')
2118
                {
2119
                  switch (c = *s++)
2120
                    {
2121
 
2122
                    case 'f':   /* frame pointer */
2123
                      if (*s++ == 'p')
2124
                        {
2125
                          mask = 0x1e;
2126
                          break;
2127
                        }
2128
                      goto error;
2129
 
2130
                    case 'g':   /* global register */
2131
                      c = *s++;
2132
                      if (isoctal (c))
2133
                        {
2134
                          mask = c - '0';
2135
                          break;
2136
                        }
2137
                      goto error;
2138
 
2139
                    case 'i':   /* in register */
2140
                      c = *s++;
2141
                      if (isoctal (c))
2142
                        {
2143
                          mask = c - '0' + 24;
2144
                          break;
2145
                        }
2146
                      goto error;
2147
 
2148
                    case 'l':   /* local register */
2149
                      c = *s++;
2150
                      if (isoctal (c))
2151
                        {
2152
                          mask = (c - '0' + 16);
2153
                          break;
2154
                        }
2155
                      goto error;
2156
 
2157
                    case 'o':   /* out register */
2158
                      c = *s++;
2159
                      if (isoctal (c))
2160
                        {
2161
                          mask = (c - '0' + 8);
2162
                          break;
2163
                        }
2164
                      goto error;
2165
 
2166
                    case 's':   /* stack pointer */
2167
                      if (*s++ == 'p')
2168
                        {
2169
                          mask = 0xe;
2170
                          break;
2171
                        }
2172
                      goto error;
2173
 
2174
                    case 'r':   /* any register */
2175
                      if (!ISDIGIT ((c = *s++)))
2176
                        {
2177
                          goto error;
2178
                        }
2179
                      /* FALLTHROUGH */
2180
                    case '0':
2181
                    case '1':
2182
                    case '2':
2183
                    case '3':
2184
                    case '4':
2185
                    case '5':
2186
                    case '6':
2187
                    case '7':
2188
                    case '8':
2189
                    case '9':
2190
                      if (ISDIGIT (*s))
2191
                        {
2192
                          if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2193
                            {
2194
                              goto error;
2195
                            }
2196
                        }
2197
                      else
2198
                        {
2199
                          c -= '0';
2200
                        }
2201
                      mask = c;
2202
                      break;
2203
 
2204
                    default:
2205
                      goto error;
2206
                    }
2207
 
2208
                  if ((mask & ~1) == 2 && sparc_arch_size == 64
2209
                      && no_undeclared_regs && ! globals[mask])
2210
                    as_bad (_("detected global register use not covered by .register pseudo-op"));
2211
 
2212
                  /* Got the register, now figure out where
2213
                     it goes in the opcode.  */
2214
                  switch (*args)
2215
                    {
2216
                    case '1':
2217
                      opcode |= mask << 14;
2218
                      continue;
2219
 
2220
                    case '2':
2221
                      opcode |= mask;
2222
                      continue;
2223
 
2224
                    case 'd':
2225
                      opcode |= mask << 25;
2226
                      continue;
2227
 
2228
                    case 'r':
2229
                      opcode |= (mask << 25) | (mask << 14);
2230
                      continue;
2231
 
2232
                    case 'O':
2233
                      opcode |= (mask << 25) | (mask << 0);
2234
                      continue;
2235
                    }
2236
                }
2237
              break;
2238
 
2239
            case 'e':           /* next operand is a floating point register */
2240
            case 'v':
2241
            case 'V':
2242
 
2243
            case 'f':
2244
            case 'B':
2245
            case 'R':
2246
 
2247 160 khays
            case '4':
2248
            case '5':
2249
 
2250 16 khays
            case 'g':
2251
            case 'H':
2252
            case 'J':
2253
              {
2254
                char format;
2255
 
2256
                if (*s++ == '%'
2257
                    && ((format = *s) == 'f')
2258
                    && ISDIGIT (*++s))
2259
                  {
2260
                    for (mask = 0; ISDIGIT (*s); ++s)
2261
                      {
2262
                        mask = 10 * mask + (*s - '0');
2263
                      }         /* read the number */
2264
 
2265
                    if ((*args == 'v'
2266
                         || *args == 'B'
2267 160 khays
                         || *args == '5'
2268 16 khays
                         || *args == 'H')
2269
                        && (mask & 1))
2270
                      {
2271
                        break;
2272
                      }         /* register must be even numbered */
2273
 
2274
                    if ((*args == 'V'
2275
                         || *args == 'R'
2276
                         || *args == 'J')
2277
                        && (mask & 3))
2278
                      {
2279
                        break;
2280
                      }         /* register must be multiple of 4 */
2281
 
2282
                    if (mask >= 64)
2283
                      {
2284
                        if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2285
                          error_message = _(": There are only 64 f registers; [0-63]");
2286
                        else
2287
                          error_message = _(": There are only 32 f registers; [0-31]");
2288
                        goto error;
2289
                      } /* on error */
2290
                    else if (mask >= 32)
2291
                      {
2292
                        if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2293
                          {
2294
                            if (*args == 'e' || *args == 'f' || *args == 'g')
2295
                              {
2296
                                error_message
2297
                                  = _(": There are only 32 single precision f registers; [0-31]");
2298
                                goto error;
2299
                              }
2300
                            v9_arg_p = 1;
2301
                            mask -= 31; /* wrap high bit */
2302
                          }
2303
                        else
2304
                          {
2305
                            error_message = _(": There are only 32 f registers; [0-31]");
2306
                            goto error;
2307
                          }
2308
                      }
2309
                  }
2310
                else
2311
                  {
2312
                    break;
2313
                  }     /* if not an 'f' register.  */
2314
 
2315
                switch (*args)
2316
                  {
2317
                  case 'v':
2318
                  case 'V':
2319
                  case 'e':
2320
                    opcode |= RS1 (mask);
2321
                    continue;
2322
 
2323
                  case 'f':
2324
                  case 'B':
2325
                  case 'R':
2326
                    opcode |= RS2 (mask);
2327
                    continue;
2328
 
2329 160 khays
                  case '4':
2330
                  case '5':
2331
                    opcode |= RS3 (mask);
2332
                    continue;
2333
 
2334 16 khays
                  case 'g':
2335
                  case 'H':
2336
                  case 'J':
2337
                    opcode |= RD (mask);
2338
                    continue;
2339
                  }             /* Pack it in.  */
2340
 
2341
                know (0);
2342
                break;
2343
              }                 /* float arg  */
2344
 
2345
            case 'F':
2346
              if (strncmp (s, "%fsr", 4) == 0)
2347
                {
2348
                  s += 4;
2349
                  continue;
2350
                }
2351
              break;
2352
 
2353 160 khays
            case '(':
2354
              if (strncmp (s, "%efsr", 5) == 0)
2355
                {
2356
                  s += 5;
2357
                  continue;
2358
                }
2359
              break;
2360
 
2361 16 khays
            case '0':           /* 64 bit immediate (set, setsw, setx insn)  */
2362
              the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere  */
2363
              goto immediate;
2364
 
2365
            case 'l':           /* 22 bit PC relative immediate  */
2366
              the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2367
              the_insn.pcrel = 1;
2368
              goto immediate;
2369
 
2370
            case 'L':           /* 30 bit immediate  */
2371
              the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2372
              the_insn.pcrel = 1;
2373
              goto immediate;
2374
 
2375
            case 'h':
2376
            case 'n':           /* 22 bit immediate  */
2377
              the_insn.reloc = BFD_RELOC_SPARC22;
2378
              goto immediate;
2379
 
2380
            case 'i':           /* 13 bit immediate  */
2381
              the_insn.reloc = BFD_RELOC_SPARC13;
2382
 
2383
              /* fallthrough */
2384
 
2385
            immediate:
2386
              if (*s == ' ')
2387
                s++;
2388
 
2389
              {
2390
                char *s1;
2391
                char *op_arg = NULL;
2392
                static expressionS op_exp;
2393
                bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2394
 
2395
                /* Check for %hi, etc.  */
2396
                if (*s == '%')
2397
                  {
2398
                    static const struct ops {
2399
                      /* The name as it appears in assembler.  */
2400
                      char *name;
2401
                      /* strlen (name), precomputed for speed */
2402
                      int len;
2403
                      /* The reloc this pseudo-op translates to.  */
2404
                      int reloc;
2405
                      /* Non-zero if for v9 only.  */
2406
                      int v9_p;
2407
                      /* Non-zero if can be used in pc-relative contexts.  */
2408
                      int pcrel_p;/*FIXME:wip*/
2409
                    } ops[] = {
2410
                      /* hix/lox must appear before hi/lo so %hix won't be
2411
                         mistaken for %hi.  */
2412
                      { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2413
                      { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2414
                      { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2415
                      { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2416
                      { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 },
2417
                      { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 },
2418
                      { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2419
                      { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2420
                      { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2421
                      { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2422
                      { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2423
                      { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2424
                      { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2425
                      { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2426
                      { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2427
                      { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2428
                      { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2429
                      { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2430
                      { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2431
 
2432
                      { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2433
 
2434
                      { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2435
                      { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2436
                      { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2437
                      { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
2438
                      { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22,
2439
                        0, 0 },
2440
                      { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10,
2441
                        0, 0 },
2442
                      { NULL, 0, 0, 0, 0 }
2443
                    };
2444
                    const struct ops *o;
2445
 
2446
                    for (o = ops; o->name; o++)
2447
                      if (strncmp (s + 1, o->name, o->len) == 0)
2448
                        break;
2449
                    if (o->name == NULL)
2450
                      break;
2451
 
2452
                    if (s[o->len + 1] != '(')
2453
                      {
2454
                        as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2455
                        return special_case;
2456
                      }
2457
 
2458
                    op_arg = o->name;
2459
                    the_insn.reloc = o->reloc;
2460
                    s += o->len + 2;
2461
                    v9_arg_p = o->v9_p;
2462
                  }
2463
 
2464
                /* Note that if the get_expression() fails, we will still
2465
                   have created U entries in the symbol table for the
2466
                   'symbols' in the input string.  Try not to create U
2467
                   symbols for registers, etc.  */
2468
 
2469
                /* This stuff checks to see if the expression ends in
2470
                   +%reg.  If it does, it removes the register from
2471
                   the expression, and re-sets 's' to point to the
2472
                   right place.  */
2473
 
2474
                if (op_arg)
2475
                  {
2476
                    int npar = 0;
2477
 
2478
                    for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2479
                      if (*s1 == '(')
2480
                        npar++;
2481
                      else if (*s1 == ')')
2482
                        {
2483
                          if (!npar)
2484
                            break;
2485
                          npar--;
2486
                        }
2487
 
2488
                    if (*s1 != ')')
2489
                      {
2490
                        as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2491
                        return special_case;
2492
                      }
2493
 
2494
                    *s1 = '\0';
2495
                    (void) get_expression (s);
2496
                    *s1 = ')';
2497
                    s = s1 + 1;
2498
                    if (*s == ',' || *s == ']' || !*s)
2499
                      continue;
2500
                    if (*s != '+' && *s != '-')
2501
                      {
2502
                        as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2503
                        return special_case;
2504
                      }
2505
                    *s1 = '0';
2506
                    s = s1;
2507
                    op_exp = the_insn.exp;
2508
                    memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2509
                  }
2510
 
2511
                for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2512
                  ;
2513
 
2514
                if (s1 != s && ISDIGIT (s1[-1]))
2515
                  {
2516
                    if (s1[-2] == '%' && s1[-3] == '+')
2517
                      s1 -= 3;
2518 163 khays
                    else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2519 16 khays
                      s1 -= 4;
2520 163 khays
                    else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+')
2521
                      s1 -= 5;
2522 16 khays
                    else
2523
                      s1 = NULL;
2524
                    if (s1)
2525
                      {
2526
                        *s1 = '\0';
2527
                        if (op_arg && s1 == s + 1)
2528
                          the_insn.exp.X_op = O_absent;
2529
                        else
2530
                          (void) get_expression (s);
2531
                        *s1 = '+';
2532
                        if (op_arg)
2533
                          *s = ')';
2534
                        s = s1;
2535
                      }
2536
                  }
2537
                else
2538
                  s1 = NULL;
2539
 
2540
                if (!s1)
2541
                  {
2542
                    (void) get_expression (s);
2543
                    if (op_arg)
2544
                      *s = ')';
2545
                    s = expr_end;
2546
                  }
2547
 
2548
                if (op_arg)
2549
                  {
2550
                    the_insn.exp2 = the_insn.exp;
2551
                    the_insn.exp = op_exp;
2552
                    if (the_insn.exp2.X_op == O_absent)
2553
                      the_insn.exp2.X_op = O_illegal;
2554
                    else if (the_insn.exp.X_op == O_absent)
2555
                      {
2556
                        the_insn.exp = the_insn.exp2;
2557
                        the_insn.exp2.X_op = O_illegal;
2558
                      }
2559
                    else if (the_insn.exp.X_op == O_constant)
2560
                      {
2561
                        valueT val = the_insn.exp.X_add_number;
2562
                        switch (the_insn.reloc)
2563
                          {
2564
                          default:
2565
                            break;
2566
 
2567
                          case BFD_RELOC_SPARC_HH22:
2568
                            val = BSR (val, 32);
2569
                            /* Fall through.  */
2570
 
2571
                          case BFD_RELOC_SPARC_LM22:
2572
                          case BFD_RELOC_HI22:
2573
                            val = (val >> 10) & 0x3fffff;
2574
                            break;
2575
 
2576
                          case BFD_RELOC_SPARC_HM10:
2577
                            val = BSR (val, 32);
2578
                            /* Fall through.  */
2579
 
2580
                          case BFD_RELOC_LO10:
2581
                            val &= 0x3ff;
2582
                            break;
2583
 
2584
                          case BFD_RELOC_SPARC_H44:
2585
                            val >>= 22;
2586
                            val &= 0x3fffff;
2587
                            break;
2588
 
2589
                          case BFD_RELOC_SPARC_M44:
2590
                            val >>= 12;
2591
                            val &= 0x3ff;
2592
                            break;
2593
 
2594
                          case BFD_RELOC_SPARC_L44:
2595
                            val &= 0xfff;
2596
                            break;
2597
 
2598
                          case BFD_RELOC_SPARC_HIX22:
2599
                            val = ~val;
2600
                            val = (val >> 10) & 0x3fffff;
2601
                            break;
2602
 
2603
                          case BFD_RELOC_SPARC_LOX10:
2604
                            val = (val & 0x3ff) | 0x1c00;
2605
                            break;
2606
                          }
2607
                        the_insn.exp = the_insn.exp2;
2608
                        the_insn.exp.X_add_number += val;
2609
                        the_insn.exp2.X_op = O_illegal;
2610
                        the_insn.reloc = old_reloc;
2611
                      }
2612
                    else if (the_insn.exp2.X_op != O_constant)
2613
                      {
2614
                        as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2615
                        return special_case;
2616
                      }
2617
                    else
2618
                      {
2619
                        if (old_reloc != BFD_RELOC_SPARC13
2620
                            || the_insn.reloc != BFD_RELOC_LO10
2621
                            || sparc_arch_size != 64
2622
                            || sparc_pic_code)
2623
                          {
2624
                            as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2625
                            return special_case;
2626
                          }
2627
                        the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2628
                      }
2629
                  }
2630
              }
2631
              /* Check for constants that don't require emitting a reloc.  */
2632
              if (the_insn.exp.X_op == O_constant
2633
                  && the_insn.exp.X_add_symbol == 0
2634
                  && the_insn.exp.X_op_symbol == 0)
2635
                {
2636
                  /* For pc-relative call instructions, we reject
2637
                     constants to get better code.  */
2638
                  if (the_insn.pcrel
2639
                      && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2640
                      && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2641
                    {
2642
                      error_message = _(": PC-relative operand can't be a constant");
2643
                      goto error;
2644
                    }
2645
 
2646
                  if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2647
                      && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2648
                    {
2649
                      error_message = _(": TLS operand can't be a constant");
2650
                      goto error;
2651
                    }
2652
 
2653
                  /* Constants that won't fit are checked in md_apply_fix
2654
                     and bfd_install_relocation.
2655
                     ??? It would be preferable to install the constants
2656
                     into the insn here and save having to create a fixS
2657
                     for each one.  There already exists code to handle
2658
                     all the various cases (e.g. in md_apply_fix and
2659
                     bfd_install_relocation) so duplicating all that code
2660
                     here isn't right.  */
2661
                }
2662
 
2663
              continue;
2664
 
2665
            case 'a':
2666
              if (*s++ == 'a')
2667
                {
2668
                  opcode |= ANNUL;
2669
                  continue;
2670
                }
2671
              break;
2672
 
2673
            case 'A':
2674
              {
2675
                int asi = 0;
2676
 
2677
                /* Parse an asi.  */
2678
                if (*s == '#')
2679
                  {
2680
                    if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2681
                      {
2682
                        error_message = _(": invalid ASI name");
2683
                        goto error;
2684
                      }
2685
                  }
2686
                else
2687
                  {
2688
                    if (! parse_const_expr_arg (&s, &asi))
2689
                      {
2690
                        error_message = _(": invalid ASI expression");
2691
                        goto error;
2692
                      }
2693
                    if (asi < 0 || asi > 255)
2694
                      {
2695
                        error_message = _(": invalid ASI number");
2696
                        goto error;
2697
                      }
2698
                  }
2699
                opcode |= ASI (asi);
2700
                continue;
2701
              }                 /* Alternate space.  */
2702
 
2703
            case 'p':
2704
              if (strncmp (s, "%psr", 4) == 0)
2705
                {
2706
                  s += 4;
2707
                  continue;
2708
                }
2709
              break;
2710
 
2711
            case 'q':           /* Floating point queue.  */
2712
              if (strncmp (s, "%fq", 3) == 0)
2713
                {
2714
                  s += 3;
2715
                  continue;
2716
                }
2717
              break;
2718
 
2719
            case 'Q':           /* Coprocessor queue.  */
2720
              if (strncmp (s, "%cq", 3) == 0)
2721
                {
2722
                  s += 3;
2723
                  continue;
2724
                }
2725
              break;
2726
 
2727
            case 'S':
2728
              if (strcmp (str, "set") == 0
2729
                  || strcmp (str, "setuw") == 0)
2730
                {
2731
                  special_case = SPECIAL_CASE_SET;
2732
                  continue;
2733
                }
2734
              else if (strcmp (str, "setsw") == 0)
2735
                {
2736
                  special_case = SPECIAL_CASE_SETSW;
2737
                  continue;
2738
                }
2739
              else if (strcmp (str, "setx") == 0)
2740
                {
2741
                  special_case = SPECIAL_CASE_SETX;
2742
                  continue;
2743
                }
2744
              else if (strncmp (str, "fdiv", 4) == 0)
2745
                {
2746
                  special_case = SPECIAL_CASE_FDIV;
2747
                  continue;
2748
                }
2749
              break;
2750
 
2751
            case 'o':
2752
              if (strncmp (s, "%asi", 4) != 0)
2753
                break;
2754
              s += 4;
2755
              continue;
2756
 
2757
            case 's':
2758
              if (strncmp (s, "%fprs", 5) != 0)
2759
                break;
2760
              s += 5;
2761
              continue;
2762
 
2763
            case 'E':
2764
              if (strncmp (s, "%ccr", 4) != 0)
2765
                break;
2766
              s += 4;
2767
              continue;
2768
 
2769
            case 't':
2770
              if (strncmp (s, "%tbr", 4) != 0)
2771
                break;
2772
              s += 4;
2773
              continue;
2774
 
2775
            case 'w':
2776
              if (strncmp (s, "%wim", 4) != 0)
2777
                break;
2778
              s += 4;
2779
              continue;
2780
 
2781
            case 'x':
2782
              {
2783
                char *push = input_line_pointer;
2784
                expressionS e;
2785
 
2786
                input_line_pointer = s;
2787
                expression (&e);
2788
                if (e.X_op == O_constant)
2789
                  {
2790
                    int n = e.X_add_number;
2791
                    if (n != e.X_add_number || (n & ~0x1ff) != 0)
2792
                      as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2793
                    else
2794
                      opcode |= e.X_add_number << 5;
2795
                  }
2796
                else
2797
                  as_bad (_("non-immediate OPF operand, ignored"));
2798
                s = input_line_pointer;
2799
                input_line_pointer = push;
2800
                continue;
2801
              }
2802
 
2803
            case 'y':
2804
              if (strncmp (s, "%y", 2) != 0)
2805
                break;
2806
              s += 2;
2807
              continue;
2808
 
2809
            case 'u':
2810
            case 'U':
2811
              {
2812
                /* Parse a sparclet cpreg.  */
2813
                int cpreg;
2814
                if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2815
                  {
2816
                    error_message = _(": invalid cpreg name");
2817
                    goto error;
2818
                  }
2819
                opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2820
                continue;
2821
              }
2822
 
2823
            default:
2824
              as_fatal (_("failed sanity check."));
2825
            }                   /* switch on arg code.  */
2826
 
2827
          /* Break out of for() loop.  */
2828
          break;
2829
        }                       /* For each arg that we expect.  */
2830
 
2831
    error:
2832
      if (match == 0)
2833
        {
2834
          /* Args don't match.  */
2835
          if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2836
              && (insn->name == insn[1].name
2837
                  || !strcmp (insn->name, insn[1].name)))
2838
            {
2839
              ++insn;
2840
              s = argsStart;
2841
              continue;
2842
            }
2843
          else
2844
            {
2845
              as_bad (_("Illegal operands%s"), error_message);
2846
              return special_case;
2847
            }
2848
        }
2849
      else
2850
        {
2851
          /* We have a match.  Now see if the architecture is OK.  */
2852
          int needed_arch_mask = insn->architecture;
2853 163 khays
          int hwcaps = insn->flags & F_HWCAP_MASK;
2854 16 khays
 
2855 163 khays
#if defined(OBJ_ELF) && !defined(TE_SOLARIS)
2856
          if (hwcaps)
2857
                  hwcap_seen |= hwcaps;
2858
#endif
2859 16 khays
          if (v9_arg_p)
2860
            {
2861
              needed_arch_mask &=
2862
                ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2863
              if (! needed_arch_mask)
2864
                needed_arch_mask =
2865
                  SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2866
            }
2867
 
2868
          if (needed_arch_mask
2869
              & SPARC_OPCODE_SUPPORTED (current_architecture))
2870
            /* OK.  */
2871
            ;
2872
          /* Can we bump up the architecture?  */
2873
          else if (needed_arch_mask
2874
                   & SPARC_OPCODE_SUPPORTED (max_architecture))
2875
            {
2876
              enum sparc_opcode_arch_val needed_architecture =
2877
                sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2878
                           & needed_arch_mask);
2879
 
2880
              gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2881
              if (warn_on_bump
2882
                  && needed_architecture > warn_after_architecture)
2883
                {
2884
                  as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2885
                           sparc_opcode_archs[current_architecture].name,
2886
                           sparc_opcode_archs[needed_architecture].name,
2887
                           str);
2888
                  warn_after_architecture = needed_architecture;
2889
                }
2890
              current_architecture = needed_architecture;
2891
            }
2892
          /* Conflict.  */
2893
          /* ??? This seems to be a bit fragile.  What if the next entry in
2894
             the opcode table is the one we want and it is supported?
2895
             It is possible to arrange the table today so that this can't
2896
             happen but what about tomorrow?  */
2897
          else
2898
            {
2899
              int arch, printed_one_p = 0;
2900
              char *p;
2901
              char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2902
 
2903
              /* Create a list of the architectures that support the insn.  */
2904
              needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2905
              p = required_archs;
2906
              arch = sparc_ffs (needed_arch_mask);
2907
              while ((1 << arch) <= needed_arch_mask)
2908
                {
2909
                  if ((1 << arch) & needed_arch_mask)
2910
                    {
2911
                      if (printed_one_p)
2912
                        *p++ = '|';
2913
                      strcpy (p, sparc_opcode_archs[arch].name);
2914
                      p += strlen (p);
2915
                      printed_one_p = 1;
2916
                    }
2917
                  ++arch;
2918
                }
2919
 
2920
              as_bad (_("Architecture mismatch on \"%s\"."), str);
2921
              as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2922
                         required_archs,
2923
                         sparc_opcode_archs[max_architecture].name);
2924
              return special_case;
2925
            }
2926 163 khays
 
2927
          /* Make sure the the hwcaps used by the instruction are
2928
             currently enabled.  */
2929
          if (hwcaps & ~hwcap_allowed)
2930
            {
2931
              const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed);
2932
 
2933
              as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
2934
                      hwcap_name, str);
2935
              return special_case;
2936
            }
2937 16 khays
        } /* If no match.  */
2938
 
2939
      break;
2940
    } /* Forever looking for a match.  */
2941
 
2942
  the_insn.opcode = opcode;
2943
  return special_case;
2944
}
2945
 
2946
/* Parse an argument that can be expressed as a keyword.
2947
   (eg: #StoreStore or %ccfr).
2948
   The result is a boolean indicating success.
2949
   If successful, INPUT_POINTER is updated.  */
2950
 
2951
static int
2952
parse_keyword_arg (int (*lookup_fn) (const char *),
2953
                   char **input_pointerP,
2954
                   int *valueP)
2955
{
2956
  int value;
2957
  char c, *p, *q;
2958
 
2959
  p = *input_pointerP;
2960
  for (q = p + (*p == '#' || *p == '%');
2961
       ISALNUM (*q) || *q == '_';
2962
       ++q)
2963
    continue;
2964
  c = *q;
2965
  *q = 0;
2966
  value = (*lookup_fn) (p);
2967
  *q = c;
2968
  if (value == -1)
2969
    return 0;
2970
  *valueP = value;
2971
  *input_pointerP = q;
2972
  return 1;
2973
}
2974
 
2975
/* Parse an argument that is a constant expression.
2976
   The result is a boolean indicating success.  */
2977
 
2978
static int
2979
parse_const_expr_arg (char **input_pointerP, int *valueP)
2980
{
2981
  char *save = input_line_pointer;
2982
  expressionS exp;
2983
 
2984
  input_line_pointer = *input_pointerP;
2985
  /* The next expression may be something other than a constant
2986
     (say if we're not processing the right variant of the insn).
2987
     Don't call expression unless we're sure it will succeed as it will
2988
     signal an error (which we want to defer until later).  */
2989
  /* FIXME: It might be better to define md_operand and have it recognize
2990
     things like %asi, etc. but continuing that route through to the end
2991
     is a lot of work.  */
2992
  if (*input_line_pointer == '%')
2993
    {
2994
      input_line_pointer = save;
2995
      return 0;
2996
    }
2997
  expression (&exp);
2998
  *input_pointerP = input_line_pointer;
2999
  input_line_pointer = save;
3000
  if (exp.X_op != O_constant)
3001
    return 0;
3002
  *valueP = exp.X_add_number;
3003
  return 1;
3004
}
3005
 
3006
/* Subroutine of sparc_ip to parse an expression.  */
3007
 
3008
static int
3009
get_expression (char *str)
3010
{
3011
  char *save_in;
3012
  segT seg;
3013
 
3014
  save_in = input_line_pointer;
3015
  input_line_pointer = str;
3016
  seg = expression (&the_insn.exp);
3017
  if (seg != absolute_section
3018
      && seg != text_section
3019
      && seg != data_section
3020
      && seg != bss_section
3021
      && seg != undefined_section)
3022
    {
3023
      the_insn.error = _("bad segment");
3024
      expr_end = input_line_pointer;
3025
      input_line_pointer = save_in;
3026
      return 1;
3027
    }
3028
  expr_end = input_line_pointer;
3029
  input_line_pointer = save_in;
3030
  return 0;
3031
}
3032
 
3033
/* Subroutine of md_assemble to output one insn.  */
3034
 
3035
static void
3036
output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn)
3037
{
3038
  char *toP = frag_more (4);
3039
 
3040
  /* Put out the opcode.  */
3041
  if (INSN_BIG_ENDIAN)
3042
    number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4);
3043
  else
3044
    number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4);
3045
 
3046
  /* Put out the symbol-dependent stuff.  */
3047
  if (theinsn->reloc != BFD_RELOC_NONE)
3048
    {
3049
      fixS *fixP =  fix_new_exp (frag_now,      /* Which frag.  */
3050
                                 (toP - frag_now->fr_literal),  /* Where.  */
3051
                                 4,             /* Size.  */
3052
                                 &theinsn->exp,
3053
                                 theinsn->pcrel,
3054
                                 theinsn->reloc);
3055
      /* Turn off overflow checking in fixup_segment.  We'll do our
3056
         own overflow checking in md_apply_fix.  This is necessary because
3057
         the insn size is 4 and fixup_segment will signal an overflow for
3058
         large 8 byte quantities.  */
3059
      fixP->fx_no_overflow = 1;
3060
      if (theinsn->reloc == BFD_RELOC_SPARC_OLO10)
3061
        fixP->tc_fix_data = theinsn->exp2.X_add_number;
3062
    }
3063
 
3064
  last_insn = insn;
3065
  last_opcode = theinsn->opcode;
3066
 
3067
#ifdef OBJ_ELF
3068
  dwarf2_emit_insn (4);
3069
#endif
3070
}
3071
 
3072
char *
3073
md_atof (int type, char *litP, int *sizeP)
3074
{
3075
  return ieee_md_atof (type, litP, sizeP, target_big_endian);
3076
}
3077
 
3078
/* Write a value out to the object file, using the appropriate
3079
   endianness.  */
3080
 
3081
void
3082
md_number_to_chars (char *buf, valueT val, int n)
3083
{
3084
  if (target_big_endian)
3085
    number_to_chars_bigendian (buf, val, n);
3086
  else if (target_little_endian_data
3087
           && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
3088
    /* Output debug words, which are not in allocated sections, as big
3089
       endian.  */
3090
    number_to_chars_bigendian (buf, val, n);
3091
  else if (target_little_endian_data || ! target_big_endian)
3092
    number_to_chars_littleendian (buf, val, n);
3093
}
3094
 
3095
/* Apply a fixS to the frags, now that we know the value it ought to
3096
   hold.  */
3097
 
3098
void
3099
md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED)
3100
{
3101
  char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3102
  offsetT val = * (offsetT *) valP;
3103
  long insn;
3104
 
3105
  gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
3106
 
3107
  fixP->fx_addnumber = val;     /* Remember value for emit_reloc.  */
3108
 
3109
#ifdef OBJ_ELF
3110
  /* SPARC ELF relocations don't use an addend in the data field.  */
3111
  if (fixP->fx_addsy != NULL)
3112
    {
3113
      switch (fixP->fx_r_type)
3114
        {
3115
        case BFD_RELOC_SPARC_TLS_GD_HI22:
3116
        case BFD_RELOC_SPARC_TLS_GD_LO10:
3117
        case BFD_RELOC_SPARC_TLS_GD_ADD:
3118
        case BFD_RELOC_SPARC_TLS_GD_CALL:
3119
        case BFD_RELOC_SPARC_TLS_LDM_HI22:
3120
        case BFD_RELOC_SPARC_TLS_LDM_LO10:
3121
        case BFD_RELOC_SPARC_TLS_LDM_ADD:
3122
        case BFD_RELOC_SPARC_TLS_LDM_CALL:
3123
        case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3124
        case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3125
        case BFD_RELOC_SPARC_TLS_LDO_ADD:
3126
        case BFD_RELOC_SPARC_TLS_IE_HI22:
3127
        case BFD_RELOC_SPARC_TLS_IE_LO10:
3128
        case BFD_RELOC_SPARC_TLS_IE_LD:
3129
        case BFD_RELOC_SPARC_TLS_IE_LDX:
3130
        case BFD_RELOC_SPARC_TLS_IE_ADD:
3131
        case BFD_RELOC_SPARC_TLS_LE_HIX22:
3132
        case BFD_RELOC_SPARC_TLS_LE_LOX10:
3133
        case BFD_RELOC_SPARC_TLS_DTPMOD32:
3134
        case BFD_RELOC_SPARC_TLS_DTPMOD64:
3135
        case BFD_RELOC_SPARC_TLS_DTPOFF32:
3136
        case BFD_RELOC_SPARC_TLS_DTPOFF64:
3137
        case BFD_RELOC_SPARC_TLS_TPOFF32:
3138
        case BFD_RELOC_SPARC_TLS_TPOFF64:
3139
          S_SET_THREAD_LOCAL (fixP->fx_addsy);
3140
 
3141
        default:
3142
          break;
3143
        }
3144
 
3145
      return;
3146
    }
3147
#endif
3148
 
3149
  /* This is a hack.  There should be a better way to
3150
     handle this.  Probably in terms of howto fields, once
3151
     we can look at these fixups in terms of howtos.  */
3152
  if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3153
    val += fixP->fx_where + fixP->fx_frag->fr_address;
3154
 
3155
#ifdef OBJ_AOUT
3156
  /* FIXME: More ridiculous gas reloc hacking.  If we are going to
3157
     generate a reloc, then we just want to let the reloc addend set
3158
     the value.  We do not want to also stuff the addend into the
3159
     object file.  Including the addend in the object file works when
3160
     doing a static link, because the linker will ignore the object
3161
     file contents.  However, the dynamic linker does not ignore the
3162
     object file contents.  */
3163
  if (fixP->fx_addsy != NULL
3164
      && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3165
    val = 0;
3166
 
3167
  /* When generating PIC code, we do not want an addend for a reloc
3168
     against a local symbol.  We adjust fx_addnumber to cancel out the
3169
     value already included in val, and to also cancel out the
3170
     adjustment which bfd_install_relocation will create.  */
3171
  if (sparc_pic_code
3172
      && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3173
      && fixP->fx_addsy != NULL
3174
      && ! S_IS_COMMON (fixP->fx_addsy)
3175
      && symbol_section_p (fixP->fx_addsy))
3176
    fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3177
 
3178
  /* When generating PIC code, we need to fiddle to get
3179
     bfd_install_relocation to do the right thing for a PC relative
3180
     reloc against a local symbol which we are going to keep.  */
3181
  if (sparc_pic_code
3182
      && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3183
      && fixP->fx_addsy != NULL
3184
      && (S_IS_EXTERNAL (fixP->fx_addsy)
3185
          || S_IS_WEAK (fixP->fx_addsy))
3186
      && S_IS_DEFINED (fixP->fx_addsy)
3187
      && ! S_IS_COMMON (fixP->fx_addsy))
3188
    {
3189
      val = 0;
3190
      fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3191
    }
3192
#endif
3193
 
3194
  /* If this is a data relocation, just output VAL.  */
3195
 
3196 166 khays
  if (fixP->fx_r_type == BFD_RELOC_8)
3197 16 khays
    {
3198 166 khays
      md_number_to_chars (buf, val, 1);
3199
    }
3200
  else if (fixP->fx_r_type == BFD_RELOC_16
3201
           || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
3202
    {
3203 16 khays
      md_number_to_chars (buf, val, 2);
3204
    }
3205
  else if (fixP->fx_r_type == BFD_RELOC_32
3206
           || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
3207
           || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3208
    {
3209
      md_number_to_chars (buf, val, 4);
3210
    }
3211
  else if (fixP->fx_r_type == BFD_RELOC_64
3212
           || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
3213
    {
3214
      md_number_to_chars (buf, val, 8);
3215
    }
3216
  else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3217
           || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3218
    {
3219
      fixP->fx_done = 0;
3220
      return;
3221
    }
3222
  else
3223
    {
3224
      /* It's a relocation against an instruction.  */
3225
 
3226
      if (INSN_BIG_ENDIAN)
3227
        insn = bfd_getb32 ((unsigned char *) buf);
3228
      else
3229
        insn = bfd_getl32 ((unsigned char *) buf);
3230
 
3231
      switch (fixP->fx_r_type)
3232
        {
3233
        case BFD_RELOC_32_PCREL_S2:
3234
          val = val >> 2;
3235
          /* FIXME: This increment-by-one deserves a comment of why it's
3236
             being done!  */
3237
          if (! sparc_pic_code
3238
              || fixP->fx_addsy == NULL
3239
              || symbol_section_p (fixP->fx_addsy))
3240
            ++val;
3241
 
3242
          insn |= val & 0x3fffffff;
3243
 
3244
          /* See if we have a delay slot.  */
3245
          if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3246
            {
3247
#define G0              0
3248
#define O7              15
3249
#define XCC             (2 << 20)
3250
#define COND(x)         (((x)&0xf)<<25)
3251
#define CONDA           COND(0x8)
3252
#define INSN_BPA        (F2(0,1) | CONDA | BPRED | XCC)
3253
#define INSN_BA         (F2(0,2) | CONDA)
3254
#define INSN_OR         F3(2, 0x2, 0)
3255
#define INSN_NOP        F2(0,4)
3256
 
3257
              long delay;
3258
 
3259
              /* If the instruction is a call with either:
3260
                 restore
3261
                 arithmetic instruction with rd == %o7
3262
                 where rs1 != %o7 and rs2 if it is register != %o7
3263
                 then we can optimize if the call destination is near
3264
                 by changing the call into a branch always.  */
3265
              if (INSN_BIG_ENDIAN)
3266
                delay = bfd_getb32 ((unsigned char *) buf + 4);
3267
              else
3268
                delay = bfd_getl32 ((unsigned char *) buf + 4);
3269
              if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3270
                break;
3271
              if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore.  */
3272
                  && ((delay & OP3 (0x28)) != 0 /* Arithmetic.  */
3273
                      || ((delay & RD (~0)) != RD (O7))))
3274
                break;
3275
              if ((delay & RS1 (~0)) == RS1 (O7)
3276
                  || ((delay & F3I (~0)) == 0
3277
                      && (delay & RS2 (~0)) == RS2 (O7)))
3278
                break;
3279
              /* Ensure the branch will fit into simm22.  */
3280
              if ((val & 0x3fe00000)
3281
                  && (val & 0x3fe00000) != 0x3fe00000)
3282
                break;
3283
              /* Check if the arch is v9 and branch will fit
3284
                 into simm19.  */
3285
              if (((val & 0x3c0000) == 0
3286
                   || (val & 0x3c0000) == 0x3c0000)
3287
                  && (sparc_arch_size == 64
3288
                      || current_architecture >= SPARC_OPCODE_ARCH_V9))
3289
                /* ba,pt %xcc  */
3290
                insn = INSN_BPA | (val & 0x7ffff);
3291
              else
3292
                /* ba  */
3293
                insn = INSN_BA | (val & 0x3fffff);
3294
              if (fixP->fx_where >= 4
3295
                  && ((delay & (0xffffffff ^ RS1 (~0)))
3296
                      == (INSN_OR | RD (O7) | RS2 (G0))))
3297
                {
3298
                  long setter;
3299
                  int reg;
3300
 
3301
                  if (INSN_BIG_ENDIAN)
3302
                    setter = bfd_getb32 ((unsigned char *) buf - 4);
3303
                  else
3304
                    setter = bfd_getl32 ((unsigned char *) buf - 4);
3305
                  if ((setter & (0xffffffff ^ RD (~0)))
3306
                      != (INSN_OR | RS1 (O7) | RS2 (G0)))
3307
                    break;
3308
                  /* The sequence was
3309
                     or %o7, %g0, %rN
3310
                     call foo
3311
                     or %rN, %g0, %o7
3312
 
3313
                     If call foo was replaced with ba, replace
3314
                     or %rN, %g0, %o7 with nop.  */
3315
                  reg = (delay & RS1 (~0)) >> 14;
3316
                  if (reg != ((setter & RD (~0)) >> 25)
3317
                      || reg == G0 || reg == O7)
3318
                    break;
3319
 
3320
                  if (INSN_BIG_ENDIAN)
3321
                    bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3322
                  else
3323
                    bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3324
                }
3325
            }
3326
          break;
3327
 
3328
        case BFD_RELOC_SPARC_11:
3329
          if (! in_signed_range (val, 0x7ff))
3330
            as_bad_where (fixP->fx_file, fixP->fx_line,
3331
                          _("relocation overflow"));
3332
          insn |= val & 0x7ff;
3333
          break;
3334
 
3335
        case BFD_RELOC_SPARC_10:
3336
          if (! in_signed_range (val, 0x3ff))
3337
            as_bad_where (fixP->fx_file, fixP->fx_line,
3338
                          _("relocation overflow"));
3339
          insn |= val & 0x3ff;
3340
          break;
3341
 
3342
        case BFD_RELOC_SPARC_7:
3343
          if (! in_bitfield_range (val, 0x7f))
3344
            as_bad_where (fixP->fx_file, fixP->fx_line,
3345
                          _("relocation overflow"));
3346
          insn |= val & 0x7f;
3347
          break;
3348
 
3349
        case BFD_RELOC_SPARC_6:
3350
          if (! in_bitfield_range (val, 0x3f))
3351
            as_bad_where (fixP->fx_file, fixP->fx_line,
3352
                          _("relocation overflow"));
3353
          insn |= val & 0x3f;
3354
          break;
3355
 
3356
        case BFD_RELOC_SPARC_5:
3357
          if (! in_bitfield_range (val, 0x1f))
3358
            as_bad_where (fixP->fx_file, fixP->fx_line,
3359
                          _("relocation overflow"));
3360
          insn |= val & 0x1f;
3361
          break;
3362
 
3363
        case BFD_RELOC_SPARC_WDISP16:
3364
          if ((val & 3)
3365
              || val >= 0x1fffc
3366
              || val <= -(offsetT) 0x20008)
3367
            as_bad_where (fixP->fx_file, fixP->fx_line,
3368
                          _("relocation overflow"));
3369
          /* FIXME: The +1 deserves a comment.  */
3370
          val = (val >> 2) + 1;
3371
          insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3372
          break;
3373
 
3374
        case BFD_RELOC_SPARC_WDISP19:
3375
          if ((val & 3)
3376
              || val >= 0xffffc
3377
              || val <= -(offsetT) 0x100008)
3378
            as_bad_where (fixP->fx_file, fixP->fx_line,
3379
                          _("relocation overflow"));
3380
          /* FIXME: The +1 deserves a comment.  */
3381
          val = (val >> 2) + 1;
3382
          insn |= val & 0x7ffff;
3383
          break;
3384
 
3385
        case BFD_RELOC_SPARC_HH22:
3386
          val = BSR (val, 32);
3387
          /* Fall through.  */
3388
 
3389
        case BFD_RELOC_SPARC_LM22:
3390
        case BFD_RELOC_HI22:
3391
          if (!fixP->fx_addsy)
3392
            insn |= (val >> 10) & 0x3fffff;
3393
          else
3394
            /* FIXME: Need comment explaining why we do this.  */
3395
            insn &= ~0xffff;
3396
          break;
3397
 
3398
        case BFD_RELOC_SPARC22:
3399
          if (val & ~0x003fffff)
3400
            as_bad_where (fixP->fx_file, fixP->fx_line,
3401
                          _("relocation overflow"));
3402
          insn |= (val & 0x3fffff);
3403
          break;
3404
 
3405
        case BFD_RELOC_SPARC_HM10:
3406
          val = BSR (val, 32);
3407
          /* Fall through.  */
3408
 
3409
        case BFD_RELOC_LO10:
3410
          if (!fixP->fx_addsy)
3411
            insn |= val & 0x3ff;
3412
          else
3413
            /* FIXME: Need comment explaining why we do this.  */
3414
            insn &= ~0xff;
3415
          break;
3416
 
3417
        case BFD_RELOC_SPARC_OLO10:
3418
          val &= 0x3ff;
3419
          val += fixP->tc_fix_data;
3420
          /* Fall through.  */
3421
 
3422
        case BFD_RELOC_SPARC13:
3423
          if (! in_signed_range (val, 0x1fff))
3424
            as_bad_where (fixP->fx_file, fixP->fx_line,
3425
                          _("relocation overflow"));
3426
          insn |= val & 0x1fff;
3427
          break;
3428
 
3429
        case BFD_RELOC_SPARC_WDISP22:
3430
          val = (val >> 2) + 1;
3431
          /* Fall through.  */
3432
        case BFD_RELOC_SPARC_BASE22:
3433
          insn |= val & 0x3fffff;
3434
          break;
3435
 
3436
        case BFD_RELOC_SPARC_H44:
3437
          if (!fixP->fx_addsy)
3438
            {
3439
              bfd_vma tval = val;
3440
              tval >>= 22;
3441
              insn |= tval & 0x3fffff;
3442
            }
3443
          break;
3444
 
3445
        case BFD_RELOC_SPARC_M44:
3446
          if (!fixP->fx_addsy)
3447
            insn |= (val >> 12) & 0x3ff;
3448
          break;
3449
 
3450
        case BFD_RELOC_SPARC_L44:
3451
          if (!fixP->fx_addsy)
3452
            insn |= val & 0xfff;
3453
          break;
3454
 
3455
        case BFD_RELOC_SPARC_HIX22:
3456
          if (!fixP->fx_addsy)
3457
            {
3458
              val ^= ~(offsetT) 0;
3459
              insn |= (val >> 10) & 0x3fffff;
3460
            }
3461
          break;
3462
 
3463
        case BFD_RELOC_SPARC_LOX10:
3464
          if (!fixP->fx_addsy)
3465
            insn |= 0x1c00 | (val & 0x3ff);
3466
          break;
3467
 
3468
        case BFD_RELOC_NONE:
3469
        default:
3470
          as_bad_where (fixP->fx_file, fixP->fx_line,
3471
                        _("bad or unhandled relocation type: 0x%02x"),
3472
                        fixP->fx_r_type);
3473
          break;
3474
        }
3475
 
3476
      if (INSN_BIG_ENDIAN)
3477
        bfd_putb32 (insn, (unsigned char *) buf);
3478
      else
3479
        bfd_putl32 (insn, (unsigned char *) buf);
3480
    }
3481
 
3482
  /* Are we finished with this relocation now?  */
3483
  if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3484
    fixP->fx_done = 1;
3485
}
3486
 
3487
/* Translate internal representation of relocation info to BFD target
3488
   format.  */
3489
 
3490
arelent **
3491
tc_gen_reloc (asection *section, fixS *fixp)
3492
{
3493
  static arelent *relocs[3];
3494
  arelent *reloc;
3495
  bfd_reloc_code_real_type code;
3496
 
3497
  relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3498
  relocs[1] = NULL;
3499
 
3500
  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3501
  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3502
  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3503
 
3504
  switch (fixp->fx_r_type)
3505
    {
3506
    case BFD_RELOC_16:
3507
    case BFD_RELOC_32:
3508
    case BFD_RELOC_HI22:
3509
    case BFD_RELOC_LO10:
3510
    case BFD_RELOC_32_PCREL_S2:
3511
    case BFD_RELOC_SPARC13:
3512
    case BFD_RELOC_SPARC22:
3513
    case BFD_RELOC_SPARC_PC22:
3514
    case BFD_RELOC_SPARC_PC10:
3515
    case BFD_RELOC_SPARC_BASE13:
3516
    case BFD_RELOC_SPARC_WDISP16:
3517
    case BFD_RELOC_SPARC_WDISP19:
3518
    case BFD_RELOC_SPARC_WDISP22:
3519
    case BFD_RELOC_64:
3520
    case BFD_RELOC_SPARC_5:
3521
    case BFD_RELOC_SPARC_6:
3522
    case BFD_RELOC_SPARC_7:
3523
    case BFD_RELOC_SPARC_10:
3524
    case BFD_RELOC_SPARC_11:
3525
    case BFD_RELOC_SPARC_HH22:
3526
    case BFD_RELOC_SPARC_HM10:
3527
    case BFD_RELOC_SPARC_LM22:
3528
    case BFD_RELOC_SPARC_PC_HH22:
3529
    case BFD_RELOC_SPARC_PC_HM10:
3530
    case BFD_RELOC_SPARC_PC_LM22:
3531
    case BFD_RELOC_SPARC_H44:
3532
    case BFD_RELOC_SPARC_M44:
3533
    case BFD_RELOC_SPARC_L44:
3534
    case BFD_RELOC_SPARC_HIX22:
3535
    case BFD_RELOC_SPARC_LOX10:
3536
    case BFD_RELOC_SPARC_REV32:
3537
    case BFD_RELOC_SPARC_OLO10:
3538
    case BFD_RELOC_SPARC_UA16:
3539
    case BFD_RELOC_SPARC_UA32:
3540
    case BFD_RELOC_SPARC_UA64:
3541
    case BFD_RELOC_8_PCREL:
3542
    case BFD_RELOC_16_PCREL:
3543
    case BFD_RELOC_32_PCREL:
3544
    case BFD_RELOC_64_PCREL:
3545
    case BFD_RELOC_SPARC_PLT32:
3546
    case BFD_RELOC_SPARC_PLT64:
3547
    case BFD_RELOC_VTABLE_ENTRY:
3548
    case BFD_RELOC_VTABLE_INHERIT:
3549
    case BFD_RELOC_SPARC_TLS_GD_HI22:
3550
    case BFD_RELOC_SPARC_TLS_GD_LO10:
3551
    case BFD_RELOC_SPARC_TLS_GD_ADD:
3552
    case BFD_RELOC_SPARC_TLS_GD_CALL:
3553
    case BFD_RELOC_SPARC_TLS_LDM_HI22:
3554
    case BFD_RELOC_SPARC_TLS_LDM_LO10:
3555
    case BFD_RELOC_SPARC_TLS_LDM_ADD:
3556
    case BFD_RELOC_SPARC_TLS_LDM_CALL:
3557
    case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3558
    case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3559
    case BFD_RELOC_SPARC_TLS_LDO_ADD:
3560
    case BFD_RELOC_SPARC_TLS_IE_HI22:
3561
    case BFD_RELOC_SPARC_TLS_IE_LO10:
3562
    case BFD_RELOC_SPARC_TLS_IE_LD:
3563
    case BFD_RELOC_SPARC_TLS_IE_LDX:
3564
    case BFD_RELOC_SPARC_TLS_IE_ADD:
3565
    case BFD_RELOC_SPARC_TLS_LE_HIX22:
3566
    case BFD_RELOC_SPARC_TLS_LE_LOX10:
3567
    case BFD_RELOC_SPARC_TLS_DTPOFF32:
3568
    case BFD_RELOC_SPARC_TLS_DTPOFF64:
3569
    case BFD_RELOC_SPARC_GOTDATA_OP_HIX22:
3570
    case BFD_RELOC_SPARC_GOTDATA_OP_LOX10:
3571
    case BFD_RELOC_SPARC_GOTDATA_OP:
3572
      code = fixp->fx_r_type;
3573
      break;
3574
    default:
3575
      abort ();
3576
      return NULL;
3577
    }
3578
 
3579
#if defined (OBJ_ELF) || defined (OBJ_AOUT)
3580
  /* If we are generating PIC code, we need to generate a different
3581
     set of relocs.  */
3582
 
3583
#ifdef OBJ_ELF
3584
#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3585
#else
3586
#define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3587
#endif
3588
#ifdef TE_VXWORKS
3589
#define GOTT_BASE "__GOTT_BASE__"
3590
#define GOTT_INDEX "__GOTT_INDEX__"
3591
#endif
3592
 
3593
  /* This code must be parallel to the OBJ_ELF tc_fix_adjustable.  */
3594
 
3595
  if (sparc_pic_code)
3596
    {
3597
      switch (code)
3598
        {
3599
        case BFD_RELOC_32_PCREL_S2:
3600
          if (generic_force_reloc (fixp))
3601
            code = BFD_RELOC_SPARC_WPLT30;
3602
          break;
3603
        case BFD_RELOC_HI22:
3604
          code = BFD_RELOC_SPARC_GOT22;
3605
          if (fixp->fx_addsy != NULL)
3606
            {
3607
              if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3608
                code = BFD_RELOC_SPARC_PC22;
3609
#ifdef TE_VXWORKS
3610
              if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3611
                  || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3612
                code = BFD_RELOC_HI22; /* Unchanged.  */
3613
#endif
3614
            }
3615
          break;
3616
        case BFD_RELOC_LO10:
3617
          code = BFD_RELOC_SPARC_GOT10;
3618
          if (fixp->fx_addsy != NULL)
3619
            {
3620
              if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3621
                code = BFD_RELOC_SPARC_PC10;
3622
#ifdef TE_VXWORKS
3623
              if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3624
                  || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3625
                code = BFD_RELOC_LO10; /* Unchanged.  */
3626
#endif
3627
            }
3628
          break;
3629
        case BFD_RELOC_SPARC13:
3630
          code = BFD_RELOC_SPARC_GOT13;
3631
          break;
3632
        default:
3633
          break;
3634
        }
3635
    }
3636
#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT)  */
3637
 
3638
  /* Nothing is aligned in DWARF debugging sections.  */
3639
  if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
3640
    switch (code)
3641
      {
3642
      case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
3643
      case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
3644
      case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
3645
      default: break;
3646
      }
3647
 
3648
  if (code == BFD_RELOC_SPARC_OLO10)
3649
    reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3650
  else
3651
    reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3652
  if (reloc->howto == 0)
3653
    {
3654
      as_bad_where (fixp->fx_file, fixp->fx_line,
3655
                    _("internal error: can't export reloc type %d (`%s')"),
3656
                    fixp->fx_r_type, bfd_get_reloc_code_name (code));
3657
      xfree (reloc);
3658
      relocs[0] = NULL;
3659
      return relocs;
3660
    }
3661
 
3662
  /* @@ Why fx_addnumber sometimes and fx_offset other times?  */
3663
#ifdef OBJ_AOUT
3664
 
3665
  if (reloc->howto->pc_relative == 0
3666
      || code == BFD_RELOC_SPARC_PC10
3667
      || code == BFD_RELOC_SPARC_PC22)
3668
    reloc->addend = fixp->fx_addnumber;
3669
  else if (sparc_pic_code
3670
           && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3671
           && fixp->fx_addsy != NULL
3672
           && (S_IS_EXTERNAL (fixp->fx_addsy)
3673
               || S_IS_WEAK (fixp->fx_addsy))
3674
           && S_IS_DEFINED (fixp->fx_addsy)
3675
           && ! S_IS_COMMON (fixp->fx_addsy))
3676
    reloc->addend = fixp->fx_addnumber;
3677
  else
3678
    reloc->addend = fixp->fx_offset - reloc->address;
3679
 
3680
#else /* elf or coff  */
3681
 
3682
  if (code != BFD_RELOC_32_PCREL_S2
3683
      && code != BFD_RELOC_SPARC_WDISP22
3684
      && code != BFD_RELOC_SPARC_WDISP16
3685
      && code != BFD_RELOC_SPARC_WDISP19
3686
      && code != BFD_RELOC_SPARC_WPLT30
3687
      && code != BFD_RELOC_SPARC_TLS_GD_CALL
3688
      && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
3689
    reloc->addend = fixp->fx_addnumber;
3690
  else if (symbol_section_p (fixp->fx_addsy))
3691
    reloc->addend = (section->vma
3692
                     + fixp->fx_addnumber
3693
                     + md_pcrel_from (fixp));
3694
  else
3695
    reloc->addend = fixp->fx_offset;
3696
#endif
3697
 
3698
  /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3699
     on the same location.  */
3700
  if (code == BFD_RELOC_SPARC_OLO10)
3701
    {
3702
      relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3703
      relocs[2] = NULL;
3704
 
3705
      reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3706
      *reloc->sym_ptr_ptr
3707
        = symbol_get_bfdsym (section_symbol (absolute_section));
3708
      reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3709
      reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3710
      reloc->addend = fixp->tc_fix_data;
3711
    }
3712
 
3713
  return relocs;
3714
}
3715
 
3716
/* We have no need to default values of symbols.  */
3717
 
3718
symbolS *
3719
md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
3720
{
3721
  return 0;
3722
}
3723
 
3724
/* Round up a section size to the appropriate boundary.  */
3725
 
3726
valueT
3727
md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
3728
{
3729
#ifndef OBJ_ELF
3730
  /* This is not right for ELF; a.out wants it, and COFF will force
3731
     the alignment anyways.  */
3732
  valueT align = ((valueT) 1
3733
                  << (valueT) bfd_get_section_alignment (stdoutput, segment));
3734
  valueT newsize;
3735
 
3736
  /* Turn alignment value into a mask.  */
3737
  align--;
3738
  newsize = (size + align) & ~align;
3739
  return newsize;
3740
#else
3741
  return size;
3742
#endif
3743
}
3744
 
3745
/* Exactly what point is a PC-relative offset relative TO?
3746
   On the sparc, they're relative to the address of the offset, plus
3747
   its size.  This gets us to the following instruction.
3748
   (??? Is this right?  FIXME-SOON)  */
3749
long
3750
md_pcrel_from (fixS *fixP)
3751
{
3752
  long ret;
3753
 
3754
  ret = fixP->fx_where + fixP->fx_frag->fr_address;
3755
  if (! sparc_pic_code
3756
      || fixP->fx_addsy == NULL
3757
      || symbol_section_p (fixP->fx_addsy))
3758
    ret += fixP->fx_size;
3759
  return ret;
3760
}
3761
 
3762
/* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3763
   of two.  */
3764
 
3765
static int
3766
mylog2 (int value)
3767
{
3768
  int shift;
3769
 
3770
  if (value <= 0)
3771
    return -1;
3772
 
3773
  for (shift = 0; (value & 1) == 0; value >>= 1)
3774
    ++shift;
3775
 
3776
  return (value == 1) ? shift : -1;
3777
}
3778
 
3779
/* Sort of like s_lcomm.  */
3780
 
3781
#ifndef OBJ_ELF
3782
static int max_alignment = 15;
3783
#endif
3784
 
3785
static void
3786
s_reserve (int ignore ATTRIBUTE_UNUSED)
3787
{
3788
  char *name;
3789
  char *p;
3790
  char c;
3791
  int align;
3792
  int size;
3793
  int temp;
3794
  symbolS *symbolP;
3795
 
3796
  name = input_line_pointer;
3797
  c = get_symbol_end ();
3798
  p = input_line_pointer;
3799
  *p = c;
3800
  SKIP_WHITESPACE ();
3801
 
3802
  if (*input_line_pointer != ',')
3803
    {
3804
      as_bad (_("Expected comma after name"));
3805
      ignore_rest_of_line ();
3806
      return;
3807
    }
3808
 
3809
  ++input_line_pointer;
3810
 
3811
  if ((size = get_absolute_expression ()) < 0)
3812
    {
3813
      as_bad (_("BSS length (%d.) <0! Ignored."), size);
3814
      ignore_rest_of_line ();
3815
      return;
3816
    }                           /* Bad length.  */
3817
 
3818
  *p = 0;
3819
  symbolP = symbol_find_or_make (name);
3820
  *p = c;
3821
 
3822
  if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3823
      && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3824
    {
3825
      as_bad (_("bad .reserve segment -- expected BSS segment"));
3826
      return;
3827
    }
3828
 
3829
  if (input_line_pointer[2] == '.')
3830
    input_line_pointer += 7;
3831
  else
3832
    input_line_pointer += 6;
3833
  SKIP_WHITESPACE ();
3834
 
3835
  if (*input_line_pointer == ',')
3836
    {
3837
      ++input_line_pointer;
3838
 
3839
      SKIP_WHITESPACE ();
3840
      if (*input_line_pointer == '\n')
3841
        {
3842
          as_bad (_("missing alignment"));
3843
          ignore_rest_of_line ();
3844
          return;
3845
        }
3846
 
3847
      align = (int) get_absolute_expression ();
3848
 
3849
#ifndef OBJ_ELF
3850
      if (align > max_alignment)
3851
        {
3852
          align = max_alignment;
3853
          as_warn (_("alignment too large; assuming %d"), align);
3854
        }
3855
#endif
3856
 
3857
      if (align < 0)
3858
        {
3859
          as_bad (_("negative alignment"));
3860
          ignore_rest_of_line ();
3861
          return;
3862
        }
3863
 
3864
      if (align != 0)
3865
        {
3866
          temp = mylog2 (align);
3867
          if (temp < 0)
3868
            {
3869
              as_bad (_("alignment not a power of 2"));
3870
              ignore_rest_of_line ();
3871
              return;
3872
            }
3873
 
3874
          align = temp;
3875
        }
3876
 
3877
      record_alignment (bss_section, align);
3878
    }
3879
  else
3880
    align = 0;
3881
 
3882
  if (!S_IS_DEFINED (symbolP)
3883
#ifdef OBJ_AOUT
3884
      && S_GET_OTHER (symbolP) == 0
3885
      && S_GET_DESC (symbolP) == 0
3886
#endif
3887
      )
3888
    {
3889
      if (! need_pass_2)
3890
        {
3891
          char *pfrag;
3892
          segT current_seg = now_seg;
3893
          subsegT current_subseg = now_subseg;
3894
 
3895
          /* Switch to bss.  */
3896
          subseg_set (bss_section, 1);
3897
 
3898
          if (align)
3899
            /* Do alignment.  */
3900
            frag_align (align, 0, 0);
3901
 
3902
          /* Detach from old frag.  */
3903
          if (S_GET_SEGMENT (symbolP) == bss_section)
3904
            symbol_get_frag (symbolP)->fr_symbol = NULL;
3905
 
3906
          symbol_set_frag (symbolP, frag_now);
3907
          pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3908
                            (offsetT) size, (char *) 0);
3909
          *pfrag = 0;
3910
 
3911
          S_SET_SEGMENT (symbolP, bss_section);
3912
 
3913
          subseg_set (current_seg, current_subseg);
3914
 
3915
#ifdef OBJ_ELF
3916
          S_SET_SIZE (symbolP, size);
3917
#endif
3918
        }
3919
    }
3920
  else
3921
    {
3922
      as_warn (_("Ignoring attempt to re-define symbol %s"),
3923
               S_GET_NAME (symbolP));
3924
    }
3925
 
3926
  demand_empty_rest_of_line ();
3927
}
3928
 
3929
static void
3930
s_common (int ignore ATTRIBUTE_UNUSED)
3931
{
3932
  char *name;
3933
  char c;
3934
  char *p;
3935
  offsetT temp, size;
3936
  symbolS *symbolP;
3937
 
3938
  name = input_line_pointer;
3939
  c = get_symbol_end ();
3940
  /* Just after name is now '\0'.  */
3941
  p = input_line_pointer;
3942
  *p = c;
3943
  SKIP_WHITESPACE ();
3944
  if (*input_line_pointer != ',')
3945
    {
3946
      as_bad (_("Expected comma after symbol-name"));
3947
      ignore_rest_of_line ();
3948
      return;
3949
    }
3950
 
3951
  /* Skip ','.  */
3952
  input_line_pointer++;
3953
 
3954
  if ((temp = get_absolute_expression ()) < 0)
3955
    {
3956
      as_bad (_(".COMMon length (%lu) out of range ignored"),
3957
              (unsigned long) temp);
3958
      ignore_rest_of_line ();
3959
      return;
3960
    }
3961
  size = temp;
3962
  *p = 0;
3963
  symbolP = symbol_find_or_make (name);
3964
  *p = c;
3965
  if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3966
    {
3967
      as_bad (_("Ignoring attempt to re-define symbol"));
3968
      ignore_rest_of_line ();
3969
      return;
3970
    }
3971
  if (S_GET_VALUE (symbolP) != 0)
3972
    {
3973
      if (S_GET_VALUE (symbolP) != (valueT) size)
3974
        {
3975
          as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
3976
                   S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
3977
        }
3978
    }
3979
  else
3980
    {
3981
#ifndef OBJ_ELF
3982
      S_SET_VALUE (symbolP, (valueT) size);
3983
      S_SET_EXTERNAL (symbolP);
3984
#endif
3985
    }
3986
  know (symbol_get_frag (symbolP) == &zero_address_frag);
3987
  if (*input_line_pointer != ',')
3988
    {
3989
      as_bad (_("Expected comma after common length"));
3990
      ignore_rest_of_line ();
3991
      return;
3992
    }
3993
  input_line_pointer++;
3994
  SKIP_WHITESPACE ();
3995
  if (*input_line_pointer != '"')
3996
    {
3997
      temp = get_absolute_expression ();
3998
 
3999
#ifndef OBJ_ELF
4000
      if (temp > max_alignment)
4001
        {
4002
          temp = max_alignment;
4003
          as_warn (_("alignment too large; assuming %ld"), (long) temp);
4004
        }
4005
#endif
4006
 
4007
      if (temp < 0)
4008
        {
4009
          as_bad (_("negative alignment"));
4010
          ignore_rest_of_line ();
4011
          return;
4012
        }
4013
 
4014
#ifdef OBJ_ELF
4015
      if (symbol_get_obj (symbolP)->local)
4016
        {
4017
          segT old_sec;
4018
          int old_subsec;
4019
          int align;
4020
 
4021
          old_sec = now_seg;
4022
          old_subsec = now_subseg;
4023
 
4024
          if (temp == 0)
4025
            align = 0;
4026
          else
4027
            align = mylog2 (temp);
4028
 
4029
          if (align < 0)
4030
            {
4031
              as_bad (_("alignment not a power of 2"));
4032
              ignore_rest_of_line ();
4033
              return;
4034
            }
4035
 
4036
          record_alignment (bss_section, align);
4037
          subseg_set (bss_section, 0);
4038
          if (align)
4039
            frag_align (align, 0, 0);
4040
          if (S_GET_SEGMENT (symbolP) == bss_section)
4041
            symbol_get_frag (symbolP)->fr_symbol = 0;
4042
          symbol_set_frag (symbolP, frag_now);
4043
          p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
4044
                        (offsetT) size, (char *) 0);
4045
          *p = 0;
4046
          S_SET_SEGMENT (symbolP, bss_section);
4047
          S_CLEAR_EXTERNAL (symbolP);
4048
          S_SET_SIZE (symbolP, size);
4049
          subseg_set (old_sec, old_subsec);
4050
        }
4051
      else
4052
#endif /* OBJ_ELF  */
4053
        {
4054
        allocate_common:
4055
          S_SET_VALUE (symbolP, (valueT) size);
4056
#ifdef OBJ_ELF
4057
          S_SET_ALIGN (symbolP, temp);
4058
          S_SET_SIZE (symbolP, size);
4059
#endif
4060
          S_SET_EXTERNAL (symbolP);
4061
          S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
4062
        }
4063
    }
4064
  else
4065
    {
4066
      input_line_pointer++;
4067
      /* @@ Some use the dot, some don't.  Can we get some consistency??  */
4068
      if (*input_line_pointer == '.')
4069
        input_line_pointer++;
4070
      /* @@ Some say data, some say bss.  */
4071
      if (strncmp (input_line_pointer, "bss\"", 4)
4072
          && strncmp (input_line_pointer, "data\"", 5))
4073
        {
4074
          while (*--input_line_pointer != '"')
4075
            ;
4076
          input_line_pointer--;
4077
          goto bad_common_segment;
4078
        }
4079
      while (*input_line_pointer++ != '"')
4080
        ;
4081
      goto allocate_common;
4082
    }
4083
 
4084
  symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
4085
 
4086
  demand_empty_rest_of_line ();
4087
  return;
4088
 
4089
  {
4090
  bad_common_segment:
4091
    p = input_line_pointer;
4092
    while (*p && *p != '\n')
4093
      p++;
4094
    c = *p;
4095
    *p = '\0';
4096
    as_bad (_("bad .common segment %s"), input_line_pointer + 1);
4097
    *p = c;
4098
    input_line_pointer = p;
4099
    ignore_rest_of_line ();
4100
    return;
4101
  }
4102
}
4103
 
4104
/* Handle the .empty pseudo-op.  This suppresses the warnings about
4105
   invalid delay slot usage.  */
4106
 
4107
static void
4108
s_empty (int ignore ATTRIBUTE_UNUSED)
4109
{
4110
  /* The easy way to implement is to just forget about the last
4111
     instruction.  */
4112
  last_insn = NULL;
4113
}
4114
 
4115
static void
4116
s_seg (int ignore ATTRIBUTE_UNUSED)
4117
{
4118
 
4119
  if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
4120
    {
4121
      input_line_pointer += 6;
4122
      s_text (0);
4123
      return;
4124
    }
4125
  if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
4126
    {
4127
      input_line_pointer += 6;
4128
      s_data (0);
4129
      return;
4130
    }
4131
  if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4132
    {
4133
      input_line_pointer += 7;
4134
      s_data1 ();
4135
      return;
4136
    }
4137
  if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4138
    {
4139
      input_line_pointer += 5;
4140
      /* We only support 2 segments -- text and data -- for now, so
4141
         things in the "bss segment" will have to go into data for now.
4142
         You can still allocate SEG_BSS stuff with .lcomm or .reserve.  */
4143
      subseg_set (data_section, 255);   /* FIXME-SOMEDAY.  */
4144
      return;
4145
    }
4146
  as_bad (_("Unknown segment type"));
4147
  demand_empty_rest_of_line ();
4148
}
4149
 
4150
static void
4151
s_data1 (void)
4152
{
4153
  subseg_set (data_section, 1);
4154
  demand_empty_rest_of_line ();
4155
}
4156
 
4157
static void
4158
s_proc (int ignore ATTRIBUTE_UNUSED)
4159
{
4160
  while (!is_end_of_line[(unsigned char) *input_line_pointer])
4161
    {
4162
      ++input_line_pointer;
4163
    }
4164
  ++input_line_pointer;
4165
}
4166
 
4167
/* This static variable is set by s_uacons to tell sparc_cons_align
4168
   that the expression does not need to be aligned.  */
4169
 
4170
static int sparc_no_align_cons = 0;
4171
 
4172
/* This static variable is set by sparc_cons to emit requested types
4173
   of relocations in cons_fix_new_sparc.  */
4174
 
4175
static const char *sparc_cons_special_reloc;
4176
 
4177
/* This handles the unaligned space allocation pseudo-ops, such as
4178
   .uaword.  .uaword is just like .word, but the value does not need
4179
   to be aligned.  */
4180
 
4181
static void
4182
s_uacons (int bytes)
4183
{
4184
  /* Tell sparc_cons_align not to align this value.  */
4185
  sparc_no_align_cons = 1;
4186
  cons (bytes);
4187
  sparc_no_align_cons = 0;
4188
}
4189
 
4190
/* This handles the native word allocation pseudo-op .nword.
4191
   For sparc_arch_size 32 it is equivalent to .word,  for
4192
   sparc_arch_size 64 it is equivalent to .xword.  */
4193
 
4194
static void
4195
s_ncons (int bytes ATTRIBUTE_UNUSED)
4196
{
4197
  cons (sparc_arch_size == 32 ? 4 : 8);
4198
}
4199
 
4200
#ifdef OBJ_ELF
4201
/* Handle the SPARC ELF .register pseudo-op.  This sets the binding of a
4202
   global register.
4203
   The syntax is:
4204
 
4205
   .register %g[2367],{#scratch|symbolname|#ignore}
4206
*/
4207
 
4208
static void
4209
s_register (int ignore ATTRIBUTE_UNUSED)
4210
{
4211
  char c;
4212
  int reg;
4213
  int flags;
4214
  const char *regname;
4215
 
4216
  if (input_line_pointer[0] != '%'
4217
      || input_line_pointer[1] != 'g'
4218
      || ((input_line_pointer[2] & ~1) != '2'
4219
          && (input_line_pointer[2] & ~1) != '6')
4220
      || input_line_pointer[3] != ',')
4221
    as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4222
  reg = input_line_pointer[2] - '0';
4223
  input_line_pointer += 4;
4224
 
4225
  if (*input_line_pointer == '#')
4226
    {
4227
      ++input_line_pointer;
4228
      regname = input_line_pointer;
4229
      c = get_symbol_end ();
4230
      if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4231
        as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4232
      if (regname[0] == 'i')
4233
        regname = NULL;
4234
      else
4235
        regname = "";
4236
    }
4237
  else
4238
    {
4239
      regname = input_line_pointer;
4240
      c = get_symbol_end ();
4241
    }
4242
  if (sparc_arch_size == 64)
4243
    {
4244
      if (globals[reg])
4245
        {
4246
          if ((regname && globals[reg] != (symbolS *) 1
4247
               && strcmp (S_GET_NAME (globals[reg]), regname))
4248
              || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
4249
            as_bad (_("redefinition of global register"));
4250
        }
4251
      else
4252
        {
4253
          if (regname == NULL)
4254
            globals[reg] = (symbolS *) 1;
4255
          else
4256
            {
4257
              if (*regname)
4258
                {
4259
                  if (symbol_find (regname))
4260
                    as_bad (_("Register symbol %s already defined."),
4261
                            regname);
4262
                }
4263
              globals[reg] = symbol_make (regname);
4264
              flags = symbol_get_bfdsym (globals[reg])->flags;
4265
              if (! *regname)
4266
                flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4267
              if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4268
                flags |= BSF_GLOBAL;
4269
              symbol_get_bfdsym (globals[reg])->flags = flags;
4270
              S_SET_VALUE (globals[reg], (valueT) reg);
4271
              S_SET_ALIGN (globals[reg], reg);
4272
              S_SET_SIZE (globals[reg], 0);
4273
              /* Although we actually want undefined_section here,
4274
                 we have to use absolute_section, because otherwise
4275
                 generic as code will make it a COM section.
4276
                 We fix this up in sparc_adjust_symtab.  */
4277
              S_SET_SEGMENT (globals[reg], absolute_section);
4278
              S_SET_OTHER (globals[reg], 0);
4279
              elf_symbol (symbol_get_bfdsym (globals[reg]))
4280
                ->internal_elf_sym.st_info =
4281
                  ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4282
              elf_symbol (symbol_get_bfdsym (globals[reg]))
4283
                ->internal_elf_sym.st_shndx = SHN_UNDEF;
4284
            }
4285
        }
4286
    }
4287
 
4288
  *input_line_pointer = c;
4289
 
4290
  demand_empty_rest_of_line ();
4291
}
4292
 
4293
/* Adjust the symbol table.  We set undefined sections for STT_REGISTER
4294
   symbols which need it.  */
4295
 
4296
void
4297
sparc_adjust_symtab (void)
4298
{
4299
  symbolS *sym;
4300
 
4301
  for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4302
    {
4303
      if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4304
                       ->internal_elf_sym.st_info) != STT_REGISTER)
4305
        continue;
4306
 
4307
      if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4308
                       ->internal_elf_sym.st_shndx != SHN_UNDEF))
4309
        continue;
4310
 
4311
      S_SET_SEGMENT (sym, undefined_section);
4312
    }
4313
}
4314
#endif
4315
 
4316
/* If the --enforce-aligned-data option is used, we require .word,
4317
   et. al., to be aligned correctly.  We do it by setting up an
4318
   rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4319
   no unexpected alignment was introduced.
4320
 
4321
   The SunOS and Solaris native assemblers enforce aligned data by
4322
   default.  We don't want to do that, because gcc can deliberately
4323
   generate misaligned data if the packed attribute is used.  Instead,
4324
   we permit misaligned data by default, and permit the user to set an
4325
   option to check for it.  */
4326
 
4327
void
4328
sparc_cons_align (int nbytes)
4329
{
4330
  int nalign;
4331
 
4332
  /* Only do this if we are enforcing aligned data.  */
4333
  if (! enforce_aligned_data)
4334
    return;
4335
 
4336
  /* Don't align if this is an unaligned pseudo-op.  */
4337
  if (sparc_no_align_cons)
4338
    return;
4339
 
4340
  nalign = mylog2 (nbytes);
4341
  if (nalign == 0)
4342
    return;
4343
 
4344
  gas_assert (nalign > 0);
4345
 
4346
  if (now_seg == absolute_section)
4347
    {
4348
      if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4349
        as_bad (_("misaligned data"));
4350
      return;
4351
    }
4352
 
4353
  frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4354
            (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4355
 
4356
  record_alignment (now_seg, nalign);
4357
}
4358
 
4359
/* This is called from HANDLE_ALIGN in tc-sparc.h.  */
4360
 
4361
void
4362
sparc_handle_align (fragS *fragp)
4363
{
4364
  int count, fix;
4365
  char *p;
4366
 
4367
  count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4368
 
4369
  switch (fragp->fr_type)
4370
    {
4371
    case rs_align_test:
4372
      if (count != 0)
4373
        as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4374
      break;
4375
 
4376
    case rs_align_code:
4377
      p = fragp->fr_literal + fragp->fr_fix;
4378
      fix = 0;
4379
 
4380
      if (count & 3)
4381
        {
4382
          fix = count & 3;
4383
          memset (p, 0, fix);
4384
          p += fix;
4385
          count -= fix;
4386
        }
4387
 
4388
      if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4389
        {
4390
          unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f  */
4391
          if (INSN_BIG_ENDIAN)
4392
            number_to_chars_bigendian (p, wval, 4);
4393
          else
4394
            number_to_chars_littleendian (p, wval, 4);
4395
          p += 4;
4396
          count -= 4;
4397
          fix += 4;
4398
        }
4399
 
4400
      if (INSN_BIG_ENDIAN)
4401
        number_to_chars_bigendian (p, 0x01000000, 4);
4402
      else
4403
        number_to_chars_littleendian (p, 0x01000000, 4);
4404
 
4405
      fragp->fr_fix += fix;
4406
      fragp->fr_var = 4;
4407
      break;
4408
 
4409
    default:
4410
      break;
4411
    }
4412
}
4413
 
4414
#ifdef OBJ_ELF
4415
/* Some special processing for a Sparc ELF file.  */
4416
 
4417
void
4418
sparc_elf_final_processing (void)
4419
{
4420
  /* Set the Sparc ELF flag bits.  FIXME: There should probably be some
4421
     sort of BFD interface for this.  */
4422
  if (sparc_arch_size == 64)
4423
    {
4424
      switch (sparc_memory_model)
4425
        {
4426
        case MM_RMO:
4427
          elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4428
          break;
4429
        case MM_PSO:
4430
          elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4431
          break;
4432
        default:
4433
          break;
4434
        }
4435
    }
4436
  else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4437
    elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4438
  if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4439
    elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4440
  else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4441
    elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4442
}
4443
 
4444
void
4445
sparc_cons (expressionS *exp, int size)
4446
{
4447
  char *save;
4448
 
4449
  SKIP_WHITESPACE ();
4450
  sparc_cons_special_reloc = NULL;
4451
  save = input_line_pointer;
4452
  if (input_line_pointer[0] == '%'
4453
      && input_line_pointer[1] == 'r'
4454
      && input_line_pointer[2] == '_')
4455
    {
4456
      if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4457
        {
4458
          input_line_pointer += 7;
4459
          sparc_cons_special_reloc = "disp";
4460
        }
4461
      else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4462
        {
4463
          if (size != 4 && size != 8)
4464
            as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4465
          else
4466
            {
4467
              input_line_pointer += 6;
4468
              sparc_cons_special_reloc = "plt";
4469
            }
4470
        }
4471
      else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4472
        {
4473
          if (size != 4 && size != 8)
4474
            as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4475
          else
4476
            {
4477
              input_line_pointer += 13;
4478
              sparc_cons_special_reloc = "tls_dtpoff";
4479
            }
4480
        }
4481
      if (sparc_cons_special_reloc)
4482
        {
4483
          int bad = 0;
4484
 
4485
          switch (size)
4486
            {
4487
            case 1:
4488
              if (*input_line_pointer != '8')
4489
                bad = 1;
4490
              input_line_pointer--;
4491
              break;
4492
            case 2:
4493
              if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4494
                bad = 1;
4495
              break;
4496
            case 4:
4497
              if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4498
                bad = 1;
4499
              break;
4500
            case 8:
4501
              if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4502
                bad = 1;
4503
              break;
4504
            default:
4505
              bad = 1;
4506
              break;
4507
            }
4508
 
4509
          if (bad)
4510
            {
4511
              as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4512
                      sparc_cons_special_reloc, size * 8, size);
4513
            }
4514
          else
4515
            {
4516
              input_line_pointer += 2;
4517
              if (*input_line_pointer != '(')
4518
                {
4519
                  as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4520
                          sparc_cons_special_reloc, size * 8);
4521
                  bad = 1;
4522
                }
4523
            }
4524
 
4525
          if (bad)
4526
            {
4527
              input_line_pointer = save;
4528
              sparc_cons_special_reloc = NULL;
4529
            }
4530
          else
4531
            {
4532
              int c;
4533
              char *end = ++input_line_pointer;
4534
              int npar = 0;
4535
 
4536
              while (! is_end_of_line[(c = *end)])
4537
                {
4538
                  if (c == '(')
4539
                    npar++;
4540
                  else if (c == ')')
4541
                    {
4542
                      if (!npar)
4543
                        break;
4544
                      npar--;
4545
                    }
4546
                  end++;
4547
                }
4548
 
4549
              if (c != ')')
4550
                as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4551
                        sparc_cons_special_reloc, size * 8);
4552
              else
4553
                {
4554
                  *end = '\0';
4555
                  expression (exp);
4556
                  *end = c;
4557
                  if (input_line_pointer != end)
4558
                    {
4559
                      as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4560
                              sparc_cons_special_reloc, size * 8);
4561
                    }
4562
                  else
4563
                    {
4564
                      input_line_pointer++;
4565
                      SKIP_WHITESPACE ();
4566
                      c = *input_line_pointer;
4567
                      if (! is_end_of_line[c] && c != ',')
4568
                        as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4569
                                sparc_cons_special_reloc, size * 8);
4570
                    }
4571
                }
4572
            }
4573
        }
4574
    }
4575
  if (sparc_cons_special_reloc == NULL)
4576
    expression (exp);
4577
}
4578
 
4579
#endif
4580
 
4581
/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4582
   reloc for a cons.  We could use the definition there, except that
4583
   we want to handle little endian relocs specially.  */
4584
 
4585
void
4586
cons_fix_new_sparc (fragS *frag,
4587
                    int where,
4588
                    unsigned int nbytes,
4589
                    expressionS *exp)
4590
{
4591
  bfd_reloc_code_real_type r;
4592
 
4593
  r = (nbytes == 1 ? BFD_RELOC_8 :
4594
       (nbytes == 2 ? BFD_RELOC_16 :
4595
        (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4596
 
4597
  if (target_little_endian_data
4598
      && nbytes == 4
4599
      && now_seg->flags & SEC_ALLOC)
4600
    r = BFD_RELOC_SPARC_REV32;
4601
 
4602
  if (sparc_cons_special_reloc)
4603
    {
4604
      if (*sparc_cons_special_reloc == 'd')
4605
        switch (nbytes)
4606
          {
4607
          case 1: r = BFD_RELOC_8_PCREL; break;
4608
          case 2: r = BFD_RELOC_16_PCREL; break;
4609
          case 4: r = BFD_RELOC_32_PCREL; break;
4610
          case 8: r = BFD_RELOC_64_PCREL; break;
4611
          default: abort ();
4612
          }
4613
      else if (*sparc_cons_special_reloc == 'p')
4614
        switch (nbytes)
4615
          {
4616
          case 4: r = BFD_RELOC_SPARC_PLT32; break;
4617
          case 8: r = BFD_RELOC_SPARC_PLT64; break;
4618
          }
4619
      else
4620
        switch (nbytes)
4621
          {
4622
          case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4623
          case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4624
          }
4625
    }
4626
  else if (sparc_no_align_cons)
4627
    {
4628
      switch (nbytes)
4629
        {
4630
        case 2: r = BFD_RELOC_SPARC_UA16; break;
4631
        case 4: r = BFD_RELOC_SPARC_UA32; break;
4632
        case 8: r = BFD_RELOC_SPARC_UA64; break;
4633
        default: abort ();
4634
        }
4635
   }
4636
 
4637
  fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4638
  sparc_cons_special_reloc = NULL;
4639
}
4640
 
4641
void
4642
sparc_cfi_frame_initial_instructions (void)
4643
{
4644
  cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
4645
}
4646
 
4647
int
4648
sparc_regname_to_dw2regnum (char *regname)
4649
{
4650
  char *p, *q;
4651
 
4652
  if (!regname[0])
4653
    return -1;
4654
 
4655
  q = "goli";
4656
  p = strchr (q, regname[0]);
4657
  if (p)
4658
    {
4659
      if (regname[1] < '0' || regname[1] > '8' || regname[2])
4660
        return -1;
4661
      return (p - q) * 8 + regname[1] - '0';
4662
    }
4663
  if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
4664
    return 14;
4665
  if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
4666
    return 30;
4667
  if (regname[0] == 'f' || regname[0] == 'r')
4668
    {
4669
      unsigned int regnum;
4670
 
4671
      regnum = strtoul (regname + 1, &q, 10);
4672
      if (p == q || *q)
4673
        return -1;
4674
      if (regnum >= ((regname[0] == 'f'
4675
                      && SPARC_OPCODE_ARCH_V9_P (max_architecture))
4676
                     ? 64 : 32))
4677
        return -1;
4678
      if (regname[0] == 'f')
4679
        {
4680
          regnum += 32;
4681
          if (regnum >= 64 && (regnum & 1))
4682
            return -1;
4683
        }
4684
      return regnum;
4685
    }
4686
  return -1;
4687
}
4688
 
4689
void
4690
sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
4691
{
4692
  sparc_cons_special_reloc = "disp";
4693
  sparc_no_align_cons = 1;
4694
  emit_expr (exp, nbytes);
4695
  sparc_no_align_cons = 0;
4696
  sparc_cons_special_reloc = NULL;
4697
}

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