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@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
2
@c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
3
@c Free Software Foundation, Inc.
4
@c This is part of the GAS manual.
5
@c For copying conditions, see the file as.texinfo.
6
@ifset GENERIC
7
@page
8
@node MIPS-Dependent
9
@chapter MIPS Dependent Features
10
@end ifset
11
@ifclear GENERIC
12
@node Machine Dependencies
13
@chapter MIPS Dependent Features
14
@end ifclear
15
 
16
@cindex MIPS processor
17
@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
18
different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
19
and MIPS64.  For information about the @sc{mips} instruction set, see
20
@cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
21
For an overview of @sc{mips} assembly conventions, see ``Appendix D:
22
Assembly Language Programming'' in the same work.
23
 
24
@menu
25
* MIPS Opts::           Assembler options
26
* MIPS Object::         ECOFF object code
27
* MIPS Stabs::          Directives for debugging information
28
* MIPS ISA::            Directives to override the ISA level
29
* MIPS symbol sizes::   Directives to override the size of symbols
30
* MIPS autoextend::     Directives for extending MIPS 16 bit instructions
31
* MIPS insn::           Directive to mark data as an instruction
32
* MIPS option stack::   Directives to save and restore options
33
* MIPS ASE instruction generation overrides:: Directives to control
34
                        generation of MIPS ASE instructions
35
* MIPS floating-point:: Directives to override floating-point options
36
* MIPS Syntax::         MIPS specific syntactical considerations
37
@end menu
38
 
39
@node MIPS Opts
40
@section Assembler options
41
 
42
The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
43
special options:
44
 
45
@table @code
46
@cindex @code{-G} option (MIPS)
47
@item -G @var{num}
48
This option sets the largest size of an object that can be referenced
49
implicitly with the @code{gp} register.  It is only accepted for targets
50
that use @sc{ecoff} format.  The default value is 8.
51
 
52
@cindex @code{-EB} option (MIPS)
53
@cindex @code{-EL} option (MIPS)
54
@cindex MIPS big-endian output
55
@cindex MIPS little-endian output
56
@cindex big-endian output, MIPS
57
@cindex little-endian output, MIPS
58
@item -EB
59
@itemx -EL
60
Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
61
little-endian output at run time (unlike the other @sc{gnu} development
62
tools, which must be configured for one or the other).  Use @samp{-EB}
63
to select big-endian output, and @samp{-EL} for little-endian.
64
 
65
@item -KPIC
66
@cindex PIC selection, MIPS
67
@cindex @option{-KPIC} option, MIPS
68
Generate SVR4-style PIC.  This option tells the assembler to generate
69
SVR4-style position-independent macro expansions.  It also tells the
70
assembler to mark the output file as PIC.
71
 
72
@item -mvxworks-pic
73
@cindex @option{-mvxworks-pic} option, MIPS
74
Generate VxWorks PIC.  This option tells the assembler to generate
75
VxWorks-style position-independent macro expansions.
76
 
77
@cindex MIPS architecture options
78
@item -mips1
79
@itemx -mips2
80
@itemx -mips3
81
@itemx -mips4
82
@itemx -mips5xo
83
@itemx -mips32
84
@itemx -mips32r2
85
@itemx -mips64
86
@itemx -mips64r2
87
Generate code for a particular MIPS Instruction Set Architecture level.
88
@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
89
@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
90
@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
91
@sc{r10000} processors.  @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2},
92
@samp{-mips64}, and @samp{-mips64r2}
93
correspond to generic
94
@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},
95
and @sc{MIPS64 Release 2}
96
ISA processors, respectively.  You can also switch
97
instruction sets during the assembly; see @ref{MIPS ISA, Directives to
98
override the ISA level}.
99
 
100
@item -mgp32
101
@itemx -mfp32
102
Some macros have different expansions for 32-bit and 64-bit registers.
103
The register sizes are normally inferred from the ISA and ABI, but these
104
flags force a certain group of registers to be treated as 32 bits wide at
105
all times.  @samp{-mgp32} controls the size of general-purpose registers
106
and @samp{-mfp32} controls the size of floating-point registers.
107
 
108
The @code{.set gp=32} and @code{.set fp=32} directives allow the size
109
of registers to be changed for parts of an object. The default value is
110
restored by @code{.set gp=default} and @code{.set fp=default}.
111
 
112
On some MIPS variants there is a 32-bit mode flag; when this flag is
113
set, 64-bit instructions generate a trap.  Also, some 32-bit OSes only
114
save the 32-bit registers on a context switch, so it is essential never
115
to use the 64-bit registers.
116
 
117
@item -mgp64
118
@itemx -mfp64
119
Assume that 64-bit registers are available.  This is provided in the
120
interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
121
 
122
The @code{.set gp=64} and @code{.set fp=64} directives allow the size
123
of registers to be changed for parts of an object. The default value is
124
restored by @code{.set gp=default} and @code{.set fp=default}.
125
 
126
@item -mips16
127
@itemx -no-mips16
128
Generate code for the MIPS 16 processor.  This is equivalent to putting
129
@code{.set mips16} at the start of the assembly file.  @samp{-no-mips16}
130
turns off this option.
131
 
132 160 khays
@item -mmicromips
133
@itemx -mno-micromips
134
Generate code for the microMIPS processor.  This is equivalent to putting
135
@code{.set micromips} at the start of the assembly file.  @samp{-mno-micromips}
136
turns off this option.  This is equivalent to putting @code{.set nomicromips}
137
at the start of the assembly file.
138
 
139 147 khays
@item -msmartmips
140
@itemx -mno-smartmips
141
Enables the SmartMIPS extensions to the MIPS32 instruction set, which
142
provides a number of new instructions which target smartcard and
143
cryptographic applications.  This is equivalent to putting
144
@code{.set smartmips} at the start of the assembly file.
145
@samp{-mno-smartmips} turns off this option.
146
 
147
@item -mips3d
148
@itemx -no-mips3d
149
Generate code for the MIPS-3D Application Specific Extension.
150
This tells the assembler to accept MIPS-3D instructions.
151
@samp{-no-mips3d} turns off this option.
152
 
153
@item -mdmx
154
@itemx -no-mdmx
155
Generate code for the MDMX Application Specific Extension.
156
This tells the assembler to accept MDMX instructions.
157
@samp{-no-mdmx} turns off this option.
158
 
159
@item -mdsp
160
@itemx -mno-dsp
161
Generate code for the DSP Release 1 Application Specific Extension.
162
This tells the assembler to accept DSP Release 1 instructions.
163
@samp{-mno-dsp} turns off this option.
164
 
165
@item -mdspr2
166
@itemx -mno-dspr2
167
Generate code for the DSP Release 2 Application Specific Extension.
168
This option implies -mdsp.
169
This tells the assembler to accept DSP Release 2 instructions.
170
@samp{-mno-dspr2} turns off this option.
171
 
172
@item -mmt
173
@itemx -mno-mt
174
Generate code for the MT Application Specific Extension.
175
This tells the assembler to accept MT instructions.
176
@samp{-mno-mt} turns off this option.
177
 
178 160 khays
@item -mmcu
179
@itemx -mno-mcu
180
Generate code for the MCU Application Specific Extension.
181
This tells the assembler to accept MCU instructions.
182
@samp{-mno-mcu} turns off this option.
183
 
184 147 khays
@item -mfix7000
185
@itemx -mno-fix7000
186
Cause nops to be inserted if the read of the destination register
187
of an mfhi or mflo instruction occurs in the following two instructions.
188
 
189
@item -mfix-loongson2f-jump
190
@itemx -mno-fix-loongson2f-jump
191
Eliminate instruction fetch from outside 256M region to work around the
192
Loongson2F @samp{jump} instructions.  Without it, under extreme cases,
193
the kernel may crash.  The issue has been solved in latest processor
194
batches, but this fix has no side effect to them.
195
 
196
@item -mfix-loongson2f-nop
197
@itemx -mno-fix-loongson2f-nop
198
Replace nops by @code{or at,at,zero} to work around the Loongson2F
199
@samp{nop} errata.  Without it, under extreme cases, cpu might
200
deadlock.  The issue has been solved in latest loongson2f batches, but
201
this fix has no side effect to them.
202
 
203
@item -mfix-vr4120
204
@itemx -mno-fix-vr4120
205
Insert nops to work around certain VR4120 errata.  This option is
206
intended to be used on GCC-generated code: it is not designed to catch
207
all problems in hand-written assembler code.
208
 
209
@item -mfix-vr4130
210
@itemx -mno-fix-vr4130
211
Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
212
 
213
@item -mfix-24k
214
@itemx -no-mfix-24k
215
Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
216
 
217
@item -mfix-cn63xxp1
218
@itemx -mno-fix-cn63xxp1
219
Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
220
certain CN63XXP1 errata.
221
 
222
@item -m4010
223
@itemx -no-m4010
224
Generate code for the LSI @sc{r4010} chip.  This tells the assembler to
225
accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
226
etc.), and to not schedule @samp{nop} instructions around accesses to
227
the @samp{HI} and @samp{LO} registers.  @samp{-no-m4010} turns off this
228
option.
229
 
230
@item -m4650
231
@itemx -no-m4650
232
Generate code for the MIPS @sc{r4650} chip.  This tells the assembler to accept
233
the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
234
instructions around accesses to the @samp{HI} and @samp{LO} registers.
235
@samp{-no-m4650} turns off this option.
236
 
237
@itemx -m3900
238
@itemx -no-m3900
239
@itemx -m4100
240
@itemx -no-m4100
241
For each option @samp{-m@var{nnnn}}, generate code for the MIPS
242
@sc{r@var{nnnn}} chip.  This tells the assembler to accept instructions
243
specific to that chip, and to schedule for that chip's hazards.
244
 
245
@item -march=@var{cpu}
246
Generate code for a particular MIPS cpu.  It is exactly equivalent to
247
@samp{-m@var{cpu}}, except that there are more value of @var{cpu}
248
understood.  Valid @var{cpu} value are:
249
 
250
@quotation
251
2000,
252
3000,
253
3900,
254
4000,
255
4010,
256
4100,
257
4111,
258
vr4120,
259
vr4130,
260
vr4181,
261
4300,
262
4400,
263
4600,
264
4650,
265
5000,
266
rm5200,
267
rm5230,
268
rm5231,
269
rm5261,
270
rm5721,
271
vr5400,
272
vr5500,
273
6000,
274
rm7000,
275
8000,
276
rm9000,
277
10000,
278
12000,
279
14000,
280
16000,
281
4kc,
282
4km,
283
4kp,
284
4ksc,
285
4kec,
286
4kem,
287
4kep,
288
4ksd,
289
m4k,
290
m4kp,
291 160 khays
m14k,
292
m14kc,
293 147 khays
24kc,
294
24kf2_1,
295
24kf,
296
24kf1_1,
297
24kec,
298
24kef2_1,
299
24kef,
300
24kef1_1,
301
34kc,
302
34kf2_1,
303
34kf,
304
34kf1_1,
305
74kc,
306
74kf2_1,
307
74kf,
308
74kf1_1,
309
74kf3_2,
310
1004kc,
311
1004kf2_1,
312
1004kf,
313
1004kf1_1,
314
5kc,
315
5kf,
316
20kc,
317
25kf,
318
sb1,
319
sb1a,
320
loongson2e,
321
loongson2f,
322
loongson3a,
323
octeon,
324
xlr
325
@end quotation
326
 
327
For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
328
accepted as synonyms for @samp{@var{n}f1_1}.  These values are
329
deprecated.
330
 
331
@item -mtune=@var{cpu}
332
Schedule and tune for a particular MIPS cpu.  Valid @var{cpu} values are
333
identical to @samp{-march=@var{cpu}}.
334
 
335
@item -mabi=@var{abi}
336
Record which ABI the source code uses.  The recognized arguments
337
are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
338
 
339
@item -msym32
340
@itemx -mno-sym32
341
@cindex -msym32
342
@cindex -mno-sym32
343
Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
344
the beginning of the assembler input.  @xref{MIPS symbol sizes}.
345
 
346
@cindex @code{-nocpp} ignored (MIPS)
347
@item -nocpp
348
This option is ignored.  It is accepted for command-line compatibility with
349
other assemblers, which use it to turn off C style preprocessing.  With
350
@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
351
@sc{gnu} assembler itself never runs the C preprocessor.
352
 
353
@item -msoft-float
354
@itemx -mhard-float
355
Disable or enable floating-point instructions.  Note that by default
356
floating-point instructions are always allowed even with CPU targets
357
that don't have support for these instructions.
358
 
359
@item -msingle-float
360
@itemx -mdouble-float
361
Disable or enable double-precision floating-point operations.  Note
362
that by default double-precision floating-point operations are always
363
allowed even with CPU targets that don't have support for these
364
operations.
365
 
366
@item --construct-floats
367
@itemx --no-construct-floats
368
The @code{--no-construct-floats} option disables the construction of
369
double width floating point constants by loading the two halves of the
370
value into the two single width floating point registers that make up
371
the double width register.  This feature is useful if the processor
372
support the FR bit in its status  register, and this bit is known (by
373
the programmer) to be set.  This bit prevents the aliasing of the double
374
width register by the single width registers.
375
 
376
By default @code{--construct-floats} is selected, allowing construction
377
of these floating point constants.
378
 
379
@item --trap
380
@itemx --no-break
381
@c FIXME!  (1) reflect these options (next item too) in option summaries;
382
@c         (2) stop teasing, say _which_ instructions expanded _how_.
383
@code{@value{AS}} automatically macro expands certain division and
384
multiplication instructions to check for overflow and division by zero.  This
385
option causes @code{@value{AS}} to generate code to take a trap exception
386
rather than a break exception when an error is detected.  The trap instructions
387
are only supported at Instruction Set Architecture level 2 and higher.
388
 
389
@item --break
390
@itemx --no-trap
391
Generate code to take a break exception rather than a trap exception when an
392
error is detected.  This is the default.
393
 
394
@item -mpdr
395
@itemx -mno-pdr
396
Control generation of @code{.pdr} sections.  Off by default on IRIX, on
397
elsewhere.
398
 
399
@item -mshared
400
@itemx -mno-shared
401
When generating code using the Unix calling conventions (selected by
402
@samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
403
which can go into a shared library.  The @samp{-mno-shared} option
404
tells gas to generate code which uses the calling convention, but can
405
not go into a shared library.  The resulting code is slightly more
406
efficient.  This option only affects the handling of the
407
@samp{.cpload} and @samp{.cpsetup} pseudo-ops.
408
@end table
409
 
410
@node MIPS Object
411
@section MIPS ECOFF object code
412
 
413
@cindex ECOFF sections
414
@cindex MIPS ECOFF sections
415
Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
416
besides the usual @code{.text}, @code{.data} and @code{.bss}.  The
417
additional sections are @code{.rdata}, used for read-only data,
418
@code{.sdata}, used for small data, and @code{.sbss}, used for small
419
common objects.
420
 
421
@cindex small objects, MIPS ECOFF
422
@cindex @code{gp} register, MIPS
423
When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
424
register to form the address of a ``small object''.  Any object in the
425
@code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
426
For external objects, or for objects in the @code{.bss} section, you can use
427
the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
428
@code{$gp}; the default value is 8, meaning that a reference to any object
429
eight bytes or smaller uses @code{$gp}.  Passing @samp{-G 0} to
430
@code{@value{AS}} prevents it from using the @code{$gp} register on the basis
431
of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
432
or @code{sbss} in any case).  The size of an object in the @code{.bss} section
433
is set by the @code{.comm} or @code{.lcomm} directive that defines it.  The
434
size of an external object may be set with the @code{.extern} directive.  For
435
example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
436
in length, whie leaving @code{sym} otherwise undefined.
437
 
438
Using small @sc{ecoff} objects requires linker support, and assumes that the
439
@code{$gp} register is correctly initialized (normally done automatically by
440
the startup code).  @sc{mips} @sc{ecoff} assembly code must not modify the
441
@code{$gp} register.
442
 
443
@node MIPS Stabs
444
@section Directives for debugging information
445
 
446
@cindex MIPS debugging directives
447
@sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
448
generating debugging information which are not support by traditional @sc{mips}
449
assemblers.  These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
450
@code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
451
@code{.stabd}, @code{.stabn}, and @code{.stabs}.  The debugging information
452
generated by the three @code{.stab} directives can only be read by @sc{gdb},
453
not by traditional @sc{mips} debuggers (this enhancement is required to fully
454
support C++ debugging).  These directives are primarily used by compilers, not
455
assembly language programmers!
456
 
457
@node MIPS symbol sizes
458
@section Directives to override the size of symbols
459
 
460
@cindex @code{.set sym32}
461
@cindex @code{.set nosym32}
462
The n64 ABI allows symbols to have any 64-bit value.  Although this
463
provides a great deal of flexibility, it means that some macros have
464
much longer expansions than their 32-bit counterparts.  For example,
465
the non-PIC expansion of @samp{dla $4,sym} is usually:
466
 
467
@smallexample
468
lui     $4,%highest(sym)
469
lui     $1,%hi(sym)
470
daddiu  $4,$4,%higher(sym)
471
daddiu  $1,$1,%lo(sym)
472
dsll32  $4,$4,0
473
daddu   $4,$4,$1
474
@end smallexample
475
 
476
whereas the 32-bit expansion is simply:
477
 
478
@smallexample
479
lui     $4,%hi(sym)
480
daddiu  $4,$4,%lo(sym)
481
@end smallexample
482
 
483
n64 code is sometimes constructed in such a way that all symbolic
484
constants are known to have 32-bit values, and in such cases, it's
485
preferable to use the 32-bit expansion instead of the 64-bit
486
expansion.
487
 
488
You can use the @code{.set sym32} directive to tell the assembler
489
that, from this point on, all expressions of the form
490
@samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
491
have 32-bit values.  For example:
492
 
493
@smallexample
494
.set sym32
495
dla     $4,sym
496
lw      $4,sym+16
497
sw      $4,sym+0x8000($4)
498
@end smallexample
499
 
500
will cause the assembler to treat @samp{sym}, @code{sym+16} and
501
@code{sym+0x8000} as 32-bit values.  The handling of non-symbolic
502
addresses is not affected.
503
 
504
The directive @code{.set nosym32} ends a @code{.set sym32} block and
505
reverts to the normal behavior.  It is also possible to change the
506
symbol size using the command-line options @option{-msym32} and
507
@option{-mno-sym32}.
508
 
509
These options and directives are always accepted, but at present,
510
they have no effect for anything other than n64.
511
 
512
@node MIPS ISA
513
@section Directives to override the ISA level
514
 
515
@cindex MIPS ISA override
516
@kindex @code{.set mips@var{n}}
517
@sc{gnu} @code{@value{AS}} supports an additional directive to change
518
the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
519
mips@var{n}}.  @var{n} should be a number from 0 to 5, or 32, 32r2, 64
520
or 64r2.
521
The values other than 0 make the assembler accept instructions
522
for the corresponding @sc{isa} level, from that point on in the
523
assembly.  @code{.set mips@var{n}} affects not only which instructions
524
are permitted, but also how certain macros are expanded.  @code{.set
525
mips0} restores the @sc{isa} level to its original level: either the
526
level you selected with command line options, or the default for your
527
configuration.  You can use this feature to permit specific @sc{mips3}
528
instructions while assembling in 32 bit mode.  Use this directive with
529
care!
530
 
531
@cindex MIPS CPU override
532
@kindex @code{.set arch=@var{cpu}}
533
The @code{.set arch=@var{cpu}} directive provides even finer control.
534
It changes the effective CPU target and allows the assembler to use
535
instructions specific to a particular CPU.  All CPUs supported by the
536
@samp{-march} command line option are also selectable by this directive.
537
The original value is restored by @code{.set arch=default}.
538
 
539
The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
540
in which it will assemble instructions for the MIPS 16 processor.  Use
541
@code{.set nomips16} to return to normal 32 bit mode.
542
 
543
Traditional @sc{mips} assemblers do not support this directive.
544
 
545 160 khays
The directive @code{.set micromips} puts the assembler into microMIPS mode,
546
in which it will assemble instructions for the microMIPS processor.  Use
547
@code{.set nomicromips} to return to normal 32 bit mode.
548
 
549
Traditional @sc{mips} assemblers do not support this directive.
550
 
551 147 khays
@node MIPS autoextend
552
@section Directives for extending MIPS 16 bit instructions
553
 
554
@kindex @code{.set autoextend}
555
@kindex @code{.set noautoextend}
556
By default, MIPS 16 instructions are automatically extended to 32 bits
557
when necessary.  The directive @code{.set noautoextend} will turn this
558
off.  When @code{.set noautoextend} is in effect, any 32 bit instruction
559
must be explicitly extended with the @code{.e} modifier (e.g.,
560
@code{li.e $4,1000}).  The directive @code{.set autoextend} may be used
561
to once again automatically extend instructions when necessary.
562
 
563
This directive is only meaningful when in MIPS 16 mode.  Traditional
564
@sc{mips} assemblers do not support this directive.
565
 
566
@node MIPS insn
567
@section Directive to mark data as an instruction
568
 
569
@kindex @code{.insn}
570
The @code{.insn} directive tells @code{@value{AS}} that the following
571 160 khays
data is actually instructions.  This makes a difference in MIPS 16 and
572
microMIPS modes: when loading the address of a label which precedes
573
instructions, @code{@value{AS}} automatically adds 1 to the value, so
574
that jumping to the loaded address will do the right thing.
575 147 khays
 
576
@kindex @code{.global}
577
The @code{.global} and @code{.globl} directives supported by
578
@code{@value{AS}} will by default mark the symbol as pointing to a
579
region of data not code.  This means that, for example, any
580
instructions following such a symbol will not be disassembled by
581
@code{objdump} as it will regard them as data.  To change this
582
behaviour an optional section name can be placed after the symbol name
583
in the @code{.global} directive.  If this section exists and is known
584
to be a code section, then the symbol will be marked as poiting at
585
code not data.  Ie the syntax for the directive is:
586
 
587
  @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
588
 
589
Here is a short example:
590
 
591
@example
592
        .global foo .text, bar, baz .data
593
foo:
594
        nop
595
bar:
596
        .word 0x0
597
baz:
598
        .word 0x1
599
 
600
@end example
601
 
602
@node MIPS option stack
603
@section Directives to save and restore options
604
 
605
@cindex MIPS option stack
606
@kindex @code{.set push}
607
@kindex @code{.set pop}
608
The directives @code{.set push} and @code{.set pop} may be used to save
609
and restore the current settings for all the options which are
610
controlled by @code{.set}.  The @code{.set push} directive saves the
611
current settings on a stack.  The @code{.set pop} directive pops the
612
stack and restores the settings.
613
 
614
These directives can be useful inside an macro which must change an
615
option such as the ISA level or instruction reordering but does not want
616
to change the state of the code which invoked the macro.
617
 
618
Traditional @sc{mips} assemblers do not support these directives.
619
 
620
@node MIPS ASE instruction generation overrides
621
@section Directives to control generation of MIPS ASE instructions
622
 
623
@cindex MIPS MIPS-3D instruction generation override
624
@kindex @code{.set mips3d}
625
@kindex @code{.set nomips3d}
626
The directive @code{.set mips3d} makes the assembler accept instructions
627
from the MIPS-3D Application Specific Extension from that point on
628
in the assembly.  The @code{.set nomips3d} directive prevents MIPS-3D
629
instructions from being accepted.
630
 
631
@cindex SmartMIPS instruction generation override
632
@kindex @code{.set smartmips}
633
@kindex @code{.set nosmartmips}
634
The directive @code{.set smartmips} makes the assembler accept
635
instructions from the SmartMIPS Application Specific Extension to the
636
MIPS32 @sc{isa} from that point on in the assembly.  The
637
@code{.set nosmartmips} directive prevents SmartMIPS instructions from
638
being accepted.
639
 
640
@cindex MIPS MDMX instruction generation override
641
@kindex @code{.set mdmx}
642
@kindex @code{.set nomdmx}
643
The directive @code{.set mdmx} makes the assembler accept instructions
644
from the MDMX Application Specific Extension from that point on
645
in the assembly.  The @code{.set nomdmx} directive prevents MDMX
646
instructions from being accepted.
647
 
648
@cindex MIPS DSP Release 1 instruction generation override
649
@kindex @code{.set dsp}
650
@kindex @code{.set nodsp}
651
The directive @code{.set dsp} makes the assembler accept instructions
652
from the DSP Release 1 Application Specific Extension from that point
653
on in the assembly.  The @code{.set nodsp} directive prevents DSP
654
Release 1 instructions from being accepted.
655
 
656
@cindex MIPS DSP Release 2 instruction generation override
657
@kindex @code{.set dspr2}
658
@kindex @code{.set nodspr2}
659
The directive @code{.set dspr2} makes the assembler accept instructions
660
from the DSP Release 2 Application Specific Extension from that point
661
on in the assembly.  This dirctive implies @code{.set dsp}.  The
662
@code{.set nodspr2} directive prevents DSP Release 2 instructions from
663
being accepted.
664
 
665
@cindex MIPS MT instruction generation override
666
@kindex @code{.set mt}
667
@kindex @code{.set nomt}
668
The directive @code{.set mt} makes the assembler accept instructions
669
from the MT Application Specific Extension from that point on
670
in the assembly.  The @code{.set nomt} directive prevents MT
671
instructions from being accepted.
672
 
673 160 khays
@cindex MIPS MCU instruction generation override
674
@kindex @code{.set mcu}
675
@kindex @code{.set nomcu}
676
The directive @code{.set mcu} makes the assembler accept instructions
677
from the MCU Application Specific Extension from that point on
678
in the assembly.  The @code{.set nomcu} directive prevents MCU
679
instructions from being accepted.
680
 
681 147 khays
Traditional @sc{mips} assemblers do not support these directives.
682
 
683
@node MIPS floating-point
684
@section Directives to override floating-point options
685
 
686
@cindex Disable floating-point instructions
687
@kindex @code{.set softfloat}
688
@kindex @code{.set hardfloat}
689
The directives @code{.set softfloat} and @code{.set hardfloat} provide
690
finer control of disabling and enabling float-point instructions.
691
These directives always override the default (that hard-float
692
instructions are accepted) or the command-line options
693
(@samp{-msoft-float} and @samp{-mhard-float}).
694
 
695
@cindex Disable single-precision floating-point operations
696
@kindex @code{.set singlefloat}
697
@kindex @code{.set doublefloat}
698
The directives @code{.set singlefloat} and @code{.set doublefloat}
699
provide finer control of disabling and enabling double-precision
700
float-point operations.  These directives always override the default
701
(that double-precision operations are accepted) or the command-line
702
options (@samp{-msingle-float} and @samp{-mdouble-float}).
703
 
704
Traditional @sc{mips} assemblers do not support these directives.
705
 
706
@node MIPS Syntax
707
@section Syntactical considerations for the MIPS assembler
708
@menu
709
* MIPS-Chars::                Special Characters
710
@end menu
711
 
712
@node MIPS-Chars
713
@subsection Special Characters
714
 
715
@cindex line comment character, MIPS
716
@cindex MIPS line comment character
717
The presence of a @samp{#} on a line indicates the start of a comment
718
that extends to the end of the current line.
719
 
720
If a @samp{#} appears as the first character of a line, the whole line
721
is treated as a comment, but in this case the line can also be a
722
logical line number directive (@pxref{Comments}) or a
723
preprocessor control command (@pxref{Preprocessing}).
724
 
725
@cindex line separator, MIPS
726
@cindex statement separator, MIPS
727
@cindex MIPS line separator
728
The @samp{;} character can be used to separate statements on the same
729
line.

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