OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [include/] [gdb/] [sim-cr16.h] - Blame information for rev 24

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 17 khays
/* This file defines the interface between the cr16 simulator and gdb.
2
 
3
   Copyright 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
4
 
5
   This file is part of GDB.
6
 
7
   This program is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3 of the License, or
10
   (at your option) any later version.
11
 
12
   This program is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
   GNU General Public License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with this program; if not, see <http://www.gnu.org/licenses/>.  */
19
 
20
#if !defined (SIM_CR16_H)
21
#define SIM_CR16_H
22
 
23
#ifdef __cplusplus
24
extern "C" { // }
25
#endif
26
 
27
enum
28
  {
29
    SIM_CR16_MEMORY_UNIFIED = 0x00000000,
30
    SIM_CR16_MEMORY_INSN    = 0x10000000,
31
    SIM_CR16_MEMORY_DATA    = 0x10000000,
32
    SIM_CR16_MEMORY_DMAP    = 0x10000000,
33
    SIM_CR16_MEMORY_IMAP    = 0x10000000
34
  };
35
 
36
extern unsigned long sim_cr16_translate_dmap_addr
37
  (unsigned long offset,
38
   int nr_bytes,
39
   unsigned long *phys,
40
   void *regcache,
41
   unsigned long (*dmap_register) (void *regcache, int reg_nr));
42
 
43
extern unsigned long sim_cr16_translate_imap_addr
44
  (unsigned long offset,
45
   int nr_bytes,
46
   unsigned long *phys,
47
   void *regcache,
48
   unsigned long (*imap_register) (void *regcache, int reg_nr));
49
 
50
extern unsigned long sim_cr16_translate_addr
51
  (unsigned long vaddr,
52
   int nr_bytes,
53
   unsigned long *phys,
54
   void *regcache,
55
   unsigned long (*dmap_register) (void *regcache, int reg_nr),
56
   unsigned long (*imap_register) (void *regcache, int reg_nr));
57
 
58
 
59
/* The simulator makes use of the following register information. */
60
 
61
enum sim_cr16_regs
62
{
63
  SIM_CR16_R0_REGNUM,
64
  SIM_CR16_R1_REGNUM,
65
  SIM_CR16_R2_REGNUM,
66
  SIM_CR16_R3_REGNUM,
67
  SIM_CR16_R4_REGNUM,
68
  SIM_CR16_R5_REGNUM,
69
  SIM_CR16_R6_REGNUM,
70
  SIM_CR16_R7_REGNUM,
71
  SIM_CR16_R8_REGNUM,
72
  SIM_CR16_R9_REGNUM,
73
  SIM_CR16_R10_REGNUM,
74
  SIM_CR16_R11_REGNUM,
75
  SIM_CR16_R12_REGNUM,
76
  SIM_CR16_R13_REGNUM,
77
  SIM_CR16_R14_REGNUM,
78
  SIM_CR16_R15_REGNUM,
79
 
80
  SIM_CR16_PC_REGNUM,
81
  SIM_CR16_ISP_REGNUM,
82
  SIM_CR16_USP_REGNUM,
83
  SIM_CR16_INTBASE_REGNUM,
84
  SIM_CR16_PSR_REGNUM,
85
  SIM_CR16_CFG_REGNUM,
86
  SIM_CR16_DBS_REGNUM,
87
  SIM_CR16_DCR_REGNUM,
88
  SIM_CR16_DSR_REGNUM,
89
  SIM_CR16_CAR0_REGNUM,
90
  SIM_CR16_CAR1_REGNUM
91
};
92
 
93
enum
94
{
95
  SIM_CR16_NR_R_REGS = 16,
96
  SIM_CR16_NR_A_REGS = 2,
97
  SIM_CR16_NR_IMAP_REGS = 2,
98
  SIM_CR16_NR_DMAP_REGS = 4,
99
  SIM_CR16_NR_CR_REGS = 11
100
};
101
 
102
#ifdef __cplusplus
103
}
104
#endif
105
 
106
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.