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Line No. Rev Author Line
1 161 khays 
2011-08-09  Chao-ying Fu
2 
            Maciej W. Rozycki
3 
 
4 
        * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
5 
        (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
6 
        (INSN_ASE_MASK): Add the MCU bit.
7 
        (INSN_MCU): New macro.
8 
        (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
9 
        (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
10 
 
11 
2011-08-09  Maciej W. Rozycki
12 
 
13 
        * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
14 
        (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
15 
        (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
16 
        (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
17 
        (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
18 
        (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
19 
        (INSN2_READ_GPR_MMN): Likewise.
20 
        (INSN2_READ_FPR_D): Change the bit used.
21 
        (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
22 
        (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
23 
        (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
24 
        (INSN2_COND_BRANCH): Likewise.
25 
        (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
26 
        (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
27 
        (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
28 
        (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
29 
        (INSN2_MOD_GPR_MN): Likewise.
30 
 
31 
2011-08-05  David S. Miller
32 
 
33 
        * sparc.h: Document new format codes '4', '5', and '('.
34 
        (OPF_LOW4, RS3): New macros.
35 
 
36 
2011-08-03  Maciej W. Rozycki
37 
 
38 
        * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
39 
        order of flags documented.
40 
 
41 
2011-07-29  Maciej W. Rozycki
42 
 
43 
        * mips.h: Clarify the description of microMIPS instruction
44 
        manipulation macros.
45 
        (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
46 
 
47 
2011-07-24  Chao-ying Fu
48 
            Maciej W. Rozycki
49 
 
50 
        * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
51 
        (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
52 
        (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
53 
        (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
54 
        (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
55 
        (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
56 
        (OP_MASK_RS3, OP_SH_RS3): Likewise.
57 
        (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
58 
        (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
59 
        (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
60 
        (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
61 
        (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
62 
        (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
63 
        (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
64 
        (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
65 
        (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
66 
        (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
67 
        (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
68 
        (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
69 
        (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
70 
        (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
71 
        (INSN_WRITE_GPR_S): New macro.
72 
        (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
73 
        (INSN2_READ_FPR_D): Likewise.
74 
        (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
75 
        (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
76 
        (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
77 
        (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
78 
        (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
79 
        (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
80 
        (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
81 
        (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
82 
        (CPU_MICROMIPS): New macro.
83 
        (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
84 
        (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
85 
        (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
86 
        (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
87 
        (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
88 
        (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
89 
        (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
90 
        (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
91 
        (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
92 
        (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
93 
        (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
94 
        (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
95 
        (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
96 
        (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
97 
        (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
98 
        (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
99 
        (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
100 
        (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
101 
        (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
102 
        (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
103 
        (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
104 
        (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
105 
        (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
106 
        (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
107 
        (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
108 
        (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
109 
        (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
110 
        (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
111 
        (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
112 
        (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
113 
        (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
114 
        (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
115 
        (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
116 
        (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
117 
        (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
118 
        (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
119 
        (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
120 
        (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
121 
        (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
122 
        (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
123 
        (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
124 
        (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
125 
        (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
126 
        (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
127 
        (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
128 
        (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
129 
        (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
130 
        (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
131 
        (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
132 
        (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
133 
        (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
134 
        (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
135 
        (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
136 
        (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
137 
        (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
138 
        (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
139 
        (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
140 
        (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
141 
        (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
142 
        (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
143 
        (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
144 
        (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
145 
        (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
146 
        (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
147 
        (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
148 
        (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
149 
        (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
150 
        (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
151 
        (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
152 
        (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
153 
        (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
154 
        (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
155 
        (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
156 
        (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
157 
        (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
158 
        (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
159 
        (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
160 
        (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
161 
        (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
162 
        (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
163 
        (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
164 
        (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
165 
        (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
166 
        (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
167 
        (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
168 
        (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
169 
        (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
170 
        (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
171 
        (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
172 
        (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
173 
        (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
174 
        (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
175 
        (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
176 
        (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
177 
        (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
178 
        (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
179 
        (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
180 
        (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
181 
        (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
182 
        (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
183 
        (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
184 
        (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
185 
        (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
186 
        (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
187 
        (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
188 
        (micromips_opcodes): New declaration.
189 
        (bfd_micromips_num_opcodes): Likewise.
190 
 
191 
2011-07-24  Maciej W. Rozycki
192 
 
193 
        * mips.h (INSN_TRAP): Rename to...
194 
        (INSN_NO_DELAY_SLOT): ... this.
195 
        (INSN_SYNC): Remove macro.
196 
 
197 
2011-07-01  Eric B. Weddington
198 
 
199 
        * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
200 
        a duplicate of AVR_ISA_SPM.
201 
 
202 
2011-07-01  Nick Clifton
203 
 
204 
        * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
205 
 
206 
2011-06-18  Robin Getz
207 
 
208 
        * bfin.h (is_macmod_signed): New func
209 
 
210 
2011-06-18  Mike Frysinger
211 
 
212 
        * bfin.h (is_macmod_pmove): Add missing space before func args.
213 
        (is_macmod_hmove): Likewise.
214 
 
215 148 khays 
2011-06-13  Walter Lee
216 
 
217 
        * tilegx.h: New file.
218 
        * tilepro.h: New file.
219 
 
220 17 khays 
2011-05-31  Paul Brook
221 
 
222 148 khays 
        * arm.h (ARM_ARCH_V7R_IDIV): Define.
223 17 khays 
 
224 148 khays 
2011-05-24  Andreas Krebbel
225 
 
226 
        * s390.h: Replace S390_OPERAND_REG_EVEN with
227 
        S390_OPERAND_REG_PAIR.
228 
 
229 
2011-05-24  Andreas Krebbel
230 
 
231 
        * s390.h: Add S390_OPCODE_REG_EVEN flag.
232 
 
233 17 khays 
2011-04-18  Julian Brown
234 
 
235 
        * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
236 
 
237 
2011-04-11  Dan McDonald
238 
 
239 
        PR gas/12296
240 
        * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
241 
 
242 
2011-03-22  Eric B. Weddington
243 
 
244 
        * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
245 
        New instruction set flags.
246 
        (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
247 
 
248 
2011-02-28  Maciej W. Rozycki
249 
 
250 
        * mips.h (M_PREF_AB): New enum value.
251 
 
252 
2011-02-12  Mike Frysinger
253 
 
254 
        * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
255 
        M_IU): Define.
256 
        (is_macmod_pmove, is_macmod_hmove): New functions.
257 
 
258 
2011-02-11  Mike Frysinger
259 
 
260 
        * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
261 
 
262 
2011-02-04  Bernd Schmidt
263 
 
264 
        * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
265 
        * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
266 
 
267 
2010-12-31  John David Anglin
268 
 
269 
        PR gas/11395
270 
        * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
271 
        "bb" entries.
272 
 
273 
2010-12-26  John David Anglin
274 
 
275 
        PR gas/11395
276 
        * hppa.h: Clear "d" bit in "add" and "sub" patterns.
277 
 
278 
2010-12-18  Richard Sandiford
279 
 
280 
        * mips.h: Update commentary after last commit.
281 
 
282 
2010-12-18  Mingjie Xing
283 
 
284 
        * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
285 
        (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
286 
        (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
287 
 
288 148 khays 
2010-11-25  Andreas Krebbel
289 
 
290 
        * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
291 
 
292 17 khays 
2010-11-23  Richard Sandiford
293 
 
294 
        * mips.h: Fix previous commit.
295 
 
296 
2010-11-23  Maciej W. Rozycki
297 
 
298 
        * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
299 
        (INSN_LOONGSON_3A): Clear bit 31.
300 
 
301 
2010-11-15  Matthew Gretton-Dann
302 
 
303 
        PR gas/12198
304 
        * arm.h (ARM_AEXT_V6M_ONLY): New define.
305 
        (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
306 
        (ARM_ARCH_V6M_ONLY): New define.
307 
 
308 
2010-11-11  Mingming Sun
309 
 
310 
        * mips.h (INSN_LOONGSON_3A): Defined.
311 
        (CPU_LOONGSON_3A): Defined.
312 
        (OPCODE_IS_MEMBER): Add LOONGSON_3A.
313 
 
314 
2010-10-09  Matt Rice
315 
 
316 
        * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
317 
        (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
318 
 
319 
2010-09-23  Matthew Gretton-Dann
320 
 
321 
        * arm.h (ARM_EXT_VIRT): New define.
322 
        (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
323 
        (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
324 
        Extensions.
325 
 
326 
2010-09-23  Matthew Gretton-Dann
327 
 
328 
        * arm.h (ARM_AEXT_ADIV): New define.
329 
        (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
330 
 
331 
2010-09-23  Matthew Gretton-Dann
332 
 
333 
        * arm.h (ARM_EXT_OS): New define.
334 
        (ARM_AEXT_V6SM): Likewise.
335 
        (ARM_ARCH_V6SM): Likewise.
336 
 
337 
2010-09-23  Matthew Gretton-Dann
338 
 
339 
        * arm.h (ARM_EXT_MP): Add.
340 
        (ARM_ARCH_V7A_MP): Likewise.
341 
 
342 
2010-09-22  Mike Frysinger
343 
 
344 
        * bfin.h: Declare pseudoChr structs/defines.
345 
 
346 
2010-09-21  Mike Frysinger
347 
 
348 
        * bfin.h: Strip trailing whitespace.
349 
 
350 
2010-07-29  DJ Delorie
351 
 
352 
        * rx.h (RX_Operand_Type): Add TwoReg.
353 
        (RX_Opcode_ID): Remove ediv and ediv2.
354 
 
355 
2010-07-27  DJ Delorie
356 
 
357 
        * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
358 
 
359 
2010-07-23  Naveen.H.S
360 
            Ina Pandit
361 
 
362 
        * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
363 
        PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
364 
        PROCESSOR_V850E2_ALL.
365 
        Remove PROCESSOR_V850EA support.
366 
        (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
367 
        V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
368 
        V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
369 
        V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
370 
        V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
371 
        V850_OPERAND_PERCENT.
372 
        Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
373 
        V850_NOT_R0.
374 
        Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
375 
        and V850E_PUSH_POP
376 
 
377 
2010-07-06  Maciej W. Rozycki
378 
 
379 
        * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
380 
        (MIPS16_INSN_BRANCH): Rename to...
381 
        (MIPS16_INSN_COND_BRANCH): ... this.
382 
 
383 
2010-07-03  Alan Modra
384 
 
385 
        * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
386 
        Renumber other PPC_OPCODE defines.
387 
 
388 
2010-07-03  Alan Modra
389 
 
390 
        * ppc.h (PPC_OPCODE_COMMON): Expand comment.
391 
 
392 
2010-06-29  Alan Modra
393 
 
394 
        * maxq.h: Delete file.
395 
 
396 
2010-06-14  Sebastian Andrzej Siewior
397 
 
398 
        * ppc.h (PPC_OPCODE_E500): Define.
399 
 
400 
2010-05-26  Catherine Moore
401 
 
402 
        * opcode/mips.h (INSN_MIPS16): Remove.
403 
 
404 
2010-04-21  Joseph Myers
405 
 
406 
        * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
407 
 
408 
2010-04-15  Nick Clifton
409 
 
410 
        * alpha.h: Update copyright notice to use GPLv3.
411 
        * arc.h: Likewise.
412 
        * arm.h: Likewise.
413 
        * avr.h: Likewise.
414 
        * bfin.h: Likewise.
415 
        * cgen.h: Likewise.
416 
        * convex.h: Likewise.
417 
        * cr16.h: Likewise.
418 
        * cris.h: Likewise.
419 
        * crx.h: Likewise.
420 
        * d10v.h: Likewise.
421 
        * d30v.h: Likewise.
422 
        * dlx.h: Likewise.
423 
        * h8300.h: Likewise.
424 
        * hppa.h: Likewise.
425 
        * i370.h: Likewise.
426 
        * i386.h: Likewise.
427 
        * i860.h: Likewise.
428 
        * i960.h: Likewise.
429 
        * ia64.h: Likewise.
430 
        * m68hc11.h: Likewise.
431 
        * m68k.h: Likewise.
432 
        * m88k.h: Likewise.
433 
        * maxq.h: Likewise.
434 
        * mips.h: Likewise.
435 
        * mmix.h: Likewise.
436 
        * mn10200.h: Likewise.
437 
        * mn10300.h: Likewise.
438 
        * msp430.h: Likewise.
439 
        * np1.h: Likewise.
440 
        * ns32k.h: Likewise.
441 
        * or32.h: Likewise.
442 
        * pdp11.h: Likewise.
443 
        * pj.h: Likewise.
444 
        * pn.h: Likewise.
445 
        * ppc.h: Likewise.
446 
        * pyr.h: Likewise.
447 
        * rx.h: Likewise.
448 
        * s390.h: Likewise.
449 
        * score-datadep.h: Likewise.
450 
        * score-inst.h: Likewise.
451 
        * sparc.h: Likewise.
452 
        * spu-insns.h: Likewise.
453 
        * spu.h: Likewise.
454 
        * tic30.h: Likewise.
455 
        * tic4x.h: Likewise.
456 
        * tic54x.h: Likewise.
457 
        * tic80.h: Likewise.
458 
        * v850.h: Likewise.
459 
        * vax.h: Likewise.
460 
 
461 
2010-03-25  Joseph Myers
462 
 
463 
        * tic6x-control-registers.h, tic6x-insn-formats.h,
464 
        tic6x-opcode-table.h, tic6x.h: New.
465 
 
466 
2010-02-25  Wu Zhangjin
467 
 
468 
        * mips.h: (LOONGSON2F_NOP_INSN): New macro.
469 
 
470 
2010-02-08  Philipp Tomsich
471 
 
472 
        * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
473 
 
474 
2010-01-14  H.J. Lu
475 
 
476 
        * ia64.h (ia64_find_opcode): Remove argument name.
477 
        (ia64_find_next_opcode): Likewise.
478 
        (ia64_dis_opcode): Likewise.
479 
        (ia64_free_opcode): Likewise.
480 
        (ia64_find_dependency): Likewise.
481 
 
482 
2009-11-22  Doug Evans
483 
 
484 
        * cgen.h: Include bfd_stdint.h.
485 
        (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
486 
 
487 
2009-11-18  Paul Brook
488 
 
489 
        * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
490 
 
491 
2009-11-17  Paul Brook
492 
        Daniel Jacobowitz
493 
 
494 
        * arm.h (ARM_EXT_V6_DSP): Define.
495 
        (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
496 
        (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
497 
 
498 
2009-11-04  DJ Delorie
499 
 
500 
        * rx.h (rx_decode_opcode) (mvtipl): Add.
501 
        (mvtcp, mvfcp, opecp): Remove.
502 
 
503 
2009-11-02  Paul Brook
504 
 
505 
        * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
506 
        FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
507 
        (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
508 
        FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
509 
        FPU_ARCH_NEON_VFP_V4): Define.
510 
 
511 
2009-10-23  Doug Evans
512 
 
513 
        * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
514 
        * cgen.h: Update.  Improve multi-inclusion macro name.
515 
 
516 
2009-10-02  Peter Bergner
517 
 
518 
        * ppc.h (PPC_OPCODE_476): Define.
519 
 
520 
2009-10-01  Peter Bergner
521 
 
522 
        * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
523 
 
524 
2009-09-29  DJ Delorie
525 
 
526 
        * rx.h: New file.
527 
 
528 
2009-09-22  Peter Bergner
529 
 
530 
        * ppc.h (ppc_cpu_t): Typedef to uint64_t.
531 
 
532 
2009-09-21  Ben Elliston
533 
 
534 
        * ppc.h (PPC_OPCODE_PPCA2): New.
535 
 
536 
2009-09-05  Martin Thuresson
537 
 
538 
        * ia64.h (struct ia64_operand): Renamed member class to op_class.
539 
 
540 
2009-08-29  Martin Thuresson
541 
 
542 
        * tic30.h (template): Rename type template to
543 
        insn_template. Updated code to use new name.
544 
        * tic54x.h (template): Rename type template to
545 
        insn_template.
546 
 
547 
2009-08-20  Nick Hudson
548 
 
549 
        * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
550 
 
551 
2009-06-11  Anthony Green
552 
 
553 
        * moxie.h (MOXIE_F3_PCREL): Define.
554 
        (moxie_form3_opc_info): Grow.
555 
 
556 
2009-06-06  Anthony Green
557 
 
558 
        * moxie.h (MOXIE_F1_M): Define.
559 
 
560 
2009-04-15  Anthony Green
561 
 
562 
        * moxie.h: Created.
563 
 
564 
2009-04-06  DJ Delorie
565 
 
566 
        * h8300.h: Add relaxation attributes to MOVA opcodes.
567 
 
568 
2009-03-10  Alan Modra
569 
 
570 
        * ppc.h (ppc_parse_cpu): Declare.
571 
 
572 
2009-03-02  Qinwei
573 
 
574 
        * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
575 
        and _IMM11 for mbitclr and mbitset.
576 
        * score-datadep.h: Update dependency information.
577 
 
578 
2009-02-26  Peter Bergner
579 
 
580 
        * ppc.h (PPC_OPCODE_POWER7): New.
581 
 
582 
2009-02-06  Doug Evans
583 
 
584 
        * i386.h: Add comment regarding sse* insns and prefixes.
585 
 
586 
2009-02-03  Sandip Matte
587 
 
588 
        * mips.h (INSN_XLR): Define.
589 
        (INSN_CHIP_MASK): Update.
590 
        (CPU_XLR): Define.
591 
        (OPCODE_IS_MEMBER): Update.
592 
        (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
593 
 
594 
2009-01-28  Doug Evans
595 
 
596 
        * opcode/i386.h: Add multiple inclusion protection.
597 
        (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
598 
        (EDI_REG_NUM): New macros.
599 
        (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
600 
        (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
601 
        (REX_PREFIX_P): New macro.
602 
 
603 
2009-01-09  Peter Bergner
604 
 
605 
        * ppc.h (struct powerpc_opcode): New field "deprecated".
606 
        (PPC_OPCODE_NOPOWER4): Delete.
607 
 
608 
2008-11-28  Joshua Kinard
609 
 
610 
        * mips.h: Define CPU_R14000, CPU_R16000.
611 
        (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
612 
 
613 
2008-11-18  Catherine Moore
614 
 
615 
        * arm.h (FPU_NEON_FP16): New.
616 
        (FPU_ARCH_NEON_FP16): New.
617 
 
618 
2008-11-06  Chao-ying Fu
619 
 
620 
        * mips.h: Doucument '1' for 5-bit sync type.
621 
 
622 
2008-08-28  H.J. Lu
623 
 
624 
        * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
625 
        IA64_RS_CR.
626 
 
627 
2008-08-01  Peter Bergner
628 
 
629 
        * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
630 
 
631 
2008-07-30  Michael J. Eager
632 
 
633 
        * ppc.h (PPC_OPCODE_405): Define.
634 
        (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
635 
 
636 
2008-06-13  Peter Bergner
637 
 
638 
        * ppc.h (ppc_cpu_t): New typedef.
639 
        (struct powerpc_opcode ): Use it.
640 
        (struct powerpc_operand ): Likewise.
641 
        (struct powerpc_macro ): Likewise.
642 
 
643 
2008-06-12  Adam Nemet
644 
 
645 
        * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
646 
        Update comment before MIPS16 field descriptors to mention MIPS16.
647 
        (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
648 
        BBIT.
649 
        (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
650 
        New bit masks and shift counts for cins and exts.
651 
 
652 
        * mips.h: Document new field descriptors +Q.
653 
        (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
654 
 
655 
2008-04-28  Adam Nemet
656 
 
657 
        * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
658 
        (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
659 
 
660 
2008-04-14  Edmar Wienskoski
661 
 
662 
        * ppc.h: (PPC_OPCODE_E500MC): New.
663 
 
664 
2008-04-03  H.J. Lu
665 
 
666 
        * i386.h (MAX_OPERANDS): Set to 5.
667 
        (MAX_MNEM_SIZE): Changed to 20.
668 
 
669 
2008-03-28  Eric B. Weddington
670 
 
671 
        * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
672 
 
673 
2008-03-09  Paul Brook
674 
 
675 
        * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
676 
 
677 
2008-03-04  Paul Brook
678 
 
679 
        * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
680 
        (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
681 
        (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
682 
 
683 
2008-02-27  Denis Vlasenko
684 
            Nick Clifton
685 
 
686 
        PR 3134
687 
        * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
688 
        with a 32-bit displacement but without the top bit of the 4th byte
689 
        set.
690 
 
691 
2008-02-18  M R Swami Reddy
692 
 
693 
        * cr16.h (cr16_num_optab): Declared.
694 
 
695 
2008-02-14  Hakan Ardo
696 
 
697 
        PR gas/2626
698 
        * avr.h (AVR_ISA_2xxe): Define.
699 
 
700 
2008-02-04  Adam Nemet
701 
 
702 
        * mips.h: Update copyright.
703 
        (INSN_CHIP_MASK): New macro.
704 
        (INSN_OCTEON): New macro.
705 
        (CPU_OCTEON): New macro.
706 
        (OPCODE_IS_MEMBER): Handle Octeon instructions.
707 
 
708 
2008-01-23  Eric B. Weddington
709 
 
710 
        * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
711 
 
712 
2008-01-03  Eric B. Weddington
713 
 
714 
        * avr.h (AVR_ISA_USB162): Add new opcode set.
715 
        (AVR_ISA_AVR3): Likewise.
716 
 
717 
2007-11-29  Mark Shinwell
718 
 
719 
        * mips.h (INSN_LOONGSON_2E): New.
720 
        (INSN_LOONGSON_2F): New.
721 
        (CPU_LOONGSON_2E): New.
722 
        (CPU_LOONGSON_2F): New.
723 
        (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
724 
 
725 
2007-11-29  Mark Shinwell
726 
 
727 
        * mips.h (INSN_ISA*): Redefine certain values as an
728 
        enumeration.  Update comments.
729 
        (mips_isa_table): New.
730 
        (ISA_MIPS*): Redefine to match enumeration.
731 
        (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
732 
        values.
733 
 
734 
2007-08-08  Ben Elliston
735 
 
736 
        * ppc.h (PPC_OPCODE_PPCPS): New.
737 
 
738 
2007-07-03  Nathan Sidwell
739 
 
740 
        * m68k.h: Document j K & E.
741 
 
742 
2007-06-29  M R Swami Reddy
743 
 
744 
        * cr16.h: New file for CR16 target.
745 
 
746 
2007-05-02  Alan Modra
747 
 
748 
        * ppc.h (PPC_OPERAND_PLUS1): Update comment.
749 
 
750 
2007-04-23  Nathan Sidwell
751 
 
752 
        * m68k.h (mcfisa_c): New.
753 
        (mcfusp, mcf_mask): Adjust.
754 
 
755 
2007-04-20  Alan Modra
756 
 
757 
        * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
758 
        (num_powerpc_operands): Declare.
759 
        (PPC_OPERAND_SIGNED et al): Redefine as hex.
760 
        (PPC_OPERAND_PLUS1): Define.
761 
 
762 
2007-03-21  H.J. Lu
763 
 
764 
        * i386.h (REX_MODE64): Renamed to ...
765 
        (REX_W): This.
766 
        (REX_EXTX): Renamed to ...
767 
        (REX_R): This.
768 
        (REX_EXTY): Renamed to ...
769 
        (REX_X): This.
770 
        (REX_EXTZ): Renamed to ...
771 
        (REX_B): This.
772 
 
773 
2007-03-15  H.J. Lu
774 
 
775 
        * i386.h: Add entries from config/tc-i386.h and move tables
776 
        to opcodes/i386-opc.h.
777 
 
778 
2007-03-13  H.J. Lu
779 
 
780 
        * i386.h (FloatDR): Removed.
781 
        (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
782 
 
783 
2007-03-01  Alan Modra
784 
 
785 
        * spu-insns.h: Add soma double-float insns.
786 
 
787 
2007-02-20  Thiemo Seufer
788 
            Chao-Ying Fu
789 
 
790 
        * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
791 
        (INSN_DSPR2): Add flag for DSP R2 instructions.
792 
        (M_BALIGN): New macro.
793 
 
794 
2007-02-14  Alan Modra
795 
 
796 
        * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
797 
        and Seg3ShortFrom with Shortform.
798 
 
799 
2007-02-11  H.J. Lu
800 
 
801 
        PR gas/4027
802 
        * i386.h (i386_optab): Put the real "test" before the pseudo
803 
        one.
804 
 
805 
2007-01-08  Kazu Hirata
806 
 
807 
        * m68k.h (m68010up): OR fido_a.
808 
 
809 
2006-12-25  Kazu Hirata
810 
 
811 
        * m68k.h (fido_a): New.
812 
 
813 
2006-12-24  Kazu Hirata
814 
 
815 
        * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
816 
        mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
817 
        values.
818 
 
819 
2006-11-08  H.J. Lu
820 
 
821 
        * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
822 
 
823 
2006-10-31  Mei Ligang
824 
 
825 
        * score-inst.h (enum score_insn_type): Add Insn_internal.
826 
 
827 
2006-10-25  Trevor Smigiel
828 
            Yukishige Shibata
829 
            Nobuhisa Fujinami
830 
            Takeaki Fukuoka
831 
            Alan Modra
832 
 
833 
        * spu-insns.h: New file.
834 
        * spu.h: New file.
835 
 
836 
2006-10-24  Andrew Pinski
837 
 
838 
        * ppc.h (PPC_OPCODE_CELL): Define.
839 
 
840 
2006-10-23  Dwarakanath Rajagopal
841 
 
842 
        * i386.h :  Modify opcode to support for the change in POPCNT opcode
843 
        in amdfam10 architecture.
844 
 
845 
2006-09-28  H.J. Lu
846 
 
847 
        * i386.h: Replace CpuMNI with CpuSSSE3.
848 
 
849 
2006-09-26  Mark Shinwell
850 
            Joseph Myers
851 
            Ian Lance Taylor
852 
            Ben Elliston
853 
 
854 
        * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
855 
 
856 
2006-09-17  Mei Ligang
857 
 
858 
        * score-datadep.h: New file.
859 
        * score-inst.h: New file.
860 
 
861 
2006-07-14  H.J. Lu
862 
 
863 
        * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
864 
        movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
865 
        movdq2q and movq2dq.
866 
 
867 
2006-07-10 Dwarakanath Rajagopal
868 
           Michael Meissner
869 
 
870 
        * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
871 
 
872 
2006-06-12  H.J. Lu
873 
 
874 
        * i386.h (i386_optab): Add "nop" with memory reference.
875 
 
876 
2006-06-12  H.J. Lu
877 
 
878 
        * i386.h (i386_optab): Update comment for 64bit NOP.
879 
 
880 
2006-06-06  Ben Elliston
881 
            Anton Blanchard
882 
 
883 
        * ppc.h (PPC_OPCODE_POWER6): Define.
884 
        Adjust whitespace.
885 
 
886 
2006-06-05  Thiemo Seufer
887 
 
888 
        * mips.h: Improve description of MT flags.
889 
 
890 
2006-05-25  Richard Sandiford
891 
 
892 
        * m68k.h (mcf_mask): Define.
893 
 
894 
2006-05-05  Thiemo Seufer
895 
            David Ung
896 
 
897 
        * mips.h (enum): Add macro M_CACHE_AB.
898 
 
899 
2006-05-04  Thiemo Seufer
900 
            Nigel Stephens
901 
            David Ung
902 
 
903 
        * mips.h: Add INSN_SMARTMIPS define.
904 
 
905 
2006-04-30  Thiemo Seufer
906 
            David Ung
907 
 
908 
        * mips.h: Defines udi bits and masks.  Add description of
909 
        characters which may appear in the args field of udi
910 
        instructions.
911 
 
912 
2006-04-26  Thiemo Seufer
913 
 
914 
        * mips.h: Improve comments describing the bitfield instruction
915 
        fields.
916 
 
917 
2006-04-26  Julian Brown
918 
 
919 
        * arm.h (FPU_VFP_EXT_V3): Define constant.
920 
        (FPU_NEON_EXT_V1): Likewise.
921 
        (FPU_VFP_HARD): Update.
922 
        (FPU_VFP_V3): Define macro.
923 
        (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
924 
 
925 
2006-04-07  Joerg Wunsch
926 
 
927 
        * avr.h (AVR_ISA_PWMx): New.
928 
 
929 
2006-03-28  Nathan Sidwell
930 
 
931 
        * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
932 
        cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
933 
        cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
934 
        cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
935 
        cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
936 
 
937 
2006-03-10  Paul Brook
938 
 
939 
        * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
940 
 
941 
2006-03-04  John David Anglin
942 
 
943 
        * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
944 
        first.  Correct mask of bb "B" opcode.
945 
 
946 
2006-02-27  H.J. Lu
947 
 
948 
        * i386.h (i386_optab): Support Intel Merom New Instructions.
949 
 
950 
2006-02-24  Paul Brook
951 
 
952 
        * arm.h: Add V7 feature bits.
953 
 
954 
2006-02-23  H.J. Lu
955 
 
956 
        * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
957 
 
958 
2006-01-31  Paul Brook
959 
        Richard Earnshaw
960 
 
961 
        * arm.h: Use ARM_CPU_FEATURE.
962 
        (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
963 
        (arm_feature_set): Change to a structure.
964 
        (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
965 
        ARM_FEATURE): New macros.
966 
 
967 
2005-12-07  Hans-Peter Nilsson
968 
 
969 
        * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
970 
        (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
971 
        (ADD_PC_INCR_OPCODE): Don't define.
972 
 
973 
2005-12-06  H.J. Lu
974 
 
975 
        PR gas/1874
976 
        * i386.h (i386_optab): Add 64bit support for monitor and mwait.
977 
 
978 
2005-11-14  David Ung
979 
 
980 
        * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
981 
        instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
982 
        save/restore encoding of the args field.
983 
 
984 
2005-10-28  Dave Brolley
985 
 
986 
        Contribute the following changes:
987 
        2005-02-16  Dave Brolley
988 
 
989 
        * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
990 
        cgen_isa_mask_* to cgen_bitset_*.
991 
        * cgen.h: Likewise.
992 
 
993 
        2003-10-21  Richard Sandiford
994 
 
995 
        * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
996 
        (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
997 
        (CGEN_CPU_TABLE): Make isas a ponter.
998 
 
999 
        2003-09-29  Dave Brolley
1000 
 
1001 
        * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1002 
        (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1003 
        (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1004 
 
1005 
        2002-12-13  Dave Brolley
1006 
 
1007 
        * cgen.h (symcat.h): #include it.
1008 
        (cgen-bitset.h): #include it.
1009 
        (CGEN_ATTR_VALUE_TYPE): Now a union.
1010 
        (CGEN_ATTR_VALUE): Reference macros generated in opcodes/-desc.h.
1011 
        (CGEN_ATTR_ENTRY): 'value' now unsigned.
1012 
        (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1013 
        * cgen-bitset.h: New file.
1014 
 
1015 
2005-09-30  Catherine Moore
1016 
 
1017 
        * bfin.h: New file.
1018 
 
1019 
2005-10-24  Jan Beulich
1020 
 
1021 
        * ia64.h (enum ia64_opnd): Move memory operand out of set of
1022 
        indirect operands.
1023 
 
1024 
2005-10-16  John David Anglin
1025 
 
1026 
        * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1027 
        Add FLAG_STRICT to pa10 ftest opcode.
1028 
 
1029 
2005-10-12  John David Anglin
1030 
 
1031 
        * hppa.h (pa_opcodes): Remove lha entries.
1032 
 
1033 
2005-10-08  John David Anglin
1034 
 
1035 
        * hppa.h (FLAG_STRICT): Revise comment.
1036 
        (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1037 
        before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1038 
        entries for "fdc".
1039 
 
1040 
2005-09-30  Catherine Moore
1041 
 
1042 
        * bfin.h: New file.
1043 
 
1044 
2005-09-24  John David Anglin
1045 
 
1046 
        * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1047 
 
1048 
2005-09-06  Chao-ying Fu
1049 
 
1050 
        * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1051 
        OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1052 
        define.
1053 
        Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1054 
        (INSN_ASE_MASK): Update to include INSN_MT.
1055 
        (INSN_MT): New define for MT ASE.
1056 
 
1057 
2005-08-25  Chao-ying Fu
1058 
 
1059 
        * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1060 
        OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1061 
        OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1062 
        OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1063 
        OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1064 
        Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1065 
        instructions.
1066 
        (INSN_DSP): New define for DSP ASE.
1067 
 
1068 
2005-08-18  Alan Modra
1069 
 
1070 
        * a29k.h: Delete.
1071 
 
1072 
2005-08-15  Daniel Jacobowitz
1073 
 
1074 
        * ppc.h (PPC_OPCODE_E300): Define.
1075 
 
1076 
2005-08-12 Martin Schwidefsky
1077 
 
1078 
        * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1079 
 
1080 
2005-07-28  John David Anglin
1081 
 
1082 
        PR gas/336
1083 
        * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1084 
        and pitlb.
1085 
 
1086 
2005-07-27  Jan Beulich
1087 
 
1088 
        * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1089 
        movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1090 
        Add movq-s as 64-bit variants of movd-s.
1091 
 
1092 
2005-07-18  John David Anglin
1093 
 
1094 
        * hppa.h: Fix punctuation in comment.
1095 
 
1096 
        * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1097 
        implicit space-register addressing.  Set space-register bits on opcodes
1098 
        using implicit space-register addressing.  Add various missing pa20
1099 
        long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1100 
        space-register addressing.  Use "fE" instead of "fe" in various
1101 
        fstw opcodes.
1102 
 
1103 
2005-07-18  Jan Beulich
1104 
 
1105 
        * i386.h (i386_optab): Operands of aam and aad are unsigned.
1106 
 
1107 
2007-07-15  H.J. Lu
1108 
 
1109 
        * i386.h (i386_optab): Support Intel VMX Instructions.
1110 
 
1111 
2005-07-10  John David Anglin
1112 
 
1113 
        * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1114 
 
1115 
2005-07-05  Jan Beulich
1116 
 
1117 
        * i386.h (i386_optab): Add new insns.
1118 
 
1119 
2005-07-01  Nick Clifton
1120 
 
1121 
        * sparc.h: Add typedefs to structure declarations.
1122 
 
1123 
2005-06-20  H.J. Lu
1124 
 
1125 
        PR 1013
1126 
        * i386.h (i386_optab): Update comments for 64bit addressing on
1127 
        mov. Allow 64bit addressing for mov and movq.
1128 
 
1129 
2005-06-11  John David Anglin
1130 
 
1131 
        * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1132 
        respectively, in various floating-point load and store patterns.
1133 
 
1134 
2005-05-23  John David Anglin
1135 
 
1136 
        * hppa.h (FLAG_STRICT): Correct comment.
1137 
        (pa_opcodes): Update load and store entries to allow both PA 1.X and
1138 
        PA 2.0 mneumonics when equivalent.  Entries with cache control
1139 
        completers now require PA 1.1.  Adjust whitespace.
1140 
 
1141 
2005-05-19  Anton Blanchard
1142 
 
1143 
        * ppc.h (PPC_OPCODE_POWER5): Define.
1144 
 
1145 
2005-05-10  Nick Clifton
1146 
 
1147 
        * Update the address and phone number of the FSF organization in
1148 
        the GPL notices in the following files:
1149 
        a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1150 
        crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1151 
        i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1152 
        mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1153 
        pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1154 
        tic54x.h, tic80.h, v850.h, vax.h
1155 
 
1156 
2005-05-09  Jan Beulich
1157 
 
1158 
        * i386.h (i386_optab): Add ht and hnt.
1159 
 
1160 
2005-04-18  Mark Kettenis
1161 
 
1162 
        * i386.h: Insert hyphens into selected VIA PadLock extensions.
1163 
        Add xcrypt-ctr.  Provide aliases without hyphens.
1164 
 
1165 
2005-04-13  H.J. Lu
1166 
 
1167 
        Moved from ../ChangeLog
1168 
 
1169 
        2005-04-12  Paul Brook
1170 
        * m88k.h: Rename psr macros to avoid conflicts.
1171 
 
1172 
        2005-03-12  Zack Weinberg
1173 
        * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1174 
        Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1175 
        and ARM_ARCH_V6ZKT2.
1176 
 
1177 
        2004-11-29  Tomer Levi
1178 
        * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1179 
        Remove redundant instruction types.
1180 
        (struct argument): X_op - new field.
1181 
        (struct cst4_entry): Remove.
1182 
        (no_op_insn): Declare.
1183 
 
1184 
        2004-11-05  Tomer Levi
1185 
        * crx.h (enum argtype): Rename types, remove unused types.
1186 
 
1187 
        2004-10-27  Tomer Levi
1188 
        * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1189 
        (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1190 
        (enum operand_type): Rearrange operands, edit comments.
1191 
        replace us with ui for unsigned immediate.
1192 
        replace d with disps/dispu/dispe for signed/unsigned/escaped
1193 
        displacements (respectively).
1194 
        replace rbase_ridx_scl2_dispu with rindex_disps for register index.
1195 
        (instruction type): Add NO_TYPE_INS.
1196 
        (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1197 
        (operand_entry): New field - 'flags'.
1198 
        (operand flags): New.
1199 
 
1200 
        2004-10-21  Tomer Levi
1201 
        * crx.h (operand_type): Remove redundant types i3, i4,
1202 
        i5, i8, i12.
1203 
        Add new unsigned immediate types us3, us4, us5, us16.
1204 
 
1205 
2005-04-12  Mark Kettenis
1206 
 
1207 
        * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1208 
        adjust them accordingly.
1209 
 
1210 
2005-04-01  Jan Beulich
1211 
 
1212 
        * i386.h (i386_optab): Add rdtscp.
1213 
 
1214 
2005-03-29  H.J. Lu
1215 
 
1216 
        * i386.h (i386_optab): Don't allow the `l' suffix for moving
1217 
        between memory and segment register. Allow movq for moving between
1218 
        general-purpose register and segment register.
1219 
 
1220 
2005-02-09  Jan Beulich
1221 
 
1222 
        PR gas/707
1223 
        * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1224 
        FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1225 
        fnstsw.
1226 
 
1227 
2006-02-07  Nathan Sidwell
1228 
 
1229 
        * m68k.h (m68008, m68ec030, m68882): Remove.
1230 
        (m68k_mask): New.
1231 
        (cpu_m68k, cpu_cf): New.
1232 
        (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1233 
        mcf5470, mcf5480): Rename to cpu_. Add m680x0 variants.
1234 
 
1235 
2005-01-25  Alexandre Oliva
1236 
 
1237 
        2004-11-10  Alexandre Oliva
1238 
        * cgen.h (enum cgen_parse_operand_type): Add
1239 
        CGEN_PARSE_OPERAND_SYMBOLIC.
1240 
 
1241 
2005-01-21  Fred Fish
1242 
 
1243 
        * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1244 
        Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1245 
        Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1246 
 
1247 
2005-01-19  Fred Fish
1248 
 
1249 
        * mips.h (struct mips_opcode): Add new pinfo2 member.
1250 
        (INSN_ALIAS): New define for opcode table entries that are
1251 
        specific instances of another entry, such as 'move' for an 'or'
1252 
        with a zero operand.
1253 
        (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1254 
        (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1255 
 
1256 
2004-12-09  Ian Lance Taylor
1257 
 
1258 
        * mips.h (CPU_RM9000): Define.
1259 
        (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1260 
 
1261 
2004-11-25 Jan Beulich
1262 
 
1263 
        * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1264 
        to/from test registers are illegal in 64-bit mode. Add missing
1265 
        NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1266 
        (previously one had to explicitly encode a rex64 prefix). Re-enable
1267 
        lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1268 
        support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1269 
 
1270 
2004-11-23 Jan Beulich
1271 
 
1272 
        * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1273 
        available only with SSE2. Change the MMX additions introduced by SSE
1274 
        and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1275 
        instructions by their now designated identifier (since combining i686
1276 
        and 3DNow! does not really imply 3DNow!A).
1277 
 
1278 
2004-11-19  Alan Modra
1279 
 
1280 
        * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1281 
        struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1282 
 
1283 
2004-11-08  Inderpreet Singh
1284 
            Vineet Sharma
1285 
 
1286 
        * maxq.h: New file: Disassembly information for the maxq port.
1287 
 
1288 
2004-11-05  H.J. Lu
1289 
 
1290 
        * i386.h (i386_optab): Put back "movzb".
1291 
 
1292 
2004-11-04  Hans-Peter Nilsson
1293 
 
1294 
        * cris.h (enum cris_insn_version_usage): Tweak formatting and
1295 
        comments.  Remove member cris_ver_sim.  Add members
1296 
        cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1297 
        cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1298 
        (struct cris_support_reg, struct cris_cond15): New types.
1299 
        (cris_conds15): Declare.
1300 
        (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1301 
        (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1302 
        (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1303 
        (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1304 
        (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1305 
        SIZE_FIELD_UNSIGNED.
1306 
 
1307 
2004-11-04 Jan Beulich
1308 
 
1309 
        * i386.h (sldx_Suf): Remove.
1310 
        (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1311 
        (q_FP): Define, implying no REX64.
1312 
        (x_FP, sl_FP): Imply FloatMF.
1313 
        (i386_optab): Split reg and mem forms of moving from segment registers
1314 
        so that the memory forms can ignore the 16-/32-bit operand size
1315 
        distinction. Adjust a few others for Intel mode. Remove *FP uses from
1316 
        all non-floating-point instructions. Unite 32- and 64-bit forms of
1317 
        movsx, movzx, and movd. Adjust floating point operations for the above
1318 
        changes to the *FP macros. Add DefaultSize to floating point control
1319 
        insns operating on larger memory ranges. Remove left over comments
1320 
        hinting at certain insns being Intel-syntax ones where the ones
1321 
        actually meant are already gone.
1322 
 
1323 
2004-10-07  Tomer Levi
1324 
 
1325 
        * crx.h: Add COPS_REG_INS - Coprocessor Special register
1326 
        instruction type.
1327 
 
1328 
2004-09-30  Paul Brook
1329 
 
1330 
        * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1331 
        (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1332 
 
1333 
2004-09-11  Theodore A. Roth
1334 
 
1335 
        * avr.h: Add support for
1336 
        atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1337 
 
1338 
2004-09-09  Segher Boessenkool
1339 
 
1340 
        * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1341 
 
1342 
2004-08-24  Dmitry Diky
1343 
 
1344 
        * msp430.h (msp430_opc): Add new instructions.
1345 
        (msp430_rcodes): Declare new instructions.
1346 
        (msp430_hcodes): Likewise..
1347 
 
1348 
2004-08-13  Nick Clifton
1349 
 
1350 
        PR/301
1351 
        * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1352 
        processors.
1353 
 
1354 
2004-08-30  Michal Ludvig
1355 
 
1356 
        * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1357 
 
1358 
2004-07-22  H.J. Lu
1359 
 
1360 
        * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1361 
 
1362 
2004-07-21  Jan Beulich
1363 
 
1364 
        * i386.h: Adjust instruction descriptions to better match the
1365 
        specification.
1366 
 
1367 
2004-07-16  Richard Earnshaw
1368 
 
1369 
        * arm.h: Remove all old content.  Replace with architecture defines
1370 
        from gas/config/tc-arm.c.
1371 
 
1372 
2004-07-09  Andreas Schwab
1373 
 
1374 
        * m68k.h: Fix comment.
1375 
 
1376 
2004-07-07  Tomer Levi
1377 
 
1378 
        * crx.h: New file.
1379 
 
1380 
2004-06-24  Alan Modra
1381 
 
1382 
        * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1383 
 
1384 
2004-05-24  Peter Barada
1385 
 
1386 
        * m68k.h: Add 'size' to m68k_opcode.
1387 
 
1388 
2004-05-05  Peter Barada
1389 
 
1390 
        * m68k.h: Switch from ColdFire chip name to core variant.
1391 
 
1392 
2004-04-22  Peter Barada
1393 
 
1394 
        * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1395 
        descriptions for new EMAC cases.
1396 
        Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1397 
        handle Motorola MAC syntax.
1398 
        Allow disassembly of ColdFire V4e object files.
1399 
 
1400 
2004-03-16  Alan Modra
1401 
 
1402 
        * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1403 
 
1404 
2004-03-12  Jakub Jelinek
1405 
 
1406 
        * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1407 
 
1408 
2004-03-12  Michal Ludvig
1409 
 
1410 
        * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1411 
 
1412 
2004-03-12  Michal Ludvig
1413 
 
1414 
        * i386.h (i386_optab): Added xstore/xcrypt insns.
1415 
 
1416 
2004-02-09  Anil Paranjpe
1417 
 
1418 
        * h8300.h (32bit ldc/stc): Add relaxing support.
1419 
 
1420 
2004-01-12  Anil Paranjpe
1421 
 
1422 
        * h8300.h (BITOP): Pass MEMRELAX flag.
1423 
 
1424 
2004-01-09  Anil Paranjpe
1425 
 
1426 
        * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1427 
        except for the H8S.
1428 
 
1429 
For older changes see ChangeLog-9103
1430 
 
1431 
Local Variables:
1432 
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1433 
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