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[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [include/] [opcode/] [ChangeLog] - Blame information for rev 163

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Line No. Rev Author Line
1 163 khays 
2011-11-01  DJ Delorie
2 
 
3 
        * rl78.h: New file.
4 
 
5 
2011-10-24  Maciej W. Rozycki
6 
 
7 
        * mips.h: Fix a typo in description.
8 
 
9 
2011-09-21  David S. Miller
10 
 
11 
        * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
12 
        (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
13 
        F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
14 
        F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
15 
 
16 161 khays 
2011-08-09  Chao-ying Fu
17 
            Maciej W. Rozycki
18 
 
19 
        * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
20 
        (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
21 
        (INSN_ASE_MASK): Add the MCU bit.
22 
        (INSN_MCU): New macro.
23 
        (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
24 
        (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
25 
 
26 
2011-08-09  Maciej W. Rozycki
27 
 
28 
        * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
29 
        (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
30 
        (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
31 
        (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
32 
        (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
33 
        (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
34 
        (INSN2_READ_GPR_MMN): Likewise.
35 
        (INSN2_READ_FPR_D): Change the bit used.
36 
        (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
37 
        (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
38 
        (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
39 
        (INSN2_COND_BRANCH): Likewise.
40 
        (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
41 
        (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
42 
        (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
43 
        (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
44 
        (INSN2_MOD_GPR_MN): Likewise.
45 
 
46 
2011-08-05  David S. Miller
47 
 
48 
        * sparc.h: Document new format codes '4', '5', and '('.
49 
        (OPF_LOW4, RS3): New macros.
50 
 
51 
2011-08-03  Maciej W. Rozycki
52 
 
53 
        * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
54 
        order of flags documented.
55 
 
56 
2011-07-29  Maciej W. Rozycki
57 
 
58 
        * mips.h: Clarify the description of microMIPS instruction
59 
        manipulation macros.
60 
        (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
61 
 
62 
2011-07-24  Chao-ying Fu
63 
            Maciej W. Rozycki
64 
 
65 
        * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
66 
        (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
67 
        (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
68 
        (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
69 
        (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
70 
        (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
71 
        (OP_MASK_RS3, OP_SH_RS3): Likewise.
72 
        (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
73 
        (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
74 
        (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
75 
        (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
76 
        (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
77 
        (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
78 
        (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
79 
        (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
80 
        (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
81 
        (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
82 
        (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
83 
        (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
84 
        (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
85 
        (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
86 
        (INSN_WRITE_GPR_S): New macro.
87 
        (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
88 
        (INSN2_READ_FPR_D): Likewise.
89 
        (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
90 
        (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
91 
        (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
92 
        (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
93 
        (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
94 
        (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
95 
        (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
96 
        (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
97 
        (CPU_MICROMIPS): New macro.
98 
        (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
99 
        (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
100 
        (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
101 
        (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
102 
        (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
103 
        (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
104 
        (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
105 
        (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
106 
        (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
107 
        (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
108 
        (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
109 
        (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
110 
        (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
111 
        (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
112 
        (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
113 
        (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
114 
        (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
115 
        (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
116 
        (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
117 
        (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
118 
        (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
119 
        (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
120 
        (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
121 
        (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
122 
        (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
123 
        (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
124 
        (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
125 
        (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
126 
        (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
127 
        (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
128 
        (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
129 
        (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
130 
        (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
131 
        (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
132 
        (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
133 
        (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
134 
        (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
135 
        (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
136 
        (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
137 
        (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
138 
        (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
139 
        (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
140 
        (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
141 
        (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
142 
        (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
143 
        (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
144 
        (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
145 
        (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
146 
        (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
147 
        (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
148 
        (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
149 
        (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
150 
        (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
151 
        (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
152 
        (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
153 
        (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
154 
        (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
155 
        (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
156 
        (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
157 
        (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
158 
        (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
159 
        (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
160 
        (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
161 
        (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
162 
        (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
163 
        (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
164 
        (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
165 
        (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
166 
        (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
167 
        (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
168 
        (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
169 
        (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
170 
        (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
171 
        (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
172 
        (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
173 
        (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
174 
        (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
175 
        (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
176 
        (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
177 
        (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
178 
        (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
179 
        (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
180 
        (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
181 
        (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
182 
        (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
183 
        (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
184 
        (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
185 
        (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
186 
        (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
187 
        (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
188 
        (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
189 
        (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
190 
        (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
191 
        (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
192 
        (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
193 
        (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
194 
        (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
195 
        (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
196 
        (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
197 
        (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
198 
        (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
199 
        (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
200 
        (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
201 
        (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
202 
        (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
203 
        (micromips_opcodes): New declaration.
204 
        (bfd_micromips_num_opcodes): Likewise.
205 
 
206 
2011-07-24  Maciej W. Rozycki
207 
 
208 
        * mips.h (INSN_TRAP): Rename to...
209 
        (INSN_NO_DELAY_SLOT): ... this.
210 
        (INSN_SYNC): Remove macro.
211 
 
212 
2011-07-01  Eric B. Weddington
213 
 
214 
        * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
215 
        a duplicate of AVR_ISA_SPM.
216 
 
217 
2011-07-01  Nick Clifton
218 
 
219 
        * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
220 
 
221 
2011-06-18  Robin Getz
222 
 
223 
        * bfin.h (is_macmod_signed): New func
224 
 
225 
2011-06-18  Mike Frysinger
226 
 
227 
        * bfin.h (is_macmod_pmove): Add missing space before func args.
228 
        (is_macmod_hmove): Likewise.
229 
 
230 148 khays 
2011-06-13  Walter Lee
231 
 
232 
        * tilegx.h: New file.
233 
        * tilepro.h: New file.
234 
 
235 17 khays 
2011-05-31  Paul Brook
236 
 
237 148 khays 
        * arm.h (ARM_ARCH_V7R_IDIV): Define.
238 17 khays 
 
239 148 khays 
2011-05-24  Andreas Krebbel
240 
 
241 
        * s390.h: Replace S390_OPERAND_REG_EVEN with
242 
        S390_OPERAND_REG_PAIR.
243 
 
244 
2011-05-24  Andreas Krebbel
245 
 
246 
        * s390.h: Add S390_OPCODE_REG_EVEN flag.
247 
 
248 17 khays 
2011-04-18  Julian Brown
249 
 
250 
        * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
251 
 
252 
2011-04-11  Dan McDonald
253 
 
254 
        PR gas/12296
255 
        * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
256 
 
257 
2011-03-22  Eric B. Weddington
258 
 
259 
        * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
260 
        New instruction set flags.
261 
        (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
262 
 
263 
2011-02-28  Maciej W. Rozycki
264 
 
265 
        * mips.h (M_PREF_AB): New enum value.
266 
 
267 
2011-02-12  Mike Frysinger
268 
 
269 
        * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
270 
        M_IU): Define.
271 
        (is_macmod_pmove, is_macmod_hmove): New functions.
272 
 
273 
2011-02-11  Mike Frysinger
274 
 
275 
        * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
276 
 
277 
2011-02-04  Bernd Schmidt
278 
 
279 
        * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
280 
        * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
281 
 
282 
2010-12-31  John David Anglin
283 
 
284 
        PR gas/11395
285 
        * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
286 
        "bb" entries.
287 
 
288 
2010-12-26  John David Anglin
289 
 
290 
        PR gas/11395
291 
        * hppa.h: Clear "d" bit in "add" and "sub" patterns.
292 
 
293 
2010-12-18  Richard Sandiford
294 
 
295 
        * mips.h: Update commentary after last commit.
296 
 
297 
2010-12-18  Mingjie Xing
298 
 
299 
        * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
300 
        (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
301 
        (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
302 
 
303 148 khays 
2010-11-25  Andreas Krebbel
304 
 
305 
        * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
306 
 
307 17 khays 
2010-11-23  Richard Sandiford
308 
 
309 
        * mips.h: Fix previous commit.
310 
 
311 
2010-11-23  Maciej W. Rozycki
312 
 
313 
        * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
314 
        (INSN_LOONGSON_3A): Clear bit 31.
315 
 
316 
2010-11-15  Matthew Gretton-Dann
317 
 
318 
        PR gas/12198
319 
        * arm.h (ARM_AEXT_V6M_ONLY): New define.
320 
        (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
321 
        (ARM_ARCH_V6M_ONLY): New define.
322 
 
323 
2010-11-11  Mingming Sun
324 
 
325 
        * mips.h (INSN_LOONGSON_3A): Defined.
326 
        (CPU_LOONGSON_3A): Defined.
327 
        (OPCODE_IS_MEMBER): Add LOONGSON_3A.
328 
 
329 
2010-10-09  Matt Rice
330 
 
331 
        * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
332 
        (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
333 
 
334 
2010-09-23  Matthew Gretton-Dann
335 
 
336 
        * arm.h (ARM_EXT_VIRT): New define.
337 
        (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
338 
        (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
339 
        Extensions.
340 
 
341 
2010-09-23  Matthew Gretton-Dann
342 
 
343 
        * arm.h (ARM_AEXT_ADIV): New define.
344 
        (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
345 
 
346 
2010-09-23  Matthew Gretton-Dann
347 
 
348 
        * arm.h (ARM_EXT_OS): New define.
349 
        (ARM_AEXT_V6SM): Likewise.
350 
        (ARM_ARCH_V6SM): Likewise.
351 
 
352 
2010-09-23  Matthew Gretton-Dann
353 
 
354 
        * arm.h (ARM_EXT_MP): Add.
355 
        (ARM_ARCH_V7A_MP): Likewise.
356 
 
357 
2010-09-22  Mike Frysinger
358 
 
359 
        * bfin.h: Declare pseudoChr structs/defines.
360 
 
361 
2010-09-21  Mike Frysinger
362 
 
363 
        * bfin.h: Strip trailing whitespace.
364 
 
365 
2010-07-29  DJ Delorie
366 
 
367 
        * rx.h (RX_Operand_Type): Add TwoReg.
368 
        (RX_Opcode_ID): Remove ediv and ediv2.
369 
 
370 
2010-07-27  DJ Delorie
371 
 
372 
        * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
373 
 
374 
2010-07-23  Naveen.H.S
375 
            Ina Pandit
376 
 
377 
        * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
378 
        PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
379 
        PROCESSOR_V850E2_ALL.
380 
        Remove PROCESSOR_V850EA support.
381 
        (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
382 
        V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
383 
        V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
384 
        V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
385 
        V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
386 
        V850_OPERAND_PERCENT.
387 
        Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
388 
        V850_NOT_R0.
389 
        Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
390 
        and V850E_PUSH_POP
391 
 
392 
2010-07-06  Maciej W. Rozycki
393 
 
394 
        * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
395 
        (MIPS16_INSN_BRANCH): Rename to...
396 
        (MIPS16_INSN_COND_BRANCH): ... this.
397 
 
398 
2010-07-03  Alan Modra
399 
 
400 
        * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
401 
        Renumber other PPC_OPCODE defines.
402 
 
403 
2010-07-03  Alan Modra
404 
 
405 
        * ppc.h (PPC_OPCODE_COMMON): Expand comment.
406 
 
407 
2010-06-29  Alan Modra
408 
 
409 
        * maxq.h: Delete file.
410 
 
411 
2010-06-14  Sebastian Andrzej Siewior
412 
 
413 
        * ppc.h (PPC_OPCODE_E500): Define.
414 
 
415 
2010-05-26  Catherine Moore
416 
 
417 
        * opcode/mips.h (INSN_MIPS16): Remove.
418 
 
419 
2010-04-21  Joseph Myers
420 
 
421 
        * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
422 
 
423 
2010-04-15  Nick Clifton
424 
 
425 
        * alpha.h: Update copyright notice to use GPLv3.
426 
        * arc.h: Likewise.
427 
        * arm.h: Likewise.
428 
        * avr.h: Likewise.
429 
        * bfin.h: Likewise.
430 
        * cgen.h: Likewise.
431 
        * convex.h: Likewise.
432 
        * cr16.h: Likewise.
433 
        * cris.h: Likewise.
434 
        * crx.h: Likewise.
435 
        * d10v.h: Likewise.
436 
        * d30v.h: Likewise.
437 
        * dlx.h: Likewise.
438 
        * h8300.h: Likewise.
439 
        * hppa.h: Likewise.
440 
        * i370.h: Likewise.
441 
        * i386.h: Likewise.
442 
        * i860.h: Likewise.
443 
        * i960.h: Likewise.
444 
        * ia64.h: Likewise.
445 
        * m68hc11.h: Likewise.
446 
        * m68k.h: Likewise.
447 
        * m88k.h: Likewise.
448 
        * maxq.h: Likewise.
449 
        * mips.h: Likewise.
450 
        * mmix.h: Likewise.
451 
        * mn10200.h: Likewise.
452 
        * mn10300.h: Likewise.
453 
        * msp430.h: Likewise.
454 
        * np1.h: Likewise.
455 
        * ns32k.h: Likewise.
456 
        * or32.h: Likewise.
457 
        * pdp11.h: Likewise.
458 
        * pj.h: Likewise.
459 
        * pn.h: Likewise.
460 
        * ppc.h: Likewise.
461 
        * pyr.h: Likewise.
462 
        * rx.h: Likewise.
463 
        * s390.h: Likewise.
464 
        * score-datadep.h: Likewise.
465 
        * score-inst.h: Likewise.
466 
        * sparc.h: Likewise.
467 
        * spu-insns.h: Likewise.
468 
        * spu.h: Likewise.
469 
        * tic30.h: Likewise.
470 
        * tic4x.h: Likewise.
471 
        * tic54x.h: Likewise.
472 
        * tic80.h: Likewise.
473 
        * v850.h: Likewise.
474 
        * vax.h: Likewise.
475 
 
476 
2010-03-25  Joseph Myers
477 
 
478 
        * tic6x-control-registers.h, tic6x-insn-formats.h,
479 
        tic6x-opcode-table.h, tic6x.h: New.
480 
 
481 
2010-02-25  Wu Zhangjin
482 
 
483 
        * mips.h: (LOONGSON2F_NOP_INSN): New macro.
484 
 
485 
2010-02-08  Philipp Tomsich
486 
 
487 
        * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
488 
 
489 
2010-01-14  H.J. Lu
490 
 
491 
        * ia64.h (ia64_find_opcode): Remove argument name.
492 
        (ia64_find_next_opcode): Likewise.
493 
        (ia64_dis_opcode): Likewise.
494 
        (ia64_free_opcode): Likewise.
495 
        (ia64_find_dependency): Likewise.
496 
 
497 
2009-11-22  Doug Evans
498 
 
499 
        * cgen.h: Include bfd_stdint.h.
500 
        (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
501 
 
502 
2009-11-18  Paul Brook
503 
 
504 
        * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
505 
 
506 
2009-11-17  Paul Brook
507 
        Daniel Jacobowitz
508 
 
509 
        * arm.h (ARM_EXT_V6_DSP): Define.
510 
        (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
511 
        (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
512 
 
513 
2009-11-04  DJ Delorie
514 
 
515 
        * rx.h (rx_decode_opcode) (mvtipl): Add.
516 
        (mvtcp, mvfcp, opecp): Remove.
517 
 
518 
2009-11-02  Paul Brook
519 
 
520 
        * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
521 
        FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
522 
        (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
523 
        FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
524 
        FPU_ARCH_NEON_VFP_V4): Define.
525 
 
526 
2009-10-23  Doug Evans
527 
 
528 
        * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
529 
        * cgen.h: Update.  Improve multi-inclusion macro name.
530 
 
531 
2009-10-02  Peter Bergner
532 
 
533 
        * ppc.h (PPC_OPCODE_476): Define.
534 
 
535 
2009-10-01  Peter Bergner
536 
 
537 
        * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
538 
 
539 
2009-09-29  DJ Delorie
540 
 
541 
        * rx.h: New file.
542 
 
543 
2009-09-22  Peter Bergner
544 
 
545 
        * ppc.h (ppc_cpu_t): Typedef to uint64_t.
546 
 
547 
2009-09-21  Ben Elliston
548 
 
549 
        * ppc.h (PPC_OPCODE_PPCA2): New.
550 
 
551 
2009-09-05  Martin Thuresson
552 
 
553 
        * ia64.h (struct ia64_operand): Renamed member class to op_class.
554 
 
555 
2009-08-29  Martin Thuresson
556 
 
557 
        * tic30.h (template): Rename type template to
558 
        insn_template. Updated code to use new name.
559 
        * tic54x.h (template): Rename type template to
560 
        insn_template.
561 
 
562 
2009-08-20  Nick Hudson
563 
 
564 
        * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
565 
 
566 
2009-06-11  Anthony Green
567 
 
568 
        * moxie.h (MOXIE_F3_PCREL): Define.
569 
        (moxie_form3_opc_info): Grow.
570 
 
571 
2009-06-06  Anthony Green
572 
 
573 
        * moxie.h (MOXIE_F1_M): Define.
574 
 
575 
2009-04-15  Anthony Green
576 
 
577 
        * moxie.h: Created.
578 
 
579 
2009-04-06  DJ Delorie
580 
 
581 
        * h8300.h: Add relaxation attributes to MOVA opcodes.
582 
 
583 
2009-03-10  Alan Modra
584 
 
585 
        * ppc.h (ppc_parse_cpu): Declare.
586 
 
587 
2009-03-02  Qinwei
588 
 
589 
        * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
590 
        and _IMM11 for mbitclr and mbitset.
591 
        * score-datadep.h: Update dependency information.
592 
 
593 
2009-02-26  Peter Bergner
594 
 
595 
        * ppc.h (PPC_OPCODE_POWER7): New.
596 
 
597 
2009-02-06  Doug Evans
598 
 
599 
        * i386.h: Add comment regarding sse* insns and prefixes.
600 
 
601 
2009-02-03  Sandip Matte
602 
 
603 
        * mips.h (INSN_XLR): Define.
604 
        (INSN_CHIP_MASK): Update.
605 
        (CPU_XLR): Define.
606 
        (OPCODE_IS_MEMBER): Update.
607 
        (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
608 
 
609 
2009-01-28  Doug Evans
610 
 
611 
        * opcode/i386.h: Add multiple inclusion protection.
612 
        (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
613 
        (EDI_REG_NUM): New macros.
614 
        (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
615 
        (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
616 
        (REX_PREFIX_P): New macro.
617 
 
618 
2009-01-09  Peter Bergner
619 
 
620 
        * ppc.h (struct powerpc_opcode): New field "deprecated".
621 
        (PPC_OPCODE_NOPOWER4): Delete.
622 
 
623 
2008-11-28  Joshua Kinard
624 
 
625 
        * mips.h: Define CPU_R14000, CPU_R16000.
626 
        (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
627 
 
628 
2008-11-18  Catherine Moore
629 
 
630 
        * arm.h (FPU_NEON_FP16): New.
631 
        (FPU_ARCH_NEON_FP16): New.
632 
 
633 
2008-11-06  Chao-ying Fu
634 
 
635 
        * mips.h: Doucument '1' for 5-bit sync type.
636 
 
637 
2008-08-28  H.J. Lu
638 
 
639 
        * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
640 
        IA64_RS_CR.
641 
 
642 
2008-08-01  Peter Bergner
643 
 
644 
        * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
645 
 
646 
2008-07-30  Michael J. Eager
647 
 
648 
        * ppc.h (PPC_OPCODE_405): Define.
649 
        (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
650 
 
651 
2008-06-13  Peter Bergner
652 
 
653 
        * ppc.h (ppc_cpu_t): New typedef.
654 
        (struct powerpc_opcode ): Use it.
655 
        (struct powerpc_operand ): Likewise.
656 
        (struct powerpc_macro ): Likewise.
657 
 
658 
2008-06-12  Adam Nemet
659 
 
660 
        * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
661 
        Update comment before MIPS16 field descriptors to mention MIPS16.
662 
        (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
663 
        BBIT.
664 
        (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
665 
        New bit masks and shift counts for cins and exts.
666 
 
667 
        * mips.h: Document new field descriptors +Q.
668 
        (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
669 
 
670 
2008-04-28  Adam Nemet
671 
 
672 
        * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
673 
        (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
674 
 
675 
2008-04-14  Edmar Wienskoski
676 
 
677 
        * ppc.h: (PPC_OPCODE_E500MC): New.
678 
 
679 
2008-04-03  H.J. Lu
680 
 
681 
        * i386.h (MAX_OPERANDS): Set to 5.
682 
        (MAX_MNEM_SIZE): Changed to 20.
683 
 
684 
2008-03-28  Eric B. Weddington
685 
 
686 
        * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
687 
 
688 
2008-03-09  Paul Brook
689 
 
690 
        * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
691 
 
692 
2008-03-04  Paul Brook
693 
 
694 
        * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
695 
        (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
696 
        (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
697 
 
698 
2008-02-27  Denis Vlasenko
699 
            Nick Clifton
700 
 
701 
        PR 3134
702 
        * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
703 
        with a 32-bit displacement but without the top bit of the 4th byte
704 
        set.
705 
 
706 
2008-02-18  M R Swami Reddy
707 
 
708 
        * cr16.h (cr16_num_optab): Declared.
709 
 
710 
2008-02-14  Hakan Ardo
711 
 
712 
        PR gas/2626
713 
        * avr.h (AVR_ISA_2xxe): Define.
714 
 
715 
2008-02-04  Adam Nemet
716 
 
717 
        * mips.h: Update copyright.
718 
        (INSN_CHIP_MASK): New macro.
719 
        (INSN_OCTEON): New macro.
720 
        (CPU_OCTEON): New macro.
721 
        (OPCODE_IS_MEMBER): Handle Octeon instructions.
722 
 
723 
2008-01-23  Eric B. Weddington
724 
 
725 
        * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
726 
 
727 
2008-01-03  Eric B. Weddington
728 
 
729 
        * avr.h (AVR_ISA_USB162): Add new opcode set.
730 
        (AVR_ISA_AVR3): Likewise.
731 
 
732 
2007-11-29  Mark Shinwell
733 
 
734 
        * mips.h (INSN_LOONGSON_2E): New.
735 
        (INSN_LOONGSON_2F): New.
736 
        (CPU_LOONGSON_2E): New.
737 
        (CPU_LOONGSON_2F): New.
738 
        (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
739 
 
740 
2007-11-29  Mark Shinwell
741 
 
742 
        * mips.h (INSN_ISA*): Redefine certain values as an
743 
        enumeration.  Update comments.
744 
        (mips_isa_table): New.
745 
        (ISA_MIPS*): Redefine to match enumeration.
746 
        (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
747 
        values.
748 
 
749 
2007-08-08  Ben Elliston
750 
 
751 
        * ppc.h (PPC_OPCODE_PPCPS): New.
752 
 
753 
2007-07-03  Nathan Sidwell
754 
 
755 
        * m68k.h: Document j K & E.
756 
 
757 
2007-06-29  M R Swami Reddy
758 
 
759 
        * cr16.h: New file for CR16 target.
760 
 
761 
2007-05-02  Alan Modra
762 
 
763 
        * ppc.h (PPC_OPERAND_PLUS1): Update comment.
764 
 
765 
2007-04-23  Nathan Sidwell
766 
 
767 
        * m68k.h (mcfisa_c): New.
768 
        (mcfusp, mcf_mask): Adjust.
769 
 
770 
2007-04-20  Alan Modra
771 
 
772 
        * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
773 
        (num_powerpc_operands): Declare.
774 
        (PPC_OPERAND_SIGNED et al): Redefine as hex.
775 
        (PPC_OPERAND_PLUS1): Define.
776 
 
777 
2007-03-21  H.J. Lu
778 
 
779 
        * i386.h (REX_MODE64): Renamed to ...
780 
        (REX_W): This.
781 
        (REX_EXTX): Renamed to ...
782 
        (REX_R): This.
783 
        (REX_EXTY): Renamed to ...
784 
        (REX_X): This.
785 
        (REX_EXTZ): Renamed to ...
786 
        (REX_B): This.
787 
 
788 
2007-03-15  H.J. Lu
789 
 
790 
        * i386.h: Add entries from config/tc-i386.h and move tables
791 
        to opcodes/i386-opc.h.
792 
 
793 
2007-03-13  H.J. Lu
794 
 
795 
        * i386.h (FloatDR): Removed.
796 
        (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
797 
 
798 
2007-03-01  Alan Modra
799 
 
800 
        * spu-insns.h: Add soma double-float insns.
801 
 
802 
2007-02-20  Thiemo Seufer
803 
            Chao-Ying Fu
804 
 
805 
        * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
806 
        (INSN_DSPR2): Add flag for DSP R2 instructions.
807 
        (M_BALIGN): New macro.
808 
 
809 
2007-02-14  Alan Modra
810 
 
811 
        * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
812 
        and Seg3ShortFrom with Shortform.
813 
 
814 
2007-02-11  H.J. Lu
815 
 
816 
        PR gas/4027
817 
        * i386.h (i386_optab): Put the real "test" before the pseudo
818 
        one.
819 
 
820 
2007-01-08  Kazu Hirata
821 
 
822 
        * m68k.h (m68010up): OR fido_a.
823 
 
824 
2006-12-25  Kazu Hirata
825 
 
826 
        * m68k.h (fido_a): New.
827 
 
828 
2006-12-24  Kazu Hirata
829 
 
830 
        * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
831 
        mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
832 
        values.
833 
 
834 
2006-11-08  H.J. Lu
835 
 
836 
        * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
837 
 
838 
2006-10-31  Mei Ligang
839 
 
840 
        * score-inst.h (enum score_insn_type): Add Insn_internal.
841 
 
842 
2006-10-25  Trevor Smigiel
843 
            Yukishige Shibata
844 
            Nobuhisa Fujinami
845 
            Takeaki Fukuoka
846 
            Alan Modra
847 
 
848 
        * spu-insns.h: New file.
849 
        * spu.h: New file.
850 
 
851 
2006-10-24  Andrew Pinski
852 
 
853 
        * ppc.h (PPC_OPCODE_CELL): Define.
854 
 
855 
2006-10-23  Dwarakanath Rajagopal
856 
 
857 
        * i386.h :  Modify opcode to support for the change in POPCNT opcode
858 
        in amdfam10 architecture.
859 
 
860 
2006-09-28  H.J. Lu
861 
 
862 
        * i386.h: Replace CpuMNI with CpuSSSE3.
863 
 
864 
2006-09-26  Mark Shinwell
865 
            Joseph Myers
866 
            Ian Lance Taylor
867 
            Ben Elliston
868 
 
869 
        * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
870 
 
871 
2006-09-17  Mei Ligang
872 
 
873 
        * score-datadep.h: New file.
874 
        * score-inst.h: New file.
875 
 
876 
2006-07-14  H.J. Lu
877 
 
878 
        * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
879 
        movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
880 
        movdq2q and movq2dq.
881 
 
882 
2006-07-10 Dwarakanath Rajagopal
883 
           Michael Meissner
884 
 
885 
        * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
886 
 
887 
2006-06-12  H.J. Lu
888 
 
889 
        * i386.h (i386_optab): Add "nop" with memory reference.
890 
 
891 
2006-06-12  H.J. Lu
892 
 
893 
        * i386.h (i386_optab): Update comment for 64bit NOP.
894 
 
895 
2006-06-06  Ben Elliston
896 
            Anton Blanchard
897 
 
898 
        * ppc.h (PPC_OPCODE_POWER6): Define.
899 
        Adjust whitespace.
900 
 
901 
2006-06-05  Thiemo Seufer
902 
 
903 
        * mips.h: Improve description of MT flags.
904 
 
905 
2006-05-25  Richard Sandiford
906 
 
907 
        * m68k.h (mcf_mask): Define.
908 
 
909 
2006-05-05  Thiemo Seufer
910 
            David Ung
911 
 
912 
        * mips.h (enum): Add macro M_CACHE_AB.
913 
 
914 
2006-05-04  Thiemo Seufer
915 
            Nigel Stephens
916 
            David Ung
917 
 
918 
        * mips.h: Add INSN_SMARTMIPS define.
919 
 
920 
2006-04-30  Thiemo Seufer
921 
            David Ung
922 
 
923 
        * mips.h: Defines udi bits and masks.  Add description of
924 
        characters which may appear in the args field of udi
925 
        instructions.
926 
 
927 
2006-04-26  Thiemo Seufer
928 
 
929 
        * mips.h: Improve comments describing the bitfield instruction
930 
        fields.
931 
 
932 
2006-04-26  Julian Brown
933 
 
934 
        * arm.h (FPU_VFP_EXT_V3): Define constant.
935 
        (FPU_NEON_EXT_V1): Likewise.
936 
        (FPU_VFP_HARD): Update.
937 
        (FPU_VFP_V3): Define macro.
938 
        (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
939 
 
940 
2006-04-07  Joerg Wunsch
941 
 
942 
        * avr.h (AVR_ISA_PWMx): New.
943 
 
944 
2006-03-28  Nathan Sidwell
945 
 
946 
        * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
947 
        cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
948 
        cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
949 
        cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
950 
        cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
951 
 
952 
2006-03-10  Paul Brook
953 
 
954 
        * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
955 
 
956 
2006-03-04  John David Anglin
957 
 
958 
        * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
959 
        first.  Correct mask of bb "B" opcode.
960 
 
961 
2006-02-27  H.J. Lu
962 
 
963 
        * i386.h (i386_optab): Support Intel Merom New Instructions.
964 
 
965 
2006-02-24  Paul Brook
966 
 
967 
        * arm.h: Add V7 feature bits.
968 
 
969 
2006-02-23  H.J. Lu
970 
 
971 
        * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
972 
 
973 
2006-01-31  Paul Brook
974 
        Richard Earnshaw
975 
 
976 
        * arm.h: Use ARM_CPU_FEATURE.
977 
        (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
978 
        (arm_feature_set): Change to a structure.
979 
        (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
980 
        ARM_FEATURE): New macros.
981 
 
982 
2005-12-07  Hans-Peter Nilsson
983 
 
984 
        * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
985 
        (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
986 
        (ADD_PC_INCR_OPCODE): Don't define.
987 
 
988 
2005-12-06  H.J. Lu
989 
 
990 
        PR gas/1874
991 
        * i386.h (i386_optab): Add 64bit support for monitor and mwait.
992 
 
993 
2005-11-14  David Ung
994 
 
995 
        * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
996 
        instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
997 
        save/restore encoding of the args field.
998 
 
999 
2005-10-28  Dave Brolley
1000 
 
1001 
        Contribute the following changes:
1002 
        2005-02-16  Dave Brolley
1003 
 
1004 
        * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1005 
        cgen_isa_mask_* to cgen_bitset_*.
1006 
        * cgen.h: Likewise.
1007 
 
1008 
        2003-10-21  Richard Sandiford
1009 
 
1010 
        * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1011 
        (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1012 
        (CGEN_CPU_TABLE): Make isas a ponter.
1013 
 
1014 
        2003-09-29  Dave Brolley
1015 
 
1016 
        * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1017 
        (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1018 
        (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1019 
 
1020 
        2002-12-13  Dave Brolley
1021 
 
1022 
        * cgen.h (symcat.h): #include it.
1023 
        (cgen-bitset.h): #include it.
1024 
        (CGEN_ATTR_VALUE_TYPE): Now a union.
1025 
        (CGEN_ATTR_VALUE): Reference macros generated in opcodes/-desc.h.
1026 
        (CGEN_ATTR_ENTRY): 'value' now unsigned.
1027 
        (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1028 
        * cgen-bitset.h: New file.
1029 
 
1030 
2005-09-30  Catherine Moore
1031 
 
1032 
        * bfin.h: New file.
1033 
 
1034 
2005-10-24  Jan Beulich
1035 
 
1036 
        * ia64.h (enum ia64_opnd): Move memory operand out of set of
1037 
        indirect operands.
1038 
 
1039 
2005-10-16  John David Anglin
1040 
 
1041 
        * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1042 
        Add FLAG_STRICT to pa10 ftest opcode.
1043 
 
1044 
2005-10-12  John David Anglin
1045 
 
1046 
        * hppa.h (pa_opcodes): Remove lha entries.
1047 
 
1048 
2005-10-08  John David Anglin
1049 
 
1050 
        * hppa.h (FLAG_STRICT): Revise comment.
1051 
        (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1052 
        before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1053 
        entries for "fdc".
1054 
 
1055 
2005-09-30  Catherine Moore
1056 
 
1057 
        * bfin.h: New file.
1058 
 
1059 
2005-09-24  John David Anglin
1060 
 
1061 
        * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1062 
 
1063 
2005-09-06  Chao-ying Fu
1064 
 
1065 
        * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1066 
        OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1067 
        define.
1068 
        Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1069 
        (INSN_ASE_MASK): Update to include INSN_MT.
1070 
        (INSN_MT): New define for MT ASE.
1071 
 
1072 
2005-08-25  Chao-ying Fu
1073 
 
1074 
        * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1075 
        OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1076 
        OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1077 
        OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1078 
        OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1079 
        Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1080 
        instructions.
1081 
        (INSN_DSP): New define for DSP ASE.
1082 
 
1083 
2005-08-18  Alan Modra
1084 
 
1085 
        * a29k.h: Delete.
1086 
 
1087 
2005-08-15  Daniel Jacobowitz
1088 
 
1089 
        * ppc.h (PPC_OPCODE_E300): Define.
1090 
 
1091 
2005-08-12 Martin Schwidefsky
1092 
 
1093 
        * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1094 
 
1095 
2005-07-28  John David Anglin
1096 
 
1097 
        PR gas/336
1098 
        * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1099 
        and pitlb.
1100 
 
1101 
2005-07-27  Jan Beulich
1102 
 
1103 
        * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1104 
        movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1105 
        Add movq-s as 64-bit variants of movd-s.
1106 
 
1107 
2005-07-18  John David Anglin
1108 
 
1109 
        * hppa.h: Fix punctuation in comment.
1110 
 
1111 
        * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1112 
        implicit space-register addressing.  Set space-register bits on opcodes
1113 
        using implicit space-register addressing.  Add various missing pa20
1114 
        long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1115 
        space-register addressing.  Use "fE" instead of "fe" in various
1116 
        fstw opcodes.
1117 
 
1118 
2005-07-18  Jan Beulich
1119 
 
1120 
        * i386.h (i386_optab): Operands of aam and aad are unsigned.
1121 
 
1122 
2007-07-15  H.J. Lu
1123 
 
1124 
        * i386.h (i386_optab): Support Intel VMX Instructions.
1125 
 
1126 
2005-07-10  John David Anglin
1127 
 
1128 
        * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1129 
 
1130 
2005-07-05  Jan Beulich
1131 
 
1132 
        * i386.h (i386_optab): Add new insns.
1133 
 
1134 
2005-07-01  Nick Clifton
1135 
 
1136 
        * sparc.h: Add typedefs to structure declarations.
1137 
 
1138 
2005-06-20  H.J. Lu
1139 
 
1140 
        PR 1013
1141 
        * i386.h (i386_optab): Update comments for 64bit addressing on
1142 
        mov. Allow 64bit addressing for mov and movq.
1143 
 
1144 
2005-06-11  John David Anglin
1145 
 
1146 
        * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1147 
        respectively, in various floating-point load and store patterns.
1148 
 
1149 
2005-05-23  John David Anglin
1150 
 
1151 
        * hppa.h (FLAG_STRICT): Correct comment.
1152 
        (pa_opcodes): Update load and store entries to allow both PA 1.X and
1153 
        PA 2.0 mneumonics when equivalent.  Entries with cache control
1154 
        completers now require PA 1.1.  Adjust whitespace.
1155 
 
1156 
2005-05-19  Anton Blanchard
1157 
 
1158 
        * ppc.h (PPC_OPCODE_POWER5): Define.
1159 
 
1160 
2005-05-10  Nick Clifton
1161 
 
1162 
        * Update the address and phone number of the FSF organization in
1163 
        the GPL notices in the following files:
1164 
        a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1165 
        crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1166 
        i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1167 
        mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1168 
        pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1169 
        tic54x.h, tic80.h, v850.h, vax.h
1170 
 
1171 
2005-05-09  Jan Beulich
1172 
 
1173 
        * i386.h (i386_optab): Add ht and hnt.
1174 
 
1175 
2005-04-18  Mark Kettenis
1176 
 
1177 
        * i386.h: Insert hyphens into selected VIA PadLock extensions.
1178 
        Add xcrypt-ctr.  Provide aliases without hyphens.
1179 
 
1180 
2005-04-13  H.J. Lu
1181 
 
1182 
        Moved from ../ChangeLog
1183 
 
1184 
        2005-04-12  Paul Brook
1185 
        * m88k.h: Rename psr macros to avoid conflicts.
1186 
 
1187 
        2005-03-12  Zack Weinberg
1188 
        * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1189 
        Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1190 
        and ARM_ARCH_V6ZKT2.
1191 
 
1192 
        2004-11-29  Tomer Levi
1193 
        * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1194 
        Remove redundant instruction types.
1195 
        (struct argument): X_op - new field.
1196 
        (struct cst4_entry): Remove.
1197 
        (no_op_insn): Declare.
1198 
 
1199 
        2004-11-05  Tomer Levi
1200 
        * crx.h (enum argtype): Rename types, remove unused types.
1201 
 
1202 
        2004-10-27  Tomer Levi
1203 
        * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1204 
        (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1205 
        (enum operand_type): Rearrange operands, edit comments.
1206 
        replace us with ui for unsigned immediate.
1207 
        replace d with disps/dispu/dispe for signed/unsigned/escaped
1208 
        displacements (respectively).
1209 
        replace rbase_ridx_scl2_dispu with rindex_disps for register index.
1210 
        (instruction type): Add NO_TYPE_INS.
1211 
        (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1212 
        (operand_entry): New field - 'flags'.
1213 
        (operand flags): New.
1214 
 
1215 
        2004-10-21  Tomer Levi
1216 
        * crx.h (operand_type): Remove redundant types i3, i4,
1217 
        i5, i8, i12.
1218 
        Add new unsigned immediate types us3, us4, us5, us16.
1219 
 
1220 
2005-04-12  Mark Kettenis
1221 
 
1222 
        * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1223 
        adjust them accordingly.
1224 
 
1225 
2005-04-01  Jan Beulich
1226 
 
1227 
        * i386.h (i386_optab): Add rdtscp.
1228 
 
1229 
2005-03-29  H.J. Lu
1230 
 
1231 
        * i386.h (i386_optab): Don't allow the `l' suffix for moving
1232 
        between memory and segment register. Allow movq for moving between
1233 
        general-purpose register and segment register.
1234 
 
1235 
2005-02-09  Jan Beulich
1236 
 
1237 
        PR gas/707
1238 
        * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1239 
        FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1240 
        fnstsw.
1241 
 
1242 
2006-02-07  Nathan Sidwell
1243 
 
1244 
        * m68k.h (m68008, m68ec030, m68882): Remove.
1245 
        (m68k_mask): New.
1246 
        (cpu_m68k, cpu_cf): New.
1247 
        (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1248 
        mcf5470, mcf5480): Rename to cpu_. Add m680x0 variants.
1249 
 
1250 
2005-01-25  Alexandre Oliva
1251 
 
1252 
        2004-11-10  Alexandre Oliva
1253 
        * cgen.h (enum cgen_parse_operand_type): Add
1254 
        CGEN_PARSE_OPERAND_SYMBOLIC.
1255 
 
1256 
2005-01-21  Fred Fish
1257 
 
1258 
        * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1259 
        Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1260 
        Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1261 
 
1262 
2005-01-19  Fred Fish
1263 
 
1264 
        * mips.h (struct mips_opcode): Add new pinfo2 member.
1265 
        (INSN_ALIAS): New define for opcode table entries that are
1266 
        specific instances of another entry, such as 'move' for an 'or'
1267 
        with a zero operand.
1268 
        (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1269 
        (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1270 
 
1271 
2004-12-09  Ian Lance Taylor
1272 
 
1273 
        * mips.h (CPU_RM9000): Define.
1274 
        (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1275 
 
1276 
2004-11-25 Jan Beulich
1277 
 
1278 
        * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1279 
        to/from test registers are illegal in 64-bit mode. Add missing
1280 
        NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1281 
        (previously one had to explicitly encode a rex64 prefix). Re-enable
1282 
        lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1283 
        support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1284 
 
1285 
2004-11-23 Jan Beulich
1286 
 
1287 
        * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1288 
        available only with SSE2. Change the MMX additions introduced by SSE
1289 
        and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1290 
        instructions by their now designated identifier (since combining i686
1291 
        and 3DNow! does not really imply 3DNow!A).
1292 
 
1293 
2004-11-19  Alan Modra
1294 
 
1295 
        * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1296 
        struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1297 
 
1298 
2004-11-08  Inderpreet Singh
1299 
            Vineet Sharma
1300 
 
1301 
        * maxq.h: New file: Disassembly information for the maxq port.
1302 
 
1303 
2004-11-05  H.J. Lu
1304 
 
1305 
        * i386.h (i386_optab): Put back "movzb".
1306 
 
1307 
2004-11-04  Hans-Peter Nilsson
1308 
 
1309 
        * cris.h (enum cris_insn_version_usage): Tweak formatting and
1310 
        comments.  Remove member cris_ver_sim.  Add members
1311 
        cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1312 
        cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1313 
        (struct cris_support_reg, struct cris_cond15): New types.
1314 
        (cris_conds15): Declare.
1315 
        (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1316 
        (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1317 
        (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1318 
        (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1319 
        (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1320 
        SIZE_FIELD_UNSIGNED.
1321 
 
1322 
2004-11-04 Jan Beulich
1323 
 
1324 
        * i386.h (sldx_Suf): Remove.
1325 
        (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1326 
        (q_FP): Define, implying no REX64.
1327 
        (x_FP, sl_FP): Imply FloatMF.
1328 
        (i386_optab): Split reg and mem forms of moving from segment registers
1329 
        so that the memory forms can ignore the 16-/32-bit operand size
1330 
        distinction. Adjust a few others for Intel mode. Remove *FP uses from
1331 
        all non-floating-point instructions. Unite 32- and 64-bit forms of
1332 
        movsx, movzx, and movd. Adjust floating point operations for the above
1333 
        changes to the *FP macros. Add DefaultSize to floating point control
1334 
        insns operating on larger memory ranges. Remove left over comments
1335 
        hinting at certain insns being Intel-syntax ones where the ones
1336 
        actually meant are already gone.
1337 
 
1338 
2004-10-07  Tomer Levi
1339 
 
1340 
        * crx.h: Add COPS_REG_INS - Coprocessor Special register
1341 
        instruction type.
1342 
 
1343 
2004-09-30  Paul Brook
1344 
 
1345 
        * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1346 
        (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1347 
 
1348 
2004-09-11  Theodore A. Roth
1349 
 
1350 
        * avr.h: Add support for
1351 
        atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1352 
 
1353 
2004-09-09  Segher Boessenkool
1354 
 
1355 
        * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1356 
 
1357 
2004-08-24  Dmitry Diky
1358 
 
1359 
        * msp430.h (msp430_opc): Add new instructions.
1360 
        (msp430_rcodes): Declare new instructions.
1361 
        (msp430_hcodes): Likewise..
1362 
 
1363 
2004-08-13  Nick Clifton
1364 
 
1365 
        PR/301
1366 
        * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1367 
        processors.
1368 
 
1369 
2004-08-30  Michal Ludvig
1370 
 
1371 
        * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1372 
 
1373 
2004-07-22  H.J. Lu
1374 
 
1375 
        * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1376 
 
1377 
2004-07-21  Jan Beulich
1378 
 
1379 
        * i386.h: Adjust instruction descriptions to better match the
1380 
        specification.
1381 
 
1382 
2004-07-16  Richard Earnshaw
1383 
 
1384 
        * arm.h: Remove all old content.  Replace with architecture defines
1385 
        from gas/config/tc-arm.c.
1386 
 
1387 
2004-07-09  Andreas Schwab
1388 
 
1389 
        * m68k.h: Fix comment.
1390 
 
1391 
2004-07-07  Tomer Levi
1392 
 
1393 
        * crx.h: New file.
1394 
 
1395 
2004-06-24  Alan Modra
1396 
 
1397 
        * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1398 
 
1399 
2004-05-24  Peter Barada
1400 
 
1401 
        * m68k.h: Add 'size' to m68k_opcode.
1402 
 
1403 
2004-05-05  Peter Barada
1404 
 
1405 
        * m68k.h: Switch from ColdFire chip name to core variant.
1406 
 
1407 
2004-04-22  Peter Barada
1408 
 
1409 
        * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1410 
        descriptions for new EMAC cases.
1411 
        Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1412 
        handle Motorola MAC syntax.
1413 
        Allow disassembly of ColdFire V4e object files.
1414 
 
1415 
2004-03-16  Alan Modra
1416 
 
1417 
        * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1418 
 
1419 
2004-03-12  Jakub Jelinek
1420 
 
1421 
        * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1422 
 
1423 
2004-03-12  Michal Ludvig
1424 
 
1425 
        * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1426 
 
1427 
2004-03-12  Michal Ludvig
1428 
 
1429 
        * i386.h (i386_optab): Added xstore/xcrypt insns.
1430 
 
1431 
2004-02-09  Anil Paranjpe
1432 
 
1433 
        * h8300.h (32bit ldc/stc): Add relaxing support.
1434 
 
1435 
2004-01-12  Anil Paranjpe
1436 
 
1437 
        * h8300.h (BITOP): Pass MEMRELAX flag.
1438 
 
1439 
2004-01-09  Anil Paranjpe
1440 
 
1441 
        * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1442 
        except for the H8S.
1443 
 
1444 
For older changes see ChangeLog-9103
1445 
 
1446 
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1448 
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1449 
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1450 
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