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[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [include/] [opcode/] [ChangeLog] - Blame information for rev 241

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Line No. Rev Author Line
1 166 khays 
2012-02-27  Alan Modra
2 
 
3 
        * crx.h (cst4_map): Update declaration.
4 
 
5 
2012-02-25  Walter Lee
6 
 
7 
        * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
8 
        TILEGX_OPC_LD_TLS.
9 
        * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
10 
        TILEPRO_OPC_LW_TLS_SN.
11 
 
12 
2012-02-08  H.J. Lu
13 
 
14 
        * i386.h (XACQUIRE_PREFIX_OPCODE): New.
15 
        (XRELEASE_PREFIX_OPCODE): Likewise.
16 
 
17 
2011-12-08  Andrew Pinski
18 
            Adam Nemet
19 
 
20 
        * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
21 
        (INSN_OCTEON2): New macro.
22 
        (CPU_OCTEON2): New macro.
23 
        (OPCODE_IS_MEMBER): Add Octeon2.
24 
 
25 
2011-11-29  Andrew Pinski
26 
 
27 
        * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
28 
        (INSN_OCTEONP): New macro.
29 
        (CPU_OCTEONP): New macro.
30 
        (OPCODE_IS_MEMBER): Add Octeon+.
31 
        (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
32 
 
33 163 khays 
2011-11-01  DJ Delorie
34 
 
35 
        * rl78.h: New file.
36 
 
37 
2011-10-24  Maciej W. Rozycki
38 
 
39 
        * mips.h: Fix a typo in description.
40 
 
41 
2011-09-21  David S. Miller
42 
 
43 
        * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
44 
        (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
45 
        F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
46 
        F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
47 
 
48 161 khays 
2011-08-09  Chao-ying Fu
49 
            Maciej W. Rozycki
50 
 
51 
        * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
52 
        (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
53 
        (INSN_ASE_MASK): Add the MCU bit.
54 
        (INSN_MCU): New macro.
55 
        (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
56 
        (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
57 
 
58 
2011-08-09  Maciej W. Rozycki
59 
 
60 
        * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
61 
        (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
62 
        (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
63 
        (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
64 
        (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
65 
        (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
66 
        (INSN2_READ_GPR_MMN): Likewise.
67 
        (INSN2_READ_FPR_D): Change the bit used.
68 
        (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
69 
        (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
70 
        (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
71 
        (INSN2_COND_BRANCH): Likewise.
72 
        (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
73 
        (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
74 
        (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
75 
        (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
76 
        (INSN2_MOD_GPR_MN): Likewise.
77 
 
78 
2011-08-05  David S. Miller
79 
 
80 
        * sparc.h: Document new format codes '4', '5', and '('.
81 
        (OPF_LOW4, RS3): New macros.
82 
 
83 
2011-08-03  Maciej W. Rozycki
84 
 
85 
        * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
86 
        order of flags documented.
87 
 
88 
2011-07-29  Maciej W. Rozycki
89 
 
90 
        * mips.h: Clarify the description of microMIPS instruction
91 
        manipulation macros.
92 
        (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
93 
 
94 
2011-07-24  Chao-ying Fu
95 
            Maciej W. Rozycki
96 
 
97 
        * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
98 
        (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
99 
        (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
100 
        (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
101 
        (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
102 
        (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
103 
        (OP_MASK_RS3, OP_SH_RS3): Likewise.
104 
        (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
105 
        (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
106 
        (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
107 
        (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
108 
        (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
109 
        (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
110 
        (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
111 
        (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
112 
        (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
113 
        (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
114 
        (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
115 
        (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
116 
        (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
117 
        (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
118 
        (INSN_WRITE_GPR_S): New macro.
119 
        (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
120 
        (INSN2_READ_FPR_D): Likewise.
121 
        (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
122 
        (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
123 
        (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
124 
        (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
125 
        (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
126 
        (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
127 
        (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
128 
        (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
129 
        (CPU_MICROMIPS): New macro.
130 
        (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
131 
        (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
132 
        (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
133 
        (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
134 
        (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
135 
        (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
136 
        (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
137 
        (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
138 
        (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
139 
        (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
140 
        (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
141 
        (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
142 
        (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
143 
        (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
144 
        (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
145 
        (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
146 
        (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
147 
        (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
148 
        (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
149 
        (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
150 
        (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
151 
        (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
152 
        (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
153 
        (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
154 
        (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
155 
        (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
156 
        (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
157 
        (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
158 
        (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
159 
        (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
160 
        (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
161 
        (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
162 
        (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
163 
        (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
164 
        (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
165 
        (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
166 
        (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
167 
        (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
168 
        (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
169 
        (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
170 
        (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
171 
        (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
172 
        (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
173 
        (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
174 
        (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
175 
        (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
176 
        (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
177 
        (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
178 
        (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
179 
        (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
180 
        (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
181 
        (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
182 
        (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
183 
        (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
184 
        (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
185 
        (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
186 
        (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
187 
        (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
188 
        (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
189 
        (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
190 
        (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
191 
        (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
192 
        (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
193 
        (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
194 
        (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
195 
        (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
196 
        (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
197 
        (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
198 
        (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
199 
        (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
200 
        (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
201 
        (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
202 
        (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
203 
        (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
204 
        (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
205 
        (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
206 
        (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
207 
        (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
208 
        (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
209 
        (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
210 
        (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
211 
        (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
212 
        (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
213 
        (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
214 
        (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
215 
        (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
216 
        (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
217 
        (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
218 
        (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
219 
        (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
220 
        (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
221 
        (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
222 
        (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
223 
        (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
224 
        (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
225 
        (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
226 
        (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
227 
        (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
228 
        (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
229 
        (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
230 
        (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
231 
        (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
232 
        (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
233 
        (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
234 
        (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
235 
        (micromips_opcodes): New declaration.
236 
        (bfd_micromips_num_opcodes): Likewise.
237 
 
238 
2011-07-24  Maciej W. Rozycki
239 
 
240 
        * mips.h (INSN_TRAP): Rename to...
241 
        (INSN_NO_DELAY_SLOT): ... this.
242 
        (INSN_SYNC): Remove macro.
243 
 
244 
2011-07-01  Eric B. Weddington
245 
 
246 
        * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
247 
        a duplicate of AVR_ISA_SPM.
248 
 
249 
2011-07-01  Nick Clifton
250 
 
251 
        * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
252 
 
253 
2011-06-18  Robin Getz
254 
 
255 
        * bfin.h (is_macmod_signed): New func
256 
 
257 
2011-06-18  Mike Frysinger
258 
 
259 
        * bfin.h (is_macmod_pmove): Add missing space before func args.
260 
        (is_macmod_hmove): Likewise.
261 
 
262 148 khays 
2011-06-13  Walter Lee
263 
 
264 
        * tilegx.h: New file.
265 
        * tilepro.h: New file.
266 
 
267 17 khays 
2011-05-31  Paul Brook
268 
 
269 148 khays 
        * arm.h (ARM_ARCH_V7R_IDIV): Define.
270 17 khays 
 
271 148 khays 
2011-05-24  Andreas Krebbel
272 
 
273 
        * s390.h: Replace S390_OPERAND_REG_EVEN with
274 
        S390_OPERAND_REG_PAIR.
275 
 
276 
2011-05-24  Andreas Krebbel
277 
 
278 
        * s390.h: Add S390_OPCODE_REG_EVEN flag.
279 
 
280 17 khays 
2011-04-18  Julian Brown
281 
 
282 
        * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
283 
 
284 
2011-04-11  Dan McDonald
285 
 
286 
        PR gas/12296
287 
        * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
288 
 
289 
2011-03-22  Eric B. Weddington
290 
 
291 
        * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
292 
        New instruction set flags.
293 
        (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
294 
 
295 
2011-02-28  Maciej W. Rozycki
296 
 
297 
        * mips.h (M_PREF_AB): New enum value.
298 
 
299 
2011-02-12  Mike Frysinger
300 
 
301 
        * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
302 
        M_IU): Define.
303 
        (is_macmod_pmove, is_macmod_hmove): New functions.
304 
 
305 
2011-02-11  Mike Frysinger
306 
 
307 
        * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
308 
 
309 
2011-02-04  Bernd Schmidt
310 
 
311 
        * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
312 
        * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
313 
 
314 
2010-12-31  John David Anglin
315 
 
316 
        PR gas/11395
317 
        * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
318 
        "bb" entries.
319 
 
320 
2010-12-26  John David Anglin
321 
 
322 
        PR gas/11395
323 
        * hppa.h: Clear "d" bit in "add" and "sub" patterns.
324 
 
325 
2010-12-18  Richard Sandiford
326 
 
327 
        * mips.h: Update commentary after last commit.
328 
 
329 
2010-12-18  Mingjie Xing
330 
 
331 
        * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
332 
        (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
333 
        (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
334 
 
335 148 khays 
2010-11-25  Andreas Krebbel
336 
 
337 
        * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
338 
 
339 17 khays 
2010-11-23  Richard Sandiford
340 
 
341 
        * mips.h: Fix previous commit.
342 
 
343 
2010-11-23  Maciej W. Rozycki
344 
 
345 
        * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
346 
        (INSN_LOONGSON_3A): Clear bit 31.
347 
 
348 
2010-11-15  Matthew Gretton-Dann
349 
 
350 
        PR gas/12198
351 
        * arm.h (ARM_AEXT_V6M_ONLY): New define.
352 
        (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
353 
        (ARM_ARCH_V6M_ONLY): New define.
354 
 
355 
2010-11-11  Mingming Sun
356 
 
357 
        * mips.h (INSN_LOONGSON_3A): Defined.
358 
        (CPU_LOONGSON_3A): Defined.
359 
        (OPCODE_IS_MEMBER): Add LOONGSON_3A.
360 
 
361 
2010-10-09  Matt Rice
362 
 
363 
        * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
364 
        (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
365 
 
366 
2010-09-23  Matthew Gretton-Dann
367 
 
368 
        * arm.h (ARM_EXT_VIRT): New define.
369 
        (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
370 
        (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
371 
        Extensions.
372 
 
373 
2010-09-23  Matthew Gretton-Dann
374 
 
375 
        * arm.h (ARM_AEXT_ADIV): New define.
376 
        (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
377 
 
378 
2010-09-23  Matthew Gretton-Dann
379 
 
380 
        * arm.h (ARM_EXT_OS): New define.
381 
        (ARM_AEXT_V6SM): Likewise.
382 
        (ARM_ARCH_V6SM): Likewise.
383 
 
384 
2010-09-23  Matthew Gretton-Dann
385 
 
386 
        * arm.h (ARM_EXT_MP): Add.
387 
        (ARM_ARCH_V7A_MP): Likewise.
388 
 
389 
2010-09-22  Mike Frysinger
390 
 
391 
        * bfin.h: Declare pseudoChr structs/defines.
392 
 
393 
2010-09-21  Mike Frysinger
394 
 
395 
        * bfin.h: Strip trailing whitespace.
396 
 
397 
2010-07-29  DJ Delorie
398 
 
399 
        * rx.h (RX_Operand_Type): Add TwoReg.
400 
        (RX_Opcode_ID): Remove ediv and ediv2.
401 
 
402 
2010-07-27  DJ Delorie
403 
 
404 
        * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
405 
 
406 
2010-07-23  Naveen.H.S
407 
            Ina Pandit
408 
 
409 
        * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
410 
        PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
411 
        PROCESSOR_V850E2_ALL.
412 
        Remove PROCESSOR_V850EA support.
413 
        (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
414 
        V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
415 
        V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
416 
        V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
417 
        V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
418 
        V850_OPERAND_PERCENT.
419 
        Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
420 
        V850_NOT_R0.
421 
        Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
422 
        and V850E_PUSH_POP
423 
 
424 
2010-07-06  Maciej W. Rozycki
425 
 
426 
        * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
427 
        (MIPS16_INSN_BRANCH): Rename to...
428 
        (MIPS16_INSN_COND_BRANCH): ... this.
429 
 
430 
2010-07-03  Alan Modra
431 
 
432 
        * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
433 
        Renumber other PPC_OPCODE defines.
434 
 
435 
2010-07-03  Alan Modra
436 
 
437 
        * ppc.h (PPC_OPCODE_COMMON): Expand comment.
438 
 
439 
2010-06-29  Alan Modra
440 
 
441 
        * maxq.h: Delete file.
442 
 
443 
2010-06-14  Sebastian Andrzej Siewior
444 
 
445 
        * ppc.h (PPC_OPCODE_E500): Define.
446 
 
447 
2010-05-26  Catherine Moore
448 
 
449 
        * opcode/mips.h (INSN_MIPS16): Remove.
450 
 
451 
2010-04-21  Joseph Myers
452 
 
453 
        * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
454 
 
455 
2010-04-15  Nick Clifton
456 
 
457 
        * alpha.h: Update copyright notice to use GPLv3.
458 
        * arc.h: Likewise.
459 
        * arm.h: Likewise.
460 
        * avr.h: Likewise.
461 
        * bfin.h: Likewise.
462 
        * cgen.h: Likewise.
463 
        * convex.h: Likewise.
464 
        * cr16.h: Likewise.
465 
        * cris.h: Likewise.
466 
        * crx.h: Likewise.
467 
        * d10v.h: Likewise.
468 
        * d30v.h: Likewise.
469 
        * dlx.h: Likewise.
470 
        * h8300.h: Likewise.
471 
        * hppa.h: Likewise.
472 
        * i370.h: Likewise.
473 
        * i386.h: Likewise.
474 
        * i860.h: Likewise.
475 
        * i960.h: Likewise.
476 
        * ia64.h: Likewise.
477 
        * m68hc11.h: Likewise.
478 
        * m68k.h: Likewise.
479 
        * m88k.h: Likewise.
480 
        * maxq.h: Likewise.
481 
        * mips.h: Likewise.
482 
        * mmix.h: Likewise.
483 
        * mn10200.h: Likewise.
484 
        * mn10300.h: Likewise.
485 
        * msp430.h: Likewise.
486 
        * np1.h: Likewise.
487 
        * ns32k.h: Likewise.
488 
        * or32.h: Likewise.
489 
        * pdp11.h: Likewise.
490 
        * pj.h: Likewise.
491 
        * pn.h: Likewise.
492 
        * ppc.h: Likewise.
493 
        * pyr.h: Likewise.
494 
        * rx.h: Likewise.
495 
        * s390.h: Likewise.
496 
        * score-datadep.h: Likewise.
497 
        * score-inst.h: Likewise.
498 
        * sparc.h: Likewise.
499 
        * spu-insns.h: Likewise.
500 
        * spu.h: Likewise.
501 
        * tic30.h: Likewise.
502 
        * tic4x.h: Likewise.
503 
        * tic54x.h: Likewise.
504 
        * tic80.h: Likewise.
505 
        * v850.h: Likewise.
506 
        * vax.h: Likewise.
507 
 
508 
2010-03-25  Joseph Myers
509 
 
510 
        * tic6x-control-registers.h, tic6x-insn-formats.h,
511 
        tic6x-opcode-table.h, tic6x.h: New.
512 
 
513 
2010-02-25  Wu Zhangjin
514 
 
515 
        * mips.h: (LOONGSON2F_NOP_INSN): New macro.
516 
 
517 
2010-02-08  Philipp Tomsich
518 
 
519 
        * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
520 
 
521 
2010-01-14  H.J. Lu
522 
 
523 
        * ia64.h (ia64_find_opcode): Remove argument name.
524 
        (ia64_find_next_opcode): Likewise.
525 
        (ia64_dis_opcode): Likewise.
526 
        (ia64_free_opcode): Likewise.
527 
        (ia64_find_dependency): Likewise.
528 
 
529 
2009-11-22  Doug Evans
530 
 
531 
        * cgen.h: Include bfd_stdint.h.
532 
        (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
533 
 
534 
2009-11-18  Paul Brook
535 
 
536 
        * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
537 
 
538 
2009-11-17  Paul Brook
539 
        Daniel Jacobowitz
540 
 
541 
        * arm.h (ARM_EXT_V6_DSP): Define.
542 
        (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
543 
        (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
544 
 
545 
2009-11-04  DJ Delorie
546 
 
547 
        * rx.h (rx_decode_opcode) (mvtipl): Add.
548 
        (mvtcp, mvfcp, opecp): Remove.
549 
 
550 
2009-11-02  Paul Brook
551 
 
552 
        * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
553 
        FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
554 
        (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
555 
        FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
556 
        FPU_ARCH_NEON_VFP_V4): Define.
557 
 
558 
2009-10-23  Doug Evans
559 
 
560 
        * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
561 
        * cgen.h: Update.  Improve multi-inclusion macro name.
562 
 
563 
2009-10-02  Peter Bergner
564 
 
565 
        * ppc.h (PPC_OPCODE_476): Define.
566 
 
567 
2009-10-01  Peter Bergner
568 
 
569 
        * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
570 
 
571 
2009-09-29  DJ Delorie
572 
 
573 
        * rx.h: New file.
574 
 
575 
2009-09-22  Peter Bergner
576 
 
577 
        * ppc.h (ppc_cpu_t): Typedef to uint64_t.
578 
 
579 
2009-09-21  Ben Elliston
580 
 
581 
        * ppc.h (PPC_OPCODE_PPCA2): New.
582 
 
583 
2009-09-05  Martin Thuresson
584 
 
585 
        * ia64.h (struct ia64_operand): Renamed member class to op_class.
586 
 
587 
2009-08-29  Martin Thuresson
588 
 
589 
        * tic30.h (template): Rename type template to
590 
        insn_template. Updated code to use new name.
591 
        * tic54x.h (template): Rename type template to
592 
        insn_template.
593 
 
594 
2009-08-20  Nick Hudson
595 
 
596 
        * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
597 
 
598 
2009-06-11  Anthony Green
599 
 
600 
        * moxie.h (MOXIE_F3_PCREL): Define.
601 
        (moxie_form3_opc_info): Grow.
602 
 
603 
2009-06-06  Anthony Green
604 
 
605 
        * moxie.h (MOXIE_F1_M): Define.
606 
 
607 
2009-04-15  Anthony Green
608 
 
609 
        * moxie.h: Created.
610 
 
611 
2009-04-06  DJ Delorie
612 
 
613 
        * h8300.h: Add relaxation attributes to MOVA opcodes.
614 
 
615 
2009-03-10  Alan Modra
616 
 
617 
        * ppc.h (ppc_parse_cpu): Declare.
618 
 
619 
2009-03-02  Qinwei
620 
 
621 
        * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
622 
        and _IMM11 for mbitclr and mbitset.
623 
        * score-datadep.h: Update dependency information.
624 
 
625 
2009-02-26  Peter Bergner
626 
 
627 
        * ppc.h (PPC_OPCODE_POWER7): New.
628 
 
629 
2009-02-06  Doug Evans
630 
 
631 
        * i386.h: Add comment regarding sse* insns and prefixes.
632 
 
633 
2009-02-03  Sandip Matte
634 
 
635 
        * mips.h (INSN_XLR): Define.
636 
        (INSN_CHIP_MASK): Update.
637 
        (CPU_XLR): Define.
638 
        (OPCODE_IS_MEMBER): Update.
639 
        (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
640 
 
641 
2009-01-28  Doug Evans
642 
 
643 
        * opcode/i386.h: Add multiple inclusion protection.
644 
        (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
645 
        (EDI_REG_NUM): New macros.
646 
        (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
647 
        (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
648 
        (REX_PREFIX_P): New macro.
649 
 
650 
2009-01-09  Peter Bergner
651 
 
652 
        * ppc.h (struct powerpc_opcode): New field "deprecated".
653 
        (PPC_OPCODE_NOPOWER4): Delete.
654 
 
655 
2008-11-28  Joshua Kinard
656 
 
657 
        * mips.h: Define CPU_R14000, CPU_R16000.
658 
        (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
659 
 
660 
2008-11-18  Catherine Moore
661 
 
662 
        * arm.h (FPU_NEON_FP16): New.
663 
        (FPU_ARCH_NEON_FP16): New.
664 
 
665 
2008-11-06  Chao-ying Fu
666 
 
667 
        * mips.h: Doucument '1' for 5-bit sync type.
668 
 
669 
2008-08-28  H.J. Lu
670 
 
671 
        * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
672 
        IA64_RS_CR.
673 
 
674 
2008-08-01  Peter Bergner
675 
 
676 
        * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
677 
 
678 
2008-07-30  Michael J. Eager
679 
 
680 
        * ppc.h (PPC_OPCODE_405): Define.
681 
        (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
682 
 
683 
2008-06-13  Peter Bergner
684 
 
685 
        * ppc.h (ppc_cpu_t): New typedef.
686 
        (struct powerpc_opcode ): Use it.
687 
        (struct powerpc_operand ): Likewise.
688 
        (struct powerpc_macro ): Likewise.
689 
 
690 
2008-06-12  Adam Nemet
691 
 
692 
        * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
693 
        Update comment before MIPS16 field descriptors to mention MIPS16.
694 
        (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
695 
        BBIT.
696 
        (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
697 
        New bit masks and shift counts for cins and exts.
698 
 
699 
        * mips.h: Document new field descriptors +Q.
700 
        (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
701 
 
702 
2008-04-28  Adam Nemet
703 
 
704 
        * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
705 
        (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
706 
 
707 
2008-04-14  Edmar Wienskoski
708 
 
709 
        * ppc.h: (PPC_OPCODE_E500MC): New.
710 
 
711 
2008-04-03  H.J. Lu
712 
 
713 
        * i386.h (MAX_OPERANDS): Set to 5.
714 
        (MAX_MNEM_SIZE): Changed to 20.
715 
 
716 
2008-03-28  Eric B. Weddington
717 
 
718 
        * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
719 
 
720 
2008-03-09  Paul Brook
721 
 
722 
        * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
723 
 
724 
2008-03-04  Paul Brook
725 
 
726 
        * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
727 
        (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
728 
        (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
729 
 
730 
2008-02-27  Denis Vlasenko
731 
            Nick Clifton
732 
 
733 
        PR 3134
734 
        * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
735 
        with a 32-bit displacement but without the top bit of the 4th byte
736 
        set.
737 
 
738 
2008-02-18  M R Swami Reddy
739 
 
740 
        * cr16.h (cr16_num_optab): Declared.
741 
 
742 
2008-02-14  Hakan Ardo
743 
 
744 
        PR gas/2626
745 
        * avr.h (AVR_ISA_2xxe): Define.
746 
 
747 
2008-02-04  Adam Nemet
748 
 
749 
        * mips.h: Update copyright.
750 
        (INSN_CHIP_MASK): New macro.
751 
        (INSN_OCTEON): New macro.
752 
        (CPU_OCTEON): New macro.
753 
        (OPCODE_IS_MEMBER): Handle Octeon instructions.
754 
 
755 
2008-01-23  Eric B. Weddington
756 
 
757 
        * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
758 
 
759 
2008-01-03  Eric B. Weddington
760 
 
761 
        * avr.h (AVR_ISA_USB162): Add new opcode set.
762 
        (AVR_ISA_AVR3): Likewise.
763 
 
764 
2007-11-29  Mark Shinwell
765 
 
766 
        * mips.h (INSN_LOONGSON_2E): New.
767 
        (INSN_LOONGSON_2F): New.
768 
        (CPU_LOONGSON_2E): New.
769 
        (CPU_LOONGSON_2F): New.
770 
        (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
771 
 
772 
2007-11-29  Mark Shinwell
773 
 
774 
        * mips.h (INSN_ISA*): Redefine certain values as an
775 
        enumeration.  Update comments.
776 
        (mips_isa_table): New.
777 
        (ISA_MIPS*): Redefine to match enumeration.
778 
        (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
779 
        values.
780 
 
781 
2007-08-08  Ben Elliston
782 
 
783 
        * ppc.h (PPC_OPCODE_PPCPS): New.
784 
 
785 
2007-07-03  Nathan Sidwell
786 
 
787 
        * m68k.h: Document j K & E.
788 
 
789 
2007-06-29  M R Swami Reddy
790 
 
791 
        * cr16.h: New file for CR16 target.
792 
 
793 
2007-05-02  Alan Modra
794 
 
795 
        * ppc.h (PPC_OPERAND_PLUS1): Update comment.
796 
 
797 
2007-04-23  Nathan Sidwell
798 
 
799 
        * m68k.h (mcfisa_c): New.
800 
        (mcfusp, mcf_mask): Adjust.
801 
 
802 
2007-04-20  Alan Modra
803 
 
804 
        * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
805 
        (num_powerpc_operands): Declare.
806 
        (PPC_OPERAND_SIGNED et al): Redefine as hex.
807 
        (PPC_OPERAND_PLUS1): Define.
808 
 
809 
2007-03-21  H.J. Lu
810 
 
811 
        * i386.h (REX_MODE64): Renamed to ...
812 
        (REX_W): This.
813 
        (REX_EXTX): Renamed to ...
814 
        (REX_R): This.
815 
        (REX_EXTY): Renamed to ...
816 
        (REX_X): This.
817 
        (REX_EXTZ): Renamed to ...
818 
        (REX_B): This.
819 
 
820 
2007-03-15  H.J. Lu
821 
 
822 
        * i386.h: Add entries from config/tc-i386.h and move tables
823 
        to opcodes/i386-opc.h.
824 
 
825 
2007-03-13  H.J. Lu
826 
 
827 
        * i386.h (FloatDR): Removed.
828 
        (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
829 
 
830 
2007-03-01  Alan Modra
831 
 
832 
        * spu-insns.h: Add soma double-float insns.
833 
 
834 
2007-02-20  Thiemo Seufer
835 
            Chao-Ying Fu
836 
 
837 
        * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
838 
        (INSN_DSPR2): Add flag for DSP R2 instructions.
839 
        (M_BALIGN): New macro.
840 
 
841 
2007-02-14  Alan Modra
842 
 
843 
        * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
844 
        and Seg3ShortFrom with Shortform.
845 
 
846 
2007-02-11  H.J. Lu
847 
 
848 
        PR gas/4027
849 
        * i386.h (i386_optab): Put the real "test" before the pseudo
850 
        one.
851 
 
852 
2007-01-08  Kazu Hirata
853 
 
854 
        * m68k.h (m68010up): OR fido_a.
855 
 
856 
2006-12-25  Kazu Hirata
857 
 
858 
        * m68k.h (fido_a): New.
859 
 
860 
2006-12-24  Kazu Hirata
861 
 
862 
        * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
863 
        mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
864 
        values.
865 
 
866 
2006-11-08  H.J. Lu
867 
 
868 
        * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
869 
 
870 
2006-10-31  Mei Ligang
871 
 
872 
        * score-inst.h (enum score_insn_type): Add Insn_internal.
873 
 
874 
2006-10-25  Trevor Smigiel
875 
            Yukishige Shibata
876 
            Nobuhisa Fujinami
877 
            Takeaki Fukuoka
878 
            Alan Modra
879 
 
880 
        * spu-insns.h: New file.
881 
        * spu.h: New file.
882 
 
883 
2006-10-24  Andrew Pinski
884 
 
885 
        * ppc.h (PPC_OPCODE_CELL): Define.
886 
 
887 
2006-10-23  Dwarakanath Rajagopal
888 
 
889 
        * i386.h :  Modify opcode to support for the change in POPCNT opcode
890 
        in amdfam10 architecture.
891 
 
892 
2006-09-28  H.J. Lu
893 
 
894 
        * i386.h: Replace CpuMNI with CpuSSSE3.
895 
 
896 
2006-09-26  Mark Shinwell
897 
            Joseph Myers
898 
            Ian Lance Taylor
899 
            Ben Elliston
900 
 
901 
        * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
902 
 
903 
2006-09-17  Mei Ligang
904 
 
905 
        * score-datadep.h: New file.
906 
        * score-inst.h: New file.
907 
 
908 
2006-07-14  H.J. Lu
909 
 
910 
        * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
911 
        movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
912 
        movdq2q and movq2dq.
913 
 
914 
2006-07-10 Dwarakanath Rajagopal
915 
           Michael Meissner
916 
 
917 
        * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
918 
 
919 
2006-06-12  H.J. Lu
920 
 
921 
        * i386.h (i386_optab): Add "nop" with memory reference.
922 
 
923 
2006-06-12  H.J. Lu
924 
 
925 
        * i386.h (i386_optab): Update comment for 64bit NOP.
926 
 
927 
2006-06-06  Ben Elliston
928 
            Anton Blanchard
929 
 
930 
        * ppc.h (PPC_OPCODE_POWER6): Define.
931 
        Adjust whitespace.
932 
 
933 
2006-06-05  Thiemo Seufer
934 
 
935 
        * mips.h: Improve description of MT flags.
936 
 
937 
2006-05-25  Richard Sandiford
938 
 
939 
        * m68k.h (mcf_mask): Define.
940 
 
941 
2006-05-05  Thiemo Seufer
942 
            David Ung
943 
 
944 
        * mips.h (enum): Add macro M_CACHE_AB.
945 
 
946 
2006-05-04  Thiemo Seufer
947 
            Nigel Stephens
948 
            David Ung
949 
 
950 
        * mips.h: Add INSN_SMARTMIPS define.
951 
 
952 
2006-04-30  Thiemo Seufer
953 
            David Ung
954 
 
955 
        * mips.h: Defines udi bits and masks.  Add description of
956 
        characters which may appear in the args field of udi
957 
        instructions.
958 
 
959 
2006-04-26  Thiemo Seufer
960 
 
961 
        * mips.h: Improve comments describing the bitfield instruction
962 
        fields.
963 
 
964 
2006-04-26  Julian Brown
965 
 
966 
        * arm.h (FPU_VFP_EXT_V3): Define constant.
967 
        (FPU_NEON_EXT_V1): Likewise.
968 
        (FPU_VFP_HARD): Update.
969 
        (FPU_VFP_V3): Define macro.
970 
        (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
971 
 
972 
2006-04-07  Joerg Wunsch
973 
 
974 
        * avr.h (AVR_ISA_PWMx): New.
975 
 
976 
2006-03-28  Nathan Sidwell
977 
 
978 
        * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
979 
        cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
980 
        cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
981 
        cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
982 
        cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
983 
 
984 
2006-03-10  Paul Brook
985 
 
986 
        * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
987 
 
988 
2006-03-04  John David Anglin
989 
 
990 
        * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
991 
        first.  Correct mask of bb "B" opcode.
992 
 
993 
2006-02-27  H.J. Lu
994 
 
995 
        * i386.h (i386_optab): Support Intel Merom New Instructions.
996 
 
997 
2006-02-24  Paul Brook
998 
 
999 
        * arm.h: Add V7 feature bits.
1000 
 
1001 
2006-02-23  H.J. Lu
1002 
 
1003 
        * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1004 
 
1005 
2006-01-31  Paul Brook
1006 
        Richard Earnshaw
1007 
 
1008 
        * arm.h: Use ARM_CPU_FEATURE.
1009 
        (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1010 
        (arm_feature_set): Change to a structure.
1011 
        (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1012 
        ARM_FEATURE): New macros.
1013 
 
1014 
2005-12-07  Hans-Peter Nilsson
1015 
 
1016 
        * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1017 
        (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1018 
        (ADD_PC_INCR_OPCODE): Don't define.
1019 
 
1020 
2005-12-06  H.J. Lu
1021 
 
1022 
        PR gas/1874
1023 
        * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1024 
 
1025 
2005-11-14  David Ung
1026 
 
1027 
        * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1028 
        instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1029 
        save/restore encoding of the args field.
1030 
 
1031 
2005-10-28  Dave Brolley
1032 
 
1033 
        Contribute the following changes:
1034 
        2005-02-16  Dave Brolley
1035 
 
1036 
        * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1037 
        cgen_isa_mask_* to cgen_bitset_*.
1038 
        * cgen.h: Likewise.
1039 
 
1040 
        2003-10-21  Richard Sandiford
1041 
 
1042 
        * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1043 
        (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1044 
        (CGEN_CPU_TABLE): Make isas a ponter.
1045 
 
1046 
        2003-09-29  Dave Brolley
1047 
 
1048 
        * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1049 
        (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1050 
        (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1051 
 
1052 
        2002-12-13  Dave Brolley
1053 
 
1054 
        * cgen.h (symcat.h): #include it.
1055 
        (cgen-bitset.h): #include it.
1056 
        (CGEN_ATTR_VALUE_TYPE): Now a union.
1057 
        (CGEN_ATTR_VALUE): Reference macros generated in opcodes/-desc.h.
1058 
        (CGEN_ATTR_ENTRY): 'value' now unsigned.
1059 
        (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1060 
        * cgen-bitset.h: New file.
1061 
 
1062 
2005-09-30  Catherine Moore
1063 
 
1064 
        * bfin.h: New file.
1065 
 
1066 
2005-10-24  Jan Beulich
1067 
 
1068 
        * ia64.h (enum ia64_opnd): Move memory operand out of set of
1069 
        indirect operands.
1070 
 
1071 
2005-10-16  John David Anglin
1072 
 
1073 
        * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1074 
        Add FLAG_STRICT to pa10 ftest opcode.
1075 
 
1076 
2005-10-12  John David Anglin
1077 
 
1078 
        * hppa.h (pa_opcodes): Remove lha entries.
1079 
 
1080 
2005-10-08  John David Anglin
1081 
 
1082 
        * hppa.h (FLAG_STRICT): Revise comment.
1083 
        (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1084 
        before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1085 
        entries for "fdc".
1086 
 
1087 
2005-09-30  Catherine Moore
1088 
 
1089 
        * bfin.h: New file.
1090 
 
1091 
2005-09-24  John David Anglin
1092 
 
1093 
        * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1094 
 
1095 
2005-09-06  Chao-ying Fu
1096 
 
1097 
        * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1098 
        OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1099 
        define.
1100 
        Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1101 
        (INSN_ASE_MASK): Update to include INSN_MT.
1102 
        (INSN_MT): New define for MT ASE.
1103 
 
1104 
2005-08-25  Chao-ying Fu
1105 
 
1106 
        * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1107 
        OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1108 
        OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1109 
        OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1110 
        OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1111 
        Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1112 
        instructions.
1113 
        (INSN_DSP): New define for DSP ASE.
1114 
 
1115 
2005-08-18  Alan Modra
1116 
 
1117 
        * a29k.h: Delete.
1118 
 
1119 
2005-08-15  Daniel Jacobowitz
1120 
 
1121 
        * ppc.h (PPC_OPCODE_E300): Define.
1122 
 
1123 
2005-08-12 Martin Schwidefsky
1124 
 
1125 
        * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1126 
 
1127 
2005-07-28  John David Anglin
1128 
 
1129 
        PR gas/336
1130 
        * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1131 
        and pitlb.
1132 
 
1133 
2005-07-27  Jan Beulich
1134 
 
1135 
        * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1136 
        movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1137 
        Add movq-s as 64-bit variants of movd-s.
1138 
 
1139 
2005-07-18  John David Anglin
1140 
 
1141 
        * hppa.h: Fix punctuation in comment.
1142 
 
1143 
        * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1144 
        implicit space-register addressing.  Set space-register bits on opcodes
1145 
        using implicit space-register addressing.  Add various missing pa20
1146 
        long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1147 
        space-register addressing.  Use "fE" instead of "fe" in various
1148 
        fstw opcodes.
1149 
 
1150 
2005-07-18  Jan Beulich
1151 
 
1152 
        * i386.h (i386_optab): Operands of aam and aad are unsigned.
1153 
 
1154 
2007-07-15  H.J. Lu
1155 
 
1156 
        * i386.h (i386_optab): Support Intel VMX Instructions.
1157 
 
1158 
2005-07-10  John David Anglin
1159 
 
1160 
        * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1161 
 
1162 
2005-07-05  Jan Beulich
1163 
 
1164 
        * i386.h (i386_optab): Add new insns.
1165 
 
1166 
2005-07-01  Nick Clifton
1167 
 
1168 
        * sparc.h: Add typedefs to structure declarations.
1169 
 
1170 
2005-06-20  H.J. Lu
1171 
 
1172 
        PR 1013
1173 
        * i386.h (i386_optab): Update comments for 64bit addressing on
1174 
        mov. Allow 64bit addressing for mov and movq.
1175 
 
1176 
2005-06-11  John David Anglin
1177 
 
1178 
        * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1179 
        respectively, in various floating-point load and store patterns.
1180 
 
1181 
2005-05-23  John David Anglin
1182 
 
1183 
        * hppa.h (FLAG_STRICT): Correct comment.
1184 
        (pa_opcodes): Update load and store entries to allow both PA 1.X and
1185 
        PA 2.0 mneumonics when equivalent.  Entries with cache control
1186 
        completers now require PA 1.1.  Adjust whitespace.
1187 
 
1188 
2005-05-19  Anton Blanchard
1189 
 
1190 
        * ppc.h (PPC_OPCODE_POWER5): Define.
1191 
 
1192 
2005-05-10  Nick Clifton
1193 
 
1194 
        * Update the address and phone number of the FSF organization in
1195 
        the GPL notices in the following files:
1196 
        a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1197 
        crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1198 
        i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1199 
        mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1200 
        pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1201 
        tic54x.h, tic80.h, v850.h, vax.h
1202 
 
1203 
2005-05-09  Jan Beulich
1204 
 
1205 
        * i386.h (i386_optab): Add ht and hnt.
1206 
 
1207 
2005-04-18  Mark Kettenis
1208 
 
1209 
        * i386.h: Insert hyphens into selected VIA PadLock extensions.
1210 
        Add xcrypt-ctr.  Provide aliases without hyphens.
1211 
 
1212 
2005-04-13  H.J. Lu
1213 
 
1214 
        Moved from ../ChangeLog
1215 
 
1216 
        2005-04-12  Paul Brook
1217 
        * m88k.h: Rename psr macros to avoid conflicts.
1218 
 
1219 
        2005-03-12  Zack Weinberg
1220 
        * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1221 
        Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1222 
        and ARM_ARCH_V6ZKT2.
1223 
 
1224 
        2004-11-29  Tomer Levi
1225 
        * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1226 
        Remove redundant instruction types.
1227 
        (struct argument): X_op - new field.
1228 
        (struct cst4_entry): Remove.
1229 
        (no_op_insn): Declare.
1230 
 
1231 
        2004-11-05  Tomer Levi
1232 
        * crx.h (enum argtype): Rename types, remove unused types.
1233 
 
1234 
        2004-10-27  Tomer Levi
1235 
        * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1236 
        (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1237 
        (enum operand_type): Rearrange operands, edit comments.
1238 
        replace us with ui for unsigned immediate.
1239 
        replace d with disps/dispu/dispe for signed/unsigned/escaped
1240 
        displacements (respectively).
1241 
        replace rbase_ridx_scl2_dispu with rindex_disps for register index.
1242 
        (instruction type): Add NO_TYPE_INS.
1243 
        (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1244 
        (operand_entry): New field - 'flags'.
1245 
        (operand flags): New.
1246 
 
1247 
        2004-10-21  Tomer Levi
1248 
        * crx.h (operand_type): Remove redundant types i3, i4,
1249 
        i5, i8, i12.
1250 
        Add new unsigned immediate types us3, us4, us5, us16.
1251 
 
1252 
2005-04-12  Mark Kettenis
1253 
 
1254 
        * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1255 
        adjust them accordingly.
1256 
 
1257 
2005-04-01  Jan Beulich
1258 
 
1259 
        * i386.h (i386_optab): Add rdtscp.
1260 
 
1261 
2005-03-29  H.J. Lu
1262 
 
1263 
        * i386.h (i386_optab): Don't allow the `l' suffix for moving
1264 
        between memory and segment register. Allow movq for moving between
1265 
        general-purpose register and segment register.
1266 
 
1267 
2005-02-09  Jan Beulich
1268 
 
1269 
        PR gas/707
1270 
        * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1271 
        FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1272 
        fnstsw.
1273 
 
1274 
2006-02-07  Nathan Sidwell
1275 
 
1276 
        * m68k.h (m68008, m68ec030, m68882): Remove.
1277 
        (m68k_mask): New.
1278 
        (cpu_m68k, cpu_cf): New.
1279 
        (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1280 
        mcf5470, mcf5480): Rename to cpu_. Add m680x0 variants.
1281 
 
1282 
2005-01-25  Alexandre Oliva
1283 
 
1284 
        2004-11-10  Alexandre Oliva
1285 
        * cgen.h (enum cgen_parse_operand_type): Add
1286 
        CGEN_PARSE_OPERAND_SYMBOLIC.
1287 
 
1288 
2005-01-21  Fred Fish
1289 
 
1290 
        * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1291 
        Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1292 
        Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1293 
 
1294 
2005-01-19  Fred Fish
1295 
 
1296 
        * mips.h (struct mips_opcode): Add new pinfo2 member.
1297 
        (INSN_ALIAS): New define for opcode table entries that are
1298 
        specific instances of another entry, such as 'move' for an 'or'
1299 
        with a zero operand.
1300 
        (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1301 
        (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1302 
 
1303 
2004-12-09  Ian Lance Taylor
1304 
 
1305 
        * mips.h (CPU_RM9000): Define.
1306 
        (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1307 
 
1308 
2004-11-25 Jan Beulich
1309 
 
1310 
        * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1311 
        to/from test registers are illegal in 64-bit mode. Add missing
1312 
        NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1313 
        (previously one had to explicitly encode a rex64 prefix). Re-enable
1314 
        lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1315 
        support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1316 
 
1317 
2004-11-23 Jan Beulich
1318 
 
1319 
        * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1320 
        available only with SSE2. Change the MMX additions introduced by SSE
1321 
        and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1322 
        instructions by their now designated identifier (since combining i686
1323 
        and 3DNow! does not really imply 3DNow!A).
1324 
 
1325 
2004-11-19  Alan Modra
1326 
 
1327 
        * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1328 
        struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1329 
 
1330 
2004-11-08  Inderpreet Singh
1331 
            Vineet Sharma
1332 
 
1333 
        * maxq.h: New file: Disassembly information for the maxq port.
1334 
 
1335 
2004-11-05  H.J. Lu
1336 
 
1337 
        * i386.h (i386_optab): Put back "movzb".
1338 
 
1339 
2004-11-04  Hans-Peter Nilsson
1340 
 
1341 
        * cris.h (enum cris_insn_version_usage): Tweak formatting and
1342 
        comments.  Remove member cris_ver_sim.  Add members
1343 
        cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1344 
        cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1345 
        (struct cris_support_reg, struct cris_cond15): New types.
1346 
        (cris_conds15): Declare.
1347 
        (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1348 
        (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1349 
        (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1350 
        (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1351 
        (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1352 
        SIZE_FIELD_UNSIGNED.
1353 
 
1354 
2004-11-04 Jan Beulich
1355 
 
1356 
        * i386.h (sldx_Suf): Remove.
1357 
        (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1358 
        (q_FP): Define, implying no REX64.
1359 
        (x_FP, sl_FP): Imply FloatMF.
1360 
        (i386_optab): Split reg and mem forms of moving from segment registers
1361 
        so that the memory forms can ignore the 16-/32-bit operand size
1362 
        distinction. Adjust a few others for Intel mode. Remove *FP uses from
1363 
        all non-floating-point instructions. Unite 32- and 64-bit forms of
1364 
        movsx, movzx, and movd. Adjust floating point operations for the above
1365 
        changes to the *FP macros. Add DefaultSize to floating point control
1366 
        insns operating on larger memory ranges. Remove left over comments
1367 
        hinting at certain insns being Intel-syntax ones where the ones
1368 
        actually meant are already gone.
1369 
 
1370 
2004-10-07  Tomer Levi
1371 
 
1372 
        * crx.h: Add COPS_REG_INS - Coprocessor Special register
1373 
        instruction type.
1374 
 
1375 
2004-09-30  Paul Brook
1376 
 
1377 
        * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1378 
        (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1379 
 
1380 
2004-09-11  Theodore A. Roth
1381 
 
1382 
        * avr.h: Add support for
1383 
        atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1384 
 
1385 
2004-09-09  Segher Boessenkool
1386 
 
1387 
        * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1388 
 
1389 
2004-08-24  Dmitry Diky
1390 
 
1391 
        * msp430.h (msp430_opc): Add new instructions.
1392 
        (msp430_rcodes): Declare new instructions.
1393 
        (msp430_hcodes): Likewise..
1394 
 
1395 
2004-08-13  Nick Clifton
1396 
 
1397 
        PR/301
1398 
        * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1399 
        processors.
1400 
 
1401 
2004-08-30  Michal Ludvig
1402 
 
1403 
        * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1404 
 
1405 
2004-07-22  H.J. Lu
1406 
 
1407 
        * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1408 
 
1409 
2004-07-21  Jan Beulich
1410 
 
1411 
        * i386.h: Adjust instruction descriptions to better match the
1412 
        specification.
1413 
 
1414 
2004-07-16  Richard Earnshaw
1415 
 
1416 
        * arm.h: Remove all old content.  Replace with architecture defines
1417 
        from gas/config/tc-arm.c.
1418 
 
1419 
2004-07-09  Andreas Schwab
1420 
 
1421 
        * m68k.h: Fix comment.
1422 
 
1423 
2004-07-07  Tomer Levi
1424 
 
1425 
        * crx.h: New file.
1426 
 
1427 
2004-06-24  Alan Modra
1428 
 
1429 
        * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1430 
 
1431 
2004-05-24  Peter Barada
1432 
 
1433 
        * m68k.h: Add 'size' to m68k_opcode.
1434 
 
1435 
2004-05-05  Peter Barada
1436 
 
1437 
        * m68k.h: Switch from ColdFire chip name to core variant.
1438 
 
1439 
2004-04-22  Peter Barada
1440 
 
1441 
        * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1442 
        descriptions for new EMAC cases.
1443 
        Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1444 
        handle Motorola MAC syntax.
1445 
        Allow disassembly of ColdFire V4e object files.
1446 
 
1447 
2004-03-16  Alan Modra
1448 
 
1449 
        * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1450 
 
1451 
2004-03-12  Jakub Jelinek
1452 
 
1453 
        * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1454 
 
1455 
2004-03-12  Michal Ludvig
1456 
 
1457 
        * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1458 
 
1459 
2004-03-12  Michal Ludvig
1460 
 
1461 
        * i386.h (i386_optab): Added xstore/xcrypt insns.
1462 
 
1463 
2004-02-09  Anil Paranjpe
1464 
 
1465 
        * h8300.h (32bit ldc/stc): Add relaxing support.
1466 
 
1467 
2004-01-12  Anil Paranjpe
1468 
 
1469 
        * h8300.h (BITOP): Pass MEMRELAX flag.
1470 
 
1471 
2004-01-09  Anil Paranjpe
1472 
 
1473 
        * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1474 
        except for the H8S.
1475 
 
1476 
For older changes see ChangeLog-9103
1477 
 
1478 
Local Variables:
1479 
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1480 
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1481 
fill-column: 74
1482 
version-control: never
1483 
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