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/* Header file for targets using CGEN: Cpu tools GENerator.
2
 
3
   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2009, 2010
4
   Free Software Foundation, Inc.
5
 
6
   This file is part of GDB, the GNU debugger, and the GNU Binutils.
7
 
8
   This program is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3 of the License, or
11
   (at your option) any later version.
12
 
13
   This program is distributed in the hope that it will be useful,
14
   but WITHOUT ANY WARRANTY; without even the implied warranty of
15
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
   GNU General Public License for more details.
17
 
18
   You should have received a copy of the GNU General Public License along
19
   with this program; if not, write to the Free Software Foundation, Inc.,
20
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
21
 
22
#ifndef OPCODE_CGEN_H
23
#define OPCODE_CGEN_H
24
 
25
#include "symcat.h"
26
#include "cgen/bitset.h"
27
 
28
/* ??? IWBN to replace bfd in the name.  */
29
#include "bfd_stdint.h"
30
 
31
/* ??? This file requires bfd.h but only to get bfd_vma.
32
   Seems like an awful lot to require just to get such a fundamental type.
33
   Perhaps the definition of bfd_vma can be moved outside of bfd.h.
34
   Or perhaps one could duplicate its definition in another file.
35
   Until such time, this file conditionally compiles definitions that require
36
   bfd_vma using __BFD_H_SEEN__.  */
37
 
38
/* Enums must be defined before they can be used.
39
   Allow them to be used in struct definitions, even though the enum must
40
   be defined elsewhere.
41
   If CGEN_ARCH isn't defined, this file is being included by something other
42
   than <arch>-desc.h.  */
43
 
44
/* Prepend the arch name, defined in <arch>-desc.h, and _cgen_ to symbol S.
45
   The lack of spaces in the arg list is important for non-stdc systems.
46
   This file is included by <arch>-desc.h.
47
   It can be included independently of <arch>-desc.h, in which case the arch
48
   dependent portions will be declared as "unknown_cgen_foo".  */
49
 
50
#ifndef CGEN_SYM
51
#define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s)
52
#endif
53
 
54
/* This file contains the static (unchanging) pieces and as much other stuff
55
   as we can reasonably put here.  It's generally cleaner to put stuff here
56
   rather than having it machine generated if possible.  */
57
 
58
/* The assembler syntax is made up of expressions (duh...).
59
   At the lowest level the values are mnemonics, register names, numbers, etc.
60
   Above that are subexpressions, if any (an example might be the
61
   "effective address" in m68k cpus).  Subexpressions are wip.
62
   At the second highest level are the insns themselves.  Above that are
63
   pseudo-insns, synthetic insns, and macros, if any.  */
64
 
65
/* Lots of cpu's have a fixed insn size, or one which rarely changes,
66
   and it's generally easier to handle these by treating the insn as an
67
   integer type, rather than an array of characters.  So we allow targets
68
   to control this.  When an integer type the value is in host byte order,
69
   when an array of characters the value is in target byte order.  */
70
 
71
typedef unsigned int CGEN_INSN_INT;
72
typedef int64_t CGEN_INSN_LGSINT; /* large/long SINT */
73
typedef uint64_t CGEN_INSN_LGUINT; /* large/long UINT */
74
 
75
#if CGEN_INT_INSN_P
76
typedef CGEN_INSN_INT CGEN_INSN_BYTES;
77
typedef CGEN_INSN_INT *CGEN_INSN_BYTES_PTR;
78
#else
79
typedef unsigned char *CGEN_INSN_BYTES;
80
typedef unsigned char *CGEN_INSN_BYTES_PTR;
81
#endif
82
 
83
#ifdef __GNUC__
84
#define CGEN_INLINE __inline__
85
#else
86
#define CGEN_INLINE
87
#endif
88
 
89
enum cgen_endian
90
{
91
  CGEN_ENDIAN_UNKNOWN,
92
  CGEN_ENDIAN_LITTLE,
93
  CGEN_ENDIAN_BIG
94
};
95
 
96
/* Forward decl.  */
97
 
98
typedef struct cgen_insn CGEN_INSN;
99
 
100
/* Opaque pointer version for use by external world.  */
101
 
102
typedef struct cgen_cpu_desc *CGEN_CPU_DESC;
103
 
104
/* Attributes.
105
   Attributes are used to describe various random things associated with
106
   an object (ifield, hardware, operand, insn, whatever) and are specified
107
   as name/value pairs.
108
   Integer attributes computed at compile time are currently all that's
109
   supported, though adding string attributes and run-time computation is
110
   straightforward.  Integer attribute values are always host int's
111
   (signed or unsigned).  For portability, this means 32 bits.
112
   Integer attributes are further categorized as boolean, bitset, integer,
113
   and enum types.  Boolean attributes appear frequently enough that they're
114
   recorded in one host int.  This limits the maximum number of boolean
115
   attributes to 32, though that's a *lot* of attributes.  */
116
 
117
/* Type of attribute values.  */
118
 
119
typedef CGEN_BITSET     CGEN_ATTR_VALUE_BITSET_TYPE;
120
typedef int             CGEN_ATTR_VALUE_ENUM_TYPE;
121
typedef union
122
{
123
  CGEN_ATTR_VALUE_BITSET_TYPE bitset;
124
  CGEN_ATTR_VALUE_ENUM_TYPE   nonbitset;
125
} CGEN_ATTR_VALUE_TYPE;
126
 
127
/* Struct to record attribute information.  */
128
 
129
typedef struct
130
{
131
  /* Boolean attributes.  */
132
  unsigned int bool_;
133
  /* Non-boolean integer attributes.  */
134
  CGEN_ATTR_VALUE_TYPE nonbool[1];
135
} CGEN_ATTR;
136
 
137
/* Define a structure member for attributes with N non-boolean entries.
138
   There is no maximum number of non-boolean attributes.
139
   There is a maximum of 32 boolean attributes (since they are all recorded
140
   in one host int).  */
141
 
142
#define CGEN_ATTR_TYPE(n) \
143
struct { unsigned int bool_; \
144
         CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; }
145
 
146
/* Return the boolean attributes.  */
147
 
148
#define CGEN_ATTR_BOOLS(a) ((a)->bool_)
149
 
150
/* Non-boolean attribute numbers are offset by this much.  */
151
 
152
#define CGEN_ATTR_NBOOL_OFFSET 32
153
 
154
/* Given a boolean attribute number, return its mask.  */
155
 
156
#define CGEN_ATTR_MASK(attr) (1 << (attr))
157
 
158
/* Return the value of boolean attribute ATTR in ATTRS.  */
159
 
160
#define CGEN_BOOL_ATTR(attrs, attr) ((CGEN_ATTR_MASK (attr) & (attrs)) != 0)
161
 
162
/* Return value of attribute ATTR in ATTR_TABLE for OBJ.
163
   OBJ is a pointer to the entity that has the attributes
164
   (??? not used at present but is reserved for future purposes - eventually
165
   the goal is to allow recording attributes in source form and computing
166
   them lazily at runtime, not sure of the details yet).  */
167
 
168
#define CGEN_ATTR_VALUE(obj, attr_table, attr) \
169
((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \
170
 ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \
171
 : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].nonbitset))
172
#define CGEN_BITSET_ATTR_VALUE(obj, attr_table, attr) \
173
 ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset)
174
 
175
/* Attribute name/value tables.
176
   These are used to assist parsing of descriptions at run-time.  */
177
 
178
typedef struct
179
{
180
  const char * name;
181
  unsigned value;
182
} CGEN_ATTR_ENTRY;
183
 
184
/* For each domain (ifld,hw,operand,insn), list of attributes.  */
185
 
186
typedef struct
187
{
188
  const char * name;
189
  const CGEN_ATTR_ENTRY * dfault;
190
  const CGEN_ATTR_ENTRY * vals;
191
} CGEN_ATTR_TABLE;
192
 
193
/* Instruction set variants.  */
194
 
195
typedef struct {
196
  const char *name;
197
 
198
  /* Default instruction size (in bits).
199
     This is used by the assembler when it encounters an unknown insn.  */
200
  unsigned int default_insn_bitsize;
201
 
202
  /* Base instruction size (in bits).
203
     For non-LIW cpus this is generally the length of the smallest insn.
204
     For LIW cpus its wip (work-in-progress).  For the m32r its 32.  */
205
  unsigned int base_insn_bitsize;
206
 
207
  /* Minimum/maximum instruction size (in bits).  */
208
  unsigned int min_insn_bitsize;
209
  unsigned int max_insn_bitsize;
210
} CGEN_ISA;
211
 
212
/* Machine variants.  */
213
 
214
typedef struct {
215
  const char *name;
216
  /* The argument to bfd_arch_info->scan.  */
217
  const char *bfd_name;
218
  /* one of enum mach_attr */
219
  int num;
220
  /* parameter from mach->cpu */
221
  unsigned int insn_chunk_bitsize;
222
} CGEN_MACH;
223
 
224
/* Parse result (also extraction result).
225
 
226
   The result of parsing an insn is stored here.
227
   To generate the actual insn, this is passed to the insert handler.
228
   When printing an insn, the result of extraction is stored here.
229
   To print the insn, this is passed to the print handler.
230
 
231
   It is machine generated so we don't define it here,
232
   but we do need a forward decl for the handler fns.
233
 
234
   There is one member for each possible field in the insn.
235
   The type depends on the field.
236
   Also recorded here is the computed length of the insn for architectures
237
   where it varies.
238
*/
239
 
240
typedef struct cgen_fields CGEN_FIELDS;
241
 
242
/* Total length of the insn, as recorded in the `fields' struct.  */
243
/* ??? The field insert handler has lots of opportunities for optimization
244
   if it ever gets inlined.  On architectures where insns all have the same
245
   size, may wish to detect that and make this macro a constant - to allow
246
   further optimizations.  */
247
 
248
#define CGEN_FIELDS_BITSIZE(fields) ((fields)->length)
249
 
250
/* Extraction support for variable length insn sets.  */
251
 
252
/* When disassembling we don't know the number of bytes to read at the start.
253
   So the first CGEN_BASE_INSN_SIZE bytes are read at the start and the rest
254
   are read when needed.  This struct controls this.  It is basically the
255
   disassemble_info stuff, except that we provide a cache for values already
256
   read (since bytes can typically be read several times to fetch multiple
257
   operands that may be in them), and that extraction of fields is needed
258
   in contexts other than disassembly.  */
259
 
260
typedef struct {
261
  /* A pointer to the disassemble_info struct.
262
     We don't require dis-asm.h so we use void * for the type here.
263
     If NULL, BYTES is full of valid data (VALID == -1).  */
264
  void *dis_info;
265
  /* Points to a working buffer of sufficient size.  */
266
  unsigned char *insn_bytes;
267
  /* Mask of bytes that are valid in INSN_BYTES.  */
268
  unsigned int valid;
269
} CGEN_EXTRACT_INFO;
270
 
271
/* Associated with each insn or expression is a set of "handlers" for
272
   performing operations like parsing, printing, etc.  These require a bfd_vma
273
   value to be passed around but we don't want all applications to need bfd.h.
274
   So this stuff is only provided if bfd.h has been included.  */
275
 
276
/* Parse handler.
277
   CD is a cpu table descriptor.
278
   INSN is a pointer to a struct describing the insn being parsed.
279
   STRP is a pointer to a pointer to the text being parsed.
280
   FIELDS is a pointer to a cgen_fields struct in which the results are placed.
281
   If the expression is successfully parsed, *STRP is updated.
282
   If not it is left alone.
283
   The result is NULL if success or an error message.  */
284
typedef const char * (cgen_parse_fn)
285
  (CGEN_CPU_DESC, const CGEN_INSN *insn_,
286
   const char **strp_, CGEN_FIELDS *fields_);
287
 
288
/* Insert handler.
289
   CD is a cpu table descriptor.
290
   INSN is a pointer to a struct describing the insn being parsed.
291
   FIELDS is a pointer to a cgen_fields struct from which the values
292
   are fetched.
293
   INSNP is a pointer to a buffer in which to place the insn.
294
   PC is the pc value of the insn.
295
   The result is an error message or NULL if success.  */
296
 
297
#ifdef __BFD_H_SEEN__
298
typedef const char * (cgen_insert_fn)
299
  (CGEN_CPU_DESC, const CGEN_INSN *insn_,
300
   CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_,
301
   bfd_vma pc_);
302
#else
303
typedef const char * (cgen_insert_fn) ();
304
#endif
305
 
306
/* Extract handler.
307
   CD is a cpu table descriptor.
308
   INSN is a pointer to a struct describing the insn being parsed.
309
   The second argument is a pointer to a struct controlling extraction
310
   (only used for variable length insns).
311
   EX_INFO is a pointer to a struct for controlling reading of further
312
   bytes for the insn.
313
   BASE_INSN is the first CGEN_BASE_INSN_SIZE bytes (host order).
314
   FIELDS is a pointer to a cgen_fields struct in which the results are placed.
315
   PC is the pc value of the insn.
316
   The result is the length of the insn in bits or zero if not recognized.  */
317
 
318
#ifdef __BFD_H_SEEN__
319
typedef int (cgen_extract_fn)
320
  (CGEN_CPU_DESC, const CGEN_INSN *insn_,
321
   CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_,
322
   CGEN_FIELDS *fields_, bfd_vma pc_);
323
#else
324
typedef int (cgen_extract_fn) ();
325
#endif
326
 
327
/* Print handler.
328
   CD is a cpu table descriptor.
329
   INFO is a pointer to the disassembly info.
330
   Eg: disassemble_info.  It's defined as `PTR' so this file can be included
331
   without dis-asm.h.
332
   INSN is a pointer to a struct describing the insn being printed.
333
   FIELDS is a pointer to a cgen_fields struct.
334
   PC is the pc value of the insn.
335
   LEN is the length of the insn, in bits.  */
336
 
337
#ifdef __BFD_H_SEEN__
338
typedef void (cgen_print_fn)
339
  (CGEN_CPU_DESC, void * info_, const CGEN_INSN *insn_,
340
   CGEN_FIELDS *fields_, bfd_vma pc_, int len_);
341
#else
342
typedef void (cgen_print_fn) ();
343
#endif
344
 
345
/* Parse/insert/extract/print handlers.
346
 
347
   Indices into the handler tables.
348
   We could use pointers here instead, but 90% of them are generally identical
349
   and that's a lot of redundant data.  Making these unsigned char indices
350
   into tables of pointers saves a bit of space.
351
   Using indices also keeps assembler code out of the disassembler and
352
   vice versa.  */
353
 
354
struct cgen_opcode_handler
355
{
356
  unsigned char parse, insert, extract, print;
357
};
358
 
359
/* Assembler interface.
360
 
361
   The interface to the assembler is intended to be clean in the sense that
362
   libopcodes.a is a standalone entity and could be used with any assembler.
363
   Not that one would necessarily want to do that but rather that it helps
364
   keep a clean interface.  The interface will obviously be slanted towards
365
   GAS, but at least it's a start.
366
   ??? Note that one possible user of the assembler besides GAS is GDB.
367
 
368
   Parsing is controlled by the assembler which calls
369
   CGEN_SYM (assemble_insn).  If it can parse and build the entire insn
370
   it doesn't call back to the assembler.  If it needs/wants to call back
371
   to the assembler, cgen_parse_operand_fn is called which can either
372
 
373
   - return a number to be inserted in the insn
374
   - return a "register" value to be inserted
375
     (the register might not be a register per pe)
376
   - queue the argument and return a marker saying the expression has been
377
     queued (eg: a fix-up)
378
   - return an error message indicating the expression wasn't recognizable
379
 
380
   The result is an error message or NULL for success.
381
   The parsed value is stored in the bfd_vma *.  */
382
 
383
/* Values for indicating what the caller wants.  */
384
 
385
enum cgen_parse_operand_type
386
{
387
  CGEN_PARSE_OPERAND_INIT,
388
  CGEN_PARSE_OPERAND_INTEGER,
389
  CGEN_PARSE_OPERAND_ADDRESS,
390
  CGEN_PARSE_OPERAND_SYMBOLIC
391
};
392
 
393
/* Values for indicating what was parsed.  */
394
 
395
enum cgen_parse_operand_result
396
{
397
  CGEN_PARSE_OPERAND_RESULT_NUMBER,
398
  CGEN_PARSE_OPERAND_RESULT_REGISTER,
399
  CGEN_PARSE_OPERAND_RESULT_QUEUED,
400
  CGEN_PARSE_OPERAND_RESULT_ERROR
401
};
402
 
403
#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily.  */
404
typedef const char * (cgen_parse_operand_fn)
405
  (CGEN_CPU_DESC,
406
   enum cgen_parse_operand_type, const char **, int, int,
407
   enum cgen_parse_operand_result *, bfd_vma *);
408
#else
409
typedef const char * (cgen_parse_operand_fn) ();
410
#endif
411
 
412
/* Set the cgen_parse_operand_fn callback.  */
413
 
414
extern void cgen_set_parse_operand_fn
415
  (CGEN_CPU_DESC, cgen_parse_operand_fn);
416
 
417
/* Called before trying to match a table entry with the insn.  */
418
 
419
extern void cgen_init_parse_operand (CGEN_CPU_DESC);
420
 
421
/* Operand values (keywords, integers, symbols, etc.)  */
422
 
423
/* Types of assembler elements.  */
424
 
425
enum cgen_asm_type
426
{
427
  CGEN_ASM_NONE, CGEN_ASM_KEYWORD, CGEN_ASM_MAX
428
};
429
 
430
#ifndef CGEN_ARCH
431
enum cgen_hw_type { CGEN_HW_MAX };
432
#endif
433
 
434
/* List of hardware elements.  */
435
 
436
typedef struct
437
{
438
  char *name;
439
  enum cgen_hw_type type;
440
  /* There is currently no example where both index specs and value specs
441
     are required, so for now both are clumped under "asm_data".  */
442
  enum cgen_asm_type asm_type;
443
  void *asm_data;
444
#ifndef CGEN_HW_NBOOL_ATTRS
445
#define CGEN_HW_NBOOL_ATTRS 1
446
#endif
447
  CGEN_ATTR_TYPE (CGEN_HW_NBOOL_ATTRS) attrs;
448
#define CGEN_HW_ATTRS(hw) (&(hw)->attrs)
449
} CGEN_HW_ENTRY;
450
 
451
/* Return value of attribute ATTR in HW.  */
452
 
453
#define CGEN_HW_ATTR_VALUE(hw, attr) \
454
CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr))
455
 
456
/* Table of hardware elements for selected mach, computed at runtime.
457
   enum cgen_hw_type is an index into this table (specifically `entries').  */
458
 
459
typedef struct {
460
  /* Pointer to null terminated table of all compiled in entries.  */
461
  const CGEN_HW_ENTRY *init_entries;
462
  unsigned int entry_size; /* since the attribute member is variable sized */
463
  /* Array of all entries, initial and run-time added.  */
464
  const CGEN_HW_ENTRY **entries;
465
  /* Number of elements in `entries'.  */
466
  unsigned int num_entries;
467
  /* For now, xrealloc is called each time a new entry is added at runtime.
468
     ??? May wish to keep track of some slop to reduce the number of calls to
469
     xrealloc, except that there's unlikely to be many and not expected to be
470
     in speed critical code.  */
471
} CGEN_HW_TABLE;
472
 
473
extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name
474
  (CGEN_CPU_DESC, const char *);
475
extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num
476
  (CGEN_CPU_DESC, unsigned int);
477
 
478
/* This struct is used to describe things like register names, etc.  */
479
 
480
typedef struct cgen_keyword_entry
481
{
482
  /* Name (as in register name).  */
483
  char * name;
484
 
485
  /* Value (as in register number).
486
     The value cannot be -1 as that is used to indicate "not found".
487
     IDEA: Have "FUNCTION" attribute? [function is called to fetch value].  */
488
  int value;
489
 
490
  /* Attributes.
491
     This should, but technically needn't, appear last.  It is a variable sized
492
     array in that one architecture may have 1 nonbool attribute and another
493
     may have more.  Having this last means the non-architecture specific code
494
     needn't care.  The goal is to eventually record
495
     attributes in their raw form, evaluate them at run-time, and cache the
496
     values, so this worry will go away anyway.  */
497
  /* ??? Moving this last should be done by treating keywords like insn lists
498
     and moving the `next' fields into a CGEN_KEYWORD_LIST struct.  */
499
  /* FIXME: Not used yet.  */
500
#ifndef CGEN_KEYWORD_NBOOL_ATTRS
501
#define CGEN_KEYWORD_NBOOL_ATTRS 1
502
#endif
503
  CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs;
504
 
505
  /* ??? Putting these here means compiled in entries can't be const.
506
     Not a really big deal, but something to consider.  */
507
  /* Next name hash table entry.  */
508
  struct cgen_keyword_entry *next_name;
509
  /* Next value hash table entry.  */
510
  struct cgen_keyword_entry *next_value;
511
} CGEN_KEYWORD_ENTRY;
512
 
513
/* Top level struct for describing a set of related keywords
514
   (e.g. register names).
515
 
516
   This struct supports run-time entry of new values, and hashed lookups.  */
517
 
518
typedef struct cgen_keyword
519
{
520
  /* Pointer to initial [compiled in] values.  */
521
  CGEN_KEYWORD_ENTRY *init_entries;
522
 
523
  /* Number of entries in `init_entries'.  */
524
  unsigned int num_init_entries;
525
 
526
  /* Hash table used for name lookup.  */
527
  CGEN_KEYWORD_ENTRY **name_hash_table;
528
 
529
  /* Hash table used for value lookup.  */
530
  CGEN_KEYWORD_ENTRY **value_hash_table;
531
 
532
  /* Number of entries in the hash_tables.  */
533
  unsigned int hash_table_size;
534
 
535
  /* Pointer to null keyword "" entry if present.  */
536
  const CGEN_KEYWORD_ENTRY *null_entry;
537
 
538
  /* String containing non-alphanumeric characters used
539
     in keywords.
540
     At present, the highest number of entries used is 1.  */
541
  char nonalpha_chars[8];
542
} CGEN_KEYWORD;
543
 
544
/* Structure used for searching.  */
545
 
546
typedef struct
547
{
548
  /* Table being searched.  */
549
  const CGEN_KEYWORD *table;
550
 
551
  /* Specification of what is being searched for.  */
552
  const char *spec;
553
 
554
  /* Current index in hash table.  */
555
  unsigned int current_hash;
556
 
557
  /* Current element in current hash chain.  */
558
  CGEN_KEYWORD_ENTRY *current_entry;
559
} CGEN_KEYWORD_SEARCH;
560
 
561
/* Lookup a keyword from its name.  */
562
 
563
const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_name
564
  (CGEN_KEYWORD *, const char *);
565
 
566
/* Lookup a keyword from its value.  */
567
 
568
const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_value
569
  (CGEN_KEYWORD *, int);
570
 
571
/* Add a keyword.  */
572
 
573
void cgen_keyword_add (CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *);
574
 
575
/* Keyword searching.
576
   This can be used to retrieve every keyword, or a subset.  */
577
 
578
CGEN_KEYWORD_SEARCH cgen_keyword_search_init
579
  (CGEN_KEYWORD *, const char *);
580
const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next
581
  (CGEN_KEYWORD_SEARCH *);
582
 
583
/* Operand value support routines.  */
584
 
585
extern const char *cgen_parse_keyword
586
  (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
587
#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily.  */
588
extern const char *cgen_parse_signed_integer
589
  (CGEN_CPU_DESC, const char **, int, long *);
590
extern const char *cgen_parse_unsigned_integer
591
  (CGEN_CPU_DESC, const char **, int, unsigned long *);
592
extern const char *cgen_parse_address
593
  (CGEN_CPU_DESC, const char **, int, int,
594
   enum cgen_parse_operand_result *, bfd_vma *);
595
extern const char *cgen_validate_signed_integer
596
  (long, long, long);
597
extern const char *cgen_validate_unsigned_integer
598
  (unsigned long, unsigned long, unsigned long);
599
#endif
600
 
601
/* Operand modes.  */
602
 
603
/* ??? This duplicates the values in arch.h.  Revisit.
604
   These however need the CGEN_ prefix [as does everything in this file].  */
605
/* ??? Targets may need to add their own modes so we may wish to move this
606
   to <arch>-opc.h, or add a hook.  */
607
 
608
enum cgen_mode {
609
  CGEN_MODE_VOID, /* ??? rename simulator's VM to VOID? */
610
  CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI,
611
  CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI,
612
  CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF,
613
  CGEN_MODE_TARGET_MAX,
614
  CGEN_MODE_INT, CGEN_MODE_UINT,
615
  CGEN_MODE_MAX
616
};
617
 
618
/* FIXME: Until simulator is updated.  */
619
 
620
#define CGEN_MODE_VM CGEN_MODE_VOID
621
 
622
/* Operands.  */
623
 
624
#ifndef CGEN_ARCH
625
enum cgen_operand_type { CGEN_OPERAND_MAX };
626
#endif
627
 
628
/* "nil" indicator for the operand instance table */
629
#define CGEN_OPERAND_NIL CGEN_OPERAND_MAX
630
 
631
/* A tree of these structs represents the multi-ifield
632
   structure of an operand's hw-index value, if it exists.  */
633
 
634
struct cgen_ifld;
635
 
636
typedef struct cgen_maybe_multi_ifield
637
{
638
  int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry);
639
                n: indexed by array of more cgen_maybe_multi_ifields.  */
640
  union
641
  {
642
    const void *p;
643
    const struct cgen_maybe_multi_ifield * multi;
644
    const struct cgen_ifld * leaf;
645
  } val;
646
}
647
CGEN_MAYBE_MULTI_IFLD;
648
 
649
/* This struct defines each entry in the operand table.  */
650
 
651
typedef struct
652
{
653
  /* Name as it appears in the syntax string.  */
654
  char *name;
655
 
656
  /* Operand type.  */
657
  enum cgen_operand_type type;
658
 
659
  /* The hardware element associated with this operand.  */
660
  enum cgen_hw_type hw_type;
661
 
662
  /* FIXME: We don't yet record ifield definitions, which we should.
663
     When we do it might make sense to delete start/length (since they will
664
     be duplicated in the ifield's definition) and replace them with a
665
     pointer to the ifield entry.  */
666
 
667
  /* Bit position.
668
     This is just a hint, and may be unused in more complex operands.
669
     May be unused for a modifier.  */
670
  unsigned char start;
671
 
672
  /* The number of bits in the operand.
673
     This is just a hint, and may be unused in more complex operands.
674
     May be unused for a modifier.  */
675
  unsigned char length;
676
 
677
  /* The (possibly-multi) ifield used as an index for this operand, if it
678
     is indexed by a field at all. This substitutes / extends the start and
679
     length fields above, but unsure at this time whether they are used
680
     anywhere.  */
681
  CGEN_MAYBE_MULTI_IFLD index_fields;
682
#if 0 /* ??? Interesting idea but relocs tend to get too complicated,
683
         and ABI dependent, for simple table lookups to work.  */
684
  /* Ideally this would be the internal (external?) reloc type.  */
685
  int reloc_type;
686
#endif
687
 
688
  /* Attributes.
689
     This should, but technically needn't, appear last.  It is a variable sized
690
     array in that one architecture may have 1 nonbool attribute and another
691
     may have more.  Having this last means the non-architecture specific code
692
     needn't care, now or tomorrow.  The goal is to eventually record
693
     attributes in their raw form, evaluate them at run-time, and cache the
694
     values, so this worry will go away anyway.  */
695
#ifndef CGEN_OPERAND_NBOOL_ATTRS
696
#define CGEN_OPERAND_NBOOL_ATTRS 1
697
#endif
698
  CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS) attrs;
699
#define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs)
700
} CGEN_OPERAND;
701
 
702
/* Return value of attribute ATTR in OPERAND.  */
703
 
704
#define CGEN_OPERAND_ATTR_VALUE(operand, attr) \
705
CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr))
706
 
707
/* Table of operands for selected mach/isa, computed at runtime.
708
   enum cgen_operand_type is an index into this table (specifically
709
   `entries').  */
710
 
711
typedef struct {
712
  /* Pointer to null terminated table of all compiled in entries.  */
713
  const CGEN_OPERAND *init_entries;
714
  unsigned int entry_size; /* since the attribute member is variable sized */
715
  /* Array of all entries, initial and run-time added.  */
716
  const CGEN_OPERAND **entries;
717
  /* Number of elements in `entries'.  */
718
  unsigned int num_entries;
719
  /* For now, xrealloc is called each time a new entry is added at runtime.
720
     ??? May wish to keep track of some slop to reduce the number of calls to
721
     xrealloc, except that there's unlikely to be many and not expected to be
722
     in speed critical code.  */
723
} CGEN_OPERAND_TABLE;
724
 
725
extern const CGEN_OPERAND * cgen_operand_lookup_by_name
726
  (CGEN_CPU_DESC, const char *);
727
extern const CGEN_OPERAND * cgen_operand_lookup_by_num
728
  (CGEN_CPU_DESC, int);
729
 
730
/* Instruction operand instances.
731
 
732
   For each instruction, a list of the hardware elements that are read and
733
   written are recorded.  */
734
 
735
/* The type of the instance.  */
736
 
737
enum cgen_opinst_type {
738
  /* End of table marker.  */
739
  CGEN_OPINST_END = 0,
740
  CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT
741
};
742
 
743
typedef struct
744
{
745
  /* Input or output indicator.  */
746
  enum cgen_opinst_type type;
747
 
748
  /* Name of operand.  */
749
  const char *name;
750
 
751
  /* The hardware element referenced.  */
752
  enum cgen_hw_type hw_type;
753
 
754
  /* The mode in which the operand is being used.  */
755
  enum cgen_mode mode;
756
 
757
  /* The operand table entry CGEN_OPERAND_NIL if there is none
758
     (i.e. an explicit hardware reference).  */
759
  enum cgen_operand_type op_type;
760
 
761
  /* If `operand' is "nil", the index (e.g. into array of registers).  */
762
  int index;
763
 
764
  /* Attributes.
765
     ??? This perhaps should be a real attribute struct but there's
766
     no current need, so we save a bit of space and just have a set of
767
     flags.  The interface is such that this can easily be made attributes
768
     should it prove useful.  */
769
  unsigned int attrs;
770
#define CGEN_OPINST_ATTRS(opinst) ((opinst)->attrs)
771
/* Return value of attribute ATTR in OPINST.  */
772
#define CGEN_OPINST_ATTR(opinst, attr) \
773
((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0)
774
/* Operand is conditionally referenced (read/written).  */
775
#define CGEN_OPINST_COND_REF 1
776
} CGEN_OPINST;
777
 
778
/* Syntax string.
779
 
780
   Each insn format and subexpression has one of these.
781
 
782
   The syntax "string" consists of characters (n > 0 && n < 128), and operand
783
   values (n >= 128), and is terminated by 0.  Operand values are 128 + index
784
   into the operand table.  The operand table doesn't exist in C, per se, as
785
   the data is recorded in the parse/insert/extract/print switch statements. */
786
 
787
/* This should be at least as large as necessary for any target. */
788
#define CGEN_MAX_SYNTAX_ELEMENTS 48
789
 
790
/* A target may know its own precise maximum.  Assert that it falls below
791
   the above limit. */
792
#ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS
793
#if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS
794
#error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS"
795
#endif
796
#endif
797
 
798
typedef unsigned short CGEN_SYNTAX_CHAR_TYPE;
799
 
800
typedef struct
801
{
802
  CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS];
803
} CGEN_SYNTAX;
804
 
805
#define CGEN_SYNTAX_STRING(syn) (syn->syntax)
806
#define CGEN_SYNTAX_CHAR_P(c) ((c) < 128)
807
#define CGEN_SYNTAX_CHAR(c) ((unsigned char)c)
808
#define CGEN_SYNTAX_FIELD(c) ((c) - 128)
809
#define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128)
810
 
811
/* ??? I can't currently think of any case where the mnemonic doesn't come
812
   first [and if one ever doesn't building the hash tables will be tricky].
813
   However, we treat mnemonics as just another operand of the instruction.
814
   A value of 1 means "this is where the mnemonic appears".  1 isn't
815
   special other than it's a non-printable ASCII char.  */
816
 
817
#define CGEN_SYNTAX_MNEMONIC       1
818
#define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC)
819
 
820
/* Instruction fields.
821
 
822
   ??? We currently don't allow adding fields at run-time.
823
   Easy to fix when needed.  */
824
 
825
typedef struct cgen_ifld {
826
  /* Enum of ifield.  */
827
  int num;
828
#define CGEN_IFLD_NUM(f) ((f)->num)
829
 
830
  /* Name of the field, distinguishes it from all other fields.  */
831
  const char *name;
832
#define CGEN_IFLD_NAME(f) ((f)->name)
833
 
834
  /* Default offset, in bits, from the start of the insn to the word
835
     containing the field.  */
836
  int word_offset;
837
#define CGEN_IFLD_WORD_OFFSET(f) ((f)->word_offset)
838
 
839
  /* Default length of the word containing the field.  */
840
  int word_size;
841
#define CGEN_IFLD_WORD_SIZE(f) ((f)->word_size)
842
 
843
  /* Default starting bit number.
844
     Whether lsb=0 or msb=0 is determined by CGEN_INSN_LSB0_P.  */
845
  int start;
846
#define CGEN_IFLD_START(f) ((f)->start)
847
 
848
  /* Length of the field, in bits.  */
849
  int length;
850
#define CGEN_IFLD_LENGTH(f) ((f)->length)
851
 
852
#ifndef CGEN_IFLD_NBOOL_ATTRS
853
#define CGEN_IFLD_NBOOL_ATTRS 1
854
#endif
855
  CGEN_ATTR_TYPE (CGEN_IFLD_NBOOL_ATTRS) attrs;
856
#define CGEN_IFLD_ATTRS(f) (&(f)->attrs)
857
} CGEN_IFLD;
858
 
859
/* Return value of attribute ATTR in IFLD.  */
860
#define CGEN_IFLD_ATTR_VALUE(ifld, attr) \
861
CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr))
862
 
863
/* Instruction data.  */
864
 
865
/* Instruction formats.
866
 
867
   Instructions are grouped by format.  Associated with an instruction is its
868
   format.  Each insn's opcode table entry contains a format table entry.
869
   ??? There is usually very few formats compared with the number of insns,
870
   so one can reduce the size of the opcode table by recording the format table
871
   as a separate entity.  Given that we currently don't, format table entries
872
   are also distinguished by their operands.  This increases the size of the
873
   table, but reduces the number of tables.  It's all minutiae anyway so it
874
   doesn't really matter [at this point in time].
875
 
876
   ??? Support for variable length ISA's is wip.  */
877
 
878
/* Accompanying each iformat description is a list of its fields.  */
879
 
880
typedef struct {
881
  const CGEN_IFLD *ifld;
882
#define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld)
883
} CGEN_IFMT_IFLD;
884
 
885
/* This should be at least as large as necessary for any target. */
886
#define CGEN_MAX_IFMT_OPERANDS 16
887
 
888
/* A target may know its own precise maximum.  Assert that it falls below
889
   the above limit. */
890
#ifdef CGEN_ACTUAL_MAX_IFMT_OPERANDS
891
#if CGEN_ACTUAL_MAX_IFMT_OPERANDS > CGEN_MAX_IFMT_OPERANDS
892
#error "CGEN_ACTUAL_MAX_IFMT_OPERANDS too high - enlarge CGEN_MAX_IFMT_OPERANDS"
893
#endif
894
#endif
895
 
896
 
897
typedef struct
898
{
899
  /* Length that MASK and VALUE have been calculated to
900
     [VALUE is recorded elsewhere].
901
     Normally it is base_insn_bitsize.  On [V]LIW architectures where the base
902
     insn size may be larger than the size of an insn, this field is less than
903
     base_insn_bitsize.  */
904
  unsigned char mask_length;
905
#define CGEN_IFMT_MASK_LENGTH(ifmt) ((ifmt)->mask_length)
906
 
907
  /* Total length of instruction, in bits.  */
908
  unsigned char length;
909
#define CGEN_IFMT_LENGTH(ifmt) ((ifmt)->length)
910
 
911
  /* Mask to apply to the first MASK_LENGTH bits.
912
     Each insn's value is stored with the insn.
913
     The first step in recognizing an insn for disassembly is
914
     (opcode & mask) == value.  */
915
  CGEN_INSN_INT mask;
916
#define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask)
917
 
918
  /* Instruction fields.
919
     +1 for trailing NULL.  */
920
  CGEN_IFMT_IFLD iflds[CGEN_MAX_IFMT_OPERANDS + 1];
921
#define CGEN_IFMT_IFLDS(ifmt) ((ifmt)->iflds)
922
} CGEN_IFMT;
923
 
924
/* Instruction values.  */
925
 
926
typedef struct
927
{
928
  /* The opcode portion of the base insn.  */
929
  CGEN_INSN_INT base_value;
930
 
931
#ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS
932
  /* Extra opcode values beyond base_value.  */
933
  unsigned long ifield_values[CGEN_MAX_EXTRA_OPCODE_OPERANDS];
934
#endif
935
} CGEN_IVALUE;
936
 
937
/* Instruction opcode table.
938
   This contains the syntax and format data of an instruction.  */
939
 
940
/* ??? Some ports already have an opcode table yet still need to use the rest
941
   of what cgen_insn has.  Plus keeping the opcode data with the operand
942
   instance data can create a pretty big file.  So we keep them separately.
943
   Not sure this is a good idea in the long run.  */
944
 
945
typedef struct
946
{
947
  /* Indices into parse/insert/extract/print handler tables.  */
948
  struct cgen_opcode_handler handlers;
949
#define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers)
950
 
951
  /* Syntax string.  */
952
  CGEN_SYNTAX syntax;
953
#define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax)
954
 
955
  /* Format entry.  */
956
  const CGEN_IFMT *format;
957
#define CGEN_OPCODE_FORMAT(opc) ((opc)->format)
958
#define CGEN_OPCODE_MASK_BITSIZE(opc) CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc))
959
#define CGEN_OPCODE_BITSIZE(opc) CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc))
960
#define CGEN_OPCODE_IFLDS(opc) CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc))
961
 
962
  /* Instruction opcode value.  */
963
  CGEN_IVALUE value;
964
#define CGEN_OPCODE_VALUE(opc) (& (opc)->value)
965
#define CGEN_OPCODE_BASE_VALUE(opc) (CGEN_OPCODE_VALUE (opc)->base_value)
966
#define CGEN_OPCODE_BASE_MASK(opc) CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc))
967
} CGEN_OPCODE;
968
 
969
/* Instruction attributes.
970
   This is made a published type as applications can cache a pointer to
971
   the attributes for speed.  */
972
 
973
#ifndef CGEN_INSN_NBOOL_ATTRS
974
#define CGEN_INSN_NBOOL_ATTRS 1
975
#endif
976
typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE;
977
 
978
/* Enum of architecture independent attributes.  */
979
 
980
#ifndef CGEN_ARCH
981
/* ??? Numbers here are recorded in two places.  */
982
typedef enum cgen_insn_attr {
983
  CGEN_INSN_ALIAS = 0
984
} CGEN_INSN_ATTR;
985
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool_ & (1 << CGEN_INSN_ALIAS))
986
#endif
987
 
988
/* This struct defines each entry in the instruction table.  */
989
 
990
typedef struct
991
{
992
  /* Each real instruction is enumerated.  */
993
  /* ??? This may go away in time.  */
994
  int num;
995
#define CGEN_INSN_NUM(insn) ((insn)->base->num)
996
 
997
  /* Name of entry (that distinguishes it from all other entries).  */
998
  /* ??? If mnemonics have operands, try to print full mnemonic.  */
999
  const char *name;
1000
#define CGEN_INSN_NAME(insn) ((insn)->base->name)
1001
 
1002
  /* Mnemonic.  This is used when parsing and printing the insn.
1003
     In the case of insns that have operands on the mnemonics, this is
1004
     only the constant part.  E.g. for conditional execution of an `add' insn,
1005
     where the full mnemonic is addeq, addne, etc., and the condition is
1006
     treated as an operand, this is only "add".  */
1007
  const char *mnemonic;
1008
#define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic)
1009
 
1010
  /* Total length of instruction, in bits.  */
1011
  int bitsize;
1012
#define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize)
1013
 
1014
#if 0 /* ??? Disabled for now as there is a problem with embedded newlines
1015
         and the table is already pretty big.  Should perhaps be moved
1016
         to a file of its own.  */
1017
  /* Semantics, as RTL.  */
1018
  /* ??? Plain text or bytecodes?  */
1019
  /* ??? Note that the operand instance table could be computed at run-time
1020
     if we parse this and cache the results.  Something to eventually do.  */
1021
  const char *rtx;
1022
#define CGEN_INSN_RTX(insn) ((insn)->base->rtx)
1023
#endif
1024
 
1025
  /* Attributes.
1026
     This must appear last.  It is a variable sized array in that one
1027
     architecture may have 1 nonbool attribute and another may have more.
1028
     Having this last means the non-architecture specific code needn't
1029
     care.  The goal is to eventually record attributes in their raw form,
1030
     evaluate them at run-time, and cache the values, so this worry will go
1031
     away anyway.  */
1032
  CGEN_INSN_ATTR_TYPE attrs;
1033
#define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs)
1034
/* Return value of attribute ATTR in INSN.  */
1035
#define CGEN_INSN_ATTR_VALUE(insn, attr) \
1036
CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
1037
#define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr) \
1038
  CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
1039
} CGEN_IBASE;
1040
 
1041
/* Return non-zero if INSN is the "invalid" insn marker.  */
1042
 
1043
#define CGEN_INSN_INVALID_P(insn) (CGEN_INSN_MNEMONIC (insn) == 0)
1044
 
1045
/* Main struct contain instruction information.
1046
   BASE is always present, the rest is present only if asked for.  */
1047
 
1048
struct cgen_insn
1049
{
1050
  /* ??? May be of use to put a type indicator here.
1051
     Then this struct could different info for different classes of insns.  */
1052
  /* ??? A speedup can be had by moving `base' into this struct.
1053
     Maybe later.  */
1054
  const CGEN_IBASE *base;
1055
  const CGEN_OPCODE *opcode;
1056
  const CGEN_OPINST *opinst;
1057
 
1058
  /* Regex to disambiguate overloaded opcodes */
1059
  void *rx;
1060
#define CGEN_INSN_RX(insn) ((insn)->rx)
1061
#define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5)
1062
};
1063
 
1064
/* Instruction lists.
1065
   This is used for adding new entries and for creating the hash lists.  */
1066
 
1067
typedef struct cgen_insn_list
1068
{
1069
  struct cgen_insn_list *next;
1070
  const CGEN_INSN *insn;
1071
} CGEN_INSN_LIST;
1072
 
1073
/* Table of instructions.  */
1074
 
1075
typedef struct
1076
{
1077
  const CGEN_INSN *init_entries;
1078
  unsigned int entry_size; /* since the attribute member is variable sized */
1079
  unsigned int num_init_entries;
1080
  CGEN_INSN_LIST *new_entries;
1081
} CGEN_INSN_TABLE;
1082
 
1083
/* Return number of instructions.  This includes any added at run-time.  */
1084
 
1085
extern int cgen_insn_count (CGEN_CPU_DESC);
1086
extern int cgen_macro_insn_count (CGEN_CPU_DESC);
1087
 
1088
/* Macros to access the other insn elements not recorded in CGEN_IBASE.  */
1089
 
1090
/* Fetch INSN's operand instance table.  */
1091
/* ??? Doesn't handle insns added at runtime.  */
1092
#define CGEN_INSN_OPERANDS(insn) ((insn)->opinst)
1093
 
1094
/* Return INSN's opcode table entry.  */
1095
#define CGEN_INSN_OPCODE(insn) ((insn)->opcode)
1096
 
1097
/* Return INSN's handler data.  */
1098
#define CGEN_INSN_HANDLERS(insn) CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn))
1099
 
1100
/* Return INSN's syntax.  */
1101
#define CGEN_INSN_SYNTAX(insn) CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn))
1102
 
1103
/* Return size of base mask in bits.  */
1104
#define CGEN_INSN_MASK_BITSIZE(insn) \
1105
  CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn))
1106
 
1107
/* Return mask of base part of INSN.  */
1108
#define CGEN_INSN_BASE_MASK(insn) \
1109
  CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn))
1110
 
1111
/* Return value of base part of INSN.  */
1112
#define CGEN_INSN_BASE_VALUE(insn) \
1113
  CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn))
1114
 
1115
/* Standard way to test whether INSN is supported by MACH.
1116
   MACH is one of enum mach_attr.
1117
   The "|1" is because the base mach is always selected.  */
1118
#define CGEN_INSN_MACH_HAS_P(insn, mach) \
1119
((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0)
1120
 
1121
/* Macro instructions.
1122
   Macro insns aren't real insns, they map to one or more real insns.
1123
   E.g. An architecture's "nop" insn may actually be an "mv r0,r0" or
1124
   some such.
1125
 
1126
   Macro insns can expand to nothing (e.g. a nop that is optimized away).
1127
   This is useful in multi-insn macros that build a constant in a register.
1128
   Of course this isn't the default behaviour and must be explicitly enabled.
1129
 
1130
   Assembly of macro-insns is relatively straightforward.  Disassembly isn't.
1131
   However, disassembly of at least some kinds of macro insns is important
1132
   in order that the disassembled code preserve the readability of the original
1133
   insn.  What is attempted here is to disassemble all "simple" macro-insns,
1134
   where "simple" is currently defined to mean "expands to one real insn".
1135
 
1136
   Simple macro-insns are handled specially.  They are emitted as ALIAS's
1137
   of real insns.  This simplifies their handling since there's usually more
1138
   of them than any other kind of macro-insn, and proper disassembly of them
1139
   falls out for free.  */
1140
 
1141
/* For each macro-insn there may be multiple expansion possibilities,
1142
   depending on the arguments.  This structure is accessed via the `data'
1143
   member of CGEN_INSN.  */
1144
 
1145
typedef struct cgen_minsn_expansion {
1146
  /* Function to do the expansion.
1147
     If the expansion fails (e.g. "no match") NULL is returned.
1148
     Space for the expansion is obtained with malloc.
1149
     It is up to the caller to free it.  */
1150
  const char * (* fn)
1151
     (const struct cgen_minsn_expansion *,
1152
      const char *, const char **, int *,
1153
      CGEN_OPERAND **);
1154
#define CGEN_MIEXPN_FN(ex) ((ex)->fn)
1155
 
1156
  /* Instruction(s) the macro expands to.
1157
     The format of STR is defined by FN.
1158
     It is typically the assembly code of the real insn, but it could also be
1159
     the original Scheme expression or a tokenized form of it (with FN being
1160
     an appropriate interpreter).  */
1161
  const char * str;
1162
#define CGEN_MIEXPN_STR(ex) ((ex)->str)
1163
} CGEN_MINSN_EXPANSION;
1164
 
1165
/* Normal expander.
1166
   When supported, this function will convert the input string to another
1167
   string and the parser will be invoked recursively.  The output string
1168
   may contain further macro invocations.  */
1169
 
1170
extern const char * cgen_expand_macro_insn
1171
  (CGEN_CPU_DESC, const struct cgen_minsn_expansion *,
1172
   const char *, const char **, int *, CGEN_OPERAND **);
1173
 
1174
/* The assembler insn table is hashed based on some function of the mnemonic
1175
   (the actually hashing done is up to the target, but we provide a few
1176
   examples like the first letter or a function of the entire mnemonic).  */
1177
 
1178
extern CGEN_INSN_LIST * cgen_asm_lookup_insn
1179
  (CGEN_CPU_DESC, const char *);
1180
#define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string))
1181
#define CGEN_ASM_NEXT_INSN(insn) ((insn)->next)
1182
 
1183
/* The disassembler insn table is hashed based on some function of machine
1184
   instruction (the actually hashing done is up to the target).  */
1185
 
1186
extern CGEN_INSN_LIST * cgen_dis_lookup_insn
1187
  (CGEN_CPU_DESC, const char *, CGEN_INSN_INT);
1188
/* FIXME: delete these two */
1189
#define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value))
1190
#define CGEN_DIS_NEXT_INSN(insn) ((insn)->next)
1191
 
1192
/* The CPU description.
1193
   A copy of this is created when the cpu table is "opened".
1194
   All global state information is recorded here.
1195
   Access macros are provided for "public" members.  */
1196
 
1197
typedef struct cgen_cpu_desc
1198
{
1199
  /* Bitmap of selected machine(s) (a la BFD machine number).  */
1200
  int machs;
1201
 
1202
  /* Bitmap of selected isa(s).  */
1203
  CGEN_BITSET *isas;
1204
#define CGEN_CPU_ISAS(cd) ((cd)->isas)
1205
 
1206
  /* Current endian.  */
1207
  enum cgen_endian endian;
1208
#define CGEN_CPU_ENDIAN(cd) ((cd)->endian)
1209
 
1210
  /* Current insn endian.  */
1211
  enum cgen_endian insn_endian;
1212
#define CGEN_CPU_INSN_ENDIAN(cd) ((cd)->insn_endian)
1213
 
1214
  /* Word size (in bits).  */
1215
  /* ??? Or maybe maximum word size - might we ever need to allow a cpu table
1216
     to be opened for both sparc32/sparc64?
1217
     ??? Another alternative is to create a table of selected machs and
1218
     lazily fetch the data from there.  */
1219
  unsigned int word_bitsize;
1220
 
1221
  /* Instruction chunk size (in bits), for purposes of endianness
1222
     conversion.  */
1223
  unsigned int insn_chunk_bitsize;
1224
 
1225
  /* Indicator if sizes are unknown.
1226
     This is used by default_insn_bitsize,base_insn_bitsize if there is a
1227
     difference between the selected isa's.  */
1228
#define CGEN_SIZE_UNKNOWN 65535
1229
 
1230
  /* Default instruction size (in bits).
1231
     This is used by the assembler when it encounters an unknown insn.  */
1232
  unsigned int default_insn_bitsize;
1233
 
1234
  /* Base instruction size (in bits).
1235
     For non-LIW cpus this is generally the length of the smallest insn.
1236
     For LIW cpus its wip (work-in-progress).  For the m32r its 32.  */
1237
  unsigned int base_insn_bitsize;
1238
 
1239
  /* Minimum/maximum instruction size (in bits).  */
1240
  unsigned int min_insn_bitsize;
1241
  unsigned int max_insn_bitsize;
1242
 
1243
  /* Instruction set variants.  */
1244
  const CGEN_ISA *isa_table;
1245
 
1246
  /* Machine variants.  */
1247
  const CGEN_MACH *mach_table;
1248
 
1249
  /* Hardware elements.  */
1250
  CGEN_HW_TABLE hw_table;
1251
 
1252
  /* Instruction fields.  */
1253
  const CGEN_IFLD *ifld_table;
1254
 
1255
  /* Operands.  */
1256
  CGEN_OPERAND_TABLE operand_table;
1257
 
1258
  /* Main instruction table.  */
1259
  CGEN_INSN_TABLE insn_table;
1260
#define CGEN_CPU_INSN_TABLE(cd) (& (cd)->insn_table)
1261
 
1262
  /* Macro instructions are defined separately and are combined with real
1263
     insns during hash table computation.  */
1264
  CGEN_INSN_TABLE macro_insn_table;
1265
 
1266
  /* Copy of CGEN_INT_INSN_P.  */
1267
  int int_insn_p;
1268
 
1269
  /* Called to rebuild the tables after something has changed.  */
1270
  void (*rebuild_tables) (CGEN_CPU_DESC);
1271
 
1272
  /* Operand parser callback.  */
1273
  cgen_parse_operand_fn * parse_operand_fn;
1274
 
1275
  /* Parse/insert/extract/print cover fns for operands.  */
1276
  const char * (*parse_operand)
1277
    (CGEN_CPU_DESC, int opindex_, const char **, CGEN_FIELDS *fields_);
1278
#ifdef __BFD_H_SEEN__
1279
  const char * (*insert_operand)
1280
    (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_,
1281
     CGEN_INSN_BYTES_PTR, bfd_vma pc_);
1282
  int (*extract_operand)
1283
    (CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
1284
     CGEN_FIELDS *fields_, bfd_vma pc_);
1285
  void (*print_operand)
1286
    (CGEN_CPU_DESC, int opindex_, void * info_, CGEN_FIELDS * fields_,
1287
     void const *attrs_, bfd_vma pc_, int length_);
1288
#else
1289
  const char * (*insert_operand) ();
1290
  int (*extract_operand) ();
1291
  void (*print_operand) ();
1292
#endif
1293
#define CGEN_CPU_PARSE_OPERAND(cd) ((cd)->parse_operand)
1294
#define CGEN_CPU_INSERT_OPERAND(cd) ((cd)->insert_operand)
1295
#define CGEN_CPU_EXTRACT_OPERAND(cd) ((cd)->extract_operand)
1296
#define CGEN_CPU_PRINT_OPERAND(cd) ((cd)->print_operand)
1297
 
1298
  /* Size of CGEN_FIELDS struct.  */
1299
  unsigned int sizeof_fields;
1300
#define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields)
1301
 
1302
  /* Set the bitsize field.  */
1303
  void (*set_fields_bitsize) (CGEN_FIELDS *fields_, int size_);
1304
#define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize)
1305
 
1306
  /* CGEN_FIELDS accessors.  */
1307
  int (*get_int_operand)
1308
    (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_);
1309
  void (*set_int_operand)
1310
    (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_);
1311
#ifdef __BFD_H_SEEN__
1312
  bfd_vma (*get_vma_operand)
1313
    (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_);
1314
  void (*set_vma_operand)
1315
    (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_);
1316
#else
1317
  long (*get_vma_operand) ();
1318
  void (*set_vma_operand) ();
1319
#endif
1320
#define CGEN_CPU_GET_INT_OPERAND(cd) ((cd)->get_int_operand)
1321
#define CGEN_CPU_SET_INT_OPERAND(cd) ((cd)->set_int_operand)
1322
#define CGEN_CPU_GET_VMA_OPERAND(cd) ((cd)->get_vma_operand)
1323
#define CGEN_CPU_SET_VMA_OPERAND(cd) ((cd)->set_vma_operand)
1324
 
1325
  /* Instruction parse/insert/extract/print handlers.  */
1326
  /* FIXME: make these types uppercase.  */
1327
  cgen_parse_fn * const *parse_handlers;
1328
  cgen_insert_fn * const *insert_handlers;
1329
  cgen_extract_fn * const *extract_handlers;
1330
  cgen_print_fn * const *print_handlers;
1331
#define CGEN_PARSE_FN(cd, insn)   (cd->parse_handlers[(insn)->opcode->handlers.parse])
1332
#define CGEN_INSERT_FN(cd, insn)  (cd->insert_handlers[(insn)->opcode->handlers.insert])
1333
#define CGEN_EXTRACT_FN(cd, insn) (cd->extract_handlers[(insn)->opcode->handlers.extract])
1334
#define CGEN_PRINT_FN(cd, insn)   (cd->print_handlers[(insn)->opcode->handlers.print])
1335
 
1336
  /* Return non-zero if insn should be added to hash table.  */
1337
  int (* asm_hash_p) (const CGEN_INSN *);
1338
 
1339
  /* Assembler hash function.  */
1340
  unsigned int (* asm_hash) (const char *);
1341
 
1342
  /* Number of entries in assembler hash table.  */
1343
  unsigned int asm_hash_size;
1344
 
1345
  /* Return non-zero if insn should be added to hash table.  */
1346
  int (* dis_hash_p) (const CGEN_INSN *);
1347
 
1348
  /* Disassembler hash function.  */
1349
  unsigned int (* dis_hash) (const char *, CGEN_INSN_INT);
1350
 
1351
  /* Number of entries in disassembler hash table.  */
1352
  unsigned int dis_hash_size;
1353
 
1354
  /* Assembler instruction hash table.  */
1355
  CGEN_INSN_LIST **asm_hash_table;
1356
  CGEN_INSN_LIST *asm_hash_table_entries;
1357
 
1358
  /* Disassembler instruction hash table.  */
1359
  CGEN_INSN_LIST **dis_hash_table;
1360
  CGEN_INSN_LIST *dis_hash_table_entries;
1361
 
1362
  /* This field could be turned into a bitfield if room for other flags is needed.  */
1363
  unsigned int signed_overflow_ok_p;
1364
 
1365
} CGEN_CPU_TABLE;
1366
 
1367
/* wip */
1368
#ifndef CGEN_WORD_ENDIAN
1369
#define CGEN_WORD_ENDIAN(cd) CGEN_CPU_ENDIAN (cd)
1370
#endif
1371
#ifndef CGEN_INSN_WORD_ENDIAN
1372
#define CGEN_INSN_WORD_ENDIAN(cd) CGEN_CPU_INSN_ENDIAN (cd)
1373
#endif
1374
 
1375
/* Prototypes of major functions.  */
1376
/* FIXME: Move more CGEN_SYM-defined functions into CGEN_CPU_DESC.
1377
   Not the init fns though, as that would drag in things that mightn't be
1378
   used and might not even exist.  */
1379
 
1380
/* Argument types to cpu_open.  */
1381
 
1382
enum cgen_cpu_open_arg {
1383
  CGEN_CPU_OPEN_END,
1384
  /* Select instruction set(s), arg is bitmap or 0 meaning "unspecified".  */
1385
  CGEN_CPU_OPEN_ISAS,
1386
  /* Select machine(s), arg is bitmap or 0 meaning "unspecified".  */
1387
  CGEN_CPU_OPEN_MACHS,
1388
  /* Select machine, arg is mach's bfd name.
1389
     Multiple machines can be specified by repeated use.  */
1390
  CGEN_CPU_OPEN_BFDMACH,
1391
  /* Select endian, arg is CGEN_ENDIAN_*.  */
1392
  CGEN_CPU_OPEN_ENDIAN
1393
};
1394
 
1395
/* Open a cpu descriptor table for use.
1396
   ??? We only support ISO C stdargs here, not K&R.
1397
   Laziness, plus experiment to see if anything requires K&R - eventually
1398
   K&R will no longer be supported - e.g. GDB is currently trying this.  */
1399
 
1400
extern CGEN_CPU_DESC CGEN_SYM (cpu_open) (enum cgen_cpu_open_arg, ...);
1401
 
1402
/* Cover fn to handle simple case.  */
1403
 
1404
extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1)
1405
   (const char *mach_name_, enum cgen_endian endian_);
1406
 
1407
/* Close it.  */
1408
 
1409
extern void CGEN_SYM (cpu_close) (CGEN_CPU_DESC);
1410
 
1411
/* Initialize the opcode table for use.
1412
   Called by init_asm/init_dis.  */
1413
 
1414
extern void CGEN_SYM (init_opcode_table) (CGEN_CPU_DESC cd_);
1415
 
1416
/* build the insn selection regex.
1417
   called by init_opcode_table */
1418
 
1419
extern char * CGEN_SYM(build_insn_regex) (CGEN_INSN *insn_);
1420
 
1421
/* Initialize the ibld table for use.
1422
   Called by init_asm/init_dis.  */
1423
 
1424
extern void CGEN_SYM (init_ibld_table) (CGEN_CPU_DESC cd_);
1425
 
1426
/* Initialize an cpu table for assembler or disassembler use.
1427
   These must be called immediately after cpu_open.  */
1428
 
1429
extern void CGEN_SYM (init_asm) (CGEN_CPU_DESC);
1430
extern void CGEN_SYM (init_dis) (CGEN_CPU_DESC);
1431
 
1432
/* Initialize the operand instance table for use.  */
1433
 
1434
extern void CGEN_SYM (init_opinst_table) (CGEN_CPU_DESC cd_);
1435
 
1436
/* Assemble an instruction.  */
1437
 
1438
extern const CGEN_INSN * CGEN_SYM (assemble_insn)
1439
  (CGEN_CPU_DESC, const char *, CGEN_FIELDS *,
1440
   CGEN_INSN_BYTES_PTR, char **);
1441
 
1442
extern const CGEN_KEYWORD CGEN_SYM (operand_mach);
1443
extern int CGEN_SYM (get_mach) (const char *);
1444
 
1445
/* Operand index computation.  */
1446
extern const CGEN_INSN * cgen_lookup_insn
1447
  (CGEN_CPU_DESC, const CGEN_INSN * insn_,
1448
   CGEN_INSN_INT int_value_, unsigned char *bytes_value_,
1449
   int length_, CGEN_FIELDS *fields_, int alias_p_);
1450
extern void cgen_get_insn_operands
1451
  (CGEN_CPU_DESC, const CGEN_INSN * insn_,
1452
   const CGEN_FIELDS *fields_, int *indices_);
1453
extern const CGEN_INSN * cgen_lookup_get_insn_operands
1454
  (CGEN_CPU_DESC, const CGEN_INSN *insn_,
1455
   CGEN_INSN_INT int_value_, unsigned char *bytes_value_,
1456
   int length_, int *indices_, CGEN_FIELDS *fields_);
1457
 
1458
/* Cover fns to bfd_get/set.  */
1459
 
1460
extern CGEN_INSN_INT cgen_get_insn_value
1461
  (CGEN_CPU_DESC, unsigned char *, int);
1462
extern void cgen_put_insn_value
1463
  (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT);
1464
 
1465
/* Read in a cpu description file.
1466
   ??? For future concerns, including adding instructions to the assembler/
1467
   disassembler at run-time.  */
1468
 
1469
extern const char * cgen_read_cpu_file (CGEN_CPU_DESC, const char * filename_);
1470
 
1471
/* Allow signed overflow of instruction fields.  */
1472
extern void cgen_set_signed_overflow_ok (CGEN_CPU_DESC);
1473
 
1474
/* Generate an error message if a signed field in an instruction overflows.  */
1475
extern void cgen_clear_signed_overflow_ok (CGEN_CPU_DESC);
1476
 
1477
/* Will an error message be generated if a signed field in an instruction overflows ? */
1478
extern unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC);
1479
 
1480
#endif /* OPCODE_CGEN_H */

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