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[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [include/] [opcode/] [mips.h] - Blame information for rev 21

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/* mips.h.  Mips opcode list for GDB, the GNU debugger.
2
   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3
   2003, 2004, 2005, 2008, 2009, 2010
4
   Free Software Foundation, Inc.
5
   Contributed by Ralph Campbell and OSF
6
   Commented and modified by Ian Lance Taylor, Cygnus Support
7
 
8
   This file is part of GDB, GAS, and the GNU binutils.
9
 
10
   GDB, GAS, and the GNU binutils are free software; you can redistribute
11
   them and/or modify them under the terms of the GNU General Public
12
   License as published by the Free Software Foundation; either version 3,
13
   or (at your option) any later version.
14
 
15
   GDB, GAS, and the GNU binutils are distributed in the hope that they
16
   will be useful, but WITHOUT ANY WARRANTY; without even the implied
17
   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
18
   the GNU General Public License for more details.
19
 
20
   You should have received a copy of the GNU General Public License
21
   along with this file; see the file COPYING3.  If not, write to the Free
22
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
23
   MA 02110-1301, USA.  */
24
 
25
#ifndef _MIPS_H_
26
#define _MIPS_H_
27
 
28
/* These are bit masks and shift counts to use to access the various
29
   fields of an instruction.  To retrieve the X field of an
30
   instruction, use the expression
31
        (i >> OP_SH_X) & OP_MASK_X
32
   To set the same field (to j), use
33
        i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
34
 
35
   Make sure you use fields that are appropriate for the instruction,
36
   of course.
37
 
38
   The 'i' format uses OP, RS, RT and IMMEDIATE.
39
 
40
   The 'j' format uses OP and TARGET.
41
 
42
   The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
43
 
44
   The 'b' format uses OP, RS, RT and DELTA.
45
 
46
   The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
47
 
48
   The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
49
 
50
   A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
51
   breakpoint instruction are not defined; Kane says the breakpoint
52
   code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
53
   only use ten bits).  An optional two-operand form of break/sdbbp
54
   allows the lower ten bits to be set too, and MIPS32 and later
55
   architectures allow 20 bits to be set with a signal operand
56
   (using CODE20).
57
 
58
   The syscall instruction uses CODE20.
59
 
60
   The general coprocessor instructions use COPZ.  */
61
 
62
#define OP_MASK_OP              0x3f
63
#define OP_SH_OP                26
64
#define OP_MASK_RS              0x1f
65
#define OP_SH_RS                21
66
#define OP_MASK_FR              0x1f
67
#define OP_SH_FR                21
68
#define OP_MASK_FMT             0x1f
69
#define OP_SH_FMT               21
70
#define OP_MASK_BCC             0x7
71
#define OP_SH_BCC               18
72
#define OP_MASK_CODE            0x3ff
73
#define OP_SH_CODE              16
74
#define OP_MASK_CODE2           0x3ff
75
#define OP_SH_CODE2             6
76
#define OP_MASK_RT              0x1f
77
#define OP_SH_RT                16
78
#define OP_MASK_FT              0x1f
79
#define OP_SH_FT                16
80
#define OP_MASK_CACHE           0x1f
81
#define OP_SH_CACHE             16
82
#define OP_MASK_RD              0x1f
83
#define OP_SH_RD                11
84
#define OP_MASK_FS              0x1f
85
#define OP_SH_FS                11
86
#define OP_MASK_PREFX           0x1f
87
#define OP_SH_PREFX             11
88
#define OP_MASK_CCC             0x7
89
#define OP_SH_CCC               8
90
#define OP_MASK_CODE20          0xfffff /* 20 bit syscall/breakpoint code.  */
91
#define OP_SH_CODE20            6
92
#define OP_MASK_SHAMT           0x1f
93
#define OP_SH_SHAMT             6
94
#define OP_MASK_FD              0x1f
95
#define OP_SH_FD                6
96
#define OP_MASK_TARGET          0x3ffffff
97
#define OP_SH_TARGET            0
98
#define OP_MASK_COPZ            0x1ffffff
99
#define OP_SH_COPZ              0
100
#define OP_MASK_IMMEDIATE       0xffff
101
#define OP_SH_IMMEDIATE         0
102
#define OP_MASK_DELTA           0xffff
103
#define OP_SH_DELTA             0
104
#define OP_MASK_FUNCT           0x3f
105
#define OP_SH_FUNCT             0
106
#define OP_MASK_SPEC            0x3f
107
#define OP_SH_SPEC              0
108
#define OP_SH_LOCC              8       /* FP condition code.  */
109
#define OP_SH_HICC              18      /* FP condition code.  */
110
#define OP_MASK_CC              0x7
111
#define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
112
#define OP_MASK_COP1NORM        0x1     /* a single bit.  */
113
#define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
114
#define OP_MASK_COP1SPEC        0xf
115
#define OP_MASK_COP1SCLR        0x4
116
#define OP_MASK_COP1CMP         0x3
117
#define OP_SH_COP1CMP           4
118
#define OP_SH_FORMAT            21      /* FP short format field.  */
119
#define OP_MASK_FORMAT          0x7
120
#define OP_SH_TRUE              16
121
#define OP_MASK_TRUE            0x1
122
#define OP_SH_GE                17
123
#define OP_MASK_GE              0x01
124
#define OP_SH_UNSIGNED          16
125
#define OP_MASK_UNSIGNED        0x1
126
#define OP_SH_HINT              16
127
#define OP_MASK_HINT            0x1f
128
#define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
129
#define OP_MASK_MMI             0x3f
130
#define OP_SH_MMISUB            6
131
#define OP_MASK_MMISUB          0x1f
132
#define OP_MASK_PERFREG         0x1f    /* Performance monitoring.  */
133
#define OP_SH_PERFREG           1
134
#define OP_SH_SEL               0        /* Coprocessor select field.  */
135
#define OP_MASK_SEL             0x7     /* The sel field of mfcZ and mtcZ.  */
136
#define OP_SH_CODE19            6       /* 19 bit wait code.  */
137
#define OP_MASK_CODE19          0x7ffff
138
#define OP_SH_ALN               21
139
#define OP_MASK_ALN             0x7
140
#define OP_SH_VSEL              21
141
#define OP_MASK_VSEL            0x1f
142
#define OP_MASK_VECBYTE         0x7     /* Selector field is really 4 bits,
143
                                           but 0x8-0xf don't select bytes.  */
144
#define OP_SH_VECBYTE           22
145
#define OP_MASK_VECALIGN        0x7     /* Vector byte-align (alni.ob) op.  */
146
#define OP_SH_VECALIGN          21
147
#define OP_MASK_INSMSB          0x1f    /* "ins" MSB.  */
148
#define OP_SH_INSMSB            11
149
#define OP_MASK_EXTMSBD         0x1f    /* "ext" MSBD.  */
150
#define OP_SH_EXTMSBD           11
151
 
152
/* MIPS DSP ASE */
153
#define OP_SH_DSPACC            11
154
#define OP_MASK_DSPACC          0x3
155
#define OP_SH_DSPACC_S          21
156
#define OP_MASK_DSPACC_S        0x3
157
#define OP_SH_DSPSFT            20
158
#define OP_MASK_DSPSFT          0x3f
159
#define OP_SH_DSPSFT_7          19
160
#define OP_MASK_DSPSFT_7        0x7f
161
#define OP_SH_SA3               21
162
#define OP_MASK_SA3             0x7
163
#define OP_SH_SA4               21
164
#define OP_MASK_SA4             0xf
165
#define OP_SH_IMM8              16
166
#define OP_MASK_IMM8            0xff
167
#define OP_SH_IMM10             16
168
#define OP_MASK_IMM10           0x3ff
169
#define OP_SH_WRDSP             11
170
#define OP_MASK_WRDSP           0x3f
171
#define OP_SH_RDDSP             16
172
#define OP_MASK_RDDSP           0x3f
173
#define OP_SH_BP                11
174
#define OP_MASK_BP              0x3
175
 
176
/* MIPS MT ASE */
177
#define OP_SH_MT_U              5
178
#define OP_MASK_MT_U            0x1
179
#define OP_SH_MT_H              4
180
#define OP_MASK_MT_H            0x1
181
#define OP_SH_MTACC_T           18
182
#define OP_MASK_MTACC_T         0x3
183
#define OP_SH_MTACC_D           13
184
#define OP_MASK_MTACC_D         0x3
185
 
186
#define OP_OP_COP0              0x10
187
#define OP_OP_COP1              0x11
188
#define OP_OP_COP2              0x12
189
#define OP_OP_COP3              0x13
190
#define OP_OP_LWC1              0x31
191
#define OP_OP_LWC2              0x32
192
#define OP_OP_LWC3              0x33    /* a.k.a. pref */
193
#define OP_OP_LDC1              0x35
194
#define OP_OP_LDC2              0x36
195
#define OP_OP_LDC3              0x37    /* a.k.a. ld */
196
#define OP_OP_SWC1              0x39
197
#define OP_OP_SWC2              0x3a
198
#define OP_OP_SWC3              0x3b
199
#define OP_OP_SDC1              0x3d
200
#define OP_OP_SDC2              0x3e
201
#define OP_OP_SDC3              0x3f    /* a.k.a. sd */
202
 
203
/* Values in the 'VSEL' field.  */
204
#define MDMX_FMTSEL_IMM_QH      0x1d
205
#define MDMX_FMTSEL_IMM_OB      0x1e
206
#define MDMX_FMTSEL_VEC_QH      0x15
207
#define MDMX_FMTSEL_VEC_OB      0x16
208
 
209
/* UDI */
210
#define OP_SH_UDI1              6
211
#define OP_MASK_UDI1            0x1f
212
#define OP_SH_UDI2              6
213
#define OP_MASK_UDI2            0x3ff
214
#define OP_SH_UDI3              6
215
#define OP_MASK_UDI3            0x7fff
216
#define OP_SH_UDI4              6
217
#define OP_MASK_UDI4            0xfffff
218
 
219
/* Octeon */
220
#define OP_SH_BBITIND           16
221
#define OP_MASK_BBITIND         0x1f
222
#define OP_SH_CINSPOS           6
223
#define OP_MASK_CINSPOS         0x1f
224
#define OP_SH_CINSLM1           11
225
#define OP_MASK_CINSLM1         0x1f
226
#define OP_SH_SEQI              6
227
#define OP_MASK_SEQI            0x3ff
228
 
229
/* Loongson */
230
#define OP_SH_OFFSET_A          6
231
#define OP_MASK_OFFSET_A        0xff
232
#define OP_SH_OFFSET_B          3
233
#define OP_MASK_OFFSET_B        0xff
234
#define OP_SH_OFFSET_C          6
235
#define OP_MASK_OFFSET_C        0x1ff
236
#define OP_SH_RZ                0
237
#define OP_MASK_RZ              0x1f
238
#define OP_SH_FZ                0
239
#define OP_MASK_FZ              0x1f
240
 
241
/* This structure holds information for a particular instruction.  */
242
 
243
struct mips_opcode
244
{
245
  /* The name of the instruction.  */
246
  const char *name;
247
  /* A string describing the arguments for this instruction.  */
248
  const char *args;
249
  /* The basic opcode for the instruction.  When assembling, this
250
     opcode is modified by the arguments to produce the actual opcode
251
     that is used.  If pinfo is INSN_MACRO, then this is 0.  */
252
  unsigned long match;
253
  /* If pinfo is not INSN_MACRO, then this is a bit mask for the
254
     relevant portions of the opcode when disassembling.  If the
255
     actual opcode anded with the match field equals the opcode field,
256
     then we have found the correct instruction.  If pinfo is
257
     INSN_MACRO, then this field is the macro identifier.  */
258
  unsigned long mask;
259
  /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
260
     of bits describing the instruction, notably any relevant hazard
261
     information.  */
262
  unsigned long pinfo;
263
  /* A collection of additional bits describing the instruction. */
264
  unsigned long pinfo2;
265
  /* A collection of bits describing the instruction sets of which this
266
     instruction or macro is a member. */
267
  unsigned long membership;
268
};
269
 
270
/* These are the characters which may appear in the args field of an
271
   instruction.  They appear in the order in which the fields appear
272
   when the instruction is used.  Commas and parentheses in the args
273
   string are ignored when assembling, and written into the output
274
   when disassembling.
275
 
276
   Each of these characters corresponds to a mask field defined above.
277
 
278
   "1" 5 bit sync type (OP_*_SHAMT)
279
   "<" 5 bit shift amount (OP_*_SHAMT)
280
   ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
281
   "a" 26 bit target address (OP_*_TARGET)
282
   "b" 5 bit base register (OP_*_RS)
283
   "c" 10 bit breakpoint code (OP_*_CODE)
284
   "d" 5 bit destination register specifier (OP_*_RD)
285
   "h" 5 bit prefx hint (OP_*_PREFX)
286
   "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
287
   "j" 16 bit signed immediate (OP_*_DELTA)
288
   "k" 5 bit cache opcode in target register position (OP_*_CACHE)
289
       Also used for immediate operands in vr5400 vector insns.
290
   "o" 16 bit signed offset (OP_*_DELTA)
291
   "p" 16 bit PC relative branch target address (OP_*_DELTA)
292
   "q" 10 bit extra breakpoint code (OP_*_CODE2)
293
   "r" 5 bit same register used as both source and target (OP_*_RS)
294
   "s" 5 bit source register specifier (OP_*_RS)
295
   "t" 5 bit target register (OP_*_RT)
296
   "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
297
   "v" 5 bit same register used as both source and destination (OP_*_RS)
298
   "w" 5 bit same register used as both target and destination (OP_*_RT)
299
   "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
300
       (used by clo and clz)
301
   "C" 25 bit coprocessor function code (OP_*_COPZ)
302
   "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
303
   "J" 19 bit wait function code (OP_*_CODE19)
304
   "x" accept and ignore register name
305
   "z" must be zero register
306
   "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
307
   "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
308
        LSB (OP_*_SHAMT).
309
        Enforces: 0 <= pos < 32.
310
   "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
311
        Requires that "+A" or "+E" occur first to set position.
312
        Enforces: 0 < (pos+size) <= 32.
313
   "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
314
        Requires that "+A" or "+E" occur first to set position.
315
        Enforces: 0 < (pos+size) <= 32.
316
        (Also used by "dext" w/ different limits, but limits for
317
        that are checked by the M_DEXT macro.)
318
   "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
319
        Enforces: 32 <= pos < 64.
320
   "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
321
        Requires that "+A" or "+E" occur first to set position.
322
        Enforces: 32 < (pos+size) <= 64.
323
   "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
324
        Requires that "+A" or "+E" occur first to set position.
325
        Enforces: 32 < (pos+size) <= 64.
326
   "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
327
        Requires that "+A" or "+E" occur first to set position.
328
        Enforces: 32 < (pos+size) <= 64.
329
 
330
   Floating point instructions:
331
   "D" 5 bit destination register (OP_*_FD)
332
   "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
333
   "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
334
   "S" 5 bit fs source 1 register (OP_*_FS)
335
   "T" 5 bit ft source 2 register (OP_*_FT)
336
   "R" 5 bit fr source 3 register (OP_*_FR)
337
   "V" 5 bit same register used as floating source and destination (OP_*_FS)
338
   "W" 5 bit same register used as floating target and destination (OP_*_FT)
339
 
340
   Coprocessor instructions:
341
   "E" 5 bit target register (OP_*_RT)
342
   "G" 5 bit destination register (OP_*_RD)
343
   "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
344
   "P" 5 bit performance-monitor register (OP_*_PERFREG)
345
   "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
346
   "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
347
   see also "k" above
348
   "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
349
        for pretty-printing in disassembly only.
350
 
351
   Macro instructions:
352
   "A" General 32 bit expression
353
   "I" 32 bit immediate (value placed in imm_expr).
354
   "+I" 32 bit immediate (value placed in imm2_expr).
355
   "F" 64 bit floating point constant in .rdata
356
   "L" 64 bit floating point constant in .lit8
357
   "f" 32 bit floating point constant
358
   "l" 32 bit floating point constant in .lit4
359
 
360
   MDMX instruction operands (note that while these use the FP register
361
   fields, they accept both $fN and $vN names for the registers):
362
   "O"  MDMX alignment offset (OP_*_ALN)
363
   "Q"  MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
364
   "X"  MDMX destination register (OP_*_FD)
365
   "Y"  MDMX source register (OP_*_FS)
366
   "Z"  MDMX source register (OP_*_FT)
367
 
368
   DSP ASE usage:
369
   "2" 2 bit unsigned immediate for byte align (OP_*_BP)
370
   "3" 3 bit unsigned immediate (OP_*_SA3)
371
   "4" 4 bit unsigned immediate (OP_*_SA4)
372
   "5" 8 bit unsigned immediate (OP_*_IMM8)
373
   "6" 5 bit unsigned immediate (OP_*_RS)
374
   "7" 2 bit dsp accumulator register (OP_*_DSPACC)
375
   "8" 6 bit unsigned immediate (OP_*_WRDSP)
376
   "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
377
   "0" 6 bit signed immediate (OP_*_DSPSFT)
378
   ":" 7 bit signed immediate (OP_*_DSPSFT_7)
379
   "'" 6 bit unsigned immediate (OP_*_RDDSP)
380
   "@" 10 bit signed immediate (OP_*_IMM10)
381
 
382
   MT ASE usage:
383
   "!" 1 bit usermode flag (OP_*_MT_U)
384
   "$" 1 bit load high flag (OP_*_MT_H)
385
   "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
386
   "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
387
   "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
388
   "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
389
   "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
390
 
391
   UDI immediates:
392
   "+1" UDI immediate bits 6-10
393
   "+2" UDI immediate bits 6-15
394
   "+3" UDI immediate bits 6-20
395
   "+4" UDI immediate bits 6-25
396
 
397
   Octeon:
398
   "+x" Bit index field of bbit.  Enforces: 0 <= index < 32.
399
   "+X" Bit index field of bbit aliasing bbit32.  Matches if 32 <= index < 64,
400
        otherwise skips to next candidate.
401
   "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
402
   "+P" Position field of cins/exts aliasing cins32/exts32.  Matches if
403
        32 <= pos < 64, otherwise skips to next candidate.
404
   "+Q" Immediate field of seqi/snei.  Enforces -512 <= imm < 512.
405
   "+s" Length-minus-one field of cins/exts.  Enforces: 0 <= lenm1 < 32.
406
   "+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing
407
        cint32/exts32.  Enforces non-negative value and that
408
        pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous
409
        position field is "+p" or "+P".
410
 
411
   Loongson-3A:
412
   "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
413
   "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
414
   "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
415
   "+z" 5-bit rz register (OP_*_RZ)
416
   "+Z" 5-bit fz register (OP_*_FZ)
417
 
418
   Other:
419
   "()" parens surrounding optional value
420
   ","  separates operands
421
   "[]" brackets around index for vector-op scalar operand specifier (vr5400)
422
   "+"  Start of extension sequence.
423
 
424
   Characters used so far, for quick reference when adding more:
425
   "1234567890"
426
   "%[]<>(),+:'@!$*&"
427
   "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
428
   "abcdefghijklopqrstuvwxz"
429
 
430
   Extension character sequences used so far ("+" followed by the
431
   following), for quick reference when adding more:
432
   "1234"
433
   "ABCDEFGHIPQSTXZ"
434
   "abcpstxz"
435
*/
436
 
437
/* These are the bits which may be set in the pinfo field of an
438
   instructions, if it is not equal to INSN_MACRO.  */
439
 
440
/* Modifies the general purpose register in OP_*_RD.  */
441
#define INSN_WRITE_GPR_D            0x00000001
442
/* Modifies the general purpose register in OP_*_RT.  */
443
#define INSN_WRITE_GPR_T            0x00000002
444
/* Modifies general purpose register 31.  */
445
#define INSN_WRITE_GPR_31           0x00000004
446
/* Modifies the floating point register in OP_*_FD.  */
447
#define INSN_WRITE_FPR_D            0x00000008
448
/* Modifies the floating point register in OP_*_FS.  */
449
#define INSN_WRITE_FPR_S            0x00000010
450
/* Modifies the floating point register in OP_*_FT.  */
451
#define INSN_WRITE_FPR_T            0x00000020
452
/* Reads the general purpose register in OP_*_RS.  */
453
#define INSN_READ_GPR_S             0x00000040
454
/* Reads the general purpose register in OP_*_RT.  */
455
#define INSN_READ_GPR_T             0x00000080
456
/* Reads the floating point register in OP_*_FS.  */
457
#define INSN_READ_FPR_S             0x00000100
458
/* Reads the floating point register in OP_*_FT.  */
459
#define INSN_READ_FPR_T             0x00000200
460
/* Reads the floating point register in OP_*_FR.  */
461
#define INSN_READ_FPR_R             0x00000400
462
/* Modifies coprocessor condition code.  */
463
#define INSN_WRITE_COND_CODE        0x00000800
464
/* Reads coprocessor condition code.  */
465
#define INSN_READ_COND_CODE         0x00001000
466
/* TLB operation.  */
467
#define INSN_TLB                    0x00002000
468
/* Reads coprocessor register other than floating point register.  */
469
#define INSN_COP                    0x00004000
470
/* Instruction loads value from memory, requiring delay.  */
471
#define INSN_LOAD_MEMORY_DELAY      0x00008000
472
/* Instruction loads value from coprocessor, requiring delay.  */
473
#define INSN_LOAD_COPROC_DELAY      0x00010000
474
/* Instruction has unconditional branch delay slot.  */
475
#define INSN_UNCOND_BRANCH_DELAY    0x00020000
476
/* Instruction has conditional branch delay slot.  */
477
#define INSN_COND_BRANCH_DELAY      0x00040000
478
/* Conditional branch likely: if branch not taken, insn nullified.  */
479
#define INSN_COND_BRANCH_LIKELY     0x00080000
480
/* Moves to coprocessor register, requiring delay.  */
481
#define INSN_COPROC_MOVE_DELAY      0x00100000
482
/* Loads coprocessor register from memory, requiring delay.  */
483
#define INSN_COPROC_MEMORY_DELAY    0x00200000
484
/* Reads the HI register.  */
485
#define INSN_READ_HI                0x00400000
486
/* Reads the LO register.  */
487
#define INSN_READ_LO                0x00800000
488
/* Modifies the HI register.  */
489
#define INSN_WRITE_HI               0x01000000
490
/* Modifies the LO register.  */
491
#define INSN_WRITE_LO               0x02000000
492
/* Takes a trap (easier to keep out of delay slot).  */
493
#define INSN_TRAP                   0x04000000
494
/* Instruction stores value into memory.  */
495
#define INSN_STORE_MEMORY           0x08000000
496
/* Instruction uses single precision floating point.  */
497
#define FP_S                        0x10000000
498
/* Instruction uses double precision floating point.  */
499
#define FP_D                        0x20000000
500
/* Instruction is part of the tx39's integer multiply family.    */
501
#define INSN_MULT                   0x40000000
502
/* Instruction synchronize shared memory.  */
503
#define INSN_SYNC                   0x80000000
504
/* Instruction is actually a macro.  It should be ignored by the
505
   disassembler, and requires special treatment by the assembler.  */
506
#define INSN_MACRO                  0xffffffff
507
 
508
/* These are the bits which may be set in the pinfo2 field of an
509
   instruction. */
510
 
511
/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
512
#define INSN2_ALIAS                 0x00000001
513
/* Instruction reads MDMX accumulator. */
514
#define INSN2_READ_MDMX_ACC         0x00000002
515
/* Instruction writes MDMX accumulator. */
516
#define INSN2_WRITE_MDMX_ACC        0x00000004
517
/* Macro uses single-precision floating-point instructions.  This should
518
   only be set for macros.  For instructions, FP_S in pinfo carries the
519
   same information.  */
520
#define INSN2_M_FP_S                0x00000008
521
/* Macro uses double-precision floating-point instructions.  This should
522
   only be set for macros.  For instructions, FP_D in pinfo carries the
523
   same information.  */
524
#define INSN2_M_FP_D                0x00000010
525
/* Modifies the general purpose register in OP_*_RZ.  */
526
#define INSN2_WRITE_GPR_Z           0x00000020
527
/* Modifies the floating point register in OP_*_FZ.  */
528
#define INSN2_WRITE_FPR_Z           0x00000040
529
/* Reads the general purpose register in OP_*_RZ.  */
530
#define INSN2_READ_GPR_Z            0x00000080
531
/* Reads the floating point register in OP_*_FZ.  */
532
#define INSN2_READ_FPR_Z            0x00000100
533
/* Reads the general purpose register in OP_*_RD.  */
534
#define INSN2_READ_GPR_D            0x00000200
535
 
536
 
537
/* Masks used to mark instructions to indicate which MIPS ISA level
538
   they were introduced in.  INSN_ISA_MASK masks an enumeration that
539
   specifies the base ISA level(s).  The remainder of a 32-bit
540
   word constructed using these macros is a bitmask of the remaining
541
   INSN_* values below.  */
542
 
543
#define INSN_ISA_MASK             0x0000000ful
544
 
545
/* We cannot start at zero due to ISA_UNKNOWN below.  */
546
#define INSN_ISA1                 1
547
#define INSN_ISA2                 2
548
#define INSN_ISA3                 3
549
#define INSN_ISA4                 4
550
#define INSN_ISA5                 5
551
#define INSN_ISA32                6
552
#define INSN_ISA32R2              7
553
#define INSN_ISA64                8
554
#define INSN_ISA64R2              9
555
/* Below this point the INSN_* values correspond to combinations of ISAs.
556
   They are only for use in the opcodes table to indicate membership of
557
   a combination of ISAs that cannot be expressed using the usual inclusion
558
   ordering on the above INSN_* values.  */
559
#define INSN_ISA3_32              10
560
#define INSN_ISA3_32R2            11
561
#define INSN_ISA4_32              12
562
#define INSN_ISA4_32R2            13
563
#define INSN_ISA5_32R2            14
564
 
565
/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
566
   INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
567
   this table describes whether at least one of the ISAs described by X
568
   is/are implemented by ISA Y.  (Think of Y as the ISA level supported by
569
   a particular core and X as the ISA level(s) at which a certain instruction
570
   is defined.)  The ISA(s) described by X is/are implemented by Y iff
571
   (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
572
   is non-zero.  */
573
static const unsigned int mips_isa_table[] =
574
  { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
575
 
576
/* Masks used for Chip specific instructions.  */
577
#define INSN_CHIP_MASK            0xc3ff0c20
578
 
579
/* Cavium Networks Octeon instructions.  */
580
#define INSN_OCTEON               0x00000800
581
 
582
/* Masks used for MIPS-defined ASEs.  */
583
#define INSN_ASE_MASK             0x3c00f000
584
 
585
/* DSP ASE */
586
#define INSN_DSP                  0x00001000
587
#define INSN_DSP64                0x00002000
588
 
589
/* 0x00004000 is unused.  */
590
 
591
/* MIPS-3D ASE */
592
#define INSN_MIPS3D               0x00008000
593
 
594
/* MIPS R4650 instruction.  */
595
#define INSN_4650                 0x00010000
596
/* LSI R4010 instruction.  */
597
#define INSN_4010                 0x00020000
598
/* NEC VR4100 instruction.  */
599
#define INSN_4100                 0x00040000
600
/* Toshiba R3900 instruction.  */
601
#define INSN_3900                 0x00080000
602
/* MIPS R10000 instruction.  */
603
#define INSN_10000                0x00100000
604
/* Broadcom SB-1 instruction.  */
605
#define INSN_SB1                  0x00200000
606
/* NEC VR4111/VR4181 instruction.  */
607
#define INSN_4111                 0x00400000
608
/* NEC VR4120 instruction.  */
609
#define INSN_4120                 0x00800000
610
/* NEC VR5400 instruction.  */
611
#define INSN_5400                 0x01000000
612
/* NEC VR5500 instruction.  */
613
#define INSN_5500                 0x02000000
614
 
615
/* MDMX ASE */
616
#define INSN_MDMX                 0x04000000
617
/* MT ASE */
618
#define INSN_MT                   0x08000000
619
/* SmartMIPS ASE  */
620
#define INSN_SMARTMIPS            0x10000000
621
/* DSP R2 ASE  */
622
#define INSN_DSPR2                0x20000000
623
/* ST Microelectronics Loongson 2E.  */
624
#define INSN_LOONGSON_2E          0x40000000
625
/* ST Microelectronics Loongson 2F.  */
626
#define INSN_LOONGSON_2F          0x80000000
627
/* Loongson 3A.  */
628
#define INSN_LOONGSON_3A          0x00000400
629
/* RMI Xlr instruction */
630
#define INSN_XLR                  0x00000020
631
 
632
/* MIPS ISA defines, use instead of hardcoding ISA level.  */
633
 
634
#define       ISA_UNKNOWN     0               /* Gas internal use.  */
635
#define       ISA_MIPS1       INSN_ISA1
636
#define       ISA_MIPS2       INSN_ISA2
637
#define       ISA_MIPS3       INSN_ISA3
638
#define       ISA_MIPS4       INSN_ISA4
639
#define       ISA_MIPS5       INSN_ISA5
640
 
641
#define       ISA_MIPS32      INSN_ISA32
642
#define       ISA_MIPS64      INSN_ISA64
643
 
644
#define       ISA_MIPS32R2    INSN_ISA32R2
645
#define       ISA_MIPS64R2    INSN_ISA64R2
646
 
647
 
648
/* CPU defines, use instead of hardcoding processor number. Keep this
649
   in sync with bfd/archures.c in order for machine selection to work.  */
650
#define CPU_UNKNOWN     0               /* Gas internal use.  */
651
#define CPU_R3000       3000
652
#define CPU_R3900       3900
653
#define CPU_R4000       4000
654
#define CPU_R4010       4010
655
#define CPU_VR4100      4100
656
#define CPU_R4111       4111
657
#define CPU_VR4120      4120
658
#define CPU_R4300       4300
659
#define CPU_R4400       4400
660
#define CPU_R4600       4600
661
#define CPU_R4650       4650
662
#define CPU_R5000       5000
663
#define CPU_VR5400      5400
664
#define CPU_VR5500      5500
665
#define CPU_R6000       6000
666
#define CPU_RM7000      7000
667
#define CPU_R8000       8000
668
#define CPU_RM9000      9000
669
#define CPU_R10000      10000
670
#define CPU_R12000      12000
671
#define CPU_R14000      14000
672
#define CPU_R16000      16000
673
#define CPU_MIPS16      16
674
#define CPU_MIPS32      32
675
#define CPU_MIPS32R2    33
676
#define CPU_MIPS5       5
677
#define CPU_MIPS64      64
678
#define CPU_MIPS64R2    65
679
#define CPU_SB1         12310201        /* octal 'SB', 01.  */
680
#define CPU_LOONGSON_2E 3001
681
#define CPU_LOONGSON_2F 3002
682
#define CPU_LOONGSON_3A 3003
683
#define CPU_OCTEON      6501
684
#define CPU_XLR         887682          /* decimal 'XLR'   */
685
 
686
/* Test for membership in an ISA including chip specific ISAs.  INSN
687
   is pointer to an element of the opcode table; ISA is the specified
688
   ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
689
   test, or zero if no CPU specific ISA test is desired.  */
690
 
691
#define OPCODE_IS_MEMBER(insn, isa, cpu)                                \
692
    (((isa & INSN_ISA_MASK) != 0                                        \
693
      && ((insn)->membership & INSN_ISA_MASK) != 0                      \
694
      && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >>                \
695
           (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0)       \
696
     || ((isa & ~INSN_ISA_MASK)                                         \
697
          & ((insn)->membership & ~INSN_ISA_MASK)) != 0                 \
698
     || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)      \
699
     || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)     \
700
     || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)     \
701
     || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)      \
702
     || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)     \
703
     || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)      \
704
     || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000   \
705
          || cpu == CPU_R16000)                                         \
706
         && ((insn)->membership & INSN_10000) != 0)                      \
707
     || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
708
     || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)      \
709
     || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)     \
710
     || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)     \
711
     || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)     \
712
     || (cpu == CPU_LOONGSON_2E                                         \
713
         && ((insn)->membership & INSN_LOONGSON_2E) != 0)               \
714
     || (cpu == CPU_LOONGSON_2F                                         \
715
         && ((insn)->membership & INSN_LOONGSON_2F) != 0)               \
716
     || (cpu == CPU_LOONGSON_3A                                         \
717
         && ((insn)->membership & INSN_LOONGSON_3A) != 0)               \
718
     || (cpu == CPU_OCTEON                                              \
719
         && ((insn)->membership & INSN_OCTEON) != 0)                     \
720
     || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0)        \
721
     || 0)       /* Please keep this term for easier source merging.  */
722
 
723
/* This is a list of macro expanded instructions.
724
 
725
   _I appended means immediate
726
   _A appended means address
727
   _AB appended means address with base register
728
   _D appended means 64 bit floating point constant
729
   _S appended means 32 bit floating point constant.  */
730
 
731
enum
732
{
733
  M_ABS,
734
  M_ADD_I,
735
  M_ADDU_I,
736
  M_AND_I,
737
  M_BALIGN,
738
  M_BEQ,
739
  M_BEQ_I,
740
  M_BEQL_I,
741
  M_BGE,
742
  M_BGEL,
743
  M_BGE_I,
744
  M_BGEL_I,
745
  M_BGEU,
746
  M_BGEUL,
747
  M_BGEU_I,
748
  M_BGEUL_I,
749
  M_BGT,
750
  M_BGTL,
751
  M_BGT_I,
752
  M_BGTL_I,
753
  M_BGTU,
754
  M_BGTUL,
755
  M_BGTU_I,
756
  M_BGTUL_I,
757
  M_BLE,
758
  M_BLEL,
759
  M_BLE_I,
760
  M_BLEL_I,
761
  M_BLEU,
762
  M_BLEUL,
763
  M_BLEU_I,
764
  M_BLEUL_I,
765
  M_BLT,
766
  M_BLTL,
767
  M_BLT_I,
768
  M_BLTL_I,
769
  M_BLTU,
770
  M_BLTUL,
771
  M_BLTU_I,
772
  M_BLTUL_I,
773
  M_BNE,
774
  M_BNE_I,
775
  M_BNEL_I,
776
  M_CACHE_AB,
777
  M_DABS,
778
  M_DADD_I,
779
  M_DADDU_I,
780
  M_DDIV_3,
781
  M_DDIV_3I,
782
  M_DDIVU_3,
783
  M_DDIVU_3I,
784
  M_DEXT,
785
  M_DINS,
786
  M_DIV_3,
787
  M_DIV_3I,
788
  M_DIVU_3,
789
  M_DIVU_3I,
790
  M_DLA_AB,
791
  M_DLCA_AB,
792
  M_DLI,
793
  M_DMUL,
794
  M_DMUL_I,
795
  M_DMULO,
796
  M_DMULO_I,
797
  M_DMULOU,
798
  M_DMULOU_I,
799
  M_DREM_3,
800
  M_DREM_3I,
801
  M_DREMU_3,
802
  M_DREMU_3I,
803
  M_DSUB_I,
804
  M_DSUBU_I,
805
  M_DSUBU_I_2,
806
  M_J_A,
807
  M_JAL_1,
808
  M_JAL_2,
809
  M_JAL_A,
810
  M_L_DOB,
811
  M_L_DAB,
812
  M_LA_AB,
813
  M_LB_A,
814
  M_LB_AB,
815
  M_LBU_A,
816
  M_LBU_AB,
817
  M_LCA_AB,
818
  M_LD_A,
819
  M_LD_OB,
820
  M_LD_AB,
821
  M_LDC1_AB,
822
  M_LDC2_AB,
823
  M_LDC3_AB,
824
  M_LDL_AB,
825
  M_LDR_AB,
826
  M_LH_A,
827
  M_LH_AB,
828
  M_LHU_A,
829
  M_LHU_AB,
830
  M_LI,
831
  M_LI_D,
832
  M_LI_DD,
833
  M_LI_S,
834
  M_LI_SS,
835
  M_LL_AB,
836
  M_LLD_AB,
837
  M_LS_A,
838
  M_LW_A,
839
  M_LW_AB,
840
  M_LWC0_A,
841
  M_LWC0_AB,
842
  M_LWC1_A,
843
  M_LWC1_AB,
844
  M_LWC2_A,
845
  M_LWC2_AB,
846
  M_LWC3_A,
847
  M_LWC3_AB,
848
  M_LWL_A,
849
  M_LWL_AB,
850
  M_LWR_A,
851
  M_LWR_AB,
852
  M_LWU_AB,
853
  M_MSGSND,
854
  M_MSGLD,
855
  M_MSGLD_T,
856
  M_MSGWAIT,
857
  M_MSGWAIT_T,
858
  M_MOVE,
859
  M_MUL,
860
  M_MUL_I,
861
  M_MULO,
862
  M_MULO_I,
863
  M_MULOU,
864
  M_MULOU_I,
865
  M_NOR_I,
866
  M_OR_I,
867
  M_PREF_AB,
868
  M_REM_3,
869
  M_REM_3I,
870
  M_REMU_3,
871
  M_REMU_3I,
872
  M_DROL,
873
  M_ROL,
874
  M_DROL_I,
875
  M_ROL_I,
876
  M_DROR,
877
  M_ROR,
878
  M_DROR_I,
879
  M_ROR_I,
880
  M_S_DA,
881
  M_S_DOB,
882
  M_S_DAB,
883
  M_S_S,
884
  M_SC_AB,
885
  M_SCD_AB,
886
  M_SD_A,
887
  M_SD_OB,
888
  M_SD_AB,
889
  M_SDC1_AB,
890
  M_SDC2_AB,
891
  M_SDC3_AB,
892
  M_SDL_AB,
893
  M_SDR_AB,
894
  M_SEQ,
895
  M_SEQ_I,
896
  M_SGE,
897
  M_SGE_I,
898
  M_SGEU,
899
  M_SGEU_I,
900
  M_SGT,
901
  M_SGT_I,
902
  M_SGTU,
903
  M_SGTU_I,
904
  M_SLE,
905
  M_SLE_I,
906
  M_SLEU,
907
  M_SLEU_I,
908
  M_SLT_I,
909
  M_SLTU_I,
910
  M_SNE,
911
  M_SNE_I,
912
  M_SB_A,
913
  M_SB_AB,
914
  M_SH_A,
915
  M_SH_AB,
916
  M_SW_A,
917
  M_SW_AB,
918
  M_SWC0_A,
919
  M_SWC0_AB,
920
  M_SWC1_A,
921
  M_SWC1_AB,
922
  M_SWC2_A,
923
  M_SWC2_AB,
924
  M_SWC3_A,
925
  M_SWC3_AB,
926
  M_SWL_A,
927
  M_SWL_AB,
928
  M_SWR_A,
929
  M_SWR_AB,
930
  M_SUB_I,
931
  M_SUBU_I,
932
  M_SUBU_I_2,
933
  M_TEQ_I,
934
  M_TGE_I,
935
  M_TGEU_I,
936
  M_TLT_I,
937
  M_TLTU_I,
938
  M_TNE_I,
939
  M_TRUNCWD,
940
  M_TRUNCWS,
941
  M_ULD,
942
  M_ULD_A,
943
  M_ULH,
944
  M_ULH_A,
945
  M_ULHU,
946
  M_ULHU_A,
947
  M_ULW,
948
  M_ULW_A,
949
  M_USH,
950
  M_USH_A,
951
  M_USW,
952
  M_USW_A,
953
  M_USD,
954
  M_USD_A,
955
  M_XOR_I,
956
  M_COP0,
957
  M_COP1,
958
  M_COP2,
959
  M_COP3,
960
  M_NUM_MACROS
961
};
962
 
963
 
964
/* The order of overloaded instructions matters.  Label arguments and
965
   register arguments look the same. Instructions that can have either
966
   for arguments must apear in the correct order in this table for the
967
   assembler to pick the right one. In other words, entries with
968
   immediate operands must apear after the same instruction with
969
   registers.
970
 
971
   Many instructions are short hand for other instructions (i.e., The
972
   jal <register> instruction is short for jalr <register>).  */
973
 
974
extern const struct mips_opcode mips_builtin_opcodes[];
975
extern const int bfd_mips_num_builtin_opcodes;
976
extern struct mips_opcode *mips_opcodes;
977
extern int bfd_mips_num_opcodes;
978
#define NUMOPCODES bfd_mips_num_opcodes
979
 
980
 
981
/* The rest of this file adds definitions for the mips16 TinyRISC
982
   processor.  */
983
 
984
/* These are the bitmasks and shift counts used for the different
985
   fields in the instruction formats.  Other than OP, no masks are
986
   provided for the fixed portions of an instruction, since they are
987
   not needed.
988
 
989
   The I format uses IMM11.
990
 
991
   The RI format uses RX and IMM8.
992
 
993
   The RR format uses RX, and RY.
994
 
995
   The RRI format uses RX, RY, and IMM5.
996
 
997
   The RRR format uses RX, RY, and RZ.
998
 
999
   The RRI_A format uses RX, RY, and IMM4.
1000
 
1001
   The SHIFT format uses RX, RY, and SHAMT.
1002
 
1003
   The I8 format uses IMM8.
1004
 
1005
   The I8_MOVR32 format uses RY and REGR32.
1006
 
1007
   The IR_MOV32R format uses REG32R and MOV32Z.
1008
 
1009
   The I64 format uses IMM8.
1010
 
1011
   The RI64 format uses RY and IMM5.
1012
   */
1013
 
1014
#define MIPS16OP_MASK_OP        0x1f
1015
#define MIPS16OP_SH_OP          11
1016
#define MIPS16OP_MASK_IMM11     0x7ff
1017
#define MIPS16OP_SH_IMM11       0
1018
#define MIPS16OP_MASK_RX        0x7
1019
#define MIPS16OP_SH_RX          8
1020
#define MIPS16OP_MASK_IMM8      0xff
1021
#define MIPS16OP_SH_IMM8        0
1022
#define MIPS16OP_MASK_RY        0x7
1023
#define MIPS16OP_SH_RY          5
1024
#define MIPS16OP_MASK_IMM5      0x1f
1025
#define MIPS16OP_SH_IMM5        0
1026
#define MIPS16OP_MASK_RZ        0x7
1027
#define MIPS16OP_SH_RZ          2
1028
#define MIPS16OP_MASK_IMM4      0xf
1029
#define MIPS16OP_SH_IMM4        0
1030
#define MIPS16OP_MASK_REGR32    0x1f
1031
#define MIPS16OP_SH_REGR32      0
1032
#define MIPS16OP_MASK_REG32R    0x1f
1033
#define MIPS16OP_SH_REG32R      3
1034
#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
1035
#define MIPS16OP_MASK_MOVE32Z   0x7
1036
#define MIPS16OP_SH_MOVE32Z     0
1037
#define MIPS16OP_MASK_IMM6      0x3f
1038
#define MIPS16OP_SH_IMM6        5
1039
 
1040
/* These are the characters which may appears in the args field of a MIPS16
1041
   instruction.  They appear in the order in which the fields appear when the
1042
   instruction is used.  Commas and parentheses in the args string are ignored
1043
   when assembling, and written into the output when disassembling.
1044
 
1045
   "y" 3 bit register (MIPS16OP_*_RY)
1046
   "x" 3 bit register (MIPS16OP_*_RX)
1047
   "z" 3 bit register (MIPS16OP_*_RZ)
1048
   "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
1049
   "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
1050
   "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
1051
   "0" zero register ($0)
1052
   "S" stack pointer ($sp or $29)
1053
   "P" program counter
1054
   "R" return address register ($ra or $31)
1055
   "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
1056
   "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
1057
   "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
1058
   "a" 26 bit jump address
1059
   "e" 11 bit extension value
1060
   "l" register list for entry instruction
1061
   "L" register list for exit instruction
1062
 
1063
   The remaining codes may be extended.  Except as otherwise noted,
1064
   the full extended operand is a 16 bit signed value.
1065
   "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1066
   ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1067
   "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1068
   "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1069
   "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1070
   "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1071
   "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1072
   "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1073
   "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1074
   "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1075
   "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1076
   "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1077
   "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1078
   "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1079
   "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1080
   "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1081
   "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1082
   "q" 11 bit branch address (MIPS16OP_*_IMM11)
1083
   "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1084
   "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1085
   "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1086
   "m" 7 bit register list for save instruction (18 bit extended)
1087
   "M" 7 bit register list for restore instruction (18 bit extended)
1088
  */
1089
 
1090
/* Save/restore encoding for the args field when all 4 registers are
1091
   either saved as arguments or saved/restored as statics.  */
1092
#define MIPS16_ALL_ARGS    0xe
1093
#define MIPS16_ALL_STATICS 0xb
1094
 
1095
/* For the mips16, we use the same opcode table format and a few of
1096
   the same flags.  However, most of the flags are different.  */
1097
 
1098
/* Modifies the register in MIPS16OP_*_RX.  */
1099
#define MIPS16_INSN_WRITE_X                 0x00000001
1100
/* Modifies the register in MIPS16OP_*_RY.  */
1101
#define MIPS16_INSN_WRITE_Y                 0x00000002
1102
/* Modifies the register in MIPS16OP_*_RZ.  */
1103
#define MIPS16_INSN_WRITE_Z                 0x00000004
1104
/* Modifies the T ($24) register.  */
1105
#define MIPS16_INSN_WRITE_T                 0x00000008
1106
/* Modifies the SP ($29) register.  */
1107
#define MIPS16_INSN_WRITE_SP                0x00000010
1108
/* Modifies the RA ($31) register.  */
1109
#define MIPS16_INSN_WRITE_31                0x00000020
1110
/* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
1111
#define MIPS16_INSN_WRITE_GPR_Y             0x00000040
1112
/* Reads the register in MIPS16OP_*_RX.  */
1113
#define MIPS16_INSN_READ_X                  0x00000080
1114
/* Reads the register in MIPS16OP_*_RY.  */
1115
#define MIPS16_INSN_READ_Y                  0x00000100
1116
/* Reads the register in MIPS16OP_*_MOVE32Z.  */
1117
#define MIPS16_INSN_READ_Z                  0x00000200
1118
/* Reads the T ($24) register.  */
1119
#define MIPS16_INSN_READ_T                  0x00000400
1120
/* Reads the SP ($29) register.  */
1121
#define MIPS16_INSN_READ_SP                 0x00000800
1122
/* Reads the RA ($31) register.  */
1123
#define MIPS16_INSN_READ_31                 0x00001000
1124
/* Reads the program counter.  */
1125
#define MIPS16_INSN_READ_PC                 0x00002000
1126
/* Reads the general purpose register in MIPS16OP_*_REGR32.  */
1127
#define MIPS16_INSN_READ_GPR_X              0x00004000
1128
/* Is an unconditional branch insn. */
1129
#define MIPS16_INSN_UNCOND_BRANCH           0x00008000
1130
/* Is a conditional branch insn. */
1131
#define MIPS16_INSN_COND_BRANCH             0x00010000
1132
 
1133
/* The following flags have the same value for the mips16 opcode
1134
   table:
1135
   INSN_UNCOND_BRANCH_DELAY
1136
   INSN_COND_BRANCH_DELAY
1137
   INSN_COND_BRANCH_LIKELY (never used)
1138
   INSN_READ_HI
1139
   INSN_READ_LO
1140
   INSN_WRITE_HI
1141
   INSN_WRITE_LO
1142
   INSN_TRAP
1143
   INSN_ISA3
1144
   */
1145
 
1146
extern const struct mips_opcode mips16_opcodes[];
1147
extern const int bfd_mips16_num_opcodes;
1148
 
1149
/* A NOP insn impemented as "or at,at,zero".
1150
   Used to implement -mfix-loongson2f.  */
1151
#define LOONGSON2F_NOP_INSN     0x00200825
1152
 
1153
#endif /* _MIPS_H_ */

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