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khays |
/* mips.h. Mips opcode list for GDB, the GNU debugger.
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Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
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2003, 2004, 2005, 2008, 2009, 2010
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Free Software Foundation, Inc.
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Contributed by Ralph Campbell and OSF
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Commented and modified by Ian Lance Taylor, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version 3,
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or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING3. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#ifndef _MIPS_H_
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#define _MIPS_H_
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/* These are bit masks and shift counts to use to access the various
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fields of an instruction. To retrieve the X field of an
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instruction, use the expression
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(i >> OP_SH_X) & OP_MASK_X
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To set the same field (to j), use
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i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
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Make sure you use fields that are appropriate for the instruction,
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of course.
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The 'i' format uses OP, RS, RT and IMMEDIATE.
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The 'j' format uses OP and TARGET.
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The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
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The 'b' format uses OP, RS, RT and DELTA.
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The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
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The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
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A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
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breakpoint instruction are not defined; Kane says the breakpoint
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code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
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only use ten bits). An optional two-operand form of break/sdbbp
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allows the lower ten bits to be set too, and MIPS32 and later
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architectures allow 20 bits to be set with a signal operand
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(using CODE20).
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The syscall instruction uses CODE20.
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The general coprocessor instructions use COPZ. */
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#define OP_MASK_OP 0x3f
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#define OP_SH_OP 26
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#define OP_MASK_RS 0x1f
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#define OP_SH_RS 21
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#define OP_MASK_FR 0x1f
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#define OP_SH_FR 21
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#define OP_MASK_FMT 0x1f
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#define OP_SH_FMT 21
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#define OP_MASK_BCC 0x7
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#define OP_SH_BCC 18
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#define OP_MASK_CODE 0x3ff
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#define OP_SH_CODE 16
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#define OP_MASK_CODE2 0x3ff
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#define OP_SH_CODE2 6
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#define OP_MASK_RT 0x1f
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#define OP_SH_RT 16
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#define OP_MASK_FT 0x1f
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#define OP_SH_FT 16
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#define OP_MASK_CACHE 0x1f
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#define OP_SH_CACHE 16
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#define OP_MASK_RD 0x1f
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#define OP_SH_RD 11
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#define OP_MASK_FS 0x1f
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#define OP_SH_FS 11
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#define OP_MASK_PREFX 0x1f
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#define OP_SH_PREFX 11
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#define OP_MASK_CCC 0x7
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#define OP_SH_CCC 8
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#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
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#define OP_SH_CODE20 6
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#define OP_MASK_SHAMT 0x1f
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#define OP_SH_SHAMT 6
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#define OP_MASK_EXTLSB OP_MASK_SHAMT
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#define OP_SH_EXTLSB OP_SH_SHAMT
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#define OP_MASK_STYPE OP_MASK_SHAMT
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#define OP_SH_STYPE OP_SH_SHAMT
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#define OP_MASK_FD 0x1f
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#define OP_SH_FD 6
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#define OP_MASK_TARGET 0x3ffffff
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#define OP_SH_TARGET 0
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#define OP_MASK_COPZ 0x1ffffff
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#define OP_SH_COPZ 0
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#define OP_MASK_IMMEDIATE 0xffff
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#define OP_SH_IMMEDIATE 0
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#define OP_MASK_DELTA 0xffff
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#define OP_SH_DELTA 0
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#define OP_MASK_FUNCT 0x3f
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#define OP_SH_FUNCT 0
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#define OP_MASK_SPEC 0x3f
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#define OP_SH_SPEC 0
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#define OP_SH_LOCC 8 /* FP condition code. */
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#define OP_SH_HICC 18 /* FP condition code. */
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#define OP_MASK_CC 0x7
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#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
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#define OP_MASK_COP1NORM 0x1 /* a single bit. */
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#define OP_SH_COP1SPEC 21 /* COP1 encodings. */
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#define OP_MASK_COP1SPEC 0xf
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#define OP_MASK_COP1SCLR 0x4
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#define OP_MASK_COP1CMP 0x3
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#define OP_SH_COP1CMP 4
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#define OP_SH_FORMAT 21 /* FP short format field. */
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#define OP_MASK_FORMAT 0x7
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#define OP_SH_TRUE 16
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#define OP_MASK_TRUE 0x1
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#define OP_SH_GE 17
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#define OP_MASK_GE 0x01
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#define OP_SH_UNSIGNED 16
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#define OP_MASK_UNSIGNED 0x1
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#define OP_SH_HINT 16
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#define OP_MASK_HINT 0x1f
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#define OP_SH_MMI 0 /* Multimedia (parallel) op. */
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#define OP_MASK_MMI 0x3f
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#define OP_SH_MMISUB 6
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#define OP_MASK_MMISUB 0x1f
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#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
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#define OP_SH_PERFREG 1
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#define OP_SH_SEL 0 /* Coprocessor select field. */
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#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
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#define OP_SH_CODE19 6 /* 19 bit wait code. */
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#define OP_MASK_CODE19 0x7ffff
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#define OP_SH_ALN 21
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#define OP_MASK_ALN 0x7
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#define OP_SH_VSEL 21
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#define OP_MASK_VSEL 0x1f
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#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
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but 0x8-0xf don't select bytes. */
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#define OP_SH_VECBYTE 22
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#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
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#define OP_SH_VECALIGN 21
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#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
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#define OP_SH_INSMSB 11
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#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
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#define OP_SH_EXTMSBD 11
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/* MIPS DSP ASE */
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#define OP_SH_DSPACC 11
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#define OP_MASK_DSPACC 0x3
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#define OP_SH_DSPACC_S 21
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#define OP_MASK_DSPACC_S 0x3
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#define OP_SH_DSPSFT 20
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#define OP_MASK_DSPSFT 0x3f
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#define OP_SH_DSPSFT_7 19
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#define OP_MASK_DSPSFT_7 0x7f
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#define OP_SH_SA3 21
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#define OP_MASK_SA3 0x7
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#define OP_SH_SA4 21
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#define OP_MASK_SA4 0xf
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#define OP_SH_IMM8 16
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#define OP_MASK_IMM8 0xff
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#define OP_SH_IMM10 16
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#define OP_MASK_IMM10 0x3ff
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#define OP_SH_WRDSP 11
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#define OP_MASK_WRDSP 0x3f
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#define OP_SH_RDDSP 16
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#define OP_MASK_RDDSP 0x3f
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#define OP_SH_BP 11
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#define OP_MASK_BP 0x3
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/* MIPS MT ASE */
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#define OP_SH_MT_U 5
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#define OP_MASK_MT_U 0x1
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#define OP_SH_MT_H 4
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#define OP_MASK_MT_H 0x1
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#define OP_SH_MTACC_T 18
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#define OP_MASK_MTACC_T 0x3
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#define OP_SH_MTACC_D 13
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#define OP_MASK_MTACC_D 0x3
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khays |
/* MIPS MCU ASE */
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#define OP_MASK_3BITPOS 0x7
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#define OP_SH_3BITPOS 12
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#define OP_MASK_OFFSET12 0xfff
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#define OP_SH_OFFSET12 0
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#define OP_OP_COP0 0x10
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#define OP_OP_COP1 0x11
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#define OP_OP_COP2 0x12
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#define OP_OP_COP3 0x13
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#define OP_OP_LWC1 0x31
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#define OP_OP_LWC2 0x32
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#define OP_OP_LWC3 0x33 /* a.k.a. pref */
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#define OP_OP_LDC1 0x35
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#define OP_OP_LDC2 0x36
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#define OP_OP_LDC3 0x37 /* a.k.a. ld */
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#define OP_OP_SWC1 0x39
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#define OP_OP_SWC2 0x3a
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#define OP_OP_SWC3 0x3b
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#define OP_OP_SDC1 0x3d
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#define OP_OP_SDC2 0x3e
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#define OP_OP_SDC3 0x3f /* a.k.a. sd */
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/* Values in the 'VSEL' field. */
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#define MDMX_FMTSEL_IMM_QH 0x1d
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#define MDMX_FMTSEL_IMM_OB 0x1e
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#define MDMX_FMTSEL_VEC_QH 0x15
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#define MDMX_FMTSEL_VEC_OB 0x16
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/* UDI */
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#define OP_SH_UDI1 6
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#define OP_MASK_UDI1 0x1f
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#define OP_SH_UDI2 6
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#define OP_MASK_UDI2 0x3ff
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#define OP_SH_UDI3 6
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#define OP_MASK_UDI3 0x7fff
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#define OP_SH_UDI4 6
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#define OP_MASK_UDI4 0xfffff
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/* Octeon */
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#define OP_SH_BBITIND 16
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#define OP_MASK_BBITIND 0x1f
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#define OP_SH_CINSPOS 6
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#define OP_MASK_CINSPOS 0x1f
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#define OP_SH_CINSLM1 11
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#define OP_MASK_CINSLM1 0x1f
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#define OP_SH_SEQI 6
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#define OP_MASK_SEQI 0x3ff
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/* Loongson */
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#define OP_SH_OFFSET_A 6
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#define OP_MASK_OFFSET_A 0xff
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#define OP_SH_OFFSET_B 3
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#define OP_MASK_OFFSET_B 0xff
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#define OP_SH_OFFSET_C 6
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#define OP_MASK_OFFSET_C 0x1ff
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#define OP_SH_RZ 0
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#define OP_MASK_RZ 0x1f
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#define OP_SH_FZ 0
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#define OP_MASK_FZ 0x1f
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khays |
/* Every MICROMIPSOP_X definition requires a corresponding OP_X
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definition, and vice versa. This simplifies various parts
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of the operand handling in GAS. The fields below only exist
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in the microMIPS encoding, so define each one to have an empty
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range. */
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#define OP_MASK_CODE10 0
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#define OP_SH_CODE10 0
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#define OP_MASK_TRAP 0
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#define OP_SH_TRAP 0
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#define OP_MASK_OFFSET10 0
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#define OP_SH_OFFSET10 0
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#define OP_MASK_RS3 0
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#define OP_SH_RS3 0
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#define OP_MASK_MB 0
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#define OP_SH_MB 0
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#define OP_MASK_MC 0
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#define OP_SH_MC 0
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#define OP_MASK_MD 0
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#define OP_SH_MD 0
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#define OP_MASK_ME 0
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#define OP_SH_ME 0
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#define OP_MASK_MF 0
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#define OP_SH_MF 0
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#define OP_MASK_MG 0
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#define OP_SH_MG 0
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#define OP_MASK_MH 0
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#define OP_SH_MH 0
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#define OP_MASK_MI 0
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#define OP_SH_MI 0
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#define OP_MASK_MJ 0
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#define OP_SH_MJ 0
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#define OP_MASK_ML 0
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#define OP_SH_ML 0
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#define OP_MASK_MM 0
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#define OP_SH_MM 0
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#define OP_MASK_MN 0
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#define OP_SH_MN 0
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#define OP_MASK_MP 0
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#define OP_SH_MP 0
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#define OP_MASK_MQ 0
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#define OP_SH_MQ 0
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#define OP_MASK_IMMA 0
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#define OP_SH_IMMA 0
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#define OP_MASK_IMMB 0
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#define OP_SH_IMMB 0
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#define OP_MASK_IMMC 0
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#define OP_SH_IMMC 0
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#define OP_MASK_IMMF 0
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#define OP_SH_IMMF 0
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#define OP_MASK_IMMG 0
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#define OP_SH_IMMG 0
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#define OP_MASK_IMMH 0
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#define OP_SH_IMMH 0
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#define OP_MASK_IMMI 0
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#define OP_SH_IMMI 0
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#define OP_MASK_IMMJ 0
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#define OP_SH_IMMJ 0
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#define OP_MASK_IMML 0
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#define OP_SH_IMML 0
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#define OP_MASK_IMMM 0
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|
|
#define OP_SH_IMMM 0
|
| 312 |
|
|
#define OP_MASK_IMMN 0
|
| 313 |
|
|
#define OP_SH_IMMN 0
|
| 314 |
|
|
#define OP_MASK_IMMO 0
|
| 315 |
|
|
#define OP_SH_IMMO 0
|
| 316 |
|
|
#define OP_MASK_IMMP 0
|
| 317 |
|
|
#define OP_SH_IMMP 0
|
| 318 |
|
|
#define OP_MASK_IMMQ 0
|
| 319 |
|
|
#define OP_SH_IMMQ 0
|
| 320 |
|
|
#define OP_MASK_IMMU 0
|
| 321 |
|
|
#define OP_SH_IMMU 0
|
| 322 |
|
|
#define OP_MASK_IMMW 0
|
| 323 |
|
|
#define OP_SH_IMMW 0
|
| 324 |
|
|
#define OP_MASK_IMMX 0
|
| 325 |
|
|
#define OP_SH_IMMX 0
|
| 326 |
|
|
#define OP_MASK_IMMY 0
|
| 327 |
|
|
#define OP_SH_IMMY 0
|
| 328 |
|
|
|
| 329 |
17 |
khays |
/* This structure holds information for a particular instruction. */
|
| 330 |
|
|
|
| 331 |
|
|
struct mips_opcode
|
| 332 |
|
|
{
|
| 333 |
|
|
/* The name of the instruction. */
|
| 334 |
|
|
const char *name;
|
| 335 |
|
|
/* A string describing the arguments for this instruction. */
|
| 336 |
|
|
const char *args;
|
| 337 |
|
|
/* The basic opcode for the instruction. When assembling, this
|
| 338 |
|
|
opcode is modified by the arguments to produce the actual opcode
|
| 339 |
|
|
that is used. If pinfo is INSN_MACRO, then this is 0. */
|
| 340 |
|
|
unsigned long match;
|
| 341 |
|
|
/* If pinfo is not INSN_MACRO, then this is a bit mask for the
|
| 342 |
|
|
relevant portions of the opcode when disassembling. If the
|
| 343 |
|
|
actual opcode anded with the match field equals the opcode field,
|
| 344 |
|
|
then we have found the correct instruction. If pinfo is
|
| 345 |
|
|
INSN_MACRO, then this field is the macro identifier. */
|
| 346 |
|
|
unsigned long mask;
|
| 347 |
|
|
/* For a macro, this is INSN_MACRO. Otherwise, it is a collection
|
| 348 |
|
|
of bits describing the instruction, notably any relevant hazard
|
| 349 |
|
|
information. */
|
| 350 |
|
|
unsigned long pinfo;
|
| 351 |
|
|
/* A collection of additional bits describing the instruction. */
|
| 352 |
|
|
unsigned long pinfo2;
|
| 353 |
|
|
/* A collection of bits describing the instruction sets of which this
|
| 354 |
|
|
instruction or macro is a member. */
|
| 355 |
|
|
unsigned long membership;
|
| 356 |
|
|
};
|
| 357 |
|
|
|
| 358 |
|
|
/* These are the characters which may appear in the args field of an
|
| 359 |
|
|
instruction. They appear in the order in which the fields appear
|
| 360 |
|
|
when the instruction is used. Commas and parentheses in the args
|
| 361 |
|
|
string are ignored when assembling, and written into the output
|
| 362 |
|
|
when disassembling.
|
| 363 |
|
|
|
| 364 |
|
|
Each of these characters corresponds to a mask field defined above.
|
| 365 |
|
|
|
| 366 |
|
|
"1" 5 bit sync type (OP_*_SHAMT)
|
| 367 |
|
|
"<" 5 bit shift amount (OP_*_SHAMT)
|
| 368 |
|
|
">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
|
| 369 |
|
|
"a" 26 bit target address (OP_*_TARGET)
|
| 370 |
|
|
"b" 5 bit base register (OP_*_RS)
|
| 371 |
|
|
"c" 10 bit breakpoint code (OP_*_CODE)
|
| 372 |
|
|
"d" 5 bit destination register specifier (OP_*_RD)
|
| 373 |
|
|
"h" 5 bit prefx hint (OP_*_PREFX)
|
| 374 |
|
|
"i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
|
| 375 |
|
|
"j" 16 bit signed immediate (OP_*_DELTA)
|
| 376 |
|
|
"k" 5 bit cache opcode in target register position (OP_*_CACHE)
|
| 377 |
|
|
Also used for immediate operands in vr5400 vector insns.
|
| 378 |
|
|
"o" 16 bit signed offset (OP_*_DELTA)
|
| 379 |
|
|
"p" 16 bit PC relative branch target address (OP_*_DELTA)
|
| 380 |
|
|
"q" 10 bit extra breakpoint code (OP_*_CODE2)
|
| 381 |
|
|
"r" 5 bit same register used as both source and target (OP_*_RS)
|
| 382 |
|
|
"s" 5 bit source register specifier (OP_*_RS)
|
| 383 |
|
|
"t" 5 bit target register (OP_*_RT)
|
| 384 |
|
|
"u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
|
| 385 |
|
|
"v" 5 bit same register used as both source and destination (OP_*_RS)
|
| 386 |
|
|
"w" 5 bit same register used as both target and destination (OP_*_RT)
|
| 387 |
|
|
"U" 5 bit same destination register in both OP_*_RD and OP_*_RT
|
| 388 |
|
|
(used by clo and clz)
|
| 389 |
|
|
"C" 25 bit coprocessor function code (OP_*_COPZ)
|
| 390 |
|
|
"B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
|
| 391 |
|
|
"J" 19 bit wait function code (OP_*_CODE19)
|
| 392 |
|
|
"x" accept and ignore register name
|
| 393 |
|
|
"z" must be zero register
|
| 394 |
|
|
"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
|
| 395 |
|
|
"+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
|
| 396 |
161 |
khays |
LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for
|
| 397 |
|
|
microMIPS compatibility).
|
| 398 |
17 |
khays |
Enforces: 0 <= pos < 32.
|
| 399 |
|
|
"+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
|
| 400 |
|
|
Requires that "+A" or "+E" occur first to set position.
|
| 401 |
|
|
Enforces: 0 < (pos+size) <= 32.
|
| 402 |
|
|
"+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
|
| 403 |
|
|
Requires that "+A" or "+E" occur first to set position.
|
| 404 |
|
|
Enforces: 0 < (pos+size) <= 32.
|
| 405 |
|
|
(Also used by "dext" w/ different limits, but limits for
|
| 406 |
|
|
that are checked by the M_DEXT macro.)
|
| 407 |
|
|
"+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
|
| 408 |
|
|
Enforces: 32 <= pos < 64.
|
| 409 |
|
|
"+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
|
| 410 |
|
|
Requires that "+A" or "+E" occur first to set position.
|
| 411 |
|
|
Enforces: 32 < (pos+size) <= 64.
|
| 412 |
|
|
"+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
|
| 413 |
|
|
Requires that "+A" or "+E" occur first to set position.
|
| 414 |
|
|
Enforces: 32 < (pos+size) <= 64.
|
| 415 |
|
|
"+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
|
| 416 |
|
|
Requires that "+A" or "+E" occur first to set position.
|
| 417 |
|
|
Enforces: 32 < (pos+size) <= 64.
|
| 418 |
|
|
|
| 419 |
|
|
Floating point instructions:
|
| 420 |
|
|
"D" 5 bit destination register (OP_*_FD)
|
| 421 |
|
|
"M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
|
| 422 |
|
|
"N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
|
| 423 |
|
|
"S" 5 bit fs source 1 register (OP_*_FS)
|
| 424 |
|
|
"T" 5 bit ft source 2 register (OP_*_FT)
|
| 425 |
|
|
"R" 5 bit fr source 3 register (OP_*_FR)
|
| 426 |
|
|
"V" 5 bit same register used as floating source and destination (OP_*_FS)
|
| 427 |
|
|
"W" 5 bit same register used as floating target and destination (OP_*_FT)
|
| 428 |
|
|
|
| 429 |
|
|
Coprocessor instructions:
|
| 430 |
|
|
"E" 5 bit target register (OP_*_RT)
|
| 431 |
|
|
"G" 5 bit destination register (OP_*_RD)
|
| 432 |
|
|
"H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
|
| 433 |
|
|
"P" 5 bit performance-monitor register (OP_*_PERFREG)
|
| 434 |
|
|
"e" 5 bit vector register byte specifier (OP_*_VECBYTE)
|
| 435 |
|
|
"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
|
| 436 |
|
|
see also "k" above
|
| 437 |
|
|
"+D" Combined destination register ("G") and sel ("H") for CP0 ops,
|
| 438 |
|
|
for pretty-printing in disassembly only.
|
| 439 |
|
|
|
| 440 |
|
|
Macro instructions:
|
| 441 |
|
|
"A" General 32 bit expression
|
| 442 |
|
|
"I" 32 bit immediate (value placed in imm_expr).
|
| 443 |
|
|
"+I" 32 bit immediate (value placed in imm2_expr).
|
| 444 |
|
|
"F" 64 bit floating point constant in .rdata
|
| 445 |
|
|
"L" 64 bit floating point constant in .lit8
|
| 446 |
|
|
"f" 32 bit floating point constant
|
| 447 |
|
|
"l" 32 bit floating point constant in .lit4
|
| 448 |
|
|
|
| 449 |
|
|
MDMX instruction operands (note that while these use the FP register
|
| 450 |
|
|
fields, they accept both $fN and $vN names for the registers):
|
| 451 |
|
|
"O" MDMX alignment offset (OP_*_ALN)
|
| 452 |
|
|
"Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
|
| 453 |
|
|
"X" MDMX destination register (OP_*_FD)
|
| 454 |
|
|
"Y" MDMX source register (OP_*_FS)
|
| 455 |
|
|
"Z" MDMX source register (OP_*_FT)
|
| 456 |
|
|
|
| 457 |
|
|
DSP ASE usage:
|
| 458 |
|
|
"2" 2 bit unsigned immediate for byte align (OP_*_BP)
|
| 459 |
|
|
"3" 3 bit unsigned immediate (OP_*_SA3)
|
| 460 |
|
|
"4" 4 bit unsigned immediate (OP_*_SA4)
|
| 461 |
|
|
"5" 8 bit unsigned immediate (OP_*_IMM8)
|
| 462 |
|
|
"6" 5 bit unsigned immediate (OP_*_RS)
|
| 463 |
|
|
"7" 2 bit dsp accumulator register (OP_*_DSPACC)
|
| 464 |
|
|
"8" 6 bit unsigned immediate (OP_*_WRDSP)
|
| 465 |
|
|
"9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
|
| 466 |
|
|
"0" 6 bit signed immediate (OP_*_DSPSFT)
|
| 467 |
|
|
":" 7 bit signed immediate (OP_*_DSPSFT_7)
|
| 468 |
|
|
"'" 6 bit unsigned immediate (OP_*_RDDSP)
|
| 469 |
|
|
"@" 10 bit signed immediate (OP_*_IMM10)
|
| 470 |
|
|
|
| 471 |
|
|
MT ASE usage:
|
| 472 |
|
|
"!" 1 bit usermode flag (OP_*_MT_U)
|
| 473 |
|
|
"$" 1 bit load high flag (OP_*_MT_H)
|
| 474 |
|
|
"*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
|
| 475 |
|
|
"&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
|
| 476 |
|
|
"g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
|
| 477 |
|
|
"+t" 5 bit coprocessor 0 destination register (OP_*_RT)
|
| 478 |
|
|
"+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
|
| 479 |
|
|
|
| 480 |
161 |
khays |
MCU ASE usage:
|
| 481 |
|
|
"~" 12 bit offset (OP_*_OFFSET12)
|
| 482 |
|
|
"\" 3 bit position for aset and aclr (OP_*_3BITPOS)
|
| 483 |
|
|
|
| 484 |
17 |
khays |
UDI immediates:
|
| 485 |
|
|
"+1" UDI immediate bits 6-10
|
| 486 |
|
|
"+2" UDI immediate bits 6-15
|
| 487 |
|
|
"+3" UDI immediate bits 6-20
|
| 488 |
|
|
"+4" UDI immediate bits 6-25
|
| 489 |
|
|
|
| 490 |
|
|
Octeon:
|
| 491 |
|
|
"+x" Bit index field of bbit. Enforces: 0 <= index < 32.
|
| 492 |
|
|
"+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64,
|
| 493 |
|
|
otherwise skips to next candidate.
|
| 494 |
|
|
"+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
|
| 495 |
|
|
"+P" Position field of cins/exts aliasing cins32/exts32. Matches if
|
| 496 |
|
|
32 <= pos < 64, otherwise skips to next candidate.
|
| 497 |
|
|
"+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512.
|
| 498 |
|
|
"+s" Length-minus-one field of cins/exts. Enforces: 0 <= lenm1 < 32.
|
| 499 |
|
|
"+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing
|
| 500 |
|
|
cint32/exts32. Enforces non-negative value and that
|
| 501 |
|
|
pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous
|
| 502 |
|
|
position field is "+p" or "+P".
|
| 503 |
|
|
|
| 504 |
|
|
Loongson-3A:
|
| 505 |
|
|
"+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
|
| 506 |
|
|
"+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
|
| 507 |
|
|
"+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
|
| 508 |
|
|
"+z" 5-bit rz register (OP_*_RZ)
|
| 509 |
|
|
"+Z" 5-bit fz register (OP_*_FZ)
|
| 510 |
|
|
|
| 511 |
|
|
Other:
|
| 512 |
|
|
"()" parens surrounding optional value
|
| 513 |
|
|
"," separates operands
|
| 514 |
|
|
"[]" brackets around index for vector-op scalar operand specifier (vr5400)
|
| 515 |
|
|
"+" Start of extension sequence.
|
| 516 |
|
|
|
| 517 |
|
|
Characters used so far, for quick reference when adding more:
|
| 518 |
|
|
"1234567890"
|
| 519 |
161 |
khays |
"%[]<>(),+:'@!$*&\~"
|
| 520 |
17 |
khays |
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
|
| 521 |
|
|
"abcdefghijklopqrstuvwxz"
|
| 522 |
|
|
|
| 523 |
|
|
Extension character sequences used so far ("+" followed by the
|
| 524 |
|
|
following), for quick reference when adding more:
|
| 525 |
|
|
"1234"
|
| 526 |
|
|
"ABCDEFGHIPQSTXZ"
|
| 527 |
|
|
"abcpstxz"
|
| 528 |
|
|
*/
|
| 529 |
|
|
|
| 530 |
|
|
/* These are the bits which may be set in the pinfo field of an
|
| 531 |
|
|
instructions, if it is not equal to INSN_MACRO. */
|
| 532 |
|
|
|
| 533 |
|
|
/* Modifies the general purpose register in OP_*_RD. */
|
| 534 |
|
|
#define INSN_WRITE_GPR_D 0x00000001
|
| 535 |
|
|
/* Modifies the general purpose register in OP_*_RT. */
|
| 536 |
|
|
#define INSN_WRITE_GPR_T 0x00000002
|
| 537 |
|
|
/* Modifies general purpose register 31. */
|
| 538 |
|
|
#define INSN_WRITE_GPR_31 0x00000004
|
| 539 |
|
|
/* Modifies the floating point register in OP_*_FD. */
|
| 540 |
|
|
#define INSN_WRITE_FPR_D 0x00000008
|
| 541 |
|
|
/* Modifies the floating point register in OP_*_FS. */
|
| 542 |
|
|
#define INSN_WRITE_FPR_S 0x00000010
|
| 543 |
|
|
/* Modifies the floating point register in OP_*_FT. */
|
| 544 |
|
|
#define INSN_WRITE_FPR_T 0x00000020
|
| 545 |
|
|
/* Reads the general purpose register in OP_*_RS. */
|
| 546 |
|
|
#define INSN_READ_GPR_S 0x00000040
|
| 547 |
|
|
/* Reads the general purpose register in OP_*_RT. */
|
| 548 |
|
|
#define INSN_READ_GPR_T 0x00000080
|
| 549 |
|
|
/* Reads the floating point register in OP_*_FS. */
|
| 550 |
|
|
#define INSN_READ_FPR_S 0x00000100
|
| 551 |
|
|
/* Reads the floating point register in OP_*_FT. */
|
| 552 |
|
|
#define INSN_READ_FPR_T 0x00000200
|
| 553 |
|
|
/* Reads the floating point register in OP_*_FR. */
|
| 554 |
|
|
#define INSN_READ_FPR_R 0x00000400
|
| 555 |
|
|
/* Modifies coprocessor condition code. */
|
| 556 |
|
|
#define INSN_WRITE_COND_CODE 0x00000800
|
| 557 |
|
|
/* Reads coprocessor condition code. */
|
| 558 |
|
|
#define INSN_READ_COND_CODE 0x00001000
|
| 559 |
|
|
/* TLB operation. */
|
| 560 |
|
|
#define INSN_TLB 0x00002000
|
| 561 |
|
|
/* Reads coprocessor register other than floating point register. */
|
| 562 |
|
|
#define INSN_COP 0x00004000
|
| 563 |
|
|
/* Instruction loads value from memory, requiring delay. */
|
| 564 |
|
|
#define INSN_LOAD_MEMORY_DELAY 0x00008000
|
| 565 |
|
|
/* Instruction loads value from coprocessor, requiring delay. */
|
| 566 |
|
|
#define INSN_LOAD_COPROC_DELAY 0x00010000
|
| 567 |
|
|
/* Instruction has unconditional branch delay slot. */
|
| 568 |
|
|
#define INSN_UNCOND_BRANCH_DELAY 0x00020000
|
| 569 |
|
|
/* Instruction has conditional branch delay slot. */
|
| 570 |
|
|
#define INSN_COND_BRANCH_DELAY 0x00040000
|
| 571 |
|
|
/* Conditional branch likely: if branch not taken, insn nullified. */
|
| 572 |
|
|
#define INSN_COND_BRANCH_LIKELY 0x00080000
|
| 573 |
|
|
/* Moves to coprocessor register, requiring delay. */
|
| 574 |
|
|
#define INSN_COPROC_MOVE_DELAY 0x00100000
|
| 575 |
|
|
/* Loads coprocessor register from memory, requiring delay. */
|
| 576 |
|
|
#define INSN_COPROC_MEMORY_DELAY 0x00200000
|
| 577 |
|
|
/* Reads the HI register. */
|
| 578 |
|
|
#define INSN_READ_HI 0x00400000
|
| 579 |
|
|
/* Reads the LO register. */
|
| 580 |
|
|
#define INSN_READ_LO 0x00800000
|
| 581 |
|
|
/* Modifies the HI register. */
|
| 582 |
|
|
#define INSN_WRITE_HI 0x01000000
|
| 583 |
|
|
/* Modifies the LO register. */
|
| 584 |
|
|
#define INSN_WRITE_LO 0x02000000
|
| 585 |
161 |
khays |
/* Not to be placed in a branch delay slot, either architecturally
|
| 586 |
|
|
or for ease of handling (such as with instructions that take a trap). */
|
| 587 |
|
|
#define INSN_NO_DELAY_SLOT 0x04000000
|
| 588 |
17 |
khays |
/* Instruction stores value into memory. */
|
| 589 |
|
|
#define INSN_STORE_MEMORY 0x08000000
|
| 590 |
|
|
/* Instruction uses single precision floating point. */
|
| 591 |
|
|
#define FP_S 0x10000000
|
| 592 |
|
|
/* Instruction uses double precision floating point. */
|
| 593 |
|
|
#define FP_D 0x20000000
|
| 594 |
|
|
/* Instruction is part of the tx39's integer multiply family. */
|
| 595 |
|
|
#define INSN_MULT 0x40000000
|
| 596 |
161 |
khays |
/* Modifies the general purpose register in MICROMIPSOP_*_RS. */
|
| 597 |
|
|
#define INSN_WRITE_GPR_S 0x80000000
|
| 598 |
17 |
khays |
/* Instruction is actually a macro. It should be ignored by the
|
| 599 |
|
|
disassembler, and requires special treatment by the assembler. */
|
| 600 |
|
|
#define INSN_MACRO 0xffffffff
|
| 601 |
|
|
|
| 602 |
|
|
/* These are the bits which may be set in the pinfo2 field of an
|
| 603 |
|
|
instruction. */
|
| 604 |
|
|
|
| 605 |
|
|
/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
|
| 606 |
|
|
#define INSN2_ALIAS 0x00000001
|
| 607 |
|
|
/* Instruction reads MDMX accumulator. */
|
| 608 |
|
|
#define INSN2_READ_MDMX_ACC 0x00000002
|
| 609 |
|
|
/* Instruction writes MDMX accumulator. */
|
| 610 |
|
|
#define INSN2_WRITE_MDMX_ACC 0x00000004
|
| 611 |
|
|
/* Macro uses single-precision floating-point instructions. This should
|
| 612 |
|
|
only be set for macros. For instructions, FP_S in pinfo carries the
|
| 613 |
|
|
same information. */
|
| 614 |
|
|
#define INSN2_M_FP_S 0x00000008
|
| 615 |
|
|
/* Macro uses double-precision floating-point instructions. This should
|
| 616 |
|
|
only be set for macros. For instructions, FP_D in pinfo carries the
|
| 617 |
|
|
same information. */
|
| 618 |
|
|
#define INSN2_M_FP_D 0x00000010
|
| 619 |
|
|
/* Modifies the general purpose register in OP_*_RZ. */
|
| 620 |
|
|
#define INSN2_WRITE_GPR_Z 0x00000020
|
| 621 |
|
|
/* Modifies the floating point register in OP_*_FZ. */
|
| 622 |
|
|
#define INSN2_WRITE_FPR_Z 0x00000040
|
| 623 |
|
|
/* Reads the general purpose register in OP_*_RZ. */
|
| 624 |
|
|
#define INSN2_READ_GPR_Z 0x00000080
|
| 625 |
|
|
/* Reads the floating point register in OP_*_FZ. */
|
| 626 |
|
|
#define INSN2_READ_FPR_Z 0x00000100
|
| 627 |
|
|
/* Reads the general purpose register in OP_*_RD. */
|
| 628 |
|
|
#define INSN2_READ_GPR_D 0x00000200
|
| 629 |
|
|
|
| 630 |
|
|
|
| 631 |
161 |
khays |
/* Instruction has a branch delay slot that requires a 16-bit instruction. */
|
| 632 |
|
|
#define INSN2_BRANCH_DELAY_16BIT 0x00000400
|
| 633 |
|
|
/* Instruction has a branch delay slot that requires a 32-bit instruction. */
|
| 634 |
|
|
#define INSN2_BRANCH_DELAY_32BIT 0x00000800
|
| 635 |
|
|
/* Reads the floating point register in MICROMIPSOP_*_FD. */
|
| 636 |
|
|
#define INSN2_READ_FPR_D 0x00001000
|
| 637 |
|
|
/* Modifies the general purpose register in MICROMIPSOP_*_MB. */
|
| 638 |
|
|
#define INSN2_WRITE_GPR_MB 0x00002000
|
| 639 |
|
|
/* Reads the general purpose register in MICROMIPSOP_*_MC. */
|
| 640 |
|
|
#define INSN2_READ_GPR_MC 0x00004000
|
| 641 |
|
|
/* Reads/writes the general purpose register in MICROMIPSOP_*_MD. */
|
| 642 |
|
|
#define INSN2_MOD_GPR_MD 0x00008000
|
| 643 |
|
|
/* Reads the general purpose register in MICROMIPSOP_*_ME. */
|
| 644 |
|
|
#define INSN2_READ_GPR_ME 0x00010000
|
| 645 |
|
|
/* Reads/writes the general purpose register in MICROMIPSOP_*_MF. */
|
| 646 |
|
|
#define INSN2_MOD_GPR_MF 0x00020000
|
| 647 |
|
|
/* Reads the general purpose register in MICROMIPSOP_*_MG. */
|
| 648 |
|
|
#define INSN2_READ_GPR_MG 0x00040000
|
| 649 |
|
|
/* Reads the general purpose register in MICROMIPSOP_*_MJ. */
|
| 650 |
|
|
#define INSN2_READ_GPR_MJ 0x00080000
|
| 651 |
|
|
/* Modifies the general purpose register in MICROMIPSOP_*_MJ. */
|
| 652 |
|
|
#define INSN2_WRITE_GPR_MJ 0x00100000
|
| 653 |
|
|
/* Reads the general purpose register in MICROMIPSOP_*_MP. */
|
| 654 |
|
|
#define INSN2_READ_GPR_MP 0x00200000
|
| 655 |
|
|
/* Modifies the general purpose register in MICROMIPSOP_*_MP. */
|
| 656 |
|
|
#define INSN2_WRITE_GPR_MP 0x00400000
|
| 657 |
|
|
/* Reads the general purpose register in MICROMIPSOP_*_MQ. */
|
| 658 |
|
|
#define INSN2_READ_GPR_MQ 0x00800000
|
| 659 |
|
|
/* Reads/Writes the stack pointer ($29). */
|
| 660 |
|
|
#define INSN2_MOD_SP 0x01000000
|
| 661 |
|
|
/* Reads the RA ($31) register. */
|
| 662 |
|
|
#define INSN2_READ_GPR_31 0x02000000
|
| 663 |
|
|
/* Reads the global pointer ($28). */
|
| 664 |
|
|
#define INSN2_READ_GP 0x04000000
|
| 665 |
|
|
/* Reads the program counter ($pc). */
|
| 666 |
|
|
#define INSN2_READ_PC 0x08000000
|
| 667 |
|
|
/* Is an unconditional branch insn. */
|
| 668 |
|
|
#define INSN2_UNCOND_BRANCH 0x10000000
|
| 669 |
|
|
/* Is a conditional branch insn. */
|
| 670 |
|
|
#define INSN2_COND_BRANCH 0x20000000
|
| 671 |
|
|
/* Modifies the general purpose registers in MICROMIPSOP_*_MH/I. */
|
| 672 |
|
|
#define INSN2_WRITE_GPR_MHI 0x40000000
|
| 673 |
|
|
/* Reads the general purpose registers in MICROMIPSOP_*_MM/N. */
|
| 674 |
|
|
#define INSN2_READ_GPR_MMN 0x80000000
|
| 675 |
|
|
|
| 676 |
17 |
khays |
/* Masks used to mark instructions to indicate which MIPS ISA level
|
| 677 |
|
|
they were introduced in. INSN_ISA_MASK masks an enumeration that
|
| 678 |
|
|
specifies the base ISA level(s). The remainder of a 32-bit
|
| 679 |
|
|
word constructed using these macros is a bitmask of the remaining
|
| 680 |
|
|
INSN_* values below. */
|
| 681 |
|
|
|
| 682 |
|
|
#define INSN_ISA_MASK 0x0000000ful
|
| 683 |
|
|
|
| 684 |
|
|
/* We cannot start at zero due to ISA_UNKNOWN below. */
|
| 685 |
|
|
#define INSN_ISA1 1
|
| 686 |
|
|
#define INSN_ISA2 2
|
| 687 |
|
|
#define INSN_ISA3 3
|
| 688 |
|
|
#define INSN_ISA4 4
|
| 689 |
|
|
#define INSN_ISA5 5
|
| 690 |
|
|
#define INSN_ISA32 6
|
| 691 |
|
|
#define INSN_ISA32R2 7
|
| 692 |
|
|
#define INSN_ISA64 8
|
| 693 |
|
|
#define INSN_ISA64R2 9
|
| 694 |
|
|
/* Below this point the INSN_* values correspond to combinations of ISAs.
|
| 695 |
|
|
They are only for use in the opcodes table to indicate membership of
|
| 696 |
|
|
a combination of ISAs that cannot be expressed using the usual inclusion
|
| 697 |
|
|
ordering on the above INSN_* values. */
|
| 698 |
|
|
#define INSN_ISA3_32 10
|
| 699 |
|
|
#define INSN_ISA3_32R2 11
|
| 700 |
|
|
#define INSN_ISA4_32 12
|
| 701 |
|
|
#define INSN_ISA4_32R2 13
|
| 702 |
|
|
#define INSN_ISA5_32R2 14
|
| 703 |
|
|
|
| 704 |
|
|
/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
|
| 705 |
|
|
INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
|
| 706 |
|
|
this table describes whether at least one of the ISAs described by X
|
| 707 |
|
|
is/are implemented by ISA Y. (Think of Y as the ISA level supported by
|
| 708 |
|
|
a particular core and X as the ISA level(s) at which a certain instruction
|
| 709 |
|
|
is defined.) The ISA(s) described by X is/are implemented by Y iff
|
| 710 |
|
|
(mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
|
| 711 |
|
|
is non-zero. */
|
| 712 |
|
|
static const unsigned int mips_isa_table[] =
|
| 713 |
|
|
{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
|
| 714 |
|
|
|
| 715 |
|
|
/* Masks used for Chip specific instructions. */
|
| 716 |
166 |
khays |
#define INSN_CHIP_MASK 0xc3ff0f20
|
| 717 |
17 |
khays |
|
| 718 |
|
|
/* Cavium Networks Octeon instructions. */
|
| 719 |
|
|
#define INSN_OCTEON 0x00000800
|
| 720 |
166 |
khays |
#define INSN_OCTEONP 0x00000200
|
| 721 |
|
|
#define INSN_OCTEON2 0x00000100
|
| 722 |
17 |
khays |
|
| 723 |
|
|
/* Masks used for MIPS-defined ASEs. */
|
| 724 |
161 |
khays |
#define INSN_ASE_MASK 0x3c00f010
|
| 725 |
17 |
khays |
|
| 726 |
|
|
/* DSP ASE */
|
| 727 |
|
|
#define INSN_DSP 0x00001000
|
| 728 |
|
|
#define INSN_DSP64 0x00002000
|
| 729 |
|
|
|
| 730 |
|
|
/* 0x00004000 is unused. */
|
| 731 |
|
|
|
| 732 |
|
|
/* MIPS-3D ASE */
|
| 733 |
|
|
#define INSN_MIPS3D 0x00008000
|
| 734 |
|
|
|
| 735 |
|
|
/* MIPS R4650 instruction. */
|
| 736 |
|
|
#define INSN_4650 0x00010000
|
| 737 |
|
|
/* LSI R4010 instruction. */
|
| 738 |
|
|
#define INSN_4010 0x00020000
|
| 739 |
|
|
/* NEC VR4100 instruction. */
|
| 740 |
|
|
#define INSN_4100 0x00040000
|
| 741 |
|
|
/* Toshiba R3900 instruction. */
|
| 742 |
|
|
#define INSN_3900 0x00080000
|
| 743 |
|
|
/* MIPS R10000 instruction. */
|
| 744 |
|
|
#define INSN_10000 0x00100000
|
| 745 |
|
|
/* Broadcom SB-1 instruction. */
|
| 746 |
|
|
#define INSN_SB1 0x00200000
|
| 747 |
|
|
/* NEC VR4111/VR4181 instruction. */
|
| 748 |
|
|
#define INSN_4111 0x00400000
|
| 749 |
|
|
/* NEC VR4120 instruction. */
|
| 750 |
|
|
#define INSN_4120 0x00800000
|
| 751 |
|
|
/* NEC VR5400 instruction. */
|
| 752 |
|
|
#define INSN_5400 0x01000000
|
| 753 |
|
|
/* NEC VR5500 instruction. */
|
| 754 |
|
|
#define INSN_5500 0x02000000
|
| 755 |
|
|
|
| 756 |
|
|
/* MDMX ASE */
|
| 757 |
|
|
#define INSN_MDMX 0x04000000
|
| 758 |
|
|
/* MT ASE */
|
| 759 |
|
|
#define INSN_MT 0x08000000
|
| 760 |
|
|
/* SmartMIPS ASE */
|
| 761 |
|
|
#define INSN_SMARTMIPS 0x10000000
|
| 762 |
|
|
/* DSP R2 ASE */
|
| 763 |
|
|
#define INSN_DSPR2 0x20000000
|
| 764 |
|
|
/* ST Microelectronics Loongson 2E. */
|
| 765 |
|
|
#define INSN_LOONGSON_2E 0x40000000
|
| 766 |
|
|
/* ST Microelectronics Loongson 2F. */
|
| 767 |
|
|
#define INSN_LOONGSON_2F 0x80000000
|
| 768 |
|
|
/* Loongson 3A. */
|
| 769 |
|
|
#define INSN_LOONGSON_3A 0x00000400
|
| 770 |
|
|
/* RMI Xlr instruction */
|
| 771 |
|
|
#define INSN_XLR 0x00000020
|
| 772 |
|
|
|
| 773 |
161 |
khays |
/* MCU (MicroController) ASE */
|
| 774 |
|
|
#define INSN_MCU 0x00000010
|
| 775 |
|
|
|
| 776 |
17 |
khays |
/* MIPS ISA defines, use instead of hardcoding ISA level. */
|
| 777 |
|
|
|
| 778 |
|
|
#define ISA_UNKNOWN 0 /* Gas internal use. */
|
| 779 |
|
|
#define ISA_MIPS1 INSN_ISA1
|
| 780 |
|
|
#define ISA_MIPS2 INSN_ISA2
|
| 781 |
|
|
#define ISA_MIPS3 INSN_ISA3
|
| 782 |
|
|
#define ISA_MIPS4 INSN_ISA4
|
| 783 |
|
|
#define ISA_MIPS5 INSN_ISA5
|
| 784 |
|
|
|
| 785 |
|
|
#define ISA_MIPS32 INSN_ISA32
|
| 786 |
|
|
#define ISA_MIPS64 INSN_ISA64
|
| 787 |
|
|
|
| 788 |
|
|
#define ISA_MIPS32R2 INSN_ISA32R2
|
| 789 |
|
|
#define ISA_MIPS64R2 INSN_ISA64R2
|
| 790 |
|
|
|
| 791 |
|
|
|
| 792 |
|
|
/* CPU defines, use instead of hardcoding processor number. Keep this
|
| 793 |
|
|
in sync with bfd/archures.c in order for machine selection to work. */
|
| 794 |
|
|
#define CPU_UNKNOWN 0 /* Gas internal use. */
|
| 795 |
|
|
#define CPU_R3000 3000
|
| 796 |
|
|
#define CPU_R3900 3900
|
| 797 |
|
|
#define CPU_R4000 4000
|
| 798 |
|
|
#define CPU_R4010 4010
|
| 799 |
|
|
#define CPU_VR4100 4100
|
| 800 |
|
|
#define CPU_R4111 4111
|
| 801 |
|
|
#define CPU_VR4120 4120
|
| 802 |
|
|
#define CPU_R4300 4300
|
| 803 |
|
|
#define CPU_R4400 4400
|
| 804 |
|
|
#define CPU_R4600 4600
|
| 805 |
|
|
#define CPU_R4650 4650
|
| 806 |
|
|
#define CPU_R5000 5000
|
| 807 |
|
|
#define CPU_VR5400 5400
|
| 808 |
|
|
#define CPU_VR5500 5500
|
| 809 |
|
|
#define CPU_R6000 6000
|
| 810 |
|
|
#define CPU_RM7000 7000
|
| 811 |
|
|
#define CPU_R8000 8000
|
| 812 |
|
|
#define CPU_RM9000 9000
|
| 813 |
|
|
#define CPU_R10000 10000
|
| 814 |
|
|
#define CPU_R12000 12000
|
| 815 |
|
|
#define CPU_R14000 14000
|
| 816 |
|
|
#define CPU_R16000 16000
|
| 817 |
|
|
#define CPU_MIPS16 16
|
| 818 |
|
|
#define CPU_MIPS32 32
|
| 819 |
|
|
#define CPU_MIPS32R2 33
|
| 820 |
|
|
#define CPU_MIPS5 5
|
| 821 |
|
|
#define CPU_MIPS64 64
|
| 822 |
|
|
#define CPU_MIPS64R2 65
|
| 823 |
|
|
#define CPU_SB1 12310201 /* octal 'SB', 01. */
|
| 824 |
|
|
#define CPU_LOONGSON_2E 3001
|
| 825 |
|
|
#define CPU_LOONGSON_2F 3002
|
| 826 |
|
|
#define CPU_LOONGSON_3A 3003
|
| 827 |
|
|
#define CPU_OCTEON 6501
|
| 828 |
166 |
khays |
#define CPU_OCTEONP 6601
|
| 829 |
|
|
#define CPU_OCTEON2 6502
|
| 830 |
17 |
khays |
#define CPU_XLR 887682 /* decimal 'XLR' */
|
| 831 |
|
|
|
| 832 |
|
|
/* Test for membership in an ISA including chip specific ISAs. INSN
|
| 833 |
|
|
is pointer to an element of the opcode table; ISA is the specified
|
| 834 |
|
|
ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
|
| 835 |
|
|
test, or zero if no CPU specific ISA test is desired. */
|
| 836 |
|
|
|
| 837 |
|
|
#define OPCODE_IS_MEMBER(insn, isa, cpu) \
|
| 838 |
|
|
(((isa & INSN_ISA_MASK) != 0 \
|
| 839 |
|
|
&& ((insn)->membership & INSN_ISA_MASK) != 0 \
|
| 840 |
|
|
&& ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \
|
| 841 |
|
|
(((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \
|
| 842 |
|
|
|| ((isa & ~INSN_ISA_MASK) \
|
| 843 |
|
|
& ((insn)->membership & ~INSN_ISA_MASK)) != 0 \
|
| 844 |
|
|
|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
|
| 845 |
|
|
|| (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
|
| 846 |
|
|
|| (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
|
| 847 |
|
|
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|
| 848 |
|
|
|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
|
| 849 |
|
|
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
|
| 850 |
|
|
|| ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \
|
| 851 |
|
|
|| cpu == CPU_R16000) \
|
| 852 |
|
|
&& ((insn)->membership & INSN_10000) != 0) \
|
| 853 |
|
|
|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
|
| 854 |
|
|
|| (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
|
| 855 |
|
|
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
|
| 856 |
|
|
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
|
| 857 |
|
|
|| (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
|
| 858 |
|
|
|| (cpu == CPU_LOONGSON_2E \
|
| 859 |
|
|
&& ((insn)->membership & INSN_LOONGSON_2E) != 0) \
|
| 860 |
|
|
|| (cpu == CPU_LOONGSON_2F \
|
| 861 |
|
|
&& ((insn)->membership & INSN_LOONGSON_2F) != 0) \
|
| 862 |
|
|
|| (cpu == CPU_LOONGSON_3A \
|
| 863 |
|
|
&& ((insn)->membership & INSN_LOONGSON_3A) != 0) \
|
| 864 |
|
|
|| (cpu == CPU_OCTEON \
|
| 865 |
|
|
&& ((insn)->membership & INSN_OCTEON) != 0) \
|
| 866 |
166 |
khays |
|| (cpu == CPU_OCTEONP \
|
| 867 |
|
|
&& ((insn)->membership & INSN_OCTEONP) != 0) \
|
| 868 |
|
|
|| (cpu == CPU_OCTEON2 \
|
| 869 |
|
|
&& ((insn)->membership & INSN_OCTEON2) != 0) \
|
| 870 |
17 |
khays |
|| (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
|
| 871 |
|
|
|| 0) /* Please keep this term for easier source merging. */
|
| 872 |
|
|
|
| 873 |
|
|
/* This is a list of macro expanded instructions.
|
| 874 |
|
|
|
| 875 |
|
|
_I appended means immediate
|
| 876 |
|
|
_A appended means address
|
| 877 |
|
|
_AB appended means address with base register
|
| 878 |
|
|
_D appended means 64 bit floating point constant
|
| 879 |
|
|
_S appended means 32 bit floating point constant. */
|
| 880 |
|
|
|
| 881 |
|
|
enum
|
| 882 |
|
|
{
|
| 883 |
|
|
M_ABS,
|
| 884 |
161 |
khays |
M_ACLR_AB,
|
| 885 |
|
|
M_ACLR_OB,
|
| 886 |
17 |
khays |
M_ADD_I,
|
| 887 |
|
|
M_ADDU_I,
|
| 888 |
|
|
M_AND_I,
|
| 889 |
161 |
khays |
M_ASET_AB,
|
| 890 |
|
|
M_ASET_OB,
|
| 891 |
17 |
khays |
M_BALIGN,
|
| 892 |
161 |
khays |
M_BC1FL,
|
| 893 |
|
|
M_BC1TL,
|
| 894 |
|
|
M_BC2FL,
|
| 895 |
|
|
M_BC2TL,
|
| 896 |
17 |
khays |
M_BEQ,
|
| 897 |
|
|
M_BEQ_I,
|
| 898 |
161 |
khays |
M_BEQL,
|
| 899 |
17 |
khays |
M_BEQL_I,
|
| 900 |
|
|
M_BGE,
|
| 901 |
|
|
M_BGEL,
|
| 902 |
|
|
M_BGE_I,
|
| 903 |
|
|
M_BGEL_I,
|
| 904 |
|
|
M_BGEU,
|
| 905 |
|
|
M_BGEUL,
|
| 906 |
|
|
M_BGEU_I,
|
| 907 |
|
|
M_BGEUL_I,
|
| 908 |
161 |
khays |
M_BGEZ,
|
| 909 |
|
|
M_BGEZL,
|
| 910 |
|
|
M_BGEZALL,
|
| 911 |
17 |
khays |
M_BGT,
|
| 912 |
|
|
M_BGTL,
|
| 913 |
|
|
M_BGT_I,
|
| 914 |
|
|
M_BGTL_I,
|
| 915 |
|
|
M_BGTU,
|
| 916 |
|
|
M_BGTUL,
|
| 917 |
|
|
M_BGTU_I,
|
| 918 |
|
|
M_BGTUL_I,
|
| 919 |
161 |
khays |
M_BGTZ,
|
| 920 |
|
|
M_BGTZL,
|
| 921 |
17 |
khays |
M_BLE,
|
| 922 |
|
|
M_BLEL,
|
| 923 |
|
|
M_BLE_I,
|
| 924 |
|
|
M_BLEL_I,
|
| 925 |
|
|
M_BLEU,
|
| 926 |
|
|
M_BLEUL,
|
| 927 |
|
|
M_BLEU_I,
|
| 928 |
|
|
M_BLEUL_I,
|
| 929 |
161 |
khays |
M_BLEZ,
|
| 930 |
|
|
M_BLEZL,
|
| 931 |
17 |
khays |
M_BLT,
|
| 932 |
|
|
M_BLTL,
|
| 933 |
|
|
M_BLT_I,
|
| 934 |
|
|
M_BLTL_I,
|
| 935 |
|
|
M_BLTU,
|
| 936 |
|
|
M_BLTUL,
|
| 937 |
|
|
M_BLTU_I,
|
| 938 |
|
|
M_BLTUL_I,
|
| 939 |
161 |
khays |
M_BLTZ,
|
| 940 |
|
|
M_BLTZL,
|
| 941 |
|
|
M_BLTZALL,
|
| 942 |
17 |
khays |
M_BNE,
|
| 943 |
161 |
khays |
M_BNEL,
|
| 944 |
17 |
khays |
M_BNE_I,
|
| 945 |
|
|
M_BNEL_I,
|
| 946 |
|
|
M_CACHE_AB,
|
| 947 |
161 |
khays |
M_CACHE_OB,
|
| 948 |
17 |
khays |
M_DABS,
|
| 949 |
|
|
M_DADD_I,
|
| 950 |
|
|
M_DADDU_I,
|
| 951 |
|
|
M_DDIV_3,
|
| 952 |
|
|
M_DDIV_3I,
|
| 953 |
|
|
M_DDIVU_3,
|
| 954 |
|
|
M_DDIVU_3I,
|
| 955 |
|
|
M_DEXT,
|
| 956 |
|
|
M_DINS,
|
| 957 |
|
|
M_DIV_3,
|
| 958 |
|
|
M_DIV_3I,
|
| 959 |
|
|
M_DIVU_3,
|
| 960 |
|
|
M_DIVU_3I,
|
| 961 |
|
|
M_DLA_AB,
|
| 962 |
|
|
M_DLCA_AB,
|
| 963 |
|
|
M_DLI,
|
| 964 |
|
|
M_DMUL,
|
| 965 |
|
|
M_DMUL_I,
|
| 966 |
|
|
M_DMULO,
|
| 967 |
|
|
M_DMULO_I,
|
| 968 |
|
|
M_DMULOU,
|
| 969 |
|
|
M_DMULOU_I,
|
| 970 |
|
|
M_DREM_3,
|
| 971 |
|
|
M_DREM_3I,
|
| 972 |
|
|
M_DREMU_3,
|
| 973 |
|
|
M_DREMU_3I,
|
| 974 |
|
|
M_DSUB_I,
|
| 975 |
|
|
M_DSUBU_I,
|
| 976 |
|
|
M_DSUBU_I_2,
|
| 977 |
|
|
M_J_A,
|
| 978 |
|
|
M_JAL_1,
|
| 979 |
|
|
M_JAL_2,
|
| 980 |
|
|
M_JAL_A,
|
| 981 |
161 |
khays |
M_JALS_1,
|
| 982 |
|
|
M_JALS_2,
|
| 983 |
|
|
M_JALS_A,
|
| 984 |
17 |
khays |
M_L_DOB,
|
| 985 |
|
|
M_L_DAB,
|
| 986 |
|
|
M_LA_AB,
|
| 987 |
|
|
M_LB_A,
|
| 988 |
|
|
M_LB_AB,
|
| 989 |
|
|
M_LBU_A,
|
| 990 |
|
|
M_LBU_AB,
|
| 991 |
|
|
M_LCA_AB,
|
| 992 |
|
|
M_LD_A,
|
| 993 |
|
|
M_LD_OB,
|
| 994 |
|
|
M_LD_AB,
|
| 995 |
|
|
M_LDC1_AB,
|
| 996 |
|
|
M_LDC2_AB,
|
| 997 |
161 |
khays |
M_LDC2_OB,
|
| 998 |
17 |
khays |
M_LDC3_AB,
|
| 999 |
|
|
M_LDL_AB,
|
| 1000 |
161 |
khays |
M_LDL_OB,
|
| 1001 |
|
|
M_LDM_AB,
|
| 1002 |
|
|
M_LDM_OB,
|
| 1003 |
|
|
M_LDP_AB,
|
| 1004 |
|
|
M_LDP_OB,
|
| 1005 |
17 |
khays |
M_LDR_AB,
|
| 1006 |
161 |
khays |
M_LDR_OB,
|
| 1007 |
17 |
khays |
M_LH_A,
|
| 1008 |
|
|
M_LH_AB,
|
| 1009 |
|
|
M_LHU_A,
|
| 1010 |
|
|
M_LHU_AB,
|
| 1011 |
|
|
M_LI,
|
| 1012 |
|
|
M_LI_D,
|
| 1013 |
|
|
M_LI_DD,
|
| 1014 |
|
|
M_LI_S,
|
| 1015 |
|
|
M_LI_SS,
|
| 1016 |
|
|
M_LL_AB,
|
| 1017 |
161 |
khays |
M_LL_OB,
|
| 1018 |
17 |
khays |
M_LLD_AB,
|
| 1019 |
161 |
khays |
M_LLD_OB,
|
| 1020 |
17 |
khays |
M_LS_A,
|
| 1021 |
|
|
M_LW_A,
|
| 1022 |
|
|
M_LW_AB,
|
| 1023 |
|
|
M_LWC0_A,
|
| 1024 |
|
|
M_LWC0_AB,
|
| 1025 |
|
|
M_LWC1_A,
|
| 1026 |
|
|
M_LWC1_AB,
|
| 1027 |
|
|
M_LWC2_A,
|
| 1028 |
|
|
M_LWC2_AB,
|
| 1029 |
161 |
khays |
M_LWC2_OB,
|
| 1030 |
17 |
khays |
M_LWC3_A,
|
| 1031 |
|
|
M_LWC3_AB,
|
| 1032 |
|
|
M_LWL_A,
|
| 1033 |
|
|
M_LWL_AB,
|
| 1034 |
161 |
khays |
M_LWL_OB,
|
| 1035 |
|
|
M_LWM_AB,
|
| 1036 |
|
|
M_LWM_OB,
|
| 1037 |
|
|
M_LWP_AB,
|
| 1038 |
|
|
M_LWP_OB,
|
| 1039 |
17 |
khays |
M_LWR_A,
|
| 1040 |
|
|
M_LWR_AB,
|
| 1041 |
161 |
khays |
M_LWR_OB,
|
| 1042 |
17 |
khays |
M_LWU_AB,
|
| 1043 |
161 |
khays |
M_LWU_OB,
|
| 1044 |
17 |
khays |
M_MSGSND,
|
| 1045 |
|
|
M_MSGLD,
|
| 1046 |
|
|
M_MSGLD_T,
|
| 1047 |
|
|
M_MSGWAIT,
|
| 1048 |
|
|
M_MSGWAIT_T,
|
| 1049 |
|
|
M_MOVE,
|
| 1050 |
|
|
M_MUL,
|
| 1051 |
|
|
M_MUL_I,
|
| 1052 |
|
|
M_MULO,
|
| 1053 |
|
|
M_MULO_I,
|
| 1054 |
|
|
M_MULOU,
|
| 1055 |
|
|
M_MULOU_I,
|
| 1056 |
|
|
M_NOR_I,
|
| 1057 |
|
|
M_OR_I,
|
| 1058 |
|
|
M_PREF_AB,
|
| 1059 |
161 |
khays |
M_PREF_OB,
|
| 1060 |
17 |
khays |
M_REM_3,
|
| 1061 |
|
|
M_REM_3I,
|
| 1062 |
|
|
M_REMU_3,
|
| 1063 |
|
|
M_REMU_3I,
|
| 1064 |
|
|
M_DROL,
|
| 1065 |
|
|
M_ROL,
|
| 1066 |
|
|
M_DROL_I,
|
| 1067 |
|
|
M_ROL_I,
|
| 1068 |
|
|
M_DROR,
|
| 1069 |
|
|
M_ROR,
|
| 1070 |
|
|
M_DROR_I,
|
| 1071 |
|
|
M_ROR_I,
|
| 1072 |
|
|
M_S_DA,
|
| 1073 |
|
|
M_S_DOB,
|
| 1074 |
|
|
M_S_DAB,
|
| 1075 |
|
|
M_S_S,
|
| 1076 |
166 |
khays |
M_SAA_AB,
|
| 1077 |
|
|
M_SAA_OB,
|
| 1078 |
|
|
M_SAAD_AB,
|
| 1079 |
|
|
M_SAAD_OB,
|
| 1080 |
17 |
khays |
M_SC_AB,
|
| 1081 |
161 |
khays |
M_SC_OB,
|
| 1082 |
17 |
khays |
M_SCD_AB,
|
| 1083 |
161 |
khays |
M_SCD_OB,
|
| 1084 |
17 |
khays |
M_SD_A,
|
| 1085 |
|
|
M_SD_OB,
|
| 1086 |
|
|
M_SD_AB,
|
| 1087 |
|
|
M_SDC1_AB,
|
| 1088 |
|
|
M_SDC2_AB,
|
| 1089 |
161 |
khays |
M_SDC2_OB,
|
| 1090 |
17 |
khays |
M_SDC3_AB,
|
| 1091 |
|
|
M_SDL_AB,
|
| 1092 |
161 |
khays |
M_SDL_OB,
|
| 1093 |
|
|
M_SDM_AB,
|
| 1094 |
|
|
M_SDM_OB,
|
| 1095 |
|
|
M_SDP_AB,
|
| 1096 |
|
|
M_SDP_OB,
|
| 1097 |
17 |
khays |
M_SDR_AB,
|
| 1098 |
161 |
khays |
M_SDR_OB,
|
| 1099 |
17 |
khays |
M_SEQ,
|
| 1100 |
|
|
M_SEQ_I,
|
| 1101 |
|
|
M_SGE,
|
| 1102 |
|
|
M_SGE_I,
|
| 1103 |
|
|
M_SGEU,
|
| 1104 |
|
|
M_SGEU_I,
|
| 1105 |
|
|
M_SGT,
|
| 1106 |
|
|
M_SGT_I,
|
| 1107 |
|
|
M_SGTU,
|
| 1108 |
|
|
M_SGTU_I,
|
| 1109 |
|
|
M_SLE,
|
| 1110 |
|
|
M_SLE_I,
|
| 1111 |
|
|
M_SLEU,
|
| 1112 |
|
|
M_SLEU_I,
|
| 1113 |
|
|
M_SLT_I,
|
| 1114 |
|
|
M_SLTU_I,
|
| 1115 |
|
|
M_SNE,
|
| 1116 |
|
|
M_SNE_I,
|
| 1117 |
|
|
M_SB_A,
|
| 1118 |
|
|
M_SB_AB,
|
| 1119 |
|
|
M_SH_A,
|
| 1120 |
|
|
M_SH_AB,
|
| 1121 |
|
|
M_SW_A,
|
| 1122 |
|
|
M_SW_AB,
|
| 1123 |
|
|
M_SWC0_A,
|
| 1124 |
|
|
M_SWC0_AB,
|
| 1125 |
|
|
M_SWC1_A,
|
| 1126 |
|
|
M_SWC1_AB,
|
| 1127 |
|
|
M_SWC2_A,
|
| 1128 |
|
|
M_SWC2_AB,
|
| 1129 |
161 |
khays |
M_SWC2_OB,
|
| 1130 |
17 |
khays |
M_SWC3_A,
|
| 1131 |
|
|
M_SWC3_AB,
|
| 1132 |
|
|
M_SWL_A,
|
| 1133 |
|
|
M_SWL_AB,
|
| 1134 |
161 |
khays |
M_SWL_OB,
|
| 1135 |
|
|
M_SWM_AB,
|
| 1136 |
|
|
M_SWM_OB,
|
| 1137 |
|
|
M_SWP_AB,
|
| 1138 |
|
|
M_SWP_OB,
|
| 1139 |
17 |
khays |
M_SWR_A,
|
| 1140 |
|
|
M_SWR_AB,
|
| 1141 |
161 |
khays |
M_SWR_OB,
|
| 1142 |
17 |
khays |
M_SUB_I,
|
| 1143 |
|
|
M_SUBU_I,
|
| 1144 |
|
|
M_SUBU_I_2,
|
| 1145 |
|
|
M_TEQ_I,
|
| 1146 |
|
|
M_TGE_I,
|
| 1147 |
|
|
M_TGEU_I,
|
| 1148 |
|
|
M_TLT_I,
|
| 1149 |
|
|
M_TLTU_I,
|
| 1150 |
|
|
M_TNE_I,
|
| 1151 |
|
|
M_TRUNCWD,
|
| 1152 |
|
|
M_TRUNCWS,
|
| 1153 |
|
|
M_ULD,
|
| 1154 |
|
|
M_ULD_A,
|
| 1155 |
|
|
M_ULH,
|
| 1156 |
|
|
M_ULH_A,
|
| 1157 |
|
|
M_ULHU,
|
| 1158 |
|
|
M_ULHU_A,
|
| 1159 |
|
|
M_ULW,
|
| 1160 |
|
|
M_ULW_A,
|
| 1161 |
|
|
M_USH,
|
| 1162 |
|
|
M_USH_A,
|
| 1163 |
|
|
M_USW,
|
| 1164 |
|
|
M_USW_A,
|
| 1165 |
|
|
M_USD,
|
| 1166 |
|
|
M_USD_A,
|
| 1167 |
|
|
M_XOR_I,
|
| 1168 |
|
|
M_COP0,
|
| 1169 |
|
|
M_COP1,
|
| 1170 |
|
|
M_COP2,
|
| 1171 |
|
|
M_COP3,
|
| 1172 |
|
|
M_NUM_MACROS
|
| 1173 |
|
|
};
|
| 1174 |
|
|
|
| 1175 |
|
|
|
| 1176 |
|
|
/* The order of overloaded instructions matters. Label arguments and
|
| 1177 |
|
|
register arguments look the same. Instructions that can have either
|
| 1178 |
|
|
for arguments must apear in the correct order in this table for the
|
| 1179 |
|
|
assembler to pick the right one. In other words, entries with
|
| 1180 |
|
|
immediate operands must apear after the same instruction with
|
| 1181 |
|
|
registers.
|
| 1182 |
|
|
|
| 1183 |
|
|
Many instructions are short hand for other instructions (i.e., The
|
| 1184 |
|
|
jal <register> instruction is short for jalr <register>). */
|
| 1185 |
|
|
|
| 1186 |
|
|
extern const struct mips_opcode mips_builtin_opcodes[];
|
| 1187 |
|
|
extern const int bfd_mips_num_builtin_opcodes;
|
| 1188 |
|
|
extern struct mips_opcode *mips_opcodes;
|
| 1189 |
|
|
extern int bfd_mips_num_opcodes;
|
| 1190 |
|
|
#define NUMOPCODES bfd_mips_num_opcodes
|
| 1191 |
|
|
|
| 1192 |
|
|
|
| 1193 |
|
|
/* The rest of this file adds definitions for the mips16 TinyRISC
|
| 1194 |
|
|
processor. */
|
| 1195 |
|
|
|
| 1196 |
|
|
/* These are the bitmasks and shift counts used for the different
|
| 1197 |
|
|
fields in the instruction formats. Other than OP, no masks are
|
| 1198 |
|
|
provided for the fixed portions of an instruction, since they are
|
| 1199 |
|
|
not needed.
|
| 1200 |
|
|
|
| 1201 |
|
|
The I format uses IMM11.
|
| 1202 |
|
|
|
| 1203 |
|
|
The RI format uses RX and IMM8.
|
| 1204 |
|
|
|
| 1205 |
|
|
The RR format uses RX, and RY.
|
| 1206 |
|
|
|
| 1207 |
|
|
The RRI format uses RX, RY, and IMM5.
|
| 1208 |
|
|
|
| 1209 |
|
|
The RRR format uses RX, RY, and RZ.
|
| 1210 |
|
|
|
| 1211 |
|
|
The RRI_A format uses RX, RY, and IMM4.
|
| 1212 |
|
|
|
| 1213 |
|
|
The SHIFT format uses RX, RY, and SHAMT.
|
| 1214 |
|
|
|
| 1215 |
|
|
The I8 format uses IMM8.
|
| 1216 |
|
|
|
| 1217 |
|
|
The I8_MOVR32 format uses RY and REGR32.
|
| 1218 |
|
|
|
| 1219 |
|
|
The IR_MOV32R format uses REG32R and MOV32Z.
|
| 1220 |
|
|
|
| 1221 |
|
|
The I64 format uses IMM8.
|
| 1222 |
|
|
|
| 1223 |
|
|
The RI64 format uses RY and IMM5.
|
| 1224 |
|
|
*/
|
| 1225 |
|
|
|
| 1226 |
|
|
#define MIPS16OP_MASK_OP 0x1f
|
| 1227 |
|
|
#define MIPS16OP_SH_OP 11
|
| 1228 |
|
|
#define MIPS16OP_MASK_IMM11 0x7ff
|
| 1229 |
|
|
#define MIPS16OP_SH_IMM11 0
|
| 1230 |
|
|
#define MIPS16OP_MASK_RX 0x7
|
| 1231 |
|
|
#define MIPS16OP_SH_RX 8
|
| 1232 |
|
|
#define MIPS16OP_MASK_IMM8 0xff
|
| 1233 |
|
|
#define MIPS16OP_SH_IMM8 0
|
| 1234 |
|
|
#define MIPS16OP_MASK_RY 0x7
|
| 1235 |
|
|
#define MIPS16OP_SH_RY 5
|
| 1236 |
|
|
#define MIPS16OP_MASK_IMM5 0x1f
|
| 1237 |
|
|
#define MIPS16OP_SH_IMM5 0
|
| 1238 |
|
|
#define MIPS16OP_MASK_RZ 0x7
|
| 1239 |
|
|
#define MIPS16OP_SH_RZ 2
|
| 1240 |
|
|
#define MIPS16OP_MASK_IMM4 0xf
|
| 1241 |
|
|
#define MIPS16OP_SH_IMM4 0
|
| 1242 |
|
|
#define MIPS16OP_MASK_REGR32 0x1f
|
| 1243 |
|
|
#define MIPS16OP_SH_REGR32 0
|
| 1244 |
|
|
#define MIPS16OP_MASK_REG32R 0x1f
|
| 1245 |
|
|
#define MIPS16OP_SH_REG32R 3
|
| 1246 |
|
|
#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
|
| 1247 |
|
|
#define MIPS16OP_MASK_MOVE32Z 0x7
|
| 1248 |
|
|
#define MIPS16OP_SH_MOVE32Z 0
|
| 1249 |
|
|
#define MIPS16OP_MASK_IMM6 0x3f
|
| 1250 |
|
|
#define MIPS16OP_SH_IMM6 5
|
| 1251 |
|
|
|
| 1252 |
|
|
/* These are the characters which may appears in the args field of a MIPS16
|
| 1253 |
|
|
instruction. They appear in the order in which the fields appear when the
|
| 1254 |
|
|
instruction is used. Commas and parentheses in the args string are ignored
|
| 1255 |
|
|
when assembling, and written into the output when disassembling.
|
| 1256 |
|
|
|
| 1257 |
|
|
"y" 3 bit register (MIPS16OP_*_RY)
|
| 1258 |
|
|
"x" 3 bit register (MIPS16OP_*_RX)
|
| 1259 |
|
|
"z" 3 bit register (MIPS16OP_*_RZ)
|
| 1260 |
|
|
"Z" 3 bit register (MIPS16OP_*_MOVE32Z)
|
| 1261 |
|
|
"v" 3 bit same register as source and destination (MIPS16OP_*_RX)
|
| 1262 |
|
|
"w" 3 bit same register as source and destination (MIPS16OP_*_RY)
|
| 1263 |
|
|
"0" zero register ($0)
|
| 1264 |
|
|
"S" stack pointer ($sp or $29)
|
| 1265 |
|
|
"P" program counter
|
| 1266 |
|
|
"R" return address register ($ra or $31)
|
| 1267 |
|
|
"X" 5 bit MIPS register (MIPS16OP_*_REGR32)
|
| 1268 |
|
|
"Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
|
| 1269 |
|
|
"6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
|
| 1270 |
|
|
"a" 26 bit jump address
|
| 1271 |
|
|
"e" 11 bit extension value
|
| 1272 |
|
|
"l" register list for entry instruction
|
| 1273 |
|
|
"L" register list for exit instruction
|
| 1274 |
|
|
|
| 1275 |
|
|
The remaining codes may be extended. Except as otherwise noted,
|
| 1276 |
|
|
the full extended operand is a 16 bit signed value.
|
| 1277 |
|
|
"<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
|
| 1278 |
|
|
">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
|
| 1279 |
|
|
"[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
|
| 1280 |
|
|
"]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
|
| 1281 |
|
|
"4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
|
| 1282 |
|
|
"5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
|
| 1283 |
|
|
"H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
|
| 1284 |
|
|
"W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
|
| 1285 |
|
|
"D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
|
| 1286 |
|
|
"j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
|
| 1287 |
|
|
"8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
|
| 1288 |
|
|
"V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
|
| 1289 |
|
|
"C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
|
| 1290 |
|
|
"U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
|
| 1291 |
|
|
"k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
|
| 1292 |
|
|
"K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
|
| 1293 |
|
|
"p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
|
| 1294 |
|
|
"q" 11 bit branch address (MIPS16OP_*_IMM11)
|
| 1295 |
|
|
"A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
|
| 1296 |
|
|
"B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
|
| 1297 |
|
|
"E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
|
| 1298 |
|
|
"m" 7 bit register list for save instruction (18 bit extended)
|
| 1299 |
|
|
"M" 7 bit register list for restore instruction (18 bit extended)
|
| 1300 |
|
|
*/
|
| 1301 |
|
|
|
| 1302 |
|
|
/* Save/restore encoding for the args field when all 4 registers are
|
| 1303 |
|
|
either saved as arguments or saved/restored as statics. */
|
| 1304 |
|
|
#define MIPS16_ALL_ARGS 0xe
|
| 1305 |
|
|
#define MIPS16_ALL_STATICS 0xb
|
| 1306 |
|
|
|
| 1307 |
|
|
/* For the mips16, we use the same opcode table format and a few of
|
| 1308 |
|
|
the same flags. However, most of the flags are different. */
|
| 1309 |
|
|
|
| 1310 |
|
|
/* Modifies the register in MIPS16OP_*_RX. */
|
| 1311 |
|
|
#define MIPS16_INSN_WRITE_X 0x00000001
|
| 1312 |
|
|
/* Modifies the register in MIPS16OP_*_RY. */
|
| 1313 |
|
|
#define MIPS16_INSN_WRITE_Y 0x00000002
|
| 1314 |
|
|
/* Modifies the register in MIPS16OP_*_RZ. */
|
| 1315 |
|
|
#define MIPS16_INSN_WRITE_Z 0x00000004
|
| 1316 |
|
|
/* Modifies the T ($24) register. */
|
| 1317 |
|
|
#define MIPS16_INSN_WRITE_T 0x00000008
|
| 1318 |
|
|
/* Modifies the SP ($29) register. */
|
| 1319 |
|
|
#define MIPS16_INSN_WRITE_SP 0x00000010
|
| 1320 |
|
|
/* Modifies the RA ($31) register. */
|
| 1321 |
|
|
#define MIPS16_INSN_WRITE_31 0x00000020
|
| 1322 |
|
|
/* Modifies the general purpose register in MIPS16OP_*_REG32R. */
|
| 1323 |
|
|
#define MIPS16_INSN_WRITE_GPR_Y 0x00000040
|
| 1324 |
|
|
/* Reads the register in MIPS16OP_*_RX. */
|
| 1325 |
|
|
#define MIPS16_INSN_READ_X 0x00000080
|
| 1326 |
|
|
/* Reads the register in MIPS16OP_*_RY. */
|
| 1327 |
|
|
#define MIPS16_INSN_READ_Y 0x00000100
|
| 1328 |
|
|
/* Reads the register in MIPS16OP_*_MOVE32Z. */
|
| 1329 |
|
|
#define MIPS16_INSN_READ_Z 0x00000200
|
| 1330 |
|
|
/* Reads the T ($24) register. */
|
| 1331 |
|
|
#define MIPS16_INSN_READ_T 0x00000400
|
| 1332 |
|
|
/* Reads the SP ($29) register. */
|
| 1333 |
|
|
#define MIPS16_INSN_READ_SP 0x00000800
|
| 1334 |
|
|
/* Reads the RA ($31) register. */
|
| 1335 |
|
|
#define MIPS16_INSN_READ_31 0x00001000
|
| 1336 |
|
|
/* Reads the program counter. */
|
| 1337 |
|
|
#define MIPS16_INSN_READ_PC 0x00002000
|
| 1338 |
|
|
/* Reads the general purpose register in MIPS16OP_*_REGR32. */
|
| 1339 |
|
|
#define MIPS16_INSN_READ_GPR_X 0x00004000
|
| 1340 |
|
|
/* Is an unconditional branch insn. */
|
| 1341 |
|
|
#define MIPS16_INSN_UNCOND_BRANCH 0x00008000
|
| 1342 |
|
|
/* Is a conditional branch insn. */
|
| 1343 |
|
|
#define MIPS16_INSN_COND_BRANCH 0x00010000
|
| 1344 |
|
|
|
| 1345 |
|
|
/* The following flags have the same value for the mips16 opcode
|
| 1346 |
|
|
table:
|
| 1347 |
161 |
khays |
|
| 1348 |
|
|
INSN_ISA3
|
| 1349 |
|
|
|
| 1350 |
17 |
khays |
INSN_UNCOND_BRANCH_DELAY
|
| 1351 |
|
|
INSN_COND_BRANCH_DELAY
|
| 1352 |
|
|
INSN_COND_BRANCH_LIKELY (never used)
|
| 1353 |
|
|
INSN_READ_HI
|
| 1354 |
|
|
INSN_READ_LO
|
| 1355 |
|
|
INSN_WRITE_HI
|
| 1356 |
|
|
INSN_WRITE_LO
|
| 1357 |
|
|
INSN_TRAP
|
| 1358 |
161 |
khays |
FP_D (never used)
|
| 1359 |
17 |
khays |
*/
|
| 1360 |
|
|
|
| 1361 |
|
|
extern const struct mips_opcode mips16_opcodes[];
|
| 1362 |
|
|
extern const int bfd_mips16_num_opcodes;
|
| 1363 |
|
|
|
| 1364 |
161 |
khays |
/* These are the bit masks and shift counts used for the different fields
|
| 1365 |
|
|
in the microMIPS instruction formats. No masks are provided for the
|
| 1366 |
|
|
fixed portions of an instruction, since they are not needed. */
|
| 1367 |
|
|
|
| 1368 |
|
|
#define MICROMIPSOP_MASK_IMMEDIATE 0xffff
|
| 1369 |
|
|
#define MICROMIPSOP_SH_IMMEDIATE 0
|
| 1370 |
|
|
#define MICROMIPSOP_MASK_DELTA 0xffff
|
| 1371 |
|
|
#define MICROMIPSOP_SH_DELTA 0
|
| 1372 |
|
|
#define MICROMIPSOP_MASK_CODE10 0x3ff
|
| 1373 |
|
|
#define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */
|
| 1374 |
|
|
#define MICROMIPSOP_MASK_TRAP 0xf
|
| 1375 |
|
|
#define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */
|
| 1376 |
|
|
#define MICROMIPSOP_MASK_SHAMT 0x1f
|
| 1377 |
|
|
#define MICROMIPSOP_SH_SHAMT 11
|
| 1378 |
|
|
#define MICROMIPSOP_MASK_TARGET 0x3ffffff
|
| 1379 |
|
|
#define MICROMIPSOP_SH_TARGET 0
|
| 1380 |
|
|
#define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */
|
| 1381 |
|
|
#define MICROMIPSOP_SH_EXTLSB 6
|
| 1382 |
|
|
#define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
|
| 1383 |
|
|
#define MICROMIPSOP_SH_EXTMSBD 11
|
| 1384 |
|
|
#define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */
|
| 1385 |
|
|
#define MICROMIPSOP_SH_INSMSB 11
|
| 1386 |
|
|
#define MICROMIPSOP_MASK_CODE 0x3ff
|
| 1387 |
|
|
#define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */
|
| 1388 |
|
|
#define MICROMIPSOP_MASK_CODE2 0x3ff
|
| 1389 |
|
|
#define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */
|
| 1390 |
|
|
#define MICROMIPSOP_MASK_CACHE 0x1f
|
| 1391 |
|
|
#define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */
|
| 1392 |
|
|
#define MICROMIPSOP_MASK_SEL 0x7
|
| 1393 |
|
|
#define MICROMIPSOP_SH_SEL 11
|
| 1394 |
|
|
#define MICROMIPSOP_MASK_OFFSET12 0xfff
|
| 1395 |
|
|
#define MICROMIPSOP_SH_OFFSET12 0
|
| 1396 |
|
|
#define MICROMIPSOP_MASK_3BITPOS 0x7
|
| 1397 |
|
|
#define MICROMIPSOP_SH_3BITPOS 21
|
| 1398 |
|
|
#define MICROMIPSOP_MASK_STYPE 0x1f
|
| 1399 |
|
|
#define MICROMIPSOP_SH_STYPE 16
|
| 1400 |
|
|
#define MICROMIPSOP_MASK_OFFSET10 0x3ff
|
| 1401 |
|
|
#define MICROMIPSOP_SH_OFFSET10 6
|
| 1402 |
|
|
#define MICROMIPSOP_MASK_RS 0x1f
|
| 1403 |
|
|
#define MICROMIPSOP_SH_RS 16
|
| 1404 |
|
|
#define MICROMIPSOP_MASK_RT 0x1f
|
| 1405 |
|
|
#define MICROMIPSOP_SH_RT 21
|
| 1406 |
|
|
#define MICROMIPSOP_MASK_RD 0x1f
|
| 1407 |
|
|
#define MICROMIPSOP_SH_RD 11
|
| 1408 |
|
|
#define MICROMIPSOP_MASK_FS 0x1f
|
| 1409 |
|
|
#define MICROMIPSOP_SH_FS 16
|
| 1410 |
|
|
#define MICROMIPSOP_MASK_FT 0x1f
|
| 1411 |
|
|
#define MICROMIPSOP_SH_FT 21
|
| 1412 |
|
|
#define MICROMIPSOP_MASK_FD 0x1f
|
| 1413 |
|
|
#define MICROMIPSOP_SH_FD 11
|
| 1414 |
|
|
#define MICROMIPSOP_MASK_FR 0x1f
|
| 1415 |
|
|
#define MICROMIPSOP_SH_FR 6
|
| 1416 |
|
|
#define MICROMIPSOP_MASK_RS3 0x1f
|
| 1417 |
|
|
#define MICROMIPSOP_SH_RS3 6
|
| 1418 |
|
|
#define MICROMIPSOP_MASK_PREFX 0x1f
|
| 1419 |
|
|
#define MICROMIPSOP_SH_PREFX 11
|
| 1420 |
|
|
#define MICROMIPSOP_MASK_BCC 0x7
|
| 1421 |
|
|
#define MICROMIPSOP_SH_BCC 18
|
| 1422 |
|
|
#define MICROMIPSOP_MASK_CCC 0x7
|
| 1423 |
|
|
#define MICROMIPSOP_SH_CCC 13
|
| 1424 |
|
|
#define MICROMIPSOP_MASK_COPZ 0x7fffff
|
| 1425 |
|
|
#define MICROMIPSOP_SH_COPZ 3
|
| 1426 |
|
|
|
| 1427 |
|
|
#define MICROMIPSOP_MASK_MB 0x7
|
| 1428 |
|
|
#define MICROMIPSOP_SH_MB 23
|
| 1429 |
|
|
#define MICROMIPSOP_MASK_MC 0x7
|
| 1430 |
|
|
#define MICROMIPSOP_SH_MC 4
|
| 1431 |
|
|
#define MICROMIPSOP_MASK_MD 0x7
|
| 1432 |
|
|
#define MICROMIPSOP_SH_MD 7
|
| 1433 |
|
|
#define MICROMIPSOP_MASK_ME 0x7
|
| 1434 |
|
|
#define MICROMIPSOP_SH_ME 1
|
| 1435 |
|
|
#define MICROMIPSOP_MASK_MF 0x7
|
| 1436 |
|
|
#define MICROMIPSOP_SH_MF 3
|
| 1437 |
|
|
#define MICROMIPSOP_MASK_MG 0x7
|
| 1438 |
|
|
#define MICROMIPSOP_SH_MG 0
|
| 1439 |
|
|
#define MICROMIPSOP_MASK_MH 0x7
|
| 1440 |
|
|
#define MICROMIPSOP_SH_MH 7
|
| 1441 |
|
|
#define MICROMIPSOP_MASK_MI 0x7
|
| 1442 |
|
|
#define MICROMIPSOP_SH_MI 7
|
| 1443 |
|
|
#define MICROMIPSOP_MASK_MJ 0x1f
|
| 1444 |
|
|
#define MICROMIPSOP_SH_MJ 0
|
| 1445 |
|
|
#define MICROMIPSOP_MASK_ML 0x7
|
| 1446 |
|
|
#define MICROMIPSOP_SH_ML 4
|
| 1447 |
|
|
#define MICROMIPSOP_MASK_MM 0x7
|
| 1448 |
|
|
#define MICROMIPSOP_SH_MM 1
|
| 1449 |
|
|
#define MICROMIPSOP_MASK_MN 0x7
|
| 1450 |
|
|
#define MICROMIPSOP_SH_MN 4
|
| 1451 |
|
|
#define MICROMIPSOP_MASK_MP 0x1f
|
| 1452 |
|
|
#define MICROMIPSOP_SH_MP 5
|
| 1453 |
|
|
#define MICROMIPSOP_MASK_MQ 0x7
|
| 1454 |
|
|
#define MICROMIPSOP_SH_MQ 7
|
| 1455 |
|
|
|
| 1456 |
|
|
#define MICROMIPSOP_MASK_IMMA 0x7f
|
| 1457 |
|
|
#define MICROMIPSOP_SH_IMMA 0
|
| 1458 |
|
|
#define MICROMIPSOP_MASK_IMMB 0x7
|
| 1459 |
|
|
#define MICROMIPSOP_SH_IMMB 1
|
| 1460 |
|
|
#define MICROMIPSOP_MASK_IMMC 0xf
|
| 1461 |
|
|
#define MICROMIPSOP_SH_IMMC 0
|
| 1462 |
|
|
#define MICROMIPSOP_MASK_IMMD 0x3ff
|
| 1463 |
|
|
#define MICROMIPSOP_SH_IMMD 0
|
| 1464 |
|
|
#define MICROMIPSOP_MASK_IMME 0x7f
|
| 1465 |
|
|
#define MICROMIPSOP_SH_IMME 0
|
| 1466 |
|
|
#define MICROMIPSOP_MASK_IMMF 0xf
|
| 1467 |
|
|
#define MICROMIPSOP_SH_IMMF 0
|
| 1468 |
|
|
#define MICROMIPSOP_MASK_IMMG 0xf
|
| 1469 |
|
|
#define MICROMIPSOP_SH_IMMG 0
|
| 1470 |
|
|
#define MICROMIPSOP_MASK_IMMH 0xf
|
| 1471 |
|
|
#define MICROMIPSOP_SH_IMMH 0
|
| 1472 |
|
|
#define MICROMIPSOP_MASK_IMMI 0x7f
|
| 1473 |
|
|
#define MICROMIPSOP_SH_IMMI 0
|
| 1474 |
|
|
#define MICROMIPSOP_MASK_IMMJ 0xf
|
| 1475 |
|
|
#define MICROMIPSOP_SH_IMMJ 0
|
| 1476 |
|
|
#define MICROMIPSOP_MASK_IMML 0xf
|
| 1477 |
|
|
#define MICROMIPSOP_SH_IMML 0
|
| 1478 |
|
|
#define MICROMIPSOP_MASK_IMMM 0x7
|
| 1479 |
|
|
#define MICROMIPSOP_SH_IMMM 1
|
| 1480 |
|
|
#define MICROMIPSOP_MASK_IMMN 0x3
|
| 1481 |
|
|
#define MICROMIPSOP_SH_IMMN 4
|
| 1482 |
|
|
#define MICROMIPSOP_MASK_IMMO 0xf
|
| 1483 |
|
|
#define MICROMIPSOP_SH_IMMO 0
|
| 1484 |
|
|
#define MICROMIPSOP_MASK_IMMP 0x1f
|
| 1485 |
|
|
#define MICROMIPSOP_SH_IMMP 0
|
| 1486 |
|
|
#define MICROMIPSOP_MASK_IMMQ 0x7fffff
|
| 1487 |
|
|
#define MICROMIPSOP_SH_IMMQ 0
|
| 1488 |
|
|
#define MICROMIPSOP_MASK_IMMU 0x1f
|
| 1489 |
|
|
#define MICROMIPSOP_SH_IMMU 0
|
| 1490 |
|
|
#define MICROMIPSOP_MASK_IMMW 0x3f
|
| 1491 |
|
|
#define MICROMIPSOP_SH_IMMW 1
|
| 1492 |
|
|
#define MICROMIPSOP_MASK_IMMX 0xf
|
| 1493 |
|
|
#define MICROMIPSOP_SH_IMMX 1
|
| 1494 |
|
|
#define MICROMIPSOP_MASK_IMMY 0x1ff
|
| 1495 |
|
|
#define MICROMIPSOP_SH_IMMY 1
|
| 1496 |
|
|
|
| 1497 |
|
|
/* Placeholders for fields that only exist in the traditional 32-bit
|
| 1498 |
|
|
instruction encoding; see the comment above for details. */
|
| 1499 |
|
|
#define MICROMIPSOP_MASK_CODE20 0
|
| 1500 |
|
|
#define MICROMIPSOP_SH_CODE20 0
|
| 1501 |
|
|
#define MICROMIPSOP_MASK_PERFREG 0
|
| 1502 |
|
|
#define MICROMIPSOP_SH_PERFREG 0
|
| 1503 |
|
|
#define MICROMIPSOP_MASK_CODE19 0
|
| 1504 |
|
|
#define MICROMIPSOP_SH_CODE19 0
|
| 1505 |
|
|
#define MICROMIPSOP_MASK_ALN 0
|
| 1506 |
|
|
#define MICROMIPSOP_SH_ALN 0
|
| 1507 |
|
|
#define MICROMIPSOP_MASK_VECBYTE 0
|
| 1508 |
|
|
#define MICROMIPSOP_SH_VECBYTE 0
|
| 1509 |
|
|
#define MICROMIPSOP_MASK_VECALIGN 0
|
| 1510 |
|
|
#define MICROMIPSOP_SH_VECALIGN 0
|
| 1511 |
|
|
#define MICROMIPSOP_MASK_DSPACC 0
|
| 1512 |
|
|
#define MICROMIPSOP_SH_DSPACC 0
|
| 1513 |
|
|
#define MICROMIPSOP_MASK_DSPACC_S 0
|
| 1514 |
|
|
#define MICROMIPSOP_SH_DSPACC_S 0
|
| 1515 |
|
|
#define MICROMIPSOP_MASK_DSPSFT 0
|
| 1516 |
|
|
#define MICROMIPSOP_SH_DSPSFT 0
|
| 1517 |
|
|
#define MICROMIPSOP_MASK_DSPSFT_7 0
|
| 1518 |
|
|
#define MICROMIPSOP_SH_DSPSFT_7 0
|
| 1519 |
|
|
#define MICROMIPSOP_MASK_SA3 0
|
| 1520 |
|
|
#define MICROMIPSOP_SH_SA3 0
|
| 1521 |
|
|
#define MICROMIPSOP_MASK_SA4 0
|
| 1522 |
|
|
#define MICROMIPSOP_SH_SA4 0
|
| 1523 |
|
|
#define MICROMIPSOP_MASK_IMM8 0
|
| 1524 |
|
|
#define MICROMIPSOP_SH_IMM8 0
|
| 1525 |
|
|
#define MICROMIPSOP_MASK_IMM10 0
|
| 1526 |
|
|
#define MICROMIPSOP_SH_IMM10 0
|
| 1527 |
|
|
#define MICROMIPSOP_MASK_WRDSP 0
|
| 1528 |
|
|
#define MICROMIPSOP_SH_WRDSP 0
|
| 1529 |
|
|
#define MICROMIPSOP_MASK_RDDSP 0
|
| 1530 |
|
|
#define MICROMIPSOP_SH_RDDSP 0
|
| 1531 |
|
|
#define MICROMIPSOP_MASK_BP 0
|
| 1532 |
|
|
#define MICROMIPSOP_SH_BP 0
|
| 1533 |
|
|
#define MICROMIPSOP_MASK_MT_U 0
|
| 1534 |
|
|
#define MICROMIPSOP_SH_MT_U 0
|
| 1535 |
|
|
#define MICROMIPSOP_MASK_MT_H 0
|
| 1536 |
|
|
#define MICROMIPSOP_SH_MT_H 0
|
| 1537 |
|
|
#define MICROMIPSOP_MASK_MTACC_T 0
|
| 1538 |
|
|
#define MICROMIPSOP_SH_MTACC_T 0
|
| 1539 |
|
|
#define MICROMIPSOP_MASK_MTACC_D 0
|
| 1540 |
|
|
#define MICROMIPSOP_SH_MTACC_D 0
|
| 1541 |
|
|
#define MICROMIPSOP_MASK_BBITIND 0
|
| 1542 |
|
|
#define MICROMIPSOP_SH_BBITIND 0
|
| 1543 |
|
|
#define MICROMIPSOP_MASK_CINSPOS 0
|
| 1544 |
|
|
#define MICROMIPSOP_SH_CINSPOS 0
|
| 1545 |
|
|
#define MICROMIPSOP_MASK_CINSLM1 0
|
| 1546 |
|
|
#define MICROMIPSOP_SH_CINSLM1 0
|
| 1547 |
|
|
#define MICROMIPSOP_MASK_SEQI 0
|
| 1548 |
|
|
#define MICROMIPSOP_SH_SEQI 0
|
| 1549 |
|
|
#define MICROMIPSOP_SH_OFFSET_A 0
|
| 1550 |
|
|
#define MICROMIPSOP_MASK_OFFSET_A 0
|
| 1551 |
|
|
#define MICROMIPSOP_SH_OFFSET_B 0
|
| 1552 |
|
|
#define MICROMIPSOP_MASK_OFFSET_B 0
|
| 1553 |
|
|
#define MICROMIPSOP_SH_OFFSET_C 0
|
| 1554 |
|
|
#define MICROMIPSOP_MASK_OFFSET_C 0
|
| 1555 |
|
|
#define MICROMIPSOP_SH_RZ 0
|
| 1556 |
|
|
#define MICROMIPSOP_MASK_RZ 0
|
| 1557 |
|
|
#define MICROMIPSOP_SH_FZ 0
|
| 1558 |
|
|
#define MICROMIPSOP_MASK_FZ 0
|
| 1559 |
|
|
|
| 1560 |
|
|
/* These are the characters which may appears in the args field of a microMIPS
|
| 1561 |
|
|
instruction. They appear in the order in which the fields appear
|
| 1562 |
|
|
when the instruction is used. Commas and parentheses in the args
|
| 1563 |
|
|
string are ignored when assembling, and written into the output
|
| 1564 |
|
|
when disassembling.
|
| 1565 |
|
|
|
| 1566 |
|
|
The followings are for 16-bit microMIPS instructions.
|
| 1567 |
|
|
|
| 1568 |
|
|
"ma" must be $28
|
| 1569 |
|
|
"mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4
|
| 1570 |
|
|
The same register used as both source and target.
|
| 1571 |
|
|
"md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7
|
| 1572 |
|
|
"me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1
|
| 1573 |
|
|
The same register used as both source and target.
|
| 1574 |
|
|
"mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
|
| 1575 |
|
|
"mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
|
| 1576 |
|
|
"mh" MIPS registers 4, 5, 6 (MICROMIPSOP_*_MH) at bit 7
|
| 1577 |
|
|
"mi" MIPS registers 5, 6, 7, 21, 22 (MICROMIPSOP_*_MI) at bit 7
|
| 1578 |
|
|
("mh" and "mi" form a valid 3-bit register pair)
|
| 1579 |
|
|
"mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
|
| 1580 |
|
|
"ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
|
| 1581 |
|
|
"mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
|
| 1582 |
|
|
"mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4
|
| 1583 |
|
|
"mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5
|
| 1584 |
|
|
"mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7
|
| 1585 |
|
|
"mr" must be program counter
|
| 1586 |
|
|
"ms" must be $29
|
| 1587 |
|
|
"mt" must be the same as the previous register
|
| 1588 |
|
|
"mx" must be the same as the destination register
|
| 1589 |
|
|
"my" must be $31
|
| 1590 |
|
|
"mz" must be $0
|
| 1591 |
|
|
|
| 1592 |
|
|
"mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA)
|
| 1593 |
|
|
"mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB)
|
| 1594 |
|
|
"mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255,
|
| 1595 |
|
|
32768, 65535) (MICROMIPSOP_*_IMMC)
|
| 1596 |
|
|
"mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD)
|
| 1597 |
|
|
"mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME)
|
| 1598 |
|
|
"mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF)
|
| 1599 |
|
|
"mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG)
|
| 1600 |
|
|
"mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH)
|
| 1601 |
|
|
"mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI)
|
| 1602 |
|
|
"mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ)
|
| 1603 |
|
|
"mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
|
| 1604 |
|
|
"mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM)
|
| 1605 |
|
|
"mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN)
|
| 1606 |
|
|
"mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
|
| 1607 |
|
|
"mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP)
|
| 1608 |
|
|
"mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU)
|
| 1609 |
|
|
"mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW)
|
| 1610 |
|
|
"mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX)
|
| 1611 |
|
|
"mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY)
|
| 1612 |
|
|
"mZ" must be zero
|
| 1613 |
|
|
|
| 1614 |
|
|
In most cases 32-bit microMIPS instructions use the same characters
|
| 1615 |
|
|
as MIPS (with ADDIUPC being a notable exception, but there are some
|
| 1616 |
|
|
others too).
|
| 1617 |
|
|
|
| 1618 |
|
|
"." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
|
| 1619 |
|
|
"1" 5-bit sync type (MICROMIPSOP_*_SHAMT)
|
| 1620 |
|
|
"<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
|
| 1621 |
|
|
">" shift amount between 32 and 63, stored after subtracting 32
|
| 1622 |
|
|
(MICROMIPSOP_*_SHAMT)
|
| 1623 |
|
|
"\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS)
|
| 1624 |
|
|
"|" 4-bit trap code (MICROMIPSOP_*_TRAP)
|
| 1625 |
|
|
"~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
|
| 1626 |
|
|
"a" 26-bit target address (MICROMIPSOP_*_TARGET)
|
| 1627 |
|
|
"b" 5-bit base register (MICROMIPSOP_*_RS)
|
| 1628 |
|
|
"c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
|
| 1629 |
|
|
"d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
|
| 1630 |
|
|
"h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
|
| 1631 |
163 |
khays |
"i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
|
| 1632 |
161 |
khays |
"j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
|
| 1633 |
|
|
"k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
|
| 1634 |
|
|
"n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
|
| 1635 |
|
|
"o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
|
| 1636 |
|
|
"p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
|
| 1637 |
|
|
"q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2)
|
| 1638 |
|
|
"r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS)
|
| 1639 |
|
|
"s" 5-bit source register specifier (MICROMIPSOP_*_RS)
|
| 1640 |
|
|
"t" 5-bit target register (MICROMIPSOP_*_RT)
|
| 1641 |
|
|
"u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE)
|
| 1642 |
|
|
"v" 5-bit same register used as both source and destination
|
| 1643 |
|
|
(MICROMIPSOP_*_RS)
|
| 1644 |
|
|
"w" 5-bit same register used as both target and destination
|
| 1645 |
|
|
(MICROMIPSOP_*_RT)
|
| 1646 |
|
|
"y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
|
| 1647 |
|
|
"z" must be zero register
|
| 1648 |
|
|
"C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
|
| 1649 |
|
|
"B" 8-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
|
| 1650 |
|
|
"K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
|
| 1651 |
|
|
|
| 1652 |
|
|
"+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
|
| 1653 |
|
|
LSB (MICROMIPSOP_*_EXTLSB).
|
| 1654 |
|
|
Enforces: 0 <= pos < 32.
|
| 1655 |
|
|
"+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB).
|
| 1656 |
|
|
Requires that "+A" or "+E" occur first to set position.
|
| 1657 |
|
|
Enforces: 0 < (pos+size) <= 32.
|
| 1658 |
|
|
"+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
|
| 1659 |
|
|
Requires that "+A" or "+E" occur first to set position.
|
| 1660 |
|
|
Enforces: 0 < (pos+size) <= 32.
|
| 1661 |
|
|
(Also used by DEXT w/ different limits, but limits for
|
| 1662 |
|
|
that are checked by the M_DEXT macro.)
|
| 1663 |
|
|
"+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB).
|
| 1664 |
|
|
Enforces: 32 <= pos < 64.
|
| 1665 |
|
|
"+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB).
|
| 1666 |
|
|
Requires that "+A" or "+E" occur first to set position.
|
| 1667 |
|
|
Enforces: 32 < (pos+size) <= 64.
|
| 1668 |
|
|
"+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD).
|
| 1669 |
|
|
Requires that "+A" or "+E" occur first to set position.
|
| 1670 |
|
|
Enforces: 32 < (pos+size) <= 64.
|
| 1671 |
|
|
"+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
|
| 1672 |
|
|
Requires that "+A" or "+E" occur first to set position.
|
| 1673 |
|
|
Enforces: 32 < (pos+size) <= 64.
|
| 1674 |
|
|
|
| 1675 |
|
|
PC-relative addition (ADDIUPC) instruction:
|
| 1676 |
|
|
"mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
|
| 1677 |
|
|
"mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23
|
| 1678 |
|
|
|
| 1679 |
|
|
Floating point instructions:
|
| 1680 |
|
|
"D" 5-bit destination register (MICROMIPSOP_*_FD)
|
| 1681 |
|
|
"M" 3-bit compare condition code (MICROMIPSOP_*_CCC)
|
| 1682 |
|
|
"N" 3-bit branch condition code (MICROMIPSOP_*_BCC)
|
| 1683 |
|
|
"R" 5-bit fr source 3 register (MICROMIPSOP_*_FR)
|
| 1684 |
|
|
"S" 5-bit fs source 1 register (MICROMIPSOP_*_FS)
|
| 1685 |
|
|
"T" 5-bit ft source 2 register (MICROMIPSOP_*_FT)
|
| 1686 |
|
|
"V" 5-bit same register used as floating source and destination or target
|
| 1687 |
|
|
(MICROMIPSOP_*_FS)
|
| 1688 |
|
|
|
| 1689 |
|
|
Coprocessor instructions:
|
| 1690 |
|
|
"E" 5-bit target register (MICROMIPSOP_*_RT)
|
| 1691 |
|
|
"G" 5-bit destination register (MICROMIPSOP_*_RD)
|
| 1692 |
|
|
"H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
|
| 1693 |
|
|
"+D" combined destination register ("G") and sel ("H") for CP0 ops,
|
| 1694 |
|
|
for pretty-printing in disassembly only
|
| 1695 |
|
|
|
| 1696 |
|
|
Macro instructions:
|
| 1697 |
|
|
"A" general 32 bit expression
|
| 1698 |
|
|
"I" 32-bit immediate (value placed in imm_expr).
|
| 1699 |
|
|
"+I" 32-bit immediate (value placed in imm2_expr).
|
| 1700 |
|
|
"F" 64-bit floating point constant in .rdata
|
| 1701 |
|
|
"L" 64-bit floating point constant in .lit8
|
| 1702 |
|
|
"f" 32-bit floating point constant
|
| 1703 |
|
|
"l" 32-bit floating point constant in .lit4
|
| 1704 |
|
|
|
| 1705 |
|
|
Other:
|
| 1706 |
|
|
"()" parens surrounding optional value
|
| 1707 |
|
|
"," separates operands
|
| 1708 |
|
|
"+" start of extension sequence
|
| 1709 |
|
|
"m" start of microMIPS extension sequence
|
| 1710 |
|
|
|
| 1711 |
|
|
Characters used so far, for quick reference when adding more:
|
| 1712 |
|
|
"1234567890"
|
| 1713 |
|
|
"<>(),+.\|~"
|
| 1714 |
|
|
"ABCDEFGHI KLMN RST V "
|
| 1715 |
|
|
"abcd f hijklmnopqrstuvw yz"
|
| 1716 |
|
|
|
| 1717 |
|
|
Extension character sequences used so far ("+" followed by the
|
| 1718 |
|
|
following), for quick reference when adding more:
|
| 1719 |
|
|
""
|
| 1720 |
|
|
""
|
| 1721 |
|
|
"ABCDEFGHI"
|
| 1722 |
|
|
""
|
| 1723 |
|
|
|
| 1724 |
|
|
Extension character sequences used so far ("m" followed by the
|
| 1725 |
|
|
following), for quick reference when adding more:
|
| 1726 |
|
|
""
|
| 1727 |
|
|
""
|
| 1728 |
|
|
" BCDEFGHIJ LMNOPQ U WXYZ"
|
| 1729 |
|
|
" bcdefghij lmn pq st xyz"
|
| 1730 |
|
|
*/
|
| 1731 |
|
|
|
| 1732 |
|
|
extern const struct mips_opcode micromips_opcodes[];
|
| 1733 |
|
|
extern const int bfd_micromips_num_opcodes;
|
| 1734 |
|
|
|
| 1735 |
17 |
khays |
/* A NOP insn impemented as "or at,at,zero".
|
| 1736 |
|
|
Used to implement -mfix-loongson2f. */
|
| 1737 |
|
|
#define LOONGSON2F_NOP_INSN 0x00200825
|
| 1738 |
|
|
|
| 1739 |
|
|
#endif /* _MIPS_H_ */
|
