URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [include/] [opcode/] [open8.h] - Blame information for rev 124

Go to most recent revision | Details | Compare with Previous | View Log


/* Opcode table for the Open8/V8/ARClite MCUs
 
   Copyright 2000, 2001, 2004, 2006, 2008, 2010, 2011
   Free Software Foundation, Inc.
 
   Contributed by Kirk Hays <khays@hayshaus.com>
 
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */
 
#define OPEN8_ISA_OPEN8   0x0001 /* Opcode set as published for the Open8.  */
#define OPEN8_ISA_V8      0x0002 /* Opcode set for original VAutomation V8.  */
#define OPEN8_ISA_ALL (OPEN8_ISA_V8 | OPEN8_ISA_OPEN8)
 
/* constraint letters
   r - any general purpose register index (R0..R7)
   e - any even numbered general purpose register, the upper two
   bits thereof
 
   u - unsigned offset expression, 8 bits, from 0 to 255,
   always 2nd byte of insn
   s - signed pc-relative offset expression, 8 bits, from -128 to 127,
   always 2nd byte of insn
   i - immediate value expression, eight bits, signed or unsigned,
   always 2nd byte of insn
 
   n - immediate value expression from 0 to 7, 3 bits
   b - immediate value expression from 0 to 7, 3 bits, indexing PSR
 
   h - 16 bit address expression for JMP variant,
   located at bytes 2 and 3 of the instruction
 
   H - 16 bit address expression for composed JMP variants,
   located at bytes 4 and 5 of the composed instruction
 
   M - 16 bit memory address for load and store,
   located at bytes 2 and 3 of the instruction
 
   a - autoincrement operator - syntactically "++", bitvalue = 1, 0 if not
   present
 
   Order is important - some binary opcodes have more than one name,
   the disassembler will only see the first match.
 
*/
 
#define R "rrr"
#define E "ee"
#define U "uuuuuuuu"
#define S "ssssssss"
#define I "iiiiiiii"
#define N "nnn"
#define B "bbb"
#define H "hhhhhhhhhhhhhhhh"
#define BIG_H "HHHHHHHHHHHHHHHH"
#define M "MMMMMMMMMMMMMMMM"
#define A "a"
 
#define REGISTER_P(x) ((x) == 'r' || (x) == 'e')
#define MAX_INSN_SIZE (5)
 
#define SUBOP_MASK  (0x07U)
#define SUBOP_SHIFT (0U)
 
#define REG_MASK  (SUBOP_MASK)
#define REG_SHIFT (SUBOP_SHIFT)
 
#define EREG_MASK  (SUBOP_MASK & 0x06U)
#define EREG_SHIFT (SUBOP_SHIFT)
 
#define U_MASK  (0x0FF00U)
#define U_SHIFT (8U)
 
#define S_MASK  (U_MASK)
#define S_SHIFT (U_SHIFT)
 
#define I_MASK  (U_MASK)
#define I_SHIFT (U_SHIFT)
 
#define N_MASK  (SUBOP_MASK)
#define N_SHIFT (SUBOP_SHIFT)
 
#define B_MASK  (SUBOP_MASK)
#define B_SHIFT (SUBOP_SHIFT)
 
#define H_MASK  (0xFFFF00ULL)
#define H_SHIFT (8U)
 
#define BIG_H_MASK  (0xFFFF000000ULL)
#define BIG_H_SHIFT (24U)
 
#define M_MASK  (0xFFFF00ULL)
#define M_SHIFT (8U)
 
#define A_MASK (0x01U)
 
#define MAKE_OPCODE(a, b, c)                    \
  (((unsigned long long) (a))                   \
   | ((unsigned long long) (b) << 8)            \
   | ((unsigned long long) (c) << 16))
 
/* Composite-mnemonics - generate two or more machine instructions,
 * introduced to simplify compiler logic for branching,
 * oftimes relaxed by peephole or linker into simple branches
 */
/* NB: these must come first, so that the composites are recognized first when
 * disassembling.
 */
OPEN8_INSN (jmpz,  "H", "10010000000010010111100" BIG_H, 5, OPEN8_ISA_ALL, \
            MAKE_OPCODE (0x090U,0x05U,0x0BCU), 0x0FFFFFFU)
/*
* brnz <label>
* jmp h
* <label>:
*/
 
OPEN8_INSN (jmpnz, "H", "10011000000010010111100" BIG_H, 5, OPEN8_ISA_ALL, \
            MAKE_OPCODE (0x098U,0x05U,0x0BCU), 0x0FFFFFFU)
/*
* brz <label>
* jmp h,
* <label>:
*/
 
OPEN8_INSN (jmplz, "H", "10010010000010010111100" BIG_H, 5, OPEN8_ISA_ALL, \
            MAKE_OPCODE (0x092U,0x05U,0x0BCU), 0x0FFFFFFU)
/*
* brgez <label>
* jmp h
* <label>:
*/
 
OPEN8_INSN (jmpgez,"H", "10011010000010010111100" BIG_H, 5, OPEN8_ISA_ALL, \
            MAKE_OPCODE (0x09AU,0x05U,0x0BCU), 0x0FFFFFFU)
/*
* brlz <label>
* jmp h
*<label>:
*/
 
OPEN8_INSN (jmpc,  "H", "10010001000010010111100" BIG_H, 5, OPEN8_ISA_ALL, \
            MAKE_OPCODE (0x091U,0x05U,0x0BCU), 0x0FFFFFFU)
/*
* brnc <label>
* jmp h
* <label>:
*/
 
OPEN8_INSN (jmpnc, "H", "10011001000010010111100" BIG_H, 5, OPEN8_ISA_ALL, \
            MAKE_OPCODE (0x099U,0x05U,0x0BCU), 0x0FFFFFFU)
/*
* brc <label>
* jmp h
* <label>:
*/
 
/* Pseudo-mnemonics - map 1:1 to actual machine instructions,
 * introduced for programmer/compiler ease.
 */
/* NB: these must come before the actual machine instructions,
 * so that the pseudo-mnemonics are recognized first when disassembling.
 */
OPEN8_INSN (stz,  "",   "01011000",         1, OPEN8_ISA_ALL, 0x058U, 0x0FFU)
/* stp 0 */
 
OPEN8_INSN (stc,  "",   "01011001",         1, OPEN8_ISA_ALL, 0x059U, 0x0FFU)
/* stp 1 */
 
OPEN8_INSN (stn,  "",   "01011010",         1, OPEN8_ISA_ALL, 0x05AU, 0x0FFU)
/* stp 2 */
 
OPEN8_INSN (sti,  "",   "01011011",         1, OPEN8_ISA_ALL, 0x05BU, 0x0FFU)
/* stp 3 */
 
OPEN8_INSN (clz,  "",   "01101000",         1, OPEN8_ISA_ALL, 0x068U, 0x0FFU)
/* clp 0 */
 
OPEN8_INSN (clc,  "",   "01101001",         1, OPEN8_ISA_ALL, 0x069U, 0x0FFU)
/* clp 1 */
 
OPEN8_INSN (cln,  "",   "01101010",         1, OPEN8_ISA_ALL, 0x06AU, 0x0FFU)
/* clp 2 */
 
OPEN8_INSN (cli,  "",   "01101011",         1, OPEN8_ISA_ALL, 0x06BU, 0x0FFU)
/* clp 3 */
 
OPEN8_INSN (brnz, "s",  "10010000" S,       2, OPEN8_ISA_ALL, 0x090U, 0x0FFU)
/* br0 0, s */
 
OPEN8_INSN (brnc, "s",  "10010001" S,       2, OPEN8_ISA_ALL, 0x091U, 0x0FFU)
/* br0 1, s */
 
OPEN8_INSN (brgez,"s",  "10010010" S,       2, OPEN8_ISA_ALL, 0x092U, 0x0FFU)
/* br0 2, s */
 
OPEN8_INSN (brz,  "s",  "10011000" S,       2, OPEN8_ISA_ALL, 0x098U, 0x0FFU)
/* br1 0, s */
 
OPEN8_INSN (brc,  "s",  "10011001" S,       2, OPEN8_ISA_ALL, 0x099U, 0x0FFU)
/* br1 1, s */
 
OPEN8_INSN (brlz, "s",  "10011010" S,       2, OPEN8_ISA_ALL, 0x09AU, 0x0FFU)
/* br1 2, s */
 
OPEN8_INSN (nop,  "",   "10111011",         1, OPEN8_ISA_ALL, 0x0BBU, 0x0FFU)
/* brk */
 
/* Native instructions */
OPEN8_INSN (inc,  "r",    "00000" R,     1, OPEN8_ISA_ALL,    0x000U, 0x0F8U)
OPEN8_INSN (adc,  "r",    "00001" R,     1, OPEN8_ISA_ALL,    0x008U, 0x0F8U)
OPEN8_INSN (tx0,  "r",    "00010" R,     1, OPEN8_ISA_ALL,    0x010U, 0x0F8U)
OPEN8_INSN (or,   "r",    "00011" R,     1, OPEN8_ISA_ALL,    0x018U, 0x0F8U)
OPEN8_INSN (and,  "r",    "00100" R,     1, OPEN8_ISA_ALL,    0x020U, 0x0F8U)
OPEN8_INSN (xor,  "r",    "00101" R,     1, OPEN8_ISA_ALL,    0x028U, 0x0F8U)
OPEN8_INSN (rol,  "r",    "00110" R,     1, OPEN8_ISA_ALL,    0x030U, 0x0F8U)
OPEN8_INSN (ror,  "r",    "00111" R,     1, OPEN8_ISA_ALL,    0x038U, 0x0F8U)
OPEN8_INSN (dec,  "r",    "01000" R,     1, OPEN8_ISA_ALL,    0x040U, 0x0F8U)
OPEN8_INSN (sbc,  "r",    "01001" R,     1, OPEN8_ISA_ALL,    0x048U, 0x0F8U)
OPEN8_INSN (add,  "r",    "01010" R,     1, OPEN8_ISA_ALL,    0x050U, 0x0F8U)
OPEN8_INSN (stp,  "b",    "01011" B,     1, OPEN8_ISA_ALL,    0x058U, 0x0F8U)
OPEN8_INSN (btt,  "b",    "01100" B,     1, OPEN8_ISA_ALL,    0x060U, 0x0F8U)
OPEN8_INSN (clp,  "b",    "01101" B,     1, OPEN8_ISA_ALL,    0x068U, 0x0F8U)
OPEN8_INSN (t0x,  "r",    "01110" R,     1, OPEN8_ISA_ALL,    0x070U, 0x0F8U)
OPEN8_INSN (cmp,  "r",    "01111" R,     1, OPEN8_ISA_ALL,    0x078U, 0x0F8U)
OPEN8_INSN (psh,  "r",    "10000" R,     1, OPEN8_ISA_ALL,    0x080U, 0x0F8U)
OPEN8_INSN (pop,  "r",    "10001" R,     1, OPEN8_ISA_ALL,    0x088U, 0x0F8U)
OPEN8_INSN (br0,  "b,s",  "10010" B S,   2, OPEN8_ISA_ALL,    0x090U, 0x0F8U)
OPEN8_INSN (br1,  "b,s",  "10011" B S,   2, OPEN8_ISA_ALL,    0x098U, 0x0F8U)
/* `usr' is defined below */
OPEN8_INSN (int,  "n",    "10101" N,     1, OPEN8_ISA_ALL,    0x0A8U, 0x0F8U)
/* `usr2' is defined below */
OPEN8_INSN (rsp,  "",     "10111000",    1, OPEN8_ISA_ALL,    0x0B8U, 0x0FFU)
OPEN8_INSN (rts,  "",     "10111001",    1, OPEN8_ISA_ALL,    0x0B9U, 0x0FFU)
OPEN8_INSN (rti,  "",     "10111010",    1, OPEN8_ISA_ALL,    0x0BAU, 0x0FFU)
OPEN8_INSN (brk,  "",     "10111011",    1, OPEN8_ISA_ALL,    0x0BBU, 0x0FFU)
OPEN8_INSN (jmp,  "h",    "10111100" H,  3, OPEN8_ISA_ALL,    0x0BCU, 0x0FFU)
OPEN8_INSN (jsr,  "h",    "10111111" H,  3, OPEN8_ISA_ALL,    0x0BFU, 0x0FFU)
OPEN8_INSN (upp,  "e",    "11000" E "0", 1, OPEN8_ISA_ALL,    0x0C0U, 0x0F9U)
OPEN8_INSN (sta,  "r,M",  "11001" R M,   3, OPEN8_ISA_ALL,    0x0C8U, 0x0F8U)
OPEN8_INSN (ldi,  "r,i",  "11100" R I,   2, OPEN8_ISA_ALL,    0x0E0U, 0x0F8U)
OPEN8_INSN (lda,  "r,M",  "11101" R M,   3, OPEN8_ISA_ALL,    0x0E8U, 0x0F8U)
 
/* Open8 specific mnemonics.  */
 
/* Open8 instructions that add auto-increment to existing V8 instructions.  */
OPEN8_INSN (stx,  "ea",   "11010" E A,   1, OPEN8_ISA_OPEN8,  0x0D0U, 0x0F8U)
OPEN8_INSN (ldx,  "ea",   "11110" E A,   1, OPEN8_ISA_OPEN8,  0x0F0U, 0x0F8U)
OPEN8_INSN (ldo,  "ea,u", "11111" E A U, 2, OPEN8_ISA_OPEN8,  0x0F8U, 0x0F8U)
OPEN8_INSN (sto,  "ea,u", "11011" E A U, 2, OPEN8_ISA_OPEN8,  0x0D8U, 0x0F8U)
 
/* Instructions that substitute for the V8 `usr' and `usr2' instructions.  */
OPEN8_INSN (dbnz, "r,s",  "10100" R S,   2, OPEN8_ISA_OPEN8,  0x0A0U, 0x0F8U)
OPEN8_INSN (mul,  "r",    "10110" R,     1, OPEN8_ISA_OPEN8,  0x0B0U, 0x0F8U)
 
/* Interrupt mask instructions that are unique to the Open8.  */
OPEN8_INSN (smsk, "",     "10111101",    1, OPEN8_ISA_OPEN8,  0x0BDU, 0x0FFU)
OPEN8_INSN (gmsk, "",     "10111110",    1, OPEN8_ISA_OPEN8,  0x0BEU, 0x0FFU)

Browse

Tools

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [include/] [opcode/] [open8.h] - Blame information for rev 124

Line No.	Rev	Author	Line
1	17	khays	`/* Opcode table for the Open8/V8/ARClite MCUs`
2
3			`Copyright 2000, 2001, 2004, 2006, 2008, 2010, 2011`
4			`Free Software Foundation, Inc.`
5
6			`Contributed by Kirk Hays <khays@hayshaus.com>`
7
8			`This program is free software; you can redistribute it and/or modify`
9			`it under the terms of the GNU General Public License as published by`
10			`the Free Software Foundation; either version 3, or (at your option)`
11			`any later version.`
12
13			`This program is distributed in the hope that it will be useful,`
14			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`GNU General Public License for more details.`
17
18			`You should have received a copy of the GNU General Public License`
19			`along with this program; if not, write to the Free Software`
20			`Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,`
21			`MA 02110-1301, USA. */`
22
23			`#define OPEN8_ISA_OPEN8 0x0001 /* Opcode set as published for the Open8. */`
24			`#define OPEN8_ISA_V8 0x0002 /* Opcode set for original VAutomation V8. */`
25			`#define OPEN8_ISA_ALL (OPEN8_ISA_V8 \| OPEN8_ISA_OPEN8)`
26
27			`/* constraint letters`
28			`r - any general purpose register index (R0..R7)`
29			`e - any even numbered general purpose register, the upper two`
30			`bits thereof`
31
32			`u - unsigned offset expression, 8 bits, from 0 to 255,`
33			`always 2nd byte of insn`
34			`s - signed pc-relative offset expression, 8 bits, from -128 to 127,`
35			`always 2nd byte of insn`
36			`i - immediate value expression, eight bits, signed or unsigned,`
37			`always 2nd byte of insn`
38
39			`n - immediate value expression from 0 to 7, 3 bits`
40			`b - immediate value expression from 0 to 7, 3 bits, indexing PSR`
41
42			`h - 16 bit address expression for JMP variant,`
43			`located at bytes 2 and 3 of the instruction`
44
45			`H - 16 bit address expression for composed JMP variants,`
46			`located at bytes 4 and 5 of the composed instruction`
47
48			`M - 16 bit memory address for load and store,`
49			`located at bytes 2 and 3 of the instruction`
50
51			`a - autoincrement operator - syntactically "++", bitvalue = 1, 0 if not`
52			`present`
53
54			`Order is important - some binary opcodes have more than one name,`
55			`the disassembler will only see the first match.`
56
57			`*/`
58
59			`#define R "rrr"`
60			`#define E "ee"`
61			`#define U "uuuuuuuu"`
62			`#define S "ssssssss"`
63			`#define I "iiiiiiii"`
64			`#define N "nnn"`
65			`#define B "bbb"`
66			`#define H "hhhhhhhhhhhhhhhh"`
67			`#define BIG_H "HHHHHHHHHHHHHHHH"`
68			`#define M "MMMMMMMMMMMMMMMM"`
69			`#define A "a"`
70
71			`#define REGISTER_P(x) ((x) == 'r' \|\| (x) == 'e')`
72			`#define MAX_INSN_SIZE (5)`
73
74			`#define SUBOP_MASK (0x07U)`
75			`#define SUBOP_SHIFT (0U)`
76
77			`#define REG_MASK (SUBOP_MASK)`
78			`#define REG_SHIFT (SUBOP_SHIFT)`
79
80			`#define EREG_MASK (SUBOP_MASK & 0x06U)`
81			`#define EREG_SHIFT (SUBOP_SHIFT)`
82
83			`#define U_MASK (0x0FF00U)`
84			`#define U_SHIFT (8U)`
85
86			`#define S_MASK (U_MASK)`
87			`#define S_SHIFT (U_SHIFT)`
88
89			`#define I_MASK (U_MASK)`
90			`#define I_SHIFT (U_SHIFT)`
91
92			`#define N_MASK (SUBOP_MASK)`
93			`#define N_SHIFT (SUBOP_SHIFT)`
94
95			`#define B_MASK (SUBOP_MASK)`
96			`#define B_SHIFT (SUBOP_SHIFT)`
97
98			`#define H_MASK (0xFFFF00ULL)`
99			`#define H_SHIFT (8U)`
100
101			`#define BIG_H_MASK (0xFFFF000000ULL)`
102			`#define BIG_H_SHIFT (24U)`
103
104			`#define M_MASK (0xFFFF00ULL)`
105			`#define M_SHIFT (8U)`
106
107			`#define A_MASK (0x01U)`
108
109			`#define MAKE_OPCODE(a, b, c) \`
110			`(((unsigned long long) (a)) \`
111			`\| ((unsigned long long) (b) << 8) \`
112			`\| ((unsigned long long) (c) << 16))`
113
114			`/* Composite-mnemonics - generate two or more machine instructions,`
115			`* introduced to simplify compiler logic for branching,`
116			`* oftimes relaxed by peephole or linker into simple branches`
117			`*/`
118			`/* NB: these must come first, so that the composites are recognized first when`
119			`* disassembling.`
120			`*/`
121			`OPEN8_INSN (jmpz, "H", "10010000000010010111100" BIG_H, 5, OPEN8_ISA_ALL, \`
122			`MAKE_OPCODE (0x090U,0x05U,0x0BCU), 0x0FFFFFFU)`
123			`/*`
124			`* brnz <label>`
125			`* jmp h`
126			`* <label>:`
127			`*/`
128
129			`OPEN8_INSN (jmpnz, "H", "10011000000010010111100" BIG_H, 5, OPEN8_ISA_ALL, \`
130			`MAKE_OPCODE (0x098U,0x05U,0x0BCU), 0x0FFFFFFU)`
131			`/*`
132			`* brz <label>`
133			`* jmp h,`
134			`* <label>:`
135			`*/`
136
137			`OPEN8_INSN (jmplz, "H", "10010010000010010111100" BIG_H, 5, OPEN8_ISA_ALL, \`
138			`MAKE_OPCODE (0x092U,0x05U,0x0BCU), 0x0FFFFFFU)`
139			`/*`
140			`* brgez <label>`
141			`* jmp h`
142			`* <label>:`
143			`*/`
144
145			`OPEN8_INSN (jmpgez,"H", "10011010000010010111100" BIG_H, 5, OPEN8_ISA_ALL, \`
146			`MAKE_OPCODE (0x09AU,0x05U,0x0BCU), 0x0FFFFFFU)`
147			`/*`
148			`* brlz <label>`
149			`* jmp h`
150			`*<label>:`
151			`*/`
152
153			`OPEN8_INSN (jmpc, "H", "10010001000010010111100" BIG_H, 5, OPEN8_ISA_ALL, \`
154			`MAKE_OPCODE (0x091U,0x05U,0x0BCU), 0x0FFFFFFU)`
155			`/*`
156			`* brnc <label>`
157			`* jmp h`
158			`* <label>:`
159			`*/`
160
161			`OPEN8_INSN (jmpnc, "H", "10011001000010010111100" BIG_H, 5, OPEN8_ISA_ALL, \`
162			`MAKE_OPCODE (0x099U,0x05U,0x0BCU), 0x0FFFFFFU)`
163			`/*`
164			`* brc <label>`
165			`* jmp h`
166			`* <label>:`
167			`*/`
168
169			`/* Pseudo-mnemonics - map 1:1 to actual machine instructions,`
170			`* introduced for programmer/compiler ease.`
171			`*/`
172			`/* NB: these must come before the actual machine instructions,`
173			`* so that the pseudo-mnemonics are recognized first when disassembling.`
174			`*/`
175			`OPEN8_INSN (stz, "", "01011000", 1, OPEN8_ISA_ALL, 0x058U, 0x0FFU)`
176			`/* stp 0 */`
177
178			`OPEN8_INSN (stc, "", "01011001", 1, OPEN8_ISA_ALL, 0x059U, 0x0FFU)`
179			`/* stp 1 */`
180
181			`OPEN8_INSN (stn, "", "01011010", 1, OPEN8_ISA_ALL, 0x05AU, 0x0FFU)`
182			`/* stp 2 */`
183
184			`OPEN8_INSN (sti, "", "01011011", 1, OPEN8_ISA_ALL, 0x05BU, 0x0FFU)`
185			`/* stp 3 */`
186
187			`OPEN8_INSN (clz, "", "01101000", 1, OPEN8_ISA_ALL, 0x068U, 0x0FFU)`
188			`/* clp 0 */`
189
190			`OPEN8_INSN (clc, "", "01101001", 1, OPEN8_ISA_ALL, 0x069U, 0x0FFU)`
191			`/* clp 1 */`
192
193			`OPEN8_INSN (cln, "", "01101010", 1, OPEN8_ISA_ALL, 0x06AU, 0x0FFU)`
194			`/* clp 2 */`
195
196			`OPEN8_INSN (cli, "", "01101011", 1, OPEN8_ISA_ALL, 0x06BU, 0x0FFU)`
197			`/* clp 3 */`
198
199			`OPEN8_INSN (brnz, "s", "10010000" S, 2, OPEN8_ISA_ALL, 0x090U, 0x0FFU)`
200			`/* br0 0, s */`
201
202			`OPEN8_INSN (brnc, "s", "10010001" S, 2, OPEN8_ISA_ALL, 0x091U, 0x0FFU)`
203			`/* br0 1, s */`
204
205			`OPEN8_INSN (brgez,"s", "10010010" S, 2, OPEN8_ISA_ALL, 0x092U, 0x0FFU)`
206			`/* br0 2, s */`
207
208			`OPEN8_INSN (brz, "s", "10011000" S, 2, OPEN8_ISA_ALL, 0x098U, 0x0FFU)`
209			`/* br1 0, s */`
210
211			`OPEN8_INSN (brc, "s", "10011001" S, 2, OPEN8_ISA_ALL, 0x099U, 0x0FFU)`
212			`/* br1 1, s */`
213
214			`OPEN8_INSN (brlz, "s", "10011010" S, 2, OPEN8_ISA_ALL, 0x09AU, 0x0FFU)`
215			`/* br1 2, s */`
216
217			`OPEN8_INSN (nop, "", "10111011", 1, OPEN8_ISA_ALL, 0x0BBU, 0x0FFU)`
218			`/* brk */`
219
220			`/* Native instructions */`
221			`OPEN8_INSN (inc, "r", "00000" R, 1, OPEN8_ISA_ALL, 0x000U, 0x0F8U)`
222			`OPEN8_INSN (adc, "r", "00001" R, 1, OPEN8_ISA_ALL, 0x008U, 0x0F8U)`
223			`OPEN8_INSN (tx0, "r", "00010" R, 1, OPEN8_ISA_ALL, 0x010U, 0x0F8U)`
224			`OPEN8_INSN (or, "r", "00011" R, 1, OPEN8_ISA_ALL, 0x018U, 0x0F8U)`
225			`OPEN8_INSN (and, "r", "00100" R, 1, OPEN8_ISA_ALL, 0x020U, 0x0F8U)`
226			`OPEN8_INSN (xor, "r", "00101" R, 1, OPEN8_ISA_ALL, 0x028U, 0x0F8U)`
227			`OPEN8_INSN (rol, "r", "00110" R, 1, OPEN8_ISA_ALL, 0x030U, 0x0F8U)`
228			`OPEN8_INSN (ror, "r", "00111" R, 1, OPEN8_ISA_ALL, 0x038U, 0x0F8U)`
229			`OPEN8_INSN (dec, "r", "01000" R, 1, OPEN8_ISA_ALL, 0x040U, 0x0F8U)`
230			`OPEN8_INSN (sbc, "r", "01001" R, 1, OPEN8_ISA_ALL, 0x048U, 0x0F8U)`
231			`OPEN8_INSN (add, "r", "01010" R, 1, OPEN8_ISA_ALL, 0x050U, 0x0F8U)`
232			`OPEN8_INSN (stp, "b", "01011" B, 1, OPEN8_ISA_ALL, 0x058U, 0x0F8U)`
233			`OPEN8_INSN (btt, "b", "01100" B, 1, OPEN8_ISA_ALL, 0x060U, 0x0F8U)`
234			`OPEN8_INSN (clp, "b", "01101" B, 1, OPEN8_ISA_ALL, 0x068U, 0x0F8U)`
235			`OPEN8_INSN (t0x, "r", "01110" R, 1, OPEN8_ISA_ALL, 0x070U, 0x0F8U)`
236			`OPEN8_INSN (cmp, "r", "01111" R, 1, OPEN8_ISA_ALL, 0x078U, 0x0F8U)`
237			`OPEN8_INSN (psh, "r", "10000" R, 1, OPEN8_ISA_ALL, 0x080U, 0x0F8U)`
238			`OPEN8_INSN (pop, "r", "10001" R, 1, OPEN8_ISA_ALL, 0x088U, 0x0F8U)`
239			`OPEN8_INSN (br0, "b,s", "10010" B S, 2, OPEN8_ISA_ALL, 0x090U, 0x0F8U)`
240			`OPEN8_INSN (br1, "b,s", "10011" B S, 2, OPEN8_ISA_ALL, 0x098U, 0x0F8U)`
241			/* `usr' is defined below */
242			`OPEN8_INSN (int, "n", "10101" N, 1, OPEN8_ISA_ALL, 0x0A8U, 0x0F8U)`
243			/* `usr2' is defined below */
244			`OPEN8_INSN (rsp, "", "10111000", 1, OPEN8_ISA_ALL, 0x0B8U, 0x0FFU)`
245			`OPEN8_INSN (rts, "", "10111001", 1, OPEN8_ISA_ALL, 0x0B9U, 0x0FFU)`
246			`OPEN8_INSN (rti, "", "10111010", 1, OPEN8_ISA_ALL, 0x0BAU, 0x0FFU)`
247			`OPEN8_INSN (brk, "", "10111011", 1, OPEN8_ISA_ALL, 0x0BBU, 0x0FFU)`
248			`OPEN8_INSN (jmp, "h", "10111100" H, 3, OPEN8_ISA_ALL, 0x0BCU, 0x0FFU)`
249			`OPEN8_INSN (jsr, "h", "10111111" H, 3, OPEN8_ISA_ALL, 0x0BFU, 0x0FFU)`
250			`OPEN8_INSN (upp, "e", "11000" E "0", 1, OPEN8_ISA_ALL, 0x0C0U, 0x0F9U)`
251			`OPEN8_INSN (sta, "r,M", "11001" R M, 3, OPEN8_ISA_ALL, 0x0C8U, 0x0F8U)`
252			`OPEN8_INSN (ldi, "r,i", "11100" R I, 2, OPEN8_ISA_ALL, 0x0E0U, 0x0F8U)`
253			`OPEN8_INSN (lda, "r,M", "11101" R M, 3, OPEN8_ISA_ALL, 0x0E8U, 0x0F8U)`
254
255			`/* Open8 specific mnemonics. */`
256
257			`/* Open8 instructions that add auto-increment to existing V8 instructions. */`
258			`OPEN8_INSN (stx, "ea", "11010" E A, 1, OPEN8_ISA_OPEN8, 0x0D0U, 0x0F8U)`
259			`OPEN8_INSN (ldx, "ea", "11110" E A, 1, OPEN8_ISA_OPEN8, 0x0F0U, 0x0F8U)`
260			`OPEN8_INSN (ldo, "ea,u", "11111" E A U, 2, OPEN8_ISA_OPEN8, 0x0F8U, 0x0F8U)`
261			`OPEN8_INSN (sto, "ea,u", "11011" E A U, 2, OPEN8_ISA_OPEN8, 0x0D8U, 0x0F8U)`
262
263			/* Instructions that substitute for the V8 `usr' and `usr2' instructions. */
264			`OPEN8_INSN (dbnz, "r,s", "10100" R S, 2, OPEN8_ISA_OPEN8, 0x0A0U, 0x0F8U)`
265			`OPEN8_INSN (mul, "r", "10110" R, 1, OPEN8_ISA_OPEN8, 0x0B0U, 0x0F8U)`
266
267			`/* Interrupt mask instructions that are unique to the Open8. */`
268			`OPEN8_INSN (smsk, "", "10111101", 1, OPEN8_ISA_OPEN8, 0x0BDU, 0x0FFU)`
269			`OPEN8_INSN (gmsk, "", "10111110", 1, OPEN8_ISA_OPEN8, 0x0BEU, 0x0FFU)`