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[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [include/] [opcode/] [sparc.h] - Blame information for rev 24

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/* Definitions for opcode table for the sparc.
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   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
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   2003, 2005, 2010 Free Software Foundation, Inc.
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   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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   the GNU Binutils.
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   GAS/GDB is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License as published by
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   the Free Software Foundation; either version 3, or (at your option)
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   any later version.
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   GAS/GDB is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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   GNU General Public License for more details.
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   You should have received a copy of the GNU General Public License
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   along with GAS or GDB; see the file COPYING3.  If not, write to
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   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
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   Boston, MA 02110-1301, USA.  */
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#include "ansidecl.h"
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/* The SPARC opcode table (and other related data) is defined in
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   the opcodes library in sparc-opc.c.  If you change anything here, make
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   sure you fix up that file, and vice versa.  */
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 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
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    instruction's name rather than the args.  This would make gas faster, pinsn
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    slower, but would mess up some macros a bit.  xoxorich. */
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/* List of instruction sets variations.
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   These values are such that each element is either a superset of a
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   preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
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   returns non-zero.
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   The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
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   Don't change this without updating sparc-opc.c.  */
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enum sparc_opcode_arch_val
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{
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  SPARC_OPCODE_ARCH_V6 = 0,
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  SPARC_OPCODE_ARCH_V7,
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  SPARC_OPCODE_ARCH_V8,
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  SPARC_OPCODE_ARCH_SPARCLET,
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  SPARC_OPCODE_ARCH_SPARCLITE,
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  /* V9 variants must appear last.  */
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  SPARC_OPCODE_ARCH_V9,
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  SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions.  */
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  SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions.  */
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  SPARC_OPCODE_ARCH_BAD  /* Error return from sparc_opcode_lookup_arch.  */
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};
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/* The highest architecture in the table.  */
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#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
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/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
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   insn encoding/decoding.  */
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#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
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/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9.  */
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#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
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/* Table of cpu variants.  */
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typedef struct sparc_opcode_arch
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{
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  const char *name;
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  /* Mask of sparc_opcode_arch_val's supported.
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     EG: For v7 this would be
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     (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
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     These are short's because sparc_opcode.architecture is.  */
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  short supported;
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} sparc_opcode_arch;
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extern const struct sparc_opcode_arch sparc_opcode_archs[];
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/* Given architecture name, look up it's sparc_opcode_arch_val value.  */
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extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *);
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/* Return the bitmask of supported architectures for ARCH.  */
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#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
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/* Non-zero if ARCH1 conflicts with ARCH2.
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   IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa.  */
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#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
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 (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
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   != SPARC_OPCODE_SUPPORTED (ARCH1)) \
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  && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
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     != SPARC_OPCODE_SUPPORTED (ARCH2)))
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/* Structure of an opcode table entry.  */
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typedef struct sparc_opcode
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{
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  const char *name;
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  unsigned long match;  /* Bits that must be set.  */
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  unsigned long lose;   /* Bits that must not be set.  */
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  const char *args;
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  /* This was called "delayed" in versions before the flags.  */
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  char flags;
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  short architecture;   /* Bitmask of sparc_opcode_arch_val's.  */
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} sparc_opcode;
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#define F_DELAYED       1       /* Delayed branch.  */
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#define F_ALIAS         2       /* Alias for a "real" instruction.  */
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#define F_UNBR          4       /* Unconditional branch.  */
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#define F_CONDBR        8       /* Conditional branch.  */
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#define F_JSR           16      /* Subroutine call.  */
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#define F_FLOAT         32      /* Floating point instruction (not a branch).  */
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#define F_FBR           64      /* Floating point branch.  */
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/* FIXME: Add F_ANACHRONISTIC flag for v9.  */
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/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
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   macro), which is 64 bits. It is handled as a special case.
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   The match component is a mask saying which bits must match a particular
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   opcode in order for an instruction to be an instance of that opcode.
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   The args component is a string containing one character for each operand of the
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   instruction.
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   Kinds of operands:
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        #       Number used by optimizer.       It is ignored.
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        1       rs1 register.
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        2       rs2 register.
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        d       rd register.
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        e       frs1 floating point register.
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        v       frs1 floating point register (double/even).
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        V       frs1 floating point register (quad/multiple of 4).
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        f       frs2 floating point register.
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        B       frs2 floating point register (double/even).
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        R       frs2 floating point register (quad/multiple of 4).
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        g       frsd floating point register.
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        H       frsd floating point register (double/even).
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        J       frsd floating point register (quad/multiple of 4).
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        b       crs1 coprocessor register
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        c       crs2 coprocessor register
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        D       crsd coprocessor register
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        m       alternate space register (asr) in rd
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        M       alternate space register (asr) in rs1
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        h       22 high bits.
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        X       5 bit unsigned immediate
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        Y       6 bit unsigned immediate
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        3       SIAM mode (3 bits). (v9b)
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        K       MEMBAR mask (7 bits). (v9)
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        j       10 bit Immediate. (v9)
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        I       11 bit Immediate. (v9)
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        i       13 bit Immediate.
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        n       22 bit immediate.
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        k       2+14 bit PC relative immediate. (v9)
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        G       19 bit PC relative immediate. (v9)
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        l       22 bit PC relative immediate.
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        L       30 bit PC relative immediate.
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        a       Annul.  The annul bit is set.
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        A       Alternate address space. Stored as 8 bits.
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        C       Coprocessor state register.
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        F       floating point state register.
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        p       Processor state register.
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        N       Branch predict clear ",pn" (v9)
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        T       Branch predict set ",pt" (v9)
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        z       %icc. (v9)
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        Z       %xcc. (v9)
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        q       Floating point queue.
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        r       Single register that is both rs1 and rd.
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        O       Single register that is both rs2 and rd.
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        Q       Coprocessor queue.
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        S       Special case.
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        t       Trap base register.
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        w       Window invalid mask register.
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        y       Y register.
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        u       sparclet coprocessor registers in rd position
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        U       sparclet coprocessor registers in rs1 position
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        E       %ccr. (v9)
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        s       %fprs. (v9)
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        P       %pc.  (v9)
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        W       %tick.  (v9)
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        o       %asi. (v9)
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        6       %fcc0. (v9)
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        7       %fcc1. (v9)
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        8       %fcc2. (v9)
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        9       %fcc3. (v9)
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        !       Privileged Register in rd (v9)
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        ?       Privileged Register in rs1 (v9)
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        *       Prefetch function constant. (v9)
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        x       OPF field (v9 impdep).
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        _       Ancillary state register in rd (v9a)
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        /       Ancillary state register in rs1 (v9a)
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  The following chars are unused: (note: ,[] are used as punctuation)
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  [45].  */
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#define OP2(x)          (((x) & 0x7) << 22)  /* Op2 field of format2 insns.  */
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#define OP3(x)          (((x) & 0x3f) << 19) /* Op3 field of format3 insns.  */
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#define OP(x)           ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns.  */
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#define OPF(x)          (((x) & 0x1ff) << 5) /* Opf field of float insns.  */
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#define OPF_LOW5(x)     OPF ((x) & 0x1f)     /* V9.  */
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#define F3F(x, y, z)    (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns.  */
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#define F3I(x)          (((x) & 0x1) << 13)  /* Immediate field of format 3 insns.  */
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#define F2(x, y)        (OP (x) | OP2(y))    /* Format 2 insns.  */
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#define F3(x, y, z)     (OP (x) | OP3(y) | F3I(z)) /* Format3 insns.  */
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#define F1(x)           (OP (x))
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#define DISP30(x)       ((x) & 0x3fffffff)
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#define ASI(x)          (((x) & 0xff) << 5)  /* Asi field of format3 insns.  */
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#define RS2(x)          ((x) & 0x1f)         /* Rs2 field.  */
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#define SIMM13(x)       ((x) & 0x1fff)       /* Simm13 field.  */
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#define RD(x)           (((x) & 0x1f) << 25) /* Destination register field.  */
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#define RS1(x)          (((x) & 0x1f) << 14) /* Rs1 field.  */
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#define ASI_RS2(x)      (SIMM13 (x))
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#define MEMBAR(x)       ((x) & 0x7f)
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#define SLCPOP(x)       (((x) & 0x7f) << 6)  /* Sparclet cpop.  */
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#define ANNUL   (1 << 29)
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#define BPRED   (1 << 19)       /* V9.  */
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#define IMMED   F3I (1)
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#define RD_G0   RD (~0)
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#define RS1_G0  RS1 (~0)
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#define RS2_G0  RS2 (~0)
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extern const struct sparc_opcode sparc_opcodes[];
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extern const int sparc_num_opcodes;
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extern int sparc_encode_asi (const char *);
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extern const char *sparc_decode_asi (int);
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extern int sparc_encode_membar (const char *);
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extern const char *sparc_decode_membar (int);
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extern int sparc_encode_prefetch (const char *);
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extern const char *sparc_decode_prefetch (int);
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extern int sparc_encode_sparclet_cpreg (const char *);
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extern const char *sparc_decode_sparclet_cpreg (int);
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/* Local Variables:
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   fill-column: 131
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   comment-column: 0
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   End: */
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