URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
145 |
khays |
MACHINE=
|
| 2 |
|
|
SCRIPT_NAME=elf
|
| 3 |
|
|
OUTPUT_FORMAT="elf32-littlearm"
|
| 4 |
|
|
BIG_OUTPUT_FORMAT="elf32-bigarm"
|
| 5 |
|
|
LITTLE_OUTPUT_FORMAT="elf32-littlearm"
|
| 6 |
|
|
TEXT_START_ADDR=0x8000
|
| 7 |
|
|
TEMPLATE_NAME=elf32
|
| 8 |
|
|
EXTRA_EM_FILE=armelf
|
| 9 |
|
|
OTHER_TEXT_SECTIONS='*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)'
|
| 10 |
|
|
OTHER_BSS_SYMBOLS='__bss_start__ = .;'
|
| 11 |
|
|
OTHER_BSS_END_SYMBOLS='_bss_end__ = . ; __bss_end__ = . ;'
|
| 12 |
|
|
OTHER_END_SYMBOLS='__end__ = . ;'
|
| 13 |
|
|
OTHER_SECTIONS='.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }'
|
| 14 |
|
|
ATTRS_SECTIONS='.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) KEEP (*(.gnu.attributes)) }'
|
| 15 |
|
|
OTHER_READONLY_SECTIONS="
|
| 16 |
|
|
.ARM.extab ${RELOCATING-0} : { *(.ARM.extab${RELOCATING+* .gnu.linkonce.armextab.*}) }
|
| 17 |
|
|
${RELOCATING+ PROVIDE_HIDDEN (__exidx_start = .); }
|
| 18 |
|
|
.ARM.exidx ${RELOCATING-0} : { *(.ARM.exidx${RELOCATING+* .gnu.linkonce.armexidx.*}) }
|
| 19 |
|
|
${RELOCATING+ PROVIDE_HIDDEN (__exidx_end = .); }"
|
| 20 |
|
|
|
| 21 |
|
|
DATA_START_SYMBOLS='__data_start = . ;';
|
| 22 |
|
|
|
| 23 |
|
|
GENERATE_SHLIB_SCRIPT=yes
|
| 24 |
|
|
|
| 25 |
|
|
ARCH=arm
|
| 26 |
|
|
MACHINE=
|
| 27 |
|
|
MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
|
| 28 |
|
|
ENTRY=_start
|
| 29 |
|
|
EMBEDDED=yes
|
| 30 |
|
|
|
| 31 |
|
|
# This sets the stack to the top of the simulator memory (2^19 bytes).
|
| 32 |
|
|
STACK_ADDR=0x80000
|
| 33 |
|
|
|
| 34 |
|
|
# ARM does not support .s* sections.
|
| 35 |
|
|
NO_SMALL_DATA=yes
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.