OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [ld/] [testsuite/] [ld-arm/] [arm-call.d] - Blame information for rev 41

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 33 khays 
 
2 
.*:     file format.*
3 
 
4 
Disassembly of section .text:
5 
 
6 
00008000 <_start>:
7 
    8000:       eb00000d        bl      803c
8 
    8004:       fa00000d        blx     8040
9 
    8008:       fb00000c        blx     8042
10 
    800c:       fb00000d        blx     804a
11 
    8010:       fa00000a        blx     8040
12 
    8014:       fb000009        blx     8042
13 
    8018:       ea000010        b       8060 <__t1_from_arm>
14 
    801c:       ea000011        b       8068 <__t2_from_arm>
15 
    8020:       1b00000e        blne    8060 <__t1_from_arm>
16 
    8024:       1b00000f        blne    8068 <__t2_from_arm>
17 
    8028:       1b000003        blne    803c
18 
    802c:       eb000002        bl      803c
19 
    8030:       faffffff        blx     8034
20 
 
21 
00008034 :
22 
    8034:       4770            bx      lr
23 
 
24 
00008036 :
25 
    8036:       4770            bx      lr
26 
 
27 
00008038 :
28 
    8038:       4770            bx      lr
29 
    803a:       46c0            nop                     ; \(mov r8, r8\)
30 
 
31 
0000803c :
32 
    803c:       e12fff1e        bx      lr
33 
 
34 
00008040 :
35 
    8040:       4770            bx      lr
36 
 
37 
00008042 :
38 
    8042:       f7ff fff8       bl      8036
39 
    8046:       f7ff fff7       bl      8038
40 
 
41 
0000804a :
42 
    804a:       f000 f801       bl      8050
43 
    804e:       46c0            nop                     ; \(mov r8, r8\)
44 
 
45 
00008050 :
46 
    8050:       f7ff fff1       bl      8036
47 
    8054:       f7ff efd4       blx     8000 <_start>
48 
    8058:       f7ff efd2       blx     8000 <_start>
49 
    805c:       0000            movs    r0, r0
50 
        ...
51 
 
52 
00008060 <__t1_from_arm>:
53 
    8060:       e51ff004        ldr     pc, \[pc, #-4\] ; 8064 <__t1_from_arm\+0x4>
54 
    8064:       00008041        .word   0x00008041
55 
 
56 
00008068 <__t2_from_arm>:
57 
    8068:       e51ff004        ldr     pc, \[pc, #-4\] ; 806c <__t2_from_arm\+0x4>
58 
    806c:       00008043        .word   0x00008043

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.