OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [ld/] [testsuite/] [ld-arm/] [mixed-app-v5.d] - Blame information for rev 60

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 33 khays
 
2
tmpdir/mixed-app-v5:     file format elf32-(little|big)arm
3
architecture: arm, flags 0x00000112:
4
EXEC_P, HAS_SYMS, D_PAGED
5
start address 0x.*
6
 
7
Disassembly of section .plt:
8
 
9
.* <.plt>:
10
 .*:    e52de004        push    {lr}            ; \(str lr, \[sp, #-4\]!\)
11
 .*:    e59fe004        ldr     lr, \[pc, #4\]  ; .* <_start-0x28>
12
 .*:    e08fe00e        add     lr, pc, lr
13
 .*:    e5bef008        ldr     pc, \[lr, #8\]!
14
 .*:    .*
15
 .*:    e28fc6.*        add     ip, pc, #.*
16
 .*:    e28cca.*        add     ip, ip, #.*     ; 0x.*
17
 .*:    e5bcf.*         ldr     pc, \[ip, #.*\]!.*
18
 .*:    e28fc6.*        add     ip, pc, #.*
19
 .*:    e28cca.*        add     ip, ip, #.*     ; 0x.*
20
 .*:    e5bcf.*         ldr     pc, \[ip, #.*\]!.*
21
Disassembly of section .text:
22
 
23
.* <_start>:
24
 .*:    e1a0c00d        mov     ip, sp
25
 .*:    e92dd800        push    {fp, ip, lr, pc}
26
 .*:    eb000004        bl      .* 
27
 .*:    e89d6800        ldm     sp, {fp, sp, lr}
28
 .*:    e12fff1e        bx      lr
29
 .*:    e1a00000        nop                     ; \(mov r0, r0\)
30
 .*:    e1a00000        nop                     ; \(mov r0, r0\)
31
 .*:    e1a00000        nop                     ; \(mov r0, r0\)
32
 
33
.* :
34
 .*:    e1a0c00d        mov     ip, sp
35
 .*:    e92dd800        push    {fp, ip, lr, pc}
36
 .*:    ebffffee        bl      .*
37
 .*:    e89d6800        ldm     sp, {fp, sp, lr}
38
 .*:    e12fff1e        bx      lr
39
 .*:    e1a00000        nop                     ; \(mov r0, r0\)
40
 .*:    e1a00000        nop                     ; \(mov r0, r0\)
41
 .*:    e1a00000        nop                     ; \(mov r0, r0\)
42
 
43
.* :
44
 .*:    e12fff1e        bx      lr
45
 .*:    e1a00000        nop                     ; \(mov r0, r0\)
46
 .*:    e1a00000        nop                     ; \(mov r0, r0\)
47
 .*:    e1a00000        nop                     ; \(mov r0, r0\)
48
 
49
.* :
50
 .*:    b500            push    {lr}
51
 .*:    f7ff efc.       blx     .* <_start-0x..>
52
 .*:    bd00            pop     {pc}
53
 .*:    4770            bx      lr
54
 .*:    46c0            nop                     ; \(mov r8, r8\)
55
 .*:    46c0            nop                     ; \(mov r8, r8\)
56
 .*:    46c0            nop                     ; \(mov r8, r8\)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.