URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [ld/] [testsuite/] [ld-arm/] [tls-descseq.d] - Blame information for rev 146

Line No.	Rev	Author	Line
1	33	khays
2			`tmpdir/tls-lib2inline.so: file format elf32-.*arm`
3			`architecture: arm, flags 0x[0-9a-f]+:`
4			`HAS_SYMS, DYNAMIC, D_PAGED`
5			`start address 0x[0-9a-f]+`
6
7			`Disassembly of section .plt:`
8
9			`[0-9a-f]+ <.plt>:`
10			`[0-9a-f]+: e52de004 push {lr} ; .*`
11			`[0-9a-f]+: e59fe004 ldr lr, \[pc, #4\] ; .*`
12			`[0-9a-f]+: e08fe00e add lr, pc, lr`
13			`[0-9a-f]+: e5bef008 ldr pc, \[lr, #8\]!`
14			`[0-9a-f]+: 000080e4 .word 0x000080e4`
15			`[0-9a-f]+: e08e0000 add r0, lr, r0`
16			`[0-9a-f]+: e5901004 ldr r1, \[r0, #4\]`
17			`[0-9a-f]+: e12fff11 bx r1`
18			`[0-9a-f]+: e52d2004 push {r2} ; .*`
19			`[0-9a-f]+: e59f200c ldr r2, \[pc, #12\] ; .*`
20			`[0-9a-f]+: e59f100c ldr r1, \[pc, #12\] ; .*`
21			`[0-9a-f]+: e79f2002 ldr r2, \[pc, r2\]`
22			`[0-9a-f]+: e081100f add r1, r1, pc`
23			`[0-9a-f]+: e12fff12 bx r2`
24			`[0-9a-f]+: 000080d4 .word 0x000080d4`
25			`[0-9a-f]+: 000080bc .word 0x000080bc`
26
27			`Disassembly of section .text:`
28
29			`[0-9a-f]+ :`
30			`[0-9a-f]+: e59f000c ldr r0, \[pc, #12\] ; .*`
31			`[0-9a-f]+: e08f0000 add r0, pc, r0`
32			`[0-9a-f]+: e5901004 ldr r1, \[r0, #4\]`
33			`[0-9a-f]+: e12fff31 blx r1`
34			`[0-9a-f]+: e1a00000 nop ; .*`
35			`[0-9a-f]+: 000080b4 .word 0x000080b4`
36
37			`[0-9a-f]+ :`
38			`[0-9a-f]+: 4802 ldr r0, \[pc, #8\] ; .*`
39			`[0-9a-f]+: 4478 add r0, pc`
40			`[0-9a-f]+: 6841 ldr r1, \[r0, #4\]`
41			`[0-9a-f]+: 4788 blx r1`
42			`[0-9a-f]+: 46c0 nop ; .*`
43			`[0-9a-f]+: 46c0 nop ; .*`
44			`[0-9a-f]+: 000080a2 .word 0x000080a2`