OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [ld/] [testsuite/] [ld-powerpc/] [tlsexe32.d] - Blame information for rev 95

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 95 khays
#source: tls32.s
2
#as: -a32
3
#ld: -melf32ppc tmpdir/libtlslib32.so
4
#objdump: -dr
5
#target: powerpc*-*-*
6
 
7
.*: +file format elf32-powerpc
8
 
9
Disassembly of section \.text:
10
 
11
.* <_start>:
12
.*:     80 7f ff f0     lwz     r3,-16\(r31\)
13
.*:     7c 63 12 14     add     r3,r3,r2
14
.*:     38 7f ff f4     addi    r3,r31,-12
15
.*:     48 01 01 85     bl      .*<__tls_get_addr_opt@plt>
16
.*:     3c 62 00 00     addis   r3,r2,0
17
.*:     38 63 90 1c     addi    r3,r3,-28644
18
.*:     3c 62 00 00     addis   r3,r2,0
19
.*:     38 63 10 00     addi    r3,r3,4096
20
.*:     39 23 80 20     addi    r9,r3,-32736
21
.*:     3d 23 00 00     addis   r9,r3,0
22
.*:     81 49 80 24     lwz     r10,-32732\(r9\)
23
.*:     3d 22 00 00     addis   r9,r2,0
24
.*:     a1 49 90 2c     lhz     r10,-28628\(r9\)
25
.*:     89 42 90 30     lbz     r10,-28624\(r2\)
26
.*:     3d 22 00 00     addis   r9,r2,0
27
.*:     99 49 90 34     stb     r10,-28620\(r9\)
28
.*:     3c 62 00 00     addis   r3,r2,0
29
.*:     38 63 90 00     addi    r3,r3,-28672
30
.*:     3c 62 00 00     addis   r3,r2,0
31
.*:     38 63 10 00     addi    r3,r3,4096
32
.*:     91 43 80 04     stw     r10,-32764\(r3\)
33
.*:     3d 23 00 00     addis   r9,r3,0
34
.*:     91 49 80 08     stw     r10,-32760\(r9\)
35
.*:     3d 22 00 00     addis   r9,r2,0
36
.*:     b1 49 90 2c     sth     r10,-28628\(r9\)
37
.*:     a1 42 90 14     lhz     r10,-28652\(r2\)
38
.*:     3d 22 00 00     addis   r9,r2,0
39
.*:     a9 49 90 18     lha     r10,-28648\(r9\)
40
Disassembly of section \.got:
41
 
42
.* <_GLOBAL_OFFSET_TABLE_-0x10>:
43
        \.\.\.
44
.*:     4e 80 00 21     blrl
45
 
46
.* <_GLOBAL_OFFSET_TABLE_>:
47
.*:     01 81 02 b8 00 00 00 00 00 00 00 00  .*

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.