OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [ld/] [testsuite/] [ld-powerpc/] [tlsopt4_32.d] - Blame information for rev 146

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 95 khays 
#source: tlsopt4_32.s
2 
#source: tlslib32.s
3 
#as: -a32
4 
#ld: -melf32ppc
5 
#objdump: -dr
6 
#target: powerpc*-*-*
7 
 
8 
.*: +file format elf32-powerpc
9 
 
10 
Disassembly of section \.text:
11 
 
12 
0+1800094 <__tls_get_addr>:
13 
 1800094:       4e 80 00 20     blr
14 
 
15 
Disassembly of section \.opt1:
16 
 
17 
0+1800098 <\.opt1>:
18 
 1800098:       3c 62 00 00     addis   r3,r2,0
19 
 180009c:       2c 04 00 00     cmpwi   r4,0
20 
 18000a0:       41 82 00 0c     beq-    .*
21 
 18000a4:       38 63 90 10     addi    r3,r3,-28656
22 
 18000a8:       48 00 00 08     b       .*
23 
 18000ac:       38 63 90 10     addi    r3,r3,-28656
24 
 
25 
Disassembly of section \.opt2:
26 
 
27 
0+18000b0 <\.opt2>:
28 
 18000b0:       3c 62 00 00     addis   r3,r2,0
29 
 18000b4:       2c 04 00 00     cmpwi   r4,0
30 
 18000b8:       41 82 00 08     beq-    .*
31 
 18000bc:       3c 62 00 00     addis   r3,r2,0
32 
 18000c0:       38 63 90 10     addi    r3,r3,-28656
33 
 
34 
Disassembly of section \.opt3:
35 
 
36 
0+18000c4 <\.opt3>:
37 
 18000c4:       3c 62 00 00     addis   r3,r2,0
38 
 18000c8:       48 00 00 0c     b       .*
39 
 18000cc:       3c 62 00 00     addis   r3,r2,0
40 
 18000d0:       48 00 00 0c     b       .*
41 
 18000d4:       38 63 90 10     addi    r3,r3,-28656
42 
 18000d8:       48 00 00 08     b       .*
43 
 18000dc:       38 63 90 08     addi    r3,r3,-28664
44 
#pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.