OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [ld/] [testsuite/] [ld-tic6x/] [shlib-noindex.dd] - Blame information for rev 117

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 117 khays 
 
2 
tmpdir/libtestn\.so:     file format elf32-tic6x-le
3 
 
4 
 
5 
Disassembly of section \.plt:
6 
 
7 
10000020 :
8 
10000020:       0100036e        ldw \.D2T2 \*\+b14\(12\),b2
9 
10000024:       0080046e        ldw \.D2T2 \*\+b14\(16\),b1
10 
10000028:       00004000        nop 3
11 
1000002c:       00080362        b \.S2 b2
12 
10000030:       00008000        nop 5
13 
10000034:       00000000        nop 1
14 
 
15 
10000038 :
16 
10000038:       0100056e        ldw \.D2T2 \*\+b14\(20\),b2
17 
1000003c:       0000002a        mvk \.S2 0,b0
18 
10000040:       0000006a        mvkh \.S2 0,b0
19 
10000044:       00002000        nop 2
20 
10000048:       00080362        b \.S2 b2
21 
1000004c:       00008000        nop 5
22 
 
23 
10000050 :
24 
10000050:       0100066e        ldw \.D2T2 \*\+b14\(24\),b2
25 
10000054:       0000062a        mvk \.S2 12,b0
26 
10000058:       0000006a        mvkh \.S2 0,b0
27 
1000005c:       00002000        nop 2
28 
10000060:       00080362        b \.S2 b2
29 
10000064:       00008000        nop 5
30 
        \.\.\.
31 
 
32 
Disassembly of section \.text:
33 
 
34 
10000080 :
35 
10000080:       000c0362        b \.S2 b3
36 
10000084:       00008000        nop 5
37 
 
38 
10000088 :
39 
10000088:       07be09c2        sub \.D2 b15,16,b15
40 
1000008c:       01bc62f6        stw \.D2T2 b3,\*\+b15\(12\)
41 
10000090:       073c82f6        stw \.D2T2 b14,\*\+b15\(16\)
42 
10000094:       0700006e        ldw \.D2T2 \*\+b14\(0\),b14
43 
10000098:       0ffffa12        b \.S2 10000050
44 
1000009c:       0ffff712        b \.S2 10000038
45 
100000a0:       0ffffc12        b \.S2 10000080
46 
100000a4:       01bc62e6        ldw \.D2T2 \*\+b15\(12\),b3
47 
100000a8:       073c82e6        ldw \.D2T2 \*\+b15\(16\),b14
48 
100000ac:       07800852        addk \.S2 16,b15
49 
100000b0:       00004000        nop 3
50 
100000b4:       000c0362        b \.S2 b3
51 
100000b8:       00008000        nop 5
52 
100000bc:       00000000        nop 1
53 
 
54 
100000c0 :
55 
100000c0:       07be09c2        sub \.D2 b15,16,b15
56 
100000c4:       023c62f4        stw \.D2T1 a4,\*\+b15\(12\)
57 
100000c8:       003c62e4        ldw \.D2T1 \*\+b15\(12\),a0
58 
100000cc:       00006000        nop 4
59 
100000d0:       00014940        add \.D1 a0,10,a0
60 
100000d4:       020008f0        or \.D1 0,a0,a4
61 
100000d8:       07be0942        add \.D2 b15,16,b15
62 
100000dc:       000c0362        b \.S2 b3
63 
100000e0:       0300096e        ldw \.D2T2 \*\+b14\(36\),b6
64 
100000e4:       0380076e        ldw \.D2T2 \*\+b14\(28\),b7
65 
100000e8:       0400086e        ldw \.D2T2 \*\+b14\(32\),b8
66 
100000ec:       04800c6e        ldw \.D2T2 \*\+b14\(48\),b9
67 
        \.\.\.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.