OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [opcodes/] [bfin-dis.c] - Blame information for rev 53

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 18 khays 
/* Disassemble ADI Blackfin Instructions.
2 
   Copyright 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 
   Free Software Foundation, Inc.
4 
 
5 
   This file is part of libopcodes.
6 
 
7 
   This library is free software; you can redistribute it and/or modify
8 
   it under the terms of the GNU General Public License as published by
9 
   the Free Software Foundation; either version 3, or (at your option)
10 
   any later version.
11 
 
12 
   It is distributed in the hope that it will be useful, but WITHOUT
13 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15 
   License for more details.
16 
 
17 
   You should have received a copy of the GNU General Public License
18 
   along with this program; if not, write to the Free Software
19 
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 
   MA 02110-1301, USA.  */
21 
 
22 
#include <stdio.h>
23 
#include <stdlib.h>
24 
#include <string.h>
25 
 
26 
#include "opcode/bfin.h"
27 
 
28 
#ifndef PRINTF
29 
#define PRINTF printf
30 
#endif
31 
 
32 
#ifndef EXIT
33 
#define EXIT exit
34 
#endif
35 
 
36 
typedef long TIword;
37 
 
38 
#define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
39 
#define XFIELD(w,p,s)       (((w) & ((1 << (s)) - 1) << (p)) >> (p))
40 
#define SIGNEXTEND(v, n)    ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
41 
#define MASKBITS(val, bits) (val & ((1 << bits) - 1))
42 
 
43 
#include "dis-asm.h"
44 
 
45 
typedef unsigned int bu32;
46 
 
47 
static char comment = 0;
48 
static char parallel = 0;
49 
 
50 
typedef enum
51 
{
52 
  c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
53 
  c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
54 
  c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
55 
  c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
56 
  c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
57 
} const_forms_t;
58 
 
59 
static const struct
60 
{
61 
  const char *name;
62 
  const int nbits;
63 
  const char reloc;
64 
  const char issigned;
65 
  const char pcrel;
66 
  const char scale;
67 
  const char offset;
68 
  const char negative;
69 
  const char positive;
70 
  const char decimal;
71 
  const char leading;
72 
  const char exact;
73 
} constant_formats[] =
74 
{
75 
  { "0",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
76 
  { "1",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
77 
  { "4",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
78 
  { "2",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
79 
  { "uimm2",      2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
80 
  { "uimm3",      3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
81 
  { "imm3",       3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
82 
  { "pcrel4",     4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
83 
  { "imm4",       4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
84 
  { "uimm4s4",    4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
85 
  { "uimm4s4d",   4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
86 
  { "uimm4",      4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
87 
  { "uimm4s2",    4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
88 
  { "negimm5s4",  5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
89 
  { "imm5",       5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
90 
  { "imm5d",      5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
91 
  { "uimm5",      5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
92 
  { "imm6",       6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 
  { "imm7",       7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
94 
  { "imm7d",      7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
95 
  { "imm8",       8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
96 
  { "uimm8",      8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
97 
  { "pcrel8",     8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
98 
  { "uimm8s4",    8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
99 
  { "pcrel8s4",   8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
100 
  { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
101 
  { "pcrel10",   10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
102 
  { "pcrel12",   12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
103 
  { "imm16s4",   16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
104 
  { "luimm16",   16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
105 
  { "imm16",     16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
106 
  { "imm16d",    16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
107 
  { "huimm16",   16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
108 
  { "rimm16",    16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
109 
  { "imm16s2",   16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
110 
  { "uimm16s4",  16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
111 
  { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
112 
  { "uimm16",    16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
113 
  { "pcrel24",   24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
114 
  { "uimm32",    32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
115 
  { "imm32",     32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 
  { "huimm32",   32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 
  { "huimm32e",  32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
118 
};
119 
 
120 
static const char *
121 
fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
122 
{
123 
  static char buf[60];
124 
 
125 
  if (constant_formats[cf].reloc)
126 
    {
127 
      bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
128 
                      : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
129 
      if (constant_formats[cf].pcrel)
130 
        ea += pc;
131 
 
132 
      /* truncate to 32-bits for proper symbol lookup/matching */
133 
      ea = (bu32)ea;
134 
 
135 
      if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
136 
        {
137 
          outf->print_address_func (ea, outf);
138 
          return "";
139 
        }
140 
      else
141 
        {
142 
          sprintf (buf, "%lx", (unsigned long) x);
143 
          return buf;
144 
        }
145 
    }
146 
 
147 
  /* Negative constants have an implied sign bit.  */
148 
  if (constant_formats[cf].negative)
149 
    {
150 
      int nb = constant_formats[cf].nbits + 1;
151 
 
152 
      x = x | (1 << constant_formats[cf].nbits);
153 
      x = SIGNEXTEND (x, nb);
154 
    }
155 
  else
156 
    x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
157 
 
158 
  if (constant_formats[cf].offset)
159 
    x += constant_formats[cf].offset;
160 
 
161 
  if (constant_formats[cf].scale)
162 
    x <<= constant_formats[cf].scale;
163 
 
164 
  if (constant_formats[cf].decimal)
165 
    {
166 
      if (constant_formats[cf].leading)
167 
        {
168 
          char ps[10];
169 
          sprintf (ps, "%%%ii", constant_formats[cf].leading);
170 
          sprintf (buf, ps, x);
171 
        }
172 
      else
173 
        sprintf (buf, "%li", x);
174 
    }
175 
  else
176 
    {
177 
      if (constant_formats[cf].issigned && x < 0)
178 
        sprintf (buf, "-0x%x", abs (x));
179 
      else
180 
        sprintf (buf, "0x%lx", (unsigned long) x);
181 
    }
182 
 
183 
  return buf;
184 
}
185 
 
186 
static bu32
187 
fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
188 
{
189 
  if (0 && constant_formats[cf].reloc)
190 
    {
191 
      bu32 ea = (((constant_formats[cf].pcrel
192 
                   ? SIGNEXTEND (x, constant_formats[cf].nbits)
193 
                   : x) + constant_formats[cf].offset)
194 
                 << constant_formats[cf].scale);
195 
      if (constant_formats[cf].pcrel)
196 
        ea += pc;
197 
 
198 
      return ea;
199 
    }
200 
 
201 
  /* Negative constants have an implied sign bit.  */
202 
  if (constant_formats[cf].negative)
203 
    {
204 
      int nb = constant_formats[cf].nbits + 1;
205 
      x = x | (1 << constant_formats[cf].nbits);
206 
      x = SIGNEXTEND (x, nb);
207 
    }
208 
  else if (constant_formats[cf].issigned)
209 
    x = SIGNEXTEND (x, constant_formats[cf].nbits);
210 
 
211 
  x += constant_formats[cf].offset;
212 
  x <<= constant_formats[cf].scale;
213 
 
214 
  return x;
215 
}
216 
 
217 
enum machine_registers
218 
{
219 
  REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
220 
  REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
221 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
222 
  REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
223 
  REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
224 
  REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
225 
  REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
226 
  REG_L2, REG_L3,
227 
  REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
228 
  REG_AQ, REG_V, REG_VS,
229 
  REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
230 
  REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
231 
  REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
232 
  REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
233 
  REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
234 
  REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
235 
  REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
236 
  REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
237 
  REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
238 
  REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
239 
  REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
240 
  REG_LASTREG,
241 
};
242 
 
243 
enum reg_class
244 
{
245 
  rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
246 
  rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
247 
  rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
248 
  rc_sysregs3, rc_allregs,
249 
  LIM_REG_CLASSES
250 
};
251 
 
252 
static const char * const reg_names[] =
253 
{
254 
  "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
255 
  "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
256 
  "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
257 
  "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
258 
  "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
259 
  "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
260 
  "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
261 
  "L2", "L3",
262 
  "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
263 
  "AQ", "V", "VS",
264 
  "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
265 
  "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
266 
  "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
267 
  "RETE", "EMUDAT",
268 
  "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
269 
  "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
270 
  "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
271 
  "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
272 
  "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
273 
  "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
274 
  "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
275 
  "AC0_COPY", "V_COPY", "RND_MOD",
276 
  "LASTREG",
277 
 
278 
};
279 
 
280 
#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
281 
 
282 
/* RL(0..7).  */
283 
static const enum machine_registers decode_dregs_lo[] =
284 
{
285 
  REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
286 
};
287 
 
288 
#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
289 
 
290 
/* RH(0..7).  */
291 
static const enum machine_registers decode_dregs_hi[] =
292 
{
293 
  REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
294 
};
295 
 
296 
#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
297 
 
298 
/* R(0..7).  */
299 
static const enum machine_registers decode_dregs[] =
300 
{
301 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
302 
};
303 
 
304 
#define dregs(x) REGNAME (decode_dregs[(x) & 7])
305 
 
306 
/* R BYTE(0..7).  */
307 
static const enum machine_registers decode_dregs_byte[] =
308 
{
309 
  REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
310 
};
311 
 
312 
#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
313 
 
314 
/* P(0..5) SP FP.  */
315 
static const enum machine_registers decode_pregs[] =
316 
{
317 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
318 
};
319 
 
320 
#define pregs(x)        REGNAME (decode_pregs[(x) & 7])
321 
#define spfp(x)         REGNAME (decode_spfp[(x) & 1])
322 
#define dregs_hilo(x, i)        REGNAME (decode_dregs_hilo[((i) << 3) | (x)])
323 
#define accum_ext(x)    REGNAME (decode_accum_ext[(x) & 1])
324 
#define accum_word(x)   REGNAME (decode_accum_word[(x) & 1])
325 
#define accum(x)        REGNAME (decode_accum[(x) & 1])
326 
 
327 
/* I(0..3).  */
328 
static const enum machine_registers decode_iregs[] =
329 
{
330 
  REG_I0, REG_I1, REG_I2, REG_I3,
331 
};
332 
 
333 
#define iregs(x) REGNAME (decode_iregs[(x) & 3])
334 
 
335 
/* M(0..3).  */
336 
static const enum machine_registers decode_mregs[] =
337 
{
338 
  REG_M0, REG_M1, REG_M2, REG_M3,
339 
};
340 
 
341 
#define mregs(x) REGNAME (decode_mregs[(x) & 3])
342 
#define bregs(x) REGNAME (decode_bregs[(x) & 3])
343 
#define lregs(x) REGNAME (decode_lregs[(x) & 3])
344 
 
345 
/* dregs pregs.  */
346 
static const enum machine_registers decode_dpregs[] =
347 
{
348 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
349 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
350 
};
351 
 
352 
#define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
353 
 
354 
/* [dregs pregs].  */
355 
static const enum machine_registers decode_gregs[] =
356 
{
357 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
358 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
359 
};
360 
 
361 
#define gregs(x, i) REGNAME (decode_gregs[((i) << 3) | (x)])
362 
 
363 
/* [dregs pregs (iregs mregs) (bregs lregs)].  */
364 
static const enum machine_registers decode_regs[] =
365 
{
366 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
367 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
368 
  REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
369 
  REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
370 
};
371 
 
372 
#define regs(x, i) REGNAME (decode_regs[((i) << 3) | (x)])
373 
 
374 
/* [dregs pregs (iregs mregs) (bregs lregs) Low Half].  */
375 
static const enum machine_registers decode_regs_lo[] =
376 
{
377 
  REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
378 
  REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
379 
  REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
380 
  REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
381 
};
382 
 
383 
#define regs_lo(x, i) REGNAME (decode_regs_lo[((i) << 3) | (x)])
384 
 
385 
/* [dregs pregs (iregs mregs) (bregs lregs) High Half].  */
386 
static const enum machine_registers decode_regs_hi[] =
387 
{
388 
  REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
389 
  REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
390 
  REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
391 
  REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
392 
};
393 
 
394 
#define regs_hi(x, i) REGNAME (decode_regs_hi[((i) << 3) | (x)])
395 
 
396 
static const enum machine_registers decode_statbits[] =
397 
{
398 
  REG_AZ,        REG_AN,        REG_AC0_COPY,    REG_V_COPY,
399 
  REG_LASTREG,   REG_LASTREG,   REG_AQ,          REG_LASTREG,
400 
  REG_RND_MOD,   REG_LASTREG,   REG_LASTREG,     REG_LASTREG,
401 
  REG_AC0,       REG_AC1,       REG_LASTREG,     REG_LASTREG,
402 
  REG_AV0,       REG_AV0S,      REG_AV1,         REG_AV1S,
403 
  REG_LASTREG,   REG_LASTREG,   REG_LASTREG,     REG_LASTREG,
404 
  REG_V,         REG_VS,        REG_LASTREG,     REG_LASTREG,
405 
  REG_LASTREG,   REG_LASTREG,   REG_LASTREG,     REG_LASTREG,
406 
};
407 
 
408 
#define statbits(x) REGNAME (decode_statbits[(x) & 31])
409 
 
410 
/* LC0 LC1.  */
411 
static const enum machine_registers decode_counters[] =
412 
{
413 
  REG_LC0, REG_LC1,
414 
};
415 
 
416 
#define counters(x)        REGNAME (decode_counters[(x) & 1])
417 
#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
418 
 
419 
/* [dregs pregs (iregs mregs) (bregs lregs)
420 
   dregs2_sysregs1 open sysregs2 sysregs3].  */
421 
static const enum machine_registers decode_allregs[] =
422 
{
423 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
424 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
425 
  REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
426 
  REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
427 
  REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
428 
  REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
429 
  REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
430 
  REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
431 
  REG_LASTREG,
432 
};
433 
 
434 
#define IS_DREG(g,r)    ((g) == 0 && (r) < 8)
435 
#define IS_PREG(g,r)    ((g) == 1 && (r) < 8)
436 
#define IS_AREG(g,r)    ((g) == 4 && (r) >= 0 && (r) < 4)
437 
#define IS_GENREG(g,r)  ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
438 
#define IS_DAGREG(g,r)  (((g) == 2 || (g) == 3) && (r) < 8)
439 
#define IS_SYSREG(g,r) \
440 
  (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
441 
#define IS_RESERVEDREG(g,r) \
442 
  (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
443 
 
444 
#define allreg(r,g)     (!IS_RESERVEDREG (g, r))
445 
#define mostreg(r,g)    (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
446 
 
447 
#define allregs(x, i)   REGNAME (decode_allregs[((i) << 3) | (x)])
448 
#define uimm16s4(x)     fmtconst (c_uimm16s4, x, 0, outf)
449 
#define uimm16s4d(x)    fmtconst (c_uimm16s4d, x, 0, outf)
450 
#define pcrel4(x)       fmtconst (c_pcrel4, x, pc, outf)
451 
#define pcrel8(x)       fmtconst (c_pcrel8, x, pc, outf)
452 
#define pcrel8s4(x)     fmtconst (c_pcrel8s4, x, pc, outf)
453 
#define pcrel10(x)      fmtconst (c_pcrel10, x, pc, outf)
454 
#define pcrel12(x)      fmtconst (c_pcrel12, x, pc, outf)
455 
#define negimm5s4(x)    fmtconst (c_negimm5s4, x, 0, outf)
456 
#define rimm16(x)       fmtconst (c_rimm16, x, 0, outf)
457 
#define huimm16(x)      fmtconst (c_huimm16, x, 0, outf)
458 
#define imm16(x)        fmtconst (c_imm16, x, 0, outf)
459 
#define imm16d(x)       fmtconst (c_imm16d, x, 0, outf)
460 
#define uimm2(x)        fmtconst (c_uimm2, x, 0, outf)
461 
#define uimm3(x)        fmtconst (c_uimm3, x, 0, outf)
462 
#define luimm16(x)      fmtconst (c_luimm16, x, 0, outf)
463 
#define uimm4(x)        fmtconst (c_uimm4, x, 0, outf)
464 
#define uimm5(x)        fmtconst (c_uimm5, x, 0, outf)
465 
#define imm16s2(x)      fmtconst (c_imm16s2, x, 0, outf)
466 
#define uimm8(x)        fmtconst (c_uimm8, x, 0, outf)
467 
#define imm16s4(x)      fmtconst (c_imm16s4, x, 0, outf)
468 
#define uimm4s2(x)      fmtconst (c_uimm4s2, x, 0, outf)
469 
#define uimm4s4(x)      fmtconst (c_uimm4s4, x, 0, outf)
470 
#define uimm4s4d(x)     fmtconst (c_uimm4s4d, x, 0, outf)
471 
#define lppcrel10(x)    fmtconst (c_lppcrel10, x, pc, outf)
472 
#define imm3(x)         fmtconst (c_imm3, x, 0, outf)
473 
#define imm4(x)         fmtconst (c_imm4, x, 0, outf)
474 
#define uimm8s4(x)      fmtconst (c_uimm8s4, x, 0, outf)
475 
#define imm5(x)         fmtconst (c_imm5, x, 0, outf)
476 
#define imm5d(x)        fmtconst (c_imm5d, x, 0, outf)
477 
#define imm6(x)         fmtconst (c_imm6, x, 0, outf)
478 
#define imm7(x)         fmtconst (c_imm7, x, 0, outf)
479 
#define imm7d(x)        fmtconst (c_imm7d, x, 0, outf)
480 
#define imm8(x)         fmtconst (c_imm8, x, 0, outf)
481 
#define pcrel24(x)      fmtconst (c_pcrel24, x, pc, outf)
482 
#define uimm16(x)       fmtconst (c_uimm16, x, 0, outf)
483 
#define uimm32(x)       fmtconst (c_uimm32, x, 0, outf)
484 
#define imm32(x)        fmtconst (c_imm32, x, 0, outf)
485 
#define huimm32(x)      fmtconst (c_huimm32, x, 0, outf)
486 
#define huimm32e(x)     fmtconst (c_huimm32e, x, 0, outf)
487 
#define imm7_val(x)     fmtconst_val (c_imm7, x, 0)
488 
#define imm16_val(x)    fmtconst_val (c_uimm16, x, 0)
489 
#define luimm16_val(x)  fmtconst_val (c_luimm16, x, 0)
490 
 
491 
/* (arch.pm)arch_disassembler_functions.  */
492 
#ifndef OUTS
493 
#define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt)
494 
#endif
495 
 
496 
static void
497 
amod0 (int s0, int x0, disassemble_info *outf)
498 
{
499 
  if (s0 == 1 && x0 == 0)
500 
    OUTS (outf, " (S)");
501 
  else if (s0 == 0 && x0 == 1)
502 
    OUTS (outf, " (CO)");
503 
  else if (s0 == 1 && x0 == 1)
504 
    OUTS (outf, " (SCO)");
505 
}
506 
 
507 
static void
508 
amod1 (int s0, int x0, disassemble_info *outf)
509 
{
510 
  if (s0 == 0 && x0 == 0)
511 
    OUTS (outf, " (NS)");
512 
  else if (s0 == 1 && x0 == 0)
513 
    OUTS (outf, " (S)");
514 
}
515 
 
516 
static void
517 
amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
518 
{
519 
  if (s0 == 1 && x0 == 0 && aop0 == 0)
520 
    OUTS (outf, " (S)");
521 
  else if (s0 == 0 && x0 == 1 && aop0 == 0)
522 
    OUTS (outf, " (CO)");
523 
  else if (s0 == 1 && x0 == 1 && aop0 == 0)
524 
    OUTS (outf, " (SCO)");
525 
  else if (s0 == 0 && x0 == 0 && aop0 == 2)
526 
    OUTS (outf, " (ASR)");
527 
  else if (s0 == 1 && x0 == 0 && aop0 == 2)
528 
    OUTS (outf, " (S, ASR)");
529 
  else if (s0 == 0 && x0 == 1 && aop0 == 2)
530 
    OUTS (outf, " (CO, ASR)");
531 
  else if (s0 == 1 && x0 == 1 && aop0 == 2)
532 
    OUTS (outf, " (SCO, ASR)");
533 
  else if (s0 == 0 && x0 == 0 && aop0 == 3)
534 
    OUTS (outf, " (ASL)");
535 
  else if (s0 == 1 && x0 == 0 && aop0 == 3)
536 
    OUTS (outf, " (S, ASL)");
537 
  else if (s0 == 0 && x0 == 1 && aop0 == 3)
538 
    OUTS (outf, " (CO, ASL)");
539 
  else if (s0 == 1 && x0 == 1 && aop0 == 3)
540 
    OUTS (outf, " (SCO, ASL)");
541 
}
542 
 
543 
static void
544 
searchmod (int r0, disassemble_info *outf)
545 
{
546 
  if (r0 == 0)
547 
    OUTS (outf, "GT");
548 
  else if (r0 == 1)
549 
    OUTS (outf, "GE");
550 
  else if (r0 == 2)
551 
    OUTS (outf, "LT");
552 
  else if (r0 == 3)
553 
    OUTS (outf, "LE");
554 
}
555 
 
556 
static void
557 
aligndir (int r0, disassemble_info *outf)
558 
{
559 
  if (r0 == 1)
560 
    OUTS (outf, " (R)");
561 
}
562 
 
563 
static int
564 
decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
565 
{
566 
  const char *s0, *s1;
567 
 
568 
  if (h0)
569 
    s0 = dregs_hi (src0);
570 
  else
571 
    s0 = dregs_lo (src0);
572 
 
573 
  if (h1)
574 
    s1 = dregs_hi (src1);
575 
  else
576 
    s1 = dregs_lo (src1);
577 
 
578 
  OUTS (outf, s0);
579 
  OUTS (outf, " * ");
580 
  OUTS (outf, s1);
581 
  return 0;
582 
}
583 
 
584 
static int
585 
decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
586 
{
587 
  const char *a;
588 
  const char *sop = "<unknown op>";
589 
 
590 
  if (which)
591 
    a = "A1";
592 
  else
593 
    a = "A0";
594 
 
595 
  if (op == 3)
596 
    {
597 
      OUTS (outf, a);
598 
      return 0;
599 
    }
600 
 
601 
  switch (op)
602 
    {
603 
    case 0: sop = " = ";   break;
604 
    case 1: sop = " += ";  break;
605 
    case 2: sop = " -= ";  break;
606 
    default: break;
607 
    }
608 
 
609 
  OUTS (outf, a);
610 
  OUTS (outf, sop);
611 
  decode_multfunc (h0, h1, src0, src1, outf);
612 
 
613 
  return 0;
614 
}
615 
 
616 
static void
617 
decode_optmode (int mod, int MM, disassemble_info *outf)
618 
{
619 
  if (mod == 0 && MM == 0)
620 
    return;
621 
 
622 
  OUTS (outf, " (");
623 
 
624 
  if (MM && !mod)
625 
    {
626 
      OUTS (outf, "M)");
627 
      return;
628 
    }
629 
 
630 
  if (MM)
631 
    OUTS (outf, "M, ");
632 
 
633 
  if (mod == M_S2RND)
634 
    OUTS (outf, "S2RND");
635 
  else if (mod == M_T)
636 
    OUTS (outf, "T");
637 
  else if (mod == M_W32)
638 
    OUTS (outf, "W32");
639 
  else if (mod == M_FU)
640 
    OUTS (outf, "FU");
641 
  else if (mod == M_TFU)
642 
    OUTS (outf, "TFU");
643 
  else if (mod == M_IS)
644 
    OUTS (outf, "IS");
645 
  else if (mod == M_ISS2)
646 
    OUTS (outf, "ISS2");
647 
  else if (mod == M_IH)
648 
    OUTS (outf, "IH");
649 
  else if (mod == M_IU)
650 
    OUTS (outf, "IU");
651 
  else
652 
    abort ();
653 
 
654 
  OUTS (outf, ")");
655 
}
656 
 
657 
static struct saved_state
658 
{
659 
  bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
660 
  bu32 ax[2], aw[2];
661 
  bu32 lt[2], lc[2], lb[2];
662 
  bu32 rets;
663 
} saved_state;
664 
 
665 
#define DREG(x)         (saved_state.dpregs[x])
666 
#define GREG(x, i)      DPREG ((x) | ((i) << 3))
667 
#define DPREG(x)        (saved_state.dpregs[x])
668 
#define DREG(x)         (saved_state.dpregs[x])
669 
#define PREG(x)         (saved_state.dpregs[(x) + 8])
670 
#define SPREG           PREG (6)
671 
#define FPREG           PREG (7)
672 
#define IREG(x)         (saved_state.iregs[x])
673 
#define MREG(x)         (saved_state.mregs[x])
674 
#define BREG(x)         (saved_state.bregs[x])
675 
#define LREG(x)         (saved_state.lregs[x])
676 
#define AXREG(x)        (saved_state.ax[x])
677 
#define AWREG(x)        (saved_state.aw[x])
678 
#define LCREG(x)        (saved_state.lc[x])
679 
#define LTREG(x)        (saved_state.lt[x])
680 
#define LBREG(x)        (saved_state.lb[x])
681 
#define RETSREG         (saved_state.rets)
682 
 
683 
static bu32 *
684 
get_allreg (int grp, int reg)
685 
{
686 
  int fullreg = (grp << 3) | reg;
687 
  /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
688 
     REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
689 
     REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
690 
     REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
691 
     REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
692 
     , , , , , , , ,
693 
     REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
694 
     REG_CYCLES2,
695 
     REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
696 
     REG_LASTREG */
697 
  switch (fullreg >> 2)
698 
    {
699 
    case 0: case 1: return &DREG (reg);
700 
    case 2: case 3: return &PREG (reg);
701 
    case 4: return &IREG (reg & 3);
702 
    case 5: return &MREG (reg & 3);
703 
    case 6: return &BREG (reg & 3);
704 
    case 7: return &LREG (reg & 3);
705 
    default:
706 
      switch (fullreg)
707 
        {
708 
        case 32: return &AXREG (0);
709 
        case 33: return &AWREG (0);
710 
        case 34: return &AXREG (1);
711 
        case 35: return &AWREG (1);
712 
        case 39: return &RETSREG;
713 
        case 48: return &LCREG (0);
714 
        case 49: return &LTREG (0);
715 
        case 50: return &LBREG (0);
716 
        case 51: return &LCREG (1);
717 
        case 52: return &LTREG (1);
718 
        case 53: return &LBREG (1);
719 
        }
720 
    }
721 
  abort ();
722 
}
723 
 
724 
static int
725 
decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
726 
{
727 
  /* ProgCtrl
728 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
729 
     | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
730 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
731 
  int poprnd  = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
732 
  int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
733 
 
734 
  if (prgfunc == 0 && poprnd == 0)
735 
    OUTS (outf, "NOP");
736 
  else if (parallel)
737 
    return 0;
738 
  else if (prgfunc == 1 && poprnd == 0)
739 
    OUTS (outf, "RTS");
740 
  else if (prgfunc == 1 && poprnd == 1)
741 
    OUTS (outf, "RTI");
742 
  else if (prgfunc == 1 && poprnd == 2)
743 
    OUTS (outf, "RTX");
744 
  else if (prgfunc == 1 && poprnd == 3)
745 
    OUTS (outf, "RTN");
746 
  else if (prgfunc == 1 && poprnd == 4)
747 
    OUTS (outf, "RTE");
748 
  else if (prgfunc == 2 && poprnd == 0)
749 
    OUTS (outf, "IDLE");
750 
  else if (prgfunc == 2 && poprnd == 3)
751 
    OUTS (outf, "CSYNC");
752 
  else if (prgfunc == 2 && poprnd == 4)
753 
    OUTS (outf, "SSYNC");
754 
  else if (prgfunc == 2 && poprnd == 5)
755 
    OUTS (outf, "EMUEXCPT");
756 
  else if (prgfunc == 3 && IS_DREG (0, poprnd))
757 
    {
758 
      OUTS (outf, "CLI ");
759 
      OUTS (outf, dregs (poprnd));
760 
    }
761 
  else if (prgfunc == 4 && IS_DREG (0, poprnd))
762 
    {
763 
      OUTS (outf, "STI ");
764 
      OUTS (outf, dregs (poprnd));
765 
    }
766 
  else if (prgfunc == 5 && IS_PREG (1, poprnd))
767 
    {
768 
      OUTS (outf, "JUMP (");
769 
      OUTS (outf, pregs (poprnd));
770 
      OUTS (outf, ")");
771 
    }
772 
  else if (prgfunc == 6 && IS_PREG (1, poprnd))
773 
    {
774 
      OUTS (outf, "CALL (");
775 
      OUTS (outf, pregs (poprnd));
776 
      OUTS (outf, ")");
777 
    }
778 
  else if (prgfunc == 7 && IS_PREG (1, poprnd))
779 
    {
780 
      OUTS (outf, "CALL (PC + ");
781 
      OUTS (outf, pregs (poprnd));
782 
      OUTS (outf, ")");
783 
    }
784 
  else if (prgfunc == 8 && IS_PREG (1, poprnd))
785 
    {
786 
      OUTS (outf, "JUMP (PC + ");
787 
      OUTS (outf, pregs (poprnd));
788 
      OUTS (outf, ")");
789 
    }
790 
  else if (prgfunc == 9)
791 
    {
792 
      OUTS (outf, "RAISE ");
793 
      OUTS (outf, uimm4 (poprnd));
794 
    }
795 
  else if (prgfunc == 10)
796 
    {
797 
      OUTS (outf, "EXCPT ");
798 
      OUTS (outf, uimm4 (poprnd));
799 
    }
800 
  else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
801 
    {
802 
      OUTS (outf, "TESTSET (");
803 
      OUTS (outf, pregs (poprnd));
804 
      OUTS (outf, ")");
805 
    }
806 
  else
807 
    return 0;
808 
  return 2;
809 
}
810 
 
811 
static int
812 
decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
813 
{
814 
  /* CaCTRL
815 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
816 
     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
817 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
818 
  int a   = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
819 
  int op  = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
820 
  int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
821 
 
822 
  if (parallel)
823 
    return 0;
824 
 
825 
  if (a == 0 && op == 0)
826 
    {
827 
      OUTS (outf, "PREFETCH[");
828 
      OUTS (outf, pregs (reg));
829 
      OUTS (outf, "]");
830 
    }
831 
  else if (a == 0 && op == 1)
832 
    {
833 
      OUTS (outf, "FLUSHINV[");
834 
      OUTS (outf, pregs (reg));
835 
      OUTS (outf, "]");
836 
    }
837 
  else if (a == 0 && op == 2)
838 
    {
839 
      OUTS (outf, "FLUSH[");
840 
      OUTS (outf, pregs (reg));
841 
      OUTS (outf, "]");
842 
    }
843 
  else if (a == 0 && op == 3)
844 
    {
845 
      OUTS (outf, "IFLUSH[");
846 
      OUTS (outf, pregs (reg));
847 
      OUTS (outf, "]");
848 
    }
849 
  else if (a == 1 && op == 0)
850 
    {
851 
      OUTS (outf, "PREFETCH[");
852 
      OUTS (outf, pregs (reg));
853 
      OUTS (outf, "++]");
854 
    }
855 
  else if (a == 1 && op == 1)
856 
    {
857 
      OUTS (outf, "FLUSHINV[");
858 
      OUTS (outf, pregs (reg));
859 
      OUTS (outf, "++]");
860 
    }
861 
  else if (a == 1 && op == 2)
862 
    {
863 
      OUTS (outf, "FLUSH[");
864 
      OUTS (outf, pregs (reg));
865 
      OUTS (outf, "++]");
866 
    }
867 
  else if (a == 1 && op == 3)
868 
    {
869 
      OUTS (outf, "IFLUSH[");
870 
      OUTS (outf, pregs (reg));
871 
      OUTS (outf, "++]");
872 
    }
873 
  else
874 
    return 0;
875 
  return 2;
876 
}
877 
 
878 
static int
879 
decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
880 
{
881 
  /* PushPopReg
882 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
883 
     | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
884 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
885 
  int W   = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
886 
  int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
887 
  int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
888 
 
889 
  if (parallel)
890 
    return 0;
891 
 
892 
  if (W == 0 && mostreg (reg, grp))
893 
    {
894 
      OUTS (outf, allregs (reg, grp));
895 
      OUTS (outf, " = [SP++]");
896 
    }
897 
  else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
898 
    {
899 
      OUTS (outf, "[--SP] = ");
900 
      OUTS (outf, allregs (reg, grp));
901 
    }
902 
  else
903 
    return 0;
904 
  return 2;
905 
}
906 
 
907 
static int
908 
decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
909 
{
910 
  /* PushPopMultiple
911 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
912 
     | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
913 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
914 
  int p  = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
915 
  int d  = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
916 
  int W  = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
917 
  int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
918 
  int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
919 
 
920 
  if (parallel)
921 
    return 0;
922 
 
923 
  if (pr > 5)
924 
    return 0;
925 
 
926 
  if (W == 1 && d == 1 && p == 1)
927 
    {
928 
      OUTS (outf, "[--SP] = (R7:");
929 
      OUTS (outf, imm5d (dr));
930 
      OUTS (outf, ", P5:");
931 
      OUTS (outf, imm5d (pr));
932 
      OUTS (outf, ")");
933 
    }
934 
  else if (W == 1 && d == 1 && p == 0 && pr == 0)
935 
    {
936 
      OUTS (outf, "[--SP] = (R7:");
937 
      OUTS (outf, imm5d (dr));
938 
      OUTS (outf, ")");
939 
    }
940 
  else if (W == 1 && d == 0 && p == 1 && dr == 0)
941 
    {
942 
      OUTS (outf, "[--SP] = (P5:");
943 
      OUTS (outf, imm5d (pr));
944 
      OUTS (outf, ")");
945 
    }
946 
  else if (W == 0 && d == 1 && p == 1)
947 
    {
948 
      OUTS (outf, "(R7:");
949 
      OUTS (outf, imm5d (dr));
950 
      OUTS (outf, ", P5:");
951 
      OUTS (outf, imm5d (pr));
952 
      OUTS (outf, ") = [SP++]");
953 
    }
954 
  else if (W == 0 && d == 1 && p == 0 && pr == 0)
955 
    {
956 
      OUTS (outf, "(R7:");
957 
      OUTS (outf, imm5d (dr));
958 
      OUTS (outf, ") = [SP++]");
959 
    }
960 
  else if (W == 0 && d == 0 && p == 1 && dr == 0)
961 
    {
962 
      OUTS (outf, "(P5:");
963 
      OUTS (outf, imm5d (pr));
964 
      OUTS (outf, ") = [SP++]");
965 
    }
966 
  else
967 
    return 0;
968 
  return 2;
969 
}
970 
 
971 
static int
972 
decode_ccMV_0 (TIword iw0, disassemble_info *outf)
973 
{
974 
  /* ccMV
975 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
976 
     | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
977 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
978 
  int s  = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
979 
  int d  = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
980 
  int T  = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
981 
  int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
982 
  int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
983 
 
984 
  if (parallel)
985 
    return 0;
986 
 
987 
  if (T == 1)
988 
    {
989 
      OUTS (outf, "IF CC ");
990 
      OUTS (outf, gregs (dst, d));
991 
      OUTS (outf, " = ");
992 
      OUTS (outf, gregs (src, s));
993 
    }
994 
  else if (T == 0)
995 
    {
996 
      OUTS (outf, "IF !CC ");
997 
      OUTS (outf, gregs (dst, d));
998 
      OUTS (outf, " = ");
999 
      OUTS (outf, gregs (src, s));
1000 
    }
1001 
  else
1002 
    return 0;
1003 
  return 2;
1004 
}
1005 
 
1006 
static int
1007 
decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1008 
{
1009 
  /* CCflag
1010 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1011 
     | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1012 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1013 
  int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1014 
  int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1015 
  int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1016 
  int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1017 
  int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1018 
 
1019 
  if (parallel)
1020 
    return 0;
1021 
 
1022 
  if (opc == 0 && I == 0 && G == 0)
1023 
    {
1024 
      OUTS (outf, "CC = ");
1025 
      OUTS (outf, dregs (x));
1026 
      OUTS (outf, " == ");
1027 
      OUTS (outf, dregs (y));
1028 
    }
1029 
  else if (opc == 1 && I == 0 && G == 0)
1030 
    {
1031 
      OUTS (outf, "CC = ");
1032 
      OUTS (outf, dregs (x));
1033 
      OUTS (outf, " < ");
1034 
      OUTS (outf, dregs (y));
1035 
    }
1036 
  else if (opc == 2 && I == 0 && G == 0)
1037 
    {
1038 
      OUTS (outf, "CC = ");
1039 
      OUTS (outf, dregs (x));
1040 
      OUTS (outf, " <= ");
1041 
      OUTS (outf, dregs (y));
1042 
    }
1043 
  else if (opc == 3 && I == 0 && G == 0)
1044 
    {
1045 
      OUTS (outf, "CC = ");
1046 
      OUTS (outf, dregs (x));
1047 
      OUTS (outf, " < ");
1048 
      OUTS (outf, dregs (y));
1049 
      OUTS (outf, " (IU)");
1050 
    }
1051 
  else if (opc == 4 && I == 0 && G == 0)
1052 
    {
1053 
      OUTS (outf, "CC = ");
1054 
      OUTS (outf, dregs (x));
1055 
      OUTS (outf, " <= ");
1056 
      OUTS (outf, dregs (y));
1057 
      OUTS (outf, " (IU)");
1058 
    }
1059 
  else if (opc == 0 && I == 1 && G == 0)
1060 
    {
1061 
      OUTS (outf, "CC = ");
1062 
      OUTS (outf, dregs (x));
1063 
      OUTS (outf, " == ");
1064 
      OUTS (outf, imm3 (y));
1065 
    }
1066 
  else if (opc == 1 && I == 1 && G == 0)
1067 
    {
1068 
      OUTS (outf, "CC = ");
1069 
      OUTS (outf, dregs (x));
1070 
      OUTS (outf, " < ");
1071 
      OUTS (outf, imm3 (y));
1072 
    }
1073 
  else if (opc == 2 && I == 1 && G == 0)
1074 
    {
1075 
      OUTS (outf, "CC = ");
1076 
      OUTS (outf, dregs (x));
1077 
      OUTS (outf, " <= ");
1078 
      OUTS (outf, imm3 (y));
1079 
    }
1080 
  else if (opc == 3 && I == 1 && G == 0)
1081 
    {
1082 
      OUTS (outf, "CC = ");
1083 
      OUTS (outf, dregs (x));
1084 
      OUTS (outf, " < ");
1085 
      OUTS (outf, uimm3 (y));
1086 
      OUTS (outf, " (IU)");
1087 
    }
1088 
  else if (opc == 4 && I == 1 && G == 0)
1089 
    {
1090 
      OUTS (outf, "CC = ");
1091 
      OUTS (outf, dregs (x));
1092 
      OUTS (outf, " <= ");
1093 
      OUTS (outf, uimm3 (y));
1094 
      OUTS (outf, " (IU)");
1095 
    }
1096 
  else if (opc == 0 && I == 0 && G == 1)
1097 
    {
1098 
      OUTS (outf, "CC = ");
1099 
      OUTS (outf, pregs (x));
1100 
      OUTS (outf, " == ");
1101 
      OUTS (outf, pregs (y));
1102 
    }
1103 
  else if (opc == 1 && I == 0 && G == 1)
1104 
    {
1105 
      OUTS (outf, "CC = ");
1106 
      OUTS (outf, pregs (x));
1107 
      OUTS (outf, " < ");
1108 
      OUTS (outf, pregs (y));
1109 
    }
1110 
  else if (opc == 2 && I == 0 && G == 1)
1111 
    {
1112 
      OUTS (outf, "CC = ");
1113 
      OUTS (outf, pregs (x));
1114 
      OUTS (outf, " <= ");
1115 
      OUTS (outf, pregs (y));
1116 
    }
1117 
  else if (opc == 3 && I == 0 && G == 1)
1118 
    {
1119 
      OUTS (outf, "CC = ");
1120 
      OUTS (outf, pregs (x));
1121 
      OUTS (outf, " < ");
1122 
      OUTS (outf, pregs (y));
1123 
      OUTS (outf, " (IU)");
1124 
    }
1125 
  else if (opc == 4 && I == 0 && G == 1)
1126 
    {
1127 
      OUTS (outf, "CC = ");
1128 
      OUTS (outf, pregs (x));
1129 
      OUTS (outf, " <= ");
1130 
      OUTS (outf, pregs (y));
1131 
      OUTS (outf, " (IU)");
1132 
    }
1133 
  else if (opc == 0 && I == 1 && G == 1)
1134 
    {
1135 
      OUTS (outf, "CC = ");
1136 
      OUTS (outf, pregs (x));
1137 
      OUTS (outf, " == ");
1138 
      OUTS (outf, imm3 (y));
1139 
    }
1140 
  else if (opc == 1 && I == 1 && G == 1)
1141 
    {
1142 
      OUTS (outf, "CC = ");
1143 
      OUTS (outf, pregs (x));
1144 
      OUTS (outf, " < ");
1145 
      OUTS (outf, imm3 (y));
1146 
    }
1147 
  else if (opc == 2 && I == 1 && G == 1)
1148 
    {
1149 
      OUTS (outf, "CC = ");
1150 
      OUTS (outf, pregs (x));
1151 
      OUTS (outf, " <= ");
1152 
      OUTS (outf, imm3 (y));
1153 
    }
1154 
  else if (opc == 3 && I == 1 && G == 1)
1155 
    {
1156 
      OUTS (outf, "CC = ");
1157 
      OUTS (outf, pregs (x));
1158 
      OUTS (outf, " < ");
1159 
      OUTS (outf, uimm3 (y));
1160 
      OUTS (outf, " (IU)");
1161 
    }
1162 
  else if (opc == 4 && I == 1 && G == 1)
1163 
    {
1164 
      OUTS (outf, "CC = ");
1165 
      OUTS (outf, pregs (x));
1166 
      OUTS (outf, " <= ");
1167 
      OUTS (outf, uimm3 (y));
1168 
      OUTS (outf, " (IU)");
1169 
    }
1170 
  else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
1171 
    OUTS (outf, "CC = A0 == A1");
1172 
 
1173 
  else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
1174 
    OUTS (outf, "CC = A0 < A1");
1175 
 
1176 
  else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
1177 
    OUTS (outf, "CC = A0 <= A1");
1178 
 
1179 
  else
1180 
    return 0;
1181 
  return 2;
1182 
}
1183 
 
1184 
static int
1185 
decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1186 
{
1187 
  /* CC2dreg
1188 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1189 
     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1190 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1191 
  int op  = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1192 
  int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1193 
 
1194 
  if (parallel)
1195 
    return 0;
1196 
 
1197 
  if (op == 0)
1198 
    {
1199 
      OUTS (outf, dregs (reg));
1200 
      OUTS (outf, " = CC");
1201 
    }
1202 
  else if (op == 1)
1203 
    {
1204 
      OUTS (outf, "CC = ");
1205 
      OUTS (outf, dregs (reg));
1206 
    }
1207 
  else if (op == 3 && reg == 0)
1208 
    OUTS (outf, "CC = !CC");
1209 
  else
1210 
    return 0;
1211 
 
1212 
  return 2;
1213 
}
1214 
 
1215 
static int
1216 
decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1217 
{
1218 
  /* CC2stat
1219 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1220 
     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1221 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1222 
  int D    = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1223 
  int op   = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1224 
  int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1225 
 
1226 
  const char *bitname = statbits (cbit);
1227 
 
1228 
  if (parallel)
1229 
    return 0;
1230 
 
1231 
  if (decode_statbits[cbit] == REG_LASTREG)
1232 
    {
1233 
      /* All ASTAT bits except CC may be operated on in hardware, but may
1234 
         not have a dedicated insn, so still decode "valid" insns.  */
1235 
      static char bitnames[64];
1236 
      if (cbit != 5)
1237 
        sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1238 
      else
1239 
        return 0;
1240 
 
1241 
      bitname = bitnames;
1242 
    }
1243 
 
1244 
  if (op == 0 && D == 0)
1245 
    {
1246 
      OUTS (outf, "CC = ");
1247 
      OUTS (outf, bitname);
1248 
    }
1249 
  else if (op == 1 && D == 0)
1250 
    {
1251 
      OUTS (outf, "CC |= ");
1252 
      OUTS (outf, bitname);
1253 
    }
1254 
  else if (op == 2 && D == 0)
1255 
    {
1256 
      OUTS (outf, "CC &= ");
1257 
      OUTS (outf, bitname);
1258 
    }
1259 
  else if (op == 3 && D == 0)
1260 
    {
1261 
      OUTS (outf, "CC ^= ");
1262 
      OUTS (outf, bitname);
1263 
    }
1264 
  else if (op == 0 && D == 1)
1265 
    {
1266 
      OUTS (outf, bitname);
1267 
      OUTS (outf, " = CC");
1268 
    }
1269 
  else if (op == 1 && D == 1)
1270 
    {
1271 
      OUTS (outf, bitname);
1272 
      OUTS (outf, " |= CC");
1273 
    }
1274 
  else if (op == 2 && D == 1)
1275 
    {
1276 
      OUTS (outf, bitname);
1277 
      OUTS (outf, " &= CC");
1278 
    }
1279 
  else if (op == 3 && D == 1)
1280 
    {
1281 
      OUTS (outf, bitname);
1282 
      OUTS (outf, " ^= CC");
1283 
    }
1284 
  else
1285 
    return 0;
1286 
 
1287 
  return 2;
1288 
}
1289 
 
1290 
static int
1291 
decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1292 
{
1293 
  /* BRCC
1294 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1295 
     | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1296 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1297 
  int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1298 
  int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1299 
  int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1300 
 
1301 
  if (parallel)
1302 
    return 0;
1303 
 
1304 
  if (T == 1 && B == 1)
1305 
    {
1306 
      OUTS (outf, "IF CC JUMP 0x");
1307 
      OUTS (outf, pcrel10 (offset));
1308 
      OUTS (outf, " (BP)");
1309 
    }
1310 
  else if (T == 0 && B == 1)
1311 
    {
1312 
      OUTS (outf, "IF !CC JUMP 0x");
1313 
      OUTS (outf, pcrel10 (offset));
1314 
      OUTS (outf, " (BP)");
1315 
    }
1316 
  else if (T == 1)
1317 
    {
1318 
      OUTS (outf, "IF CC JUMP 0x");
1319 
      OUTS (outf, pcrel10 (offset));
1320 
    }
1321 
  else if (T == 0)
1322 
    {
1323 
      OUTS (outf, "IF !CC JUMP 0x");
1324 
      OUTS (outf, pcrel10 (offset));
1325 
    }
1326 
  else
1327 
    return 0;
1328 
 
1329 
  return 2;
1330 
}
1331 
 
1332 
static int
1333 
decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1334 
{
1335 
  /* UJUMP
1336 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1337 
     | 0 | 0 | 1 | 0 |.offset........................................|
1338 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1339 
  int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1340 
 
1341 
  if (parallel)
1342 
    return 0;
1343 
 
1344 
  OUTS (outf, "JUMP.S 0x");
1345 
  OUTS (outf, pcrel12 (offset));
1346 
  return 2;
1347 
}
1348 
 
1349 
static int
1350 
decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1351 
{
1352 
  /* REGMV
1353 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1354 
     | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1355 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1356 
  int gs  = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1357 
  int gd  = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1358 
  int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1359 
  int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1360 
 
1361 
  /* Reserved slots cannot be a src/dst.  */
1362 
  if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1363 
    goto invalid_move;
1364 
 
1365 
  /* Standard register moves  */
1366 
  if ((gs < 2) ||                               /* Dregs/Pregs as source  */
1367 
      (gd < 2) ||                               /* Dregs/Pregs as dest    */
1368 
      (gs == 4 && src < 4) ||                   /* Accumulators as source */
1369 
      (gd == 4 && dst < 4 && (gs < 4)) ||       /* Accumulators as dest   */
1370 
      (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src  */
1371 
      (gd == 7 && dst == 7))                    /* EMUDAT as dest         */
1372 
    goto valid_move;
1373 
 
1374 
  /* dareg = dareg (IMBL) */
1375 
  if (gs < 4 && gd < 4)
1376 
    goto valid_move;
1377 
 
1378 
  /* USP can be src to sysregs, but not dagregs.  */
1379 
  if ((gs == 7 && src == 0) && (gd >= 4))
1380 
    goto valid_move;
1381 
 
1382 
  /* USP can move between genregs (only check Accumulators).  */
1383 
  if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1384 
      ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1385 
    goto valid_move;
1386 
 
1387 
  /* Still here ?  Invalid reg pair.  */
1388 
 invalid_move:
1389 
  return 0;
1390 
 
1391 
 valid_move:
1392 
  OUTS (outf, allregs (dst, gd));
1393 
  OUTS (outf, " = ");
1394 
  OUTS (outf, allregs (src, gs));
1395 
  return 2;
1396 
}
1397 
 
1398 
static int
1399 
decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1400 
{
1401 
  /* ALU2op
1402 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1403 
     | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1404 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1405 
  int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1406 
  int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1407 
  int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1408 
 
1409 
  if (opc == 0)
1410 
    {
1411 
      OUTS (outf, dregs (dst));
1412 
      OUTS (outf, " >>>= ");
1413 
      OUTS (outf, dregs (src));
1414 
    }
1415 
  else if (opc == 1)
1416 
    {
1417 
      OUTS (outf, dregs (dst));
1418 
      OUTS (outf, " >>= ");
1419 
      OUTS (outf, dregs (src));
1420 
    }
1421 
  else if (opc == 2)
1422 
    {
1423 
      OUTS (outf, dregs (dst));
1424 
      OUTS (outf, " <<= ");
1425 
      OUTS (outf, dregs (src));
1426 
    }
1427 
  else if (opc == 3)
1428 
    {
1429 
      OUTS (outf, dregs (dst));
1430 
      OUTS (outf, " *= ");
1431 
      OUTS (outf, dregs (src));
1432 
    }
1433 
  else if (opc == 4)
1434 
    {
1435 
      OUTS (outf, dregs (dst));
1436 
      OUTS (outf, " = (");
1437 
      OUTS (outf, dregs (dst));
1438 
      OUTS (outf, " + ");
1439 
      OUTS (outf, dregs (src));
1440 
      OUTS (outf, ") << 0x1");
1441 
    }
1442 
  else if (opc == 5)
1443 
    {
1444 
      OUTS (outf, dregs (dst));
1445 
      OUTS (outf, " = (");
1446 
      OUTS (outf, dregs (dst));
1447 
      OUTS (outf, " + ");
1448 
      OUTS (outf, dregs (src));
1449 
      OUTS (outf, ") << 0x2");
1450 
    }
1451 
  else if (opc == 8)
1452 
    {
1453 
      OUTS (outf, "DIVQ (");
1454 
      OUTS (outf, dregs (dst));
1455 
      OUTS (outf, ", ");
1456 
      OUTS (outf, dregs (src));
1457 
      OUTS (outf, ")");
1458 
    }
1459 
  else if (opc == 9)
1460 
    {
1461 
      OUTS (outf, "DIVS (");
1462 
      OUTS (outf, dregs (dst));
1463 
      OUTS (outf, ", ");
1464 
      OUTS (outf, dregs (src));
1465 
      OUTS (outf, ")");
1466 
    }
1467 
  else if (opc == 10)
1468 
    {
1469 
      OUTS (outf, dregs (dst));
1470 
      OUTS (outf, " = ");
1471 
      OUTS (outf, dregs_lo (src));
1472 
      OUTS (outf, " (X)");
1473 
    }
1474 
  else if (opc == 11)
1475 
    {
1476 
      OUTS (outf, dregs (dst));
1477 
      OUTS (outf, " = ");
1478 
      OUTS (outf, dregs_lo (src));
1479 
      OUTS (outf, " (Z)");
1480 
    }
1481 
  else if (opc == 12)
1482 
    {
1483 
      OUTS (outf, dregs (dst));
1484 
      OUTS (outf, " = ");
1485 
      OUTS (outf, dregs_byte (src));
1486 
      OUTS (outf, " (X)");
1487 
    }
1488 
  else if (opc == 13)
1489 
    {
1490 
      OUTS (outf, dregs (dst));
1491 
      OUTS (outf, " = ");
1492 
      OUTS (outf, dregs_byte (src));
1493 
      OUTS (outf, " (Z)");
1494 
    }
1495 
  else if (opc == 14)
1496 
    {
1497 
      OUTS (outf, dregs (dst));
1498 
      OUTS (outf, " = -");
1499 
      OUTS (outf, dregs (src));
1500 
    }
1501 
  else if (opc == 15)
1502 
    {
1503 
      OUTS (outf, dregs (dst));
1504 
      OUTS (outf, " =~ ");
1505 
      OUTS (outf, dregs (src));
1506 
    }
1507 
  else
1508 
    return 0;
1509 
 
1510 
  return 2;
1511 
}
1512 
 
1513 
static int
1514 
decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1515 
{
1516 
  /* PTR2op
1517 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1518 
     | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1519 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1520 
  int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1521 
  int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1522 
  int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1523 
 
1524 
  if (opc == 0)
1525 
    {
1526 
      OUTS (outf, pregs (dst));
1527 
      OUTS (outf, " -= ");
1528 
      OUTS (outf, pregs (src));
1529 
    }
1530 
  else if (opc == 1)
1531 
    {
1532 
      OUTS (outf, pregs (dst));
1533 
      OUTS (outf, " = ");
1534 
      OUTS (outf, pregs (src));
1535 
      OUTS (outf, " << 0x2");
1536 
    }
1537 
  else if (opc == 3)
1538 
    {
1539 
      OUTS (outf, pregs (dst));
1540 
      OUTS (outf, " = ");
1541 
      OUTS (outf, pregs (src));
1542 
      OUTS (outf, " >> 0x2");
1543 
    }
1544 
  else if (opc == 4)
1545 
    {
1546 
      OUTS (outf, pregs (dst));
1547 
      OUTS (outf, " = ");
1548 
      OUTS (outf, pregs (src));
1549 
      OUTS (outf, " >> 0x1");
1550 
    }
1551 
  else if (opc == 5)
1552 
    {
1553 
      OUTS (outf, pregs (dst));
1554 
      OUTS (outf, " += ");
1555 
      OUTS (outf, pregs (src));
1556 
      OUTS (outf, " (BREV)");
1557 
    }
1558 
  else if (opc == 6)
1559 
    {
1560 
      OUTS (outf, pregs (dst));
1561 
      OUTS (outf, " = (");
1562 
      OUTS (outf, pregs (dst));
1563 
      OUTS (outf, " + ");
1564 
      OUTS (outf, pregs (src));
1565 
      OUTS (outf, ") << 0x1");
1566 
    }
1567 
  else if (opc == 7)
1568 
    {
1569 
      OUTS (outf, pregs (dst));
1570 
      OUTS (outf, " = (");
1571 
      OUTS (outf, pregs (dst));
1572 
      OUTS (outf, " + ");
1573 
      OUTS (outf, pregs (src));
1574 
      OUTS (outf, ") << 0x2");
1575 
    }
1576 
  else
1577 
    return 0;
1578 
 
1579 
  return 2;
1580 
}
1581 
 
1582 
static int
1583 
decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1584 
{
1585 
  /* LOGI2op
1586 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1587 
     | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1588 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1589 
  int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1590 
  int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1591 
  int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1592 
 
1593 
  if (parallel)
1594 
    return 0;
1595 
 
1596 
  if (opc == 0)
1597 
    {
1598 
      OUTS (outf, "CC = !BITTST (");
1599 
      OUTS (outf, dregs (dst));
1600 
      OUTS (outf, ", ");
1601 
      OUTS (outf, uimm5 (src));
1602 
      OUTS (outf, ");\t\t/* bit");
1603 
      OUTS (outf, imm7d (src));
1604 
      OUTS (outf, " */");
1605 
      comment = 1;
1606 
    }
1607 
  else if (opc == 1)
1608 
    {
1609 
      OUTS (outf, "CC = BITTST (");
1610 
      OUTS (outf, dregs (dst));
1611 
      OUTS (outf, ", ");
1612 
      OUTS (outf, uimm5 (src));
1613 
      OUTS (outf, ");\t\t/* bit");
1614 
      OUTS (outf, imm7d (src));
1615 
      OUTS (outf, " */");
1616 
      comment = 1;
1617 
    }
1618 
  else if (opc == 2)
1619 
    {
1620 
      OUTS (outf, "BITSET (");
1621 
      OUTS (outf, dregs (dst));
1622 
      OUTS (outf, ", ");
1623 
      OUTS (outf, uimm5 (src));
1624 
      OUTS (outf, ");\t\t/* bit");
1625 
      OUTS (outf, imm7d (src));
1626 
      OUTS (outf, " */");
1627 
      comment = 1;
1628 
    }
1629 
  else if (opc == 3)
1630 
    {
1631 
      OUTS (outf, "BITTGL (");
1632 
      OUTS (outf, dregs (dst));
1633 
      OUTS (outf, ", ");
1634 
      OUTS (outf, uimm5 (src));
1635 
      OUTS (outf, ");\t\t/* bit");
1636 
      OUTS (outf, imm7d (src));
1637 
      OUTS (outf, " */");
1638 
      comment = 1;
1639 
    }
1640 
  else if (opc == 4)
1641 
    {
1642 
      OUTS (outf, "BITCLR (");
1643 
      OUTS (outf, dregs (dst));
1644 
      OUTS (outf, ", ");
1645 
      OUTS (outf, uimm5 (src));
1646 
      OUTS (outf, ");\t\t/* bit");
1647 
      OUTS (outf, imm7d (src));
1648 
      OUTS (outf, " */");
1649 
      comment = 1;
1650 
    }
1651 
  else if (opc == 5)
1652 
    {
1653 
      OUTS (outf, dregs (dst));
1654 
      OUTS (outf, " >>>= ");
1655 
      OUTS (outf, uimm5 (src));
1656 
    }
1657 
  else if (opc == 6)
1658 
    {
1659 
      OUTS (outf, dregs (dst));
1660 
      OUTS (outf, " >>= ");
1661 
      OUTS (outf, uimm5 (src));
1662 
    }
1663 
  else if (opc == 7)
1664 
    {
1665 
      OUTS (outf, dregs (dst));
1666 
      OUTS (outf, " <<= ");
1667 
      OUTS (outf, uimm5 (src));
1668 
    }
1669 
  else
1670 
    return 0;
1671 
 
1672 
  return 2;
1673 
}
1674 
 
1675 
static int
1676 
decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1677 
{
1678 
  /* COMP3op
1679 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1680 
     | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1681 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1682 
  int opc  = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1683 
  int dst  = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1684 
  int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1685 
  int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1686 
 
1687 
  if (opc == 5 && src1 == src0)
1688 
    {
1689 
      OUTS (outf, pregs (dst));
1690 
      OUTS (outf, " = ");
1691 
      OUTS (outf, pregs (src0));
1692 
      OUTS (outf, " << 0x1");
1693 
    }
1694 
  else if (opc == 1)
1695 
    {
1696 
      OUTS (outf, dregs (dst));
1697 
      OUTS (outf, " = ");
1698 
      OUTS (outf, dregs (src0));
1699 
      OUTS (outf, " - ");
1700 
      OUTS (outf, dregs (src1));
1701 
    }
1702 
  else if (opc == 2)
1703 
    {
1704 
      OUTS (outf, dregs (dst));
1705 
      OUTS (outf, " = ");
1706 
      OUTS (outf, dregs (src0));
1707 
      OUTS (outf, " & ");
1708 
      OUTS (outf, dregs (src1));
1709 
    }
1710 
  else if (opc == 3)
1711 
    {
1712 
      OUTS (outf, dregs (dst));
1713 
      OUTS (outf, " = ");
1714 
      OUTS (outf, dregs (src0));
1715 
      OUTS (outf, " | ");
1716 
      OUTS (outf, dregs (src1));
1717 
    }
1718 
  else if (opc == 4)
1719 
    {
1720 
      OUTS (outf, dregs (dst));
1721 
      OUTS (outf, " = ");
1722 
      OUTS (outf, dregs (src0));
1723 
      OUTS (outf, " ^ ");
1724 
      OUTS (outf, dregs (src1));
1725 
    }
1726 
  else if (opc == 5)
1727 
    {
1728 
      OUTS (outf, pregs (dst));
1729 
      OUTS (outf, " = ");
1730 
      OUTS (outf, pregs (src0));
1731 
      OUTS (outf, " + ");
1732 
      OUTS (outf, pregs (src1));
1733 
    }
1734 
  else if (opc == 6)
1735 
    {
1736 
      OUTS (outf, pregs (dst));
1737 
      OUTS (outf, " = ");
1738 
      OUTS (outf, pregs (src0));
1739 
      OUTS (outf, " + (");
1740 
      OUTS (outf, pregs (src1));
1741 
      OUTS (outf, " << 0x1)");
1742 
    }
1743 
  else if (opc == 7)
1744 
    {
1745 
      OUTS (outf, pregs (dst));
1746 
      OUTS (outf, " = ");
1747 
      OUTS (outf, pregs (src0));
1748 
      OUTS (outf, " + (");
1749 
      OUTS (outf, pregs (src1));
1750 
      OUTS (outf, " << 0x2)");
1751 
    }
1752 
  else if (opc == 0)
1753 
    {
1754 
      OUTS (outf, dregs (dst));
1755 
      OUTS (outf, " = ");
1756 
      OUTS (outf, dregs (src0));
1757 
      OUTS (outf, " + ");
1758 
      OUTS (outf, dregs (src1));
1759 
    }
1760 
  else
1761 
    return 0;
1762 
 
1763 
  return 2;
1764 
}
1765 
 
1766 
static int
1767 
decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1768 
{
1769 
  /* COMPI2opD
1770 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1771 
     | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1772 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1773 
  int op  = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1774 
  int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1775 
  int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1776 
 
1777 
  bu32 *pval = get_allreg (0, dst);
1778 
 
1779 
  if (parallel)
1780 
    return 0;
1781 
 
1782 
  /* Since we don't have 32-bit immediate loads, we allow the disassembler
1783 
     to combine them, so it prints out the right values.
1784 
     Here we keep track of the registers.  */
1785 
  if (op == 0)
1786 
    {
1787 
      *pval = imm7_val (src);
1788 
      if (src & 0x40)
1789 
        *pval |= 0xFFFFFF80;
1790 
      else
1791 
        *pval &= 0x7F;
1792 
    }
1793 
 
1794 
  if (op == 0)
1795 
    {
1796 
      OUTS (outf, dregs (dst));
1797 
      OUTS (outf, " = ");
1798 
      OUTS (outf, imm7 (src));
1799 
      OUTS (outf, " (X);\t\t/*\t\t");
1800 
      OUTS (outf, dregs (dst));
1801 
      OUTS (outf, "=");
1802 
      OUTS (outf, uimm32 (*pval));
1803 
      OUTS (outf, "(");
1804 
      OUTS (outf, imm32 (*pval));
1805 
      OUTS (outf, ") */");
1806 
      comment = 1;
1807 
    }
1808 
  else if (op == 1)
1809 
    {
1810 
      OUTS (outf, dregs (dst));
1811 
      OUTS (outf, " += ");
1812 
      OUTS (outf, imm7 (src));
1813 
      OUTS (outf, ";\t\t/* (");
1814 
      OUTS (outf, imm7d (src));
1815 
      OUTS (outf, ") */");
1816 
      comment = 1;
1817 
    }
1818 
  else
1819 
    return 0;
1820 
 
1821 
  return 2;
1822 
}
1823 
 
1824 
static int
1825 
decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1826 
{
1827 
  /* COMPI2opP
1828 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1829 
     | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1830 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1831 
  int op  = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1832 
  int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1833 
  int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1834 
 
1835 
  bu32 *pval = get_allreg (1, dst);
1836 
 
1837 
  if (parallel)
1838 
    return 0;
1839 
 
1840 
  if (op == 0)
1841 
    {
1842 
      *pval = imm7_val (src);
1843 
      if (src & 0x40)
1844 
        *pval |= 0xFFFFFF80;
1845 
      else
1846 
        *pval &= 0x7F;
1847 
    }
1848 
 
1849 
  if (op == 0)
1850 
    {
1851 
      OUTS (outf, pregs (dst));
1852 
      OUTS (outf, " = ");
1853 
      OUTS (outf, imm7 (src));
1854 
      OUTS (outf, " (X);\t\t/*\t\t");
1855 
      OUTS (outf, pregs (dst));
1856 
      OUTS (outf, "=");
1857 
      OUTS (outf, uimm32 (*pval));
1858 
      OUTS (outf, "(");
1859 
      OUTS (outf, imm32 (*pval));
1860 
      OUTS (outf, ") */");
1861 
      comment = 1;
1862 
    }
1863 
  else if (op == 1)
1864 
    {
1865 
      OUTS (outf, pregs (dst));
1866 
      OUTS (outf, " += ");
1867 
      OUTS (outf, imm7 (src));
1868 
      OUTS (outf, ";\t\t/* (");
1869 
      OUTS (outf, imm7d (src));
1870 
      OUTS (outf, ") */");
1871 
      comment = 1;
1872 
    }
1873 
  else
1874 
    return 0;
1875 
 
1876 
  return 2;
1877 
}
1878 
 
1879 
static int
1880 
decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1881 
{
1882 
  /* LDSTpmod
1883 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1884 
     | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1885 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1886 
  int W   = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1887 
  int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1888 
  int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1889 
  int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1890 
  int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1891 
 
1892 
  if (aop == 1 && W == 0 && idx == ptr)
1893 
    {
1894 
      OUTS (outf, dregs_lo (reg));
1895 
      OUTS (outf, " = W[");
1896 
      OUTS (outf, pregs (ptr));
1897 
      OUTS (outf, "]");
1898 
    }
1899 
  else if (aop == 2 && W == 0 && idx == ptr)
1900 
    {
1901 
      OUTS (outf, dregs_hi (reg));
1902 
      OUTS (outf, " = W[");
1903 
      OUTS (outf, pregs (ptr));
1904 
      OUTS (outf, "]");
1905 
    }
1906 
  else if (aop == 1 && W == 1 && idx == ptr)
1907 
    {
1908 
      OUTS (outf, "W[");
1909 
      OUTS (outf, pregs (ptr));
1910 
      OUTS (outf, "] = ");
1911 
      OUTS (outf, dregs_lo (reg));
1912 
    }
1913 
  else if (aop == 2 && W == 1 && idx == ptr)
1914 
    {
1915 
      OUTS (outf, "W[");
1916 
      OUTS (outf, pregs (ptr));
1917 
      OUTS (outf, "] = ");
1918 
      OUTS (outf, dregs_hi (reg));
1919 
    }
1920 
  else if (aop == 0 && W == 0)
1921 
    {
1922 
      OUTS (outf, dregs (reg));
1923 
      OUTS (outf, " = [");
1924 
      OUTS (outf, pregs (ptr));
1925 
      OUTS (outf, " ++ ");
1926 
      OUTS (outf, pregs (idx));
1927 
      OUTS (outf, "]");
1928 
    }
1929 
  else if (aop == 1 && W == 0)
1930 
    {
1931 
      OUTS (outf, dregs_lo (reg));
1932 
      OUTS (outf, " = W[");
1933 
      OUTS (outf, pregs (ptr));
1934 
      OUTS (outf, " ++ ");
1935 
      OUTS (outf, pregs (idx));
1936 
      OUTS (outf, "]");
1937 
    }
1938 
  else if (aop == 2 && W == 0)
1939 
    {
1940 
      OUTS (outf, dregs_hi (reg));
1941 
      OUTS (outf, " = W[");
1942 
      OUTS (outf, pregs (ptr));
1943 
      OUTS (outf, " ++ ");
1944 
      OUTS (outf, pregs (idx));
1945 
      OUTS (outf, "]");
1946 
    }
1947 
  else if (aop == 3 && W == 0)
1948 
    {
1949 
      OUTS (outf, dregs (reg));
1950 
      OUTS (outf, " = W[");
1951 
      OUTS (outf, pregs (ptr));
1952 
      OUTS (outf, " ++ ");
1953 
      OUTS (outf, pregs (idx));
1954 
      OUTS (outf, "] (Z)");
1955 
    }
1956 
  else if (aop == 3 && W == 1)
1957 
    {
1958 
      OUTS (outf, dregs (reg));
1959 
      OUTS (outf, " = W[");
1960 
      OUTS (outf, pregs (ptr));
1961 
      OUTS (outf, " ++ ");
1962 
      OUTS (outf, pregs (idx));
1963 
      OUTS (outf, "] (X)");
1964 
    }
1965 
  else if (aop == 0 && W == 1)
1966 
    {
1967 
      OUTS (outf, "[");
1968 
      OUTS (outf, pregs (ptr));
1969 
      OUTS (outf, " ++ ");
1970 
      OUTS (outf, pregs (idx));
1971 
      OUTS (outf, "] = ");
1972 
      OUTS (outf, dregs (reg));
1973 
    }
1974 
  else if (aop == 1 && W == 1)
1975 
    {
1976 
      OUTS (outf, "W[");
1977 
      OUTS (outf, pregs (ptr));
1978 
      OUTS (outf, " ++ ");
1979 
      OUTS (outf, pregs (idx));
1980 
      OUTS (outf, "] = ");
1981 
      OUTS (outf, dregs_lo (reg));
1982 
    }
1983 
  else if (aop == 2 && W == 1)
1984 
    {
1985 
      OUTS (outf, "W[");
1986 
      OUTS (outf, pregs (ptr));
1987 
      OUTS (outf, " ++ ");
1988 
      OUTS (outf, pregs (idx));
1989 
      OUTS (outf, "] = ");
1990 
      OUTS (outf, dregs_hi (reg));
1991 
    }
1992 
  else
1993 
    return 0;
1994 
 
1995 
  return 2;
1996 
}
1997 
 
1998 
static int
1999 
decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
2000 
{
2001 
  /* dagMODim
2002 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2003 
     | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2004 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2005 
  int i  = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
2006 
  int m  = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
2007 
  int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
2008 
  int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
2009 
 
2010 
  if (op == 0 && br == 1)
2011 
    {
2012 
      OUTS (outf, iregs (i));
2013 
      OUTS (outf, " += ");
2014 
      OUTS (outf, mregs (m));
2015 
      OUTS (outf, " (BREV)");
2016 
    }
2017 
  else if (op == 0)
2018 
    {
2019 
      OUTS (outf, iregs (i));
2020 
      OUTS (outf, " += ");
2021 
      OUTS (outf, mregs (m));
2022 
    }
2023 
  else if (op == 1 && br == 0)
2024 
    {
2025 
      OUTS (outf, iregs (i));
2026 
      OUTS (outf, " -= ");
2027 
      OUTS (outf, mregs (m));
2028 
    }
2029 
  else
2030 
    return 0;
2031 
 
2032 
  return 2;
2033 
}
2034 
 
2035 
static int
2036 
decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2037 
{
2038 
  /* dagMODik
2039 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2040 
     | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2041 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2042 
  int i  = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2043 
  int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2044 
 
2045 
  if (op == 0)
2046 
    {
2047 
      OUTS (outf, iregs (i));
2048 
      OUTS (outf, " += 0x2");
2049 
    }
2050 
  else if (op == 1)
2051 
    {
2052 
      OUTS (outf, iregs (i));
2053 
      OUTS (outf, " -= 0x2");
2054 
    }
2055 
  else if (op == 2)
2056 
    {
2057 
      OUTS (outf, iregs (i));
2058 
      OUTS (outf, " += 0x4");
2059 
    }
2060 
  else if (op == 3)
2061 
    {
2062 
      OUTS (outf, iregs (i));
2063 
      OUTS (outf, " -= 0x4");
2064 
    }
2065 
  else
2066 
    return 0;
2067 
 
2068 
  if (! parallel)
2069 
    {
2070 
      OUTS (outf, ";\t\t/* (  ");
2071 
      if (op == 0 || op == 1)
2072 
        OUTS (outf, "2");
2073 
      else if (op == 2 || op == 3)
2074 
        OUTS (outf, "4");
2075 
      OUTS (outf, ") */");
2076 
      comment = 1;
2077 
    }
2078 
 
2079 
  return 2;
2080 
}
2081 
 
2082 
static int
2083 
decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2084 
{
2085 
  /* dspLDST
2086 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2087 
     | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2088 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2089 
  int i   = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2090 
  int m   = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2091 
  int W   = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2092 
  int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2093 
  int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2094 
 
2095 
  if (aop == 0 && W == 0 && m == 0)
2096 
    {
2097 
      OUTS (outf, dregs (reg));
2098 
      OUTS (outf, " = [");
2099 
      OUTS (outf, iregs (i));
2100 
      OUTS (outf, "++]");
2101 
    }
2102 
  else if (aop == 0 && W == 0 && m == 1)
2103 
    {
2104 
      OUTS (outf, dregs_lo (reg));
2105 
      OUTS (outf, " = W[");
2106 
      OUTS (outf, iregs (i));
2107 
      OUTS (outf, "++]");
2108 
    }
2109 
  else if (aop == 0 && W == 0 && m == 2)
2110 
    {
2111 
      OUTS (outf, dregs_hi (reg));
2112 
      OUTS (outf, " = W[");
2113 
      OUTS (outf, iregs (i));
2114 
      OUTS (outf, "++]");
2115 
    }
2116 
  else if (aop == 1 && W == 0 && m == 0)
2117 
    {
2118 
      OUTS (outf, dregs (reg));
2119 
      OUTS (outf, " = [");
2120 
      OUTS (outf, iregs (i));
2121 
      OUTS (outf, "--]");
2122 
    }
2123 
  else if (aop == 1 && W == 0 && m == 1)
2124 
    {
2125 
      OUTS (outf, dregs_lo (reg));
2126 
      OUTS (outf, " = W[");
2127 
      OUTS (outf, iregs (i));
2128 
      OUTS (outf, "--]");
2129 
    }
2130 
  else if (aop == 1 && W == 0 && m == 2)
2131 
    {
2132 
      OUTS (outf, dregs_hi (reg));
2133 
      OUTS (outf, " = W[");
2134 
      OUTS (outf, iregs (i));
2135 
      OUTS (outf, "--]");
2136 
    }
2137 
  else if (aop == 2 && W == 0 && m == 0)
2138 
    {
2139 
      OUTS (outf, dregs (reg));
2140 
      OUTS (outf, " = [");
2141 
      OUTS (outf, iregs (i));
2142 
      OUTS (outf, "]");
2143 
    }
2144 
  else if (aop == 2 && W == 0 && m == 1)
2145 
    {
2146 
      OUTS (outf, dregs_lo (reg));
2147 
      OUTS (outf, " = W[");
2148 
      OUTS (outf, iregs (i));
2149 
      OUTS (outf, "]");
2150 
    }
2151 
  else if (aop == 2 && W == 0 && m == 2)
2152 
    {
2153 
      OUTS (outf, dregs_hi (reg));
2154 
      OUTS (outf, " = W[");
2155 
      OUTS (outf, iregs (i));
2156 
      OUTS (outf, "]");
2157 
    }
2158 
  else if (aop == 0 && W == 1 && m == 0)
2159 
    {
2160 
      OUTS (outf, "[");
2161 
      OUTS (outf, iregs (i));
2162 
      OUTS (outf, "++] = ");
2163 
      OUTS (outf, dregs (reg));
2164 
    }
2165 
  else if (aop == 0 && W == 1 && m == 1)
2166 
    {
2167 
      OUTS (outf, "W[");
2168 
      OUTS (outf, iregs (i));
2169 
      OUTS (outf, "++] = ");
2170 
      OUTS (outf, dregs_lo (reg));
2171 
    }
2172 
  else if (aop == 0 && W == 1 && m == 2)
2173 
    {
2174 
      OUTS (outf, "W[");
2175 
      OUTS (outf, iregs (i));
2176 
      OUTS (outf, "++] = ");
2177 
      OUTS (outf, dregs_hi (reg));
2178 
    }
2179 
  else if (aop == 1 && W == 1 && m == 0)
2180 
    {
2181 
      OUTS (outf, "[");
2182 
      OUTS (outf, iregs (i));
2183 
      OUTS (outf, "--] = ");
2184 
      OUTS (outf, dregs (reg));
2185 
    }
2186 
  else if (aop == 1 && W == 1 && m == 1)
2187 
    {
2188 
      OUTS (outf, "W[");
2189 
      OUTS (outf, iregs (i));
2190 
      OUTS (outf, "--] = ");
2191 
      OUTS (outf, dregs_lo (reg));
2192 
    }
2193 
  else if (aop == 1 && W == 1 && m == 2)
2194 
    {
2195 
      OUTS (outf, "W[");
2196 
      OUTS (outf, iregs (i));
2197 
      OUTS (outf, "--] = ");
2198 
      OUTS (outf, dregs_hi (reg));
2199 
    }
2200 
  else if (aop == 2 && W == 1 && m == 0)
2201 
    {
2202 
      OUTS (outf, "[");
2203 
      OUTS (outf, iregs (i));
2204 
      OUTS (outf, "] = ");
2205 
      OUTS (outf, dregs (reg));
2206 
    }
2207 
  else if (aop == 2 && W == 1 && m == 1)
2208 
    {
2209 
      OUTS (outf, "W[");
2210 
      OUTS (outf, iregs (i));
2211 
      OUTS (outf, "] = ");
2212 
      OUTS (outf, dregs_lo (reg));
2213 
    }
2214 
  else if (aop == 2 && W == 1 && m == 2)
2215 
    {
2216 
      OUTS (outf, "W[");
2217 
      OUTS (outf, iregs (i));
2218 
      OUTS (outf, "] = ");
2219 
      OUTS (outf, dregs_hi (reg));
2220 
    }
2221 
  else if (aop == 3 && W == 0)
2222 
    {
2223 
      OUTS (outf, dregs (reg));
2224 
      OUTS (outf, " = [");
2225 
      OUTS (outf, iregs (i));
2226 
      OUTS (outf, " ++ ");
2227 
      OUTS (outf, mregs (m));
2228 
      OUTS (outf, "]");
2229 
    }
2230 
  else if (aop == 3 && W == 1)
2231 
    {
2232 
      OUTS (outf, "[");
2233 
      OUTS (outf, iregs (i));
2234 
      OUTS (outf, " ++ ");
2235 
      OUTS (outf, mregs (m));
2236 
      OUTS (outf, "] = ");
2237 
      OUTS (outf, dregs (reg));
2238 
    }
2239 
  else
2240 
    return 0;
2241 
 
2242 
  return 2;
2243 
}
2244 
 
2245 
static int
2246 
decode_LDST_0 (TIword iw0, disassemble_info *outf)
2247 
{
2248 
  /* LDST
2249 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2250 
     | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2251 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2252 
  int Z   = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2253 
  int W   = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2254 
  int sz  = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2255 
  int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2256 
  int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2257 
  int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2258 
 
2259 
  if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2260 
    {
2261 
      OUTS (outf, dregs (reg));
2262 
      OUTS (outf, " = [");
2263 
      OUTS (outf, pregs (ptr));
2264 
      OUTS (outf, "++]");
2265 
    }
2266 
  else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2267 
    {
2268 
      OUTS (outf, pregs (reg));
2269 
      OUTS (outf, " = [");
2270 
      OUTS (outf, pregs (ptr));
2271 
      OUTS (outf, "++]");
2272 
    }
2273 
  else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2274 
    {
2275 
      OUTS (outf, dregs (reg));
2276 
      OUTS (outf, " = W[");
2277 
      OUTS (outf, pregs (ptr));
2278 
      OUTS (outf, "++] (Z)");
2279 
    }
2280 
  else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2281 
    {
2282 
      OUTS (outf, dregs (reg));
2283 
      OUTS (outf, " = W[");
2284 
      OUTS (outf, pregs (ptr));
2285 
      OUTS (outf, "++] (X)");
2286 
    }
2287 
  else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2288 
    {
2289 
      OUTS (outf, dregs (reg));
2290 
      OUTS (outf, " = B[");
2291 
      OUTS (outf, pregs (ptr));
2292 
      OUTS (outf, "++] (Z)");
2293 
    }
2294 
  else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2295 
    {
2296 
      OUTS (outf, dregs (reg));
2297 
      OUTS (outf, " = B[");
2298 
      OUTS (outf, pregs (ptr));
2299 
      OUTS (outf, "++] (X)");
2300 
    }
2301 
  else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2302 
    {
2303 
      OUTS (outf, dregs (reg));
2304 
      OUTS (outf, " = [");
2305 
      OUTS (outf, pregs (ptr));
2306 
      OUTS (outf, "--]");
2307 
    }
2308 
  else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2309 
    {
2310 
      OUTS (outf, pregs (reg));
2311 
      OUTS (outf, " = [");
2312 
      OUTS (outf, pregs (ptr));
2313 
      OUTS (outf, "--]");
2314 
    }
2315 
  else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2316 
    {
2317 
      OUTS (outf, dregs (reg));
2318 
      OUTS (outf, " = W[");
2319 
      OUTS (outf, pregs (ptr));
2320 
      OUTS (outf, "--] (Z)");
2321 
    }
2322 
  else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2323 
    {
2324 
      OUTS (outf, dregs (reg));
2325 
      OUTS (outf, " = W[");
2326 
      OUTS (outf, pregs (ptr));
2327 
      OUTS (outf, "--] (X)");
2328 
    }
2329 
  else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2330 
    {
2331 
      OUTS (outf, dregs (reg));
2332 
      OUTS (outf, " = B[");
2333 
      OUTS (outf, pregs (ptr));
2334 
      OUTS (outf, "--] (Z)");
2335 
    }
2336 
  else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2337 
    {
2338 
      OUTS (outf, dregs (reg));
2339 
      OUTS (outf, " = B[");
2340 
      OUTS (outf, pregs (ptr));
2341 
      OUTS (outf, "--] (X)");
2342 
    }
2343 
  else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2344 
    {
2345 
      OUTS (outf, dregs (reg));
2346 
      OUTS (outf, " = [");
2347 
      OUTS (outf, pregs (ptr));
2348 
      OUTS (outf, "]");
2349 
    }
2350 
  else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2351 
    {
2352 
      OUTS (outf, pregs (reg));
2353 
      OUTS (outf, " = [");
2354 
      OUTS (outf, pregs (ptr));
2355 
      OUTS (outf, "]");
2356 
    }
2357 
  else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2358 
    {
2359 
      OUTS (outf, dregs (reg));
2360 
      OUTS (outf, " = W[");
2361 
      OUTS (outf, pregs (ptr));
2362 
      OUTS (outf, "] (Z)");
2363 
    }
2364 
  else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2365 
    {
2366 
      OUTS (outf, dregs (reg));
2367 
      OUTS (outf, " = W[");
2368 
      OUTS (outf, pregs (ptr));
2369 
      OUTS (outf, "] (X)");
2370 
    }
2371 
  else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2372 
    {
2373 
      OUTS (outf, dregs (reg));
2374 
      OUTS (outf, " = B[");
2375 
      OUTS (outf, pregs (ptr));
2376 
      OUTS (outf, "] (Z)");
2377 
    }
2378 
  else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2379 
    {
2380 
      OUTS (outf, dregs (reg));
2381 
      OUTS (outf, " = B[");
2382 
      OUTS (outf, pregs (ptr));
2383 
      OUTS (outf, "] (X)");
2384 
    }
2385 
  else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2386 
    {
2387 
      OUTS (outf, "[");
2388 
      OUTS (outf, pregs (ptr));
2389 
      OUTS (outf, "++] = ");
2390 
      OUTS (outf, dregs (reg));
2391 
    }
2392 
  else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2393 
    {
2394 
      OUTS (outf, "[");
2395 
      OUTS (outf, pregs (ptr));
2396 
      OUTS (outf, "++] = ");
2397 
      OUTS (outf, pregs (reg));
2398 
    }
2399 
  else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2400 
    {
2401 
      OUTS (outf, "W[");
2402 
      OUTS (outf, pregs (ptr));
2403 
      OUTS (outf, "++] = ");
2404 
      OUTS (outf, dregs (reg));
2405 
    }
2406 
  else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2407 
    {
2408 
      OUTS (outf, "B[");
2409 
      OUTS (outf, pregs (ptr));
2410 
      OUTS (outf, "++] = ");
2411 
      OUTS (outf, dregs (reg));
2412 
    }
2413 
  else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2414 
    {
2415 
      OUTS (outf, "[");
2416 
      OUTS (outf, pregs (ptr));
2417 
      OUTS (outf, "--] = ");
2418 
      OUTS (outf, dregs (reg));
2419 
    }
2420 
  else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2421 
    {
2422 
      OUTS (outf, "[");
2423 
      OUTS (outf, pregs (ptr));
2424 
      OUTS (outf, "--] = ");
2425 
      OUTS (outf, pregs (reg));
2426 
    }
2427 
  else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2428 
    {
2429 
      OUTS (outf, "W[");
2430 
      OUTS (outf, pregs (ptr));
2431 
      OUTS (outf, "--] = ");
2432 
      OUTS (outf, dregs (reg));
2433 
    }
2434 
  else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2435 
    {
2436 
      OUTS (outf, "B[");
2437 
      OUTS (outf, pregs (ptr));
2438 
      OUTS (outf, "--] = ");
2439 
      OUTS (outf, dregs (reg));
2440 
    }
2441 
  else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2442 
    {
2443 
      OUTS (outf, "[");
2444 
      OUTS (outf, pregs (ptr));
2445 
      OUTS (outf, "] = ");
2446 
      OUTS (outf, dregs (reg));
2447 
    }
2448 
  else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2449 
    {
2450 
      OUTS (outf, "[");
2451 
      OUTS (outf, pregs (ptr));
2452 
      OUTS (outf, "] = ");
2453 
      OUTS (outf, pregs (reg));
2454 
    }
2455 
  else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2456 
    {
2457 
      OUTS (outf, "W[");
2458 
      OUTS (outf, pregs (ptr));
2459 
      OUTS (outf, "] = ");
2460 
      OUTS (outf, dregs (reg));
2461 
    }
2462 
  else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2463 
    {
2464 
      OUTS (outf, "B[");
2465 
      OUTS (outf, pregs (ptr));
2466 
      OUTS (outf, "] = ");
2467 
      OUTS (outf, dregs (reg));
2468 
    }
2469 
  else
2470 
    return 0;
2471 
 
2472 
  return 2;
2473 
}
2474 
 
2475 
static int
2476 
decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2477 
{
2478 
  /* LDSTiiFP
2479 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2480 
     | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2481 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2482 
  int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2483 
  int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2484 
  int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2485 
 
2486 
  if (W == 0)
2487 
    {
2488 
      OUTS (outf, dpregs (reg));
2489 
      OUTS (outf, " = [FP ");
2490 
      OUTS (outf, negimm5s4 (offset));
2491 
      OUTS (outf, "]");
2492 
    }
2493 
  else if (W == 1)
2494 
    {
2495 
      OUTS (outf, "[FP ");
2496 
      OUTS (outf, negimm5s4 (offset));
2497 
      OUTS (outf, "] = ");
2498 
      OUTS (outf, dpregs (reg));
2499 
    }
2500 
  else
2501 
    return 0;
2502 
 
2503 
  return 2;
2504 
}
2505 
 
2506 
static int
2507 
decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2508 
{
2509 
  /* LDSTii
2510 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2511 
     | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2512 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2513 
  int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2514 
  int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2515 
  int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2516 
  int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2517 
  int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2518 
 
2519 
  if (W == 0 && op == 0)
2520 
    {
2521 
      OUTS (outf, dregs (reg));
2522 
      OUTS (outf, " = [");
2523 
      OUTS (outf, pregs (ptr));
2524 
      OUTS (outf, " + ");
2525 
      OUTS (outf, uimm4s4 (offset));
2526 
      OUTS (outf, "]");
2527 
    }
2528 
  else if (W == 0 && op == 1)
2529 
    {
2530 
      OUTS (outf, dregs (reg));
2531 
      OUTS (outf, " = W[");
2532 
      OUTS (outf, pregs (ptr));
2533 
      OUTS (outf, " + ");
2534 
      OUTS (outf, uimm4s2 (offset));
2535 
      OUTS (outf, "] (Z)");
2536 
    }
2537 
  else if (W == 0 && op == 2)
2538 
    {
2539 
      OUTS (outf, dregs (reg));
2540 
      OUTS (outf, " = W[");
2541 
      OUTS (outf, pregs (ptr));
2542 
      OUTS (outf, " + ");
2543 
      OUTS (outf, uimm4s2 (offset));
2544 
      OUTS (outf, "] (X)");
2545 
    }
2546 
  else if (W == 0 && op == 3)
2547 
    {
2548 
      OUTS (outf, pregs (reg));
2549 
      OUTS (outf, " = [");
2550 
      OUTS (outf, pregs (ptr));
2551 
      OUTS (outf, " + ");
2552 
      OUTS (outf, uimm4s4 (offset));
2553 
      OUTS (outf, "]");
2554 
    }
2555 
  else if (W == 1 && op == 0)
2556 
    {
2557 
      OUTS (outf, "[");
2558 
      OUTS (outf, pregs (ptr));
2559 
      OUTS (outf, " + ");
2560 
      OUTS (outf, uimm4s4 (offset));
2561 
      OUTS (outf, "] = ");
2562 
      OUTS (outf, dregs (reg));
2563 
    }
2564 
  else if (W == 1 && op == 1)
2565 
    {
2566 
      OUTS (outf, "W[");
2567 
      OUTS (outf, pregs (ptr));
2568 
      OUTS (outf, " + ");
2569 
      OUTS (outf, uimm4s2 (offset));
2570 
      OUTS (outf, "] = ");
2571 
      OUTS (outf, dregs (reg));
2572 
    }
2573 
  else if (W == 1 && op == 3)
2574 
    {
2575 
      OUTS (outf, "[");
2576 
      OUTS (outf, pregs (ptr));
2577 
      OUTS (outf, " + ");
2578 
      OUTS (outf, uimm4s4 (offset));
2579 
      OUTS (outf, "] = ");
2580 
      OUTS (outf, pregs (reg));
2581 
    }
2582 
  else
2583 
    return 0;
2584 
 
2585 
  return 2;
2586 
}
2587 
 
2588 
static int
2589 
decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2590 
{
2591 
  /* LoopSetup
2592 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2593 
     | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2594 
     |.reg...........| - | - |.eoffset...............................|
2595 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2596 
  int c   = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2597 
  int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2598 
  int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2599 
  int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2600 
  int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2601 
 
2602 
  if (parallel)
2603 
    return 0;
2604 
 
2605 
  if (reg > 7)
2606 
    return 0;
2607 
 
2608 
  if (rop == 0)
2609 
    {
2610 
      OUTS (outf, "LSETUP");
2611 
      OUTS (outf, "(0x");
2612 
      OUTS (outf, pcrel4 (soffset));
2613 
      OUTS (outf, ", 0x");
2614 
      OUTS (outf, lppcrel10 (eoffset));
2615 
      OUTS (outf, ") ");
2616 
      OUTS (outf, counters (c));
2617 
    }
2618 
  else if (rop == 1)
2619 
    {
2620 
      OUTS (outf, "LSETUP");
2621 
      OUTS (outf, "(0x");
2622 
      OUTS (outf, pcrel4 (soffset));
2623 
      OUTS (outf, ", 0x");
2624 
      OUTS (outf, lppcrel10 (eoffset));
2625 
      OUTS (outf, ") ");
2626 
      OUTS (outf, counters (c));
2627 
      OUTS (outf, " = ");
2628 
      OUTS (outf, pregs (reg));
2629 
    }
2630 
  else if (rop == 3)
2631 
    {
2632 
      OUTS (outf, "LSETUP");
2633 
      OUTS (outf, "(0x");
2634 
      OUTS (outf, pcrel4 (soffset));
2635 
      OUTS (outf, ", 0x");
2636 
      OUTS (outf, lppcrel10 (eoffset));
2637 
      OUTS (outf, ") ");
2638 
      OUTS (outf, counters (c));
2639 
      OUTS (outf, " = ");
2640 
      OUTS (outf, pregs (reg));
2641 
      OUTS (outf, " >> 0x1");
2642 
    }
2643 
  else
2644 
    return 0;
2645 
 
2646 
  return 4;
2647 
}
2648 
 
2649 
static int
2650 
decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2651 
{
2652 
  /* LDIMMhalf
2653 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2654 
     | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2655 
     |.hword.........................................................|
2656 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2657 
  int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2658 
  int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2659 
  int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2660 
  int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2661 
  int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2662 
  int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2663 
 
2664 
  bu32 *pval = get_allreg (grp, reg);
2665 
 
2666 
  if (parallel)
2667 
    return 0;
2668 
 
2669 
  /* Since we don't have 32-bit immediate loads, we allow the disassembler
2670 
     to combine them, so it prints out the right values.
2671 
     Here we keep track of the registers.  */
2672 
  if (H == 0 && S == 1 && Z == 0)
2673 
    {
2674 
      /* regs = imm16 (x) */
2675 
      *pval = imm16_val (hword);
2676 
      if (hword & 0x8000)
2677 
        *pval |= 0xFFFF0000;
2678 
      else
2679 
        *pval &= 0xFFFF;
2680 
    }
2681 
  else if (H == 0 && S == 0 && Z == 1)
2682 
    {
2683 
      /* regs = luimm16 (Z) */
2684 
      *pval = luimm16_val (hword);
2685 
      *pval &= 0xFFFF;
2686 
    }
2687 
  else if (H == 0 && S == 0 && Z == 0)
2688 
    {
2689 
      /* regs_lo = luimm16 */
2690 
      *pval &= 0xFFFF0000;
2691 
      *pval |= luimm16_val (hword);
2692 
    }
2693 
  else if (H == 1 && S == 0 && Z == 0)
2694 
    {
2695 
      /* regs_hi = huimm16 */
2696 
      *pval &= 0xFFFF;
2697 
      *pval |= luimm16_val (hword) << 16;
2698 
    }
2699 
 
2700 
  /* Here we do the disassembly */
2701 
  if (grp == 0 && H == 0 && S == 0 && Z == 0)
2702 
    {
2703 
      OUTS (outf, dregs_lo (reg));
2704 
      OUTS (outf, " = ");
2705 
      OUTS (outf, uimm16 (hword));
2706 
    }
2707 
  else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2708 
    {
2709 
      OUTS (outf, dregs_hi (reg));
2710 
      OUTS (outf, " = ");
2711 
      OUTS (outf, uimm16 (hword));
2712 
    }
2713 
  else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2714 
    {
2715 
      OUTS (outf, dregs (reg));
2716 
      OUTS (outf, " = ");
2717 
      OUTS (outf, imm16 (hword));
2718 
      OUTS (outf, " (X)");
2719 
    }
2720 
  else if (H == 0 && S == 1 && Z == 0)
2721 
    {
2722 
      OUTS (outf, regs (reg, grp));
2723 
      OUTS (outf, " = ");
2724 
      OUTS (outf, imm16 (hword));
2725 
      OUTS (outf, " (X)");
2726 
    }
2727 
  else if (H == 0 && S == 0 && Z == 1)
2728 
    {
2729 
      OUTS (outf, regs (reg, grp));
2730 
      OUTS (outf, " = ");
2731 
      OUTS (outf, uimm16 (hword));
2732 
      OUTS (outf, " (Z)");
2733 
    }
2734 
  else if (H == 0 && S == 0 && Z == 0)
2735 
    {
2736 
      OUTS (outf, regs_lo (reg, grp));
2737 
      OUTS (outf, " = ");
2738 
      OUTS (outf, uimm16 (hword));
2739 
    }
2740 
  else if (H == 1 && S == 0 && Z == 0)
2741 
    {
2742 
      OUTS (outf, regs_hi (reg, grp));
2743 
      OUTS (outf, " = ");
2744 
      OUTS (outf, uimm16 (hword));
2745 
    }
2746 
  else
2747 
    return 0;
2748 
 
2749 
  /* And we print out the 32-bit value if it is a pointer.  */
2750 
  if (S == 0 && Z == 0)
2751 
    {
2752 
      OUTS (outf, ";\t\t/* (");
2753 
      OUTS (outf, imm16d (hword));
2754 
      OUTS (outf, ")\t");
2755 
 
2756 
      /* If it is an MMR, don't print the symbol.  */
2757 
      if (*pval < 0xFFC00000 && grp == 1)
2758 
        {
2759 
          OUTS (outf, regs (reg, grp));
2760 
          OUTS (outf, "=0x");
2761 
          OUTS (outf, huimm32e (*pval));
2762 
        }
2763 
      else
2764 
        {
2765 
          OUTS (outf, regs (reg, grp));
2766 
          OUTS (outf, "=0x");
2767 
          OUTS (outf, huimm32e (*pval));
2768 
          OUTS (outf, "(");
2769 
          OUTS (outf, imm32 (*pval));
2770 
          OUTS (outf, ")");
2771 
        }
2772 
 
2773 
      OUTS (outf, " */");
2774 
      comment = 1;
2775 
    }
2776 
  if (S == 1 || Z == 1)
2777 
    {
2778 
      OUTS (outf, ";\t\t/*\t\t");
2779 
      OUTS (outf, regs (reg, grp));
2780 
      OUTS (outf, "=0x");
2781 
      OUTS (outf, huimm32e (*pval));
2782 
      OUTS (outf, "(");
2783 
      OUTS (outf, imm32 (*pval));
2784 
      OUTS (outf, ") */");
2785 
      comment = 1;
2786 
    }
2787 
  return 4;
2788 
}
2789 
 
2790 
static int
2791 
decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2792 
{
2793 
  /* CALLa
2794 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2795 
     | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2796 
     |.lsw...........................................................|
2797 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2798 
  int S   = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2799 
  int lsw = ((iw1 >> 0) & 0xffff);
2800 
  int msw = ((iw0 >> 0) & 0xff);
2801 
 
2802 
  if (parallel)
2803 
    return 0;
2804 
 
2805 
  if (S == 1)
2806 
    OUTS (outf, "CALL 0x");
2807 
  else if (S == 0)
2808 
    OUTS (outf, "JUMP.L 0x");
2809 
  else
2810 
    return 0;
2811 
 
2812 
  OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2813 
  return 4;
2814 
}
2815 
 
2816 
static int
2817 
decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2818 
{
2819 
  /* LDSTidxI
2820 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2821 
     | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2822 
     |.offset........................................................|
2823 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2824 
  int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2825 
  int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2826 
  int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2827 
  int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2828 
  int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2829 
  int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2830 
 
2831 
  if (W == 0 && sz == 0 && Z == 0)
2832 
    {
2833 
      OUTS (outf, dregs (reg));
2834 
      OUTS (outf, " = [");
2835 
      OUTS (outf, pregs (ptr));
2836 
      OUTS (outf, " + ");
2837 
      OUTS (outf, imm16s4 (offset));
2838 
      OUTS (outf, "]");
2839 
    }
2840 
  else if (W == 0 && sz == 0 && Z == 1)
2841 
    {
2842 
      OUTS (outf, pregs (reg));
2843 
      OUTS (outf, " = [");
2844 
      OUTS (outf, pregs (ptr));
2845 
      OUTS (outf, " + ");
2846 
      OUTS (outf, imm16s4 (offset));
2847 
      OUTS (outf, "]");
2848 
    }
2849 
  else if (W == 0 && sz == 1 && Z == 0)
2850 
    {
2851 
      OUTS (outf, dregs (reg));
2852 
      OUTS (outf, " = W[");
2853 
      OUTS (outf, pregs (ptr));
2854 
      OUTS (outf, " + ");
2855 
      OUTS (outf, imm16s2 (offset));
2856 
      OUTS (outf, "] (Z)");
2857 
    }
2858 
  else if (W == 0 && sz == 1 && Z == 1)
2859 
    {
2860 
      OUTS (outf, dregs (reg));
2861 
      OUTS (outf, " = W[");
2862 
      OUTS (outf, pregs (ptr));
2863 
      OUTS (outf, " + ");
2864 
      OUTS (outf, imm16s2 (offset));
2865 
      OUTS (outf, "] (X)");
2866 
    }
2867 
  else if (W == 0 && sz == 2 && Z == 0)
2868 
    {
2869 
      OUTS (outf, dregs (reg));
2870 
      OUTS (outf, " = B[");
2871 
      OUTS (outf, pregs (ptr));
2872 
      OUTS (outf, " + ");
2873 
      OUTS (outf, imm16 (offset));
2874 
      OUTS (outf, "] (Z)");
2875 
    }
2876 
  else if (W == 0 && sz == 2 && Z == 1)
2877 
    {
2878 
      OUTS (outf, dregs (reg));
2879 
      OUTS (outf, " = B[");
2880 
      OUTS (outf, pregs (ptr));
2881 
      OUTS (outf, " + ");
2882 
      OUTS (outf, imm16 (offset));
2883 
      OUTS (outf, "] (X)");
2884 
    }
2885 
  else if (W == 1 && sz == 0 && Z == 0)
2886 
    {
2887 
      OUTS (outf, "[");
2888 
      OUTS (outf, pregs (ptr));
2889 
      OUTS (outf, " + ");
2890 
      OUTS (outf, imm16s4 (offset));
2891 
      OUTS (outf, "] = ");
2892 
      OUTS (outf, dregs (reg));
2893 
    }
2894 
  else if (W == 1 && sz == 0 && Z == 1)
2895 
    {
2896 
      OUTS (outf, "[");
2897 
      OUTS (outf, pregs (ptr));
2898 
      OUTS (outf, " + ");
2899 
      OUTS (outf, imm16s4 (offset));
2900 
      OUTS (outf, "] = ");
2901 
      OUTS (outf, pregs (reg));
2902 
    }
2903 
  else if (W == 1 && sz == 1 && Z == 0)
2904 
    {
2905 
      OUTS (outf, "W[");
2906 
      OUTS (outf, pregs (ptr));
2907 
      OUTS (outf, " + ");
2908 
      OUTS (outf, imm16s2 (offset));
2909 
      OUTS (outf, "] = ");
2910 
      OUTS (outf, dregs (reg));
2911 
    }
2912 
  else if (W == 1 && sz == 2 && Z == 0)
2913 
    {
2914 
      OUTS (outf, "B[");
2915 
      OUTS (outf, pregs (ptr));
2916 
      OUTS (outf, " + ");
2917 
      OUTS (outf, imm16 (offset));
2918 
      OUTS (outf, "] = ");
2919 
      OUTS (outf, dregs (reg));
2920 
    }
2921 
  else
2922 
    return 0;
2923 
 
2924 
  return 4;
2925 
}
2926 
 
2927 
static int
2928 
decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2929 
{
2930 
  /* linkage
2931 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2932 
     | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2933 
     |.framesize.....................................................|
2934 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2935 
  int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2936 
  int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2937 
 
2938 
  if (parallel)
2939 
    return 0;
2940 
 
2941 
  if (R == 0)
2942 
    {
2943 
      OUTS (outf, "LINK ");
2944 
      OUTS (outf, uimm16s4 (framesize));
2945 
      OUTS (outf, ";\t\t/* (");
2946 
      OUTS (outf, uimm16s4d (framesize));
2947 
      OUTS (outf, ") */");
2948 
      comment = 1;
2949 
    }
2950 
  else if (R == 1)
2951 
    OUTS (outf, "UNLINK");
2952 
  else
2953 
    return 0;
2954 
 
2955 
  return 4;
2956 
}
2957 
 
2958 
static int
2959 
decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2960 
{
2961 
  /* dsp32mac
2962 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2963 
     | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2964 
     |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2965 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2966 
  int op1  = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2967 
  int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2968 
  int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2969 
  int MM   = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2970 
  int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2971 
  int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2972 
  int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2973 
  int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2974 
  int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2975 
  int h10  = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2976 
  int h00  = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2977 
  int op0  = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2978 
  int h11  = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2979 
  int h01  = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2980 
 
2981 
  if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2982 
    return 0;
2983 
 
2984 
  if (op1 == 3 && MM)
2985 
    return 0;
2986 
 
2987 
  if ((w1 || w0) && mmod == M_W32)
2988 
    return 0;
2989 
 
2990 
  if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
2991 
    return 0;
2992 
 
2993 
  if (w1 == 1 || op1 != 3)
2994 
    {
2995 
      if (w1)
2996 
        OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
2997 
 
2998 
      if (op1 == 3)
2999 
        OUTS (outf, " = A1");
3000 
      else
3001 
        {
3002 
          if (w1)
3003 
            OUTS (outf, " = (");
3004 
          decode_macfunc (1, op1, h01, h11, src0, src1, outf);
3005 
          if (w1)
3006 
            OUTS (outf, ")");
3007 
        }
3008 
 
3009 
      if (w0 == 1 || op0 != 3)
3010 
        {
3011 
          if (MM)
3012 
            OUTS (outf, " (M)");
3013 
          OUTS (outf, ", ");
3014 
        }
3015 
    }
3016 
 
3017 
  if (w0 == 1 || op0 != 3)
3018 
    {
3019 
      /* Clear MM option since it only matters for MAC1, and if we made
3020 
         it this far, we've already shown it or we want to ignore it.  */
3021 
      MM = 0;
3022 
 
3023 
      if (w0)
3024 
        OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3025 
 
3026 
      if (op0 == 3)
3027 
        OUTS (outf, " = A0");
3028 
      else
3029 
        {
3030 
          if (w0)
3031 
            OUTS (outf, " = (");
3032 
          decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3033 
          if (w0)
3034 
            OUTS (outf, ")");
3035 
        }
3036 
    }
3037 
 
3038 
  decode_optmode (mmod, MM, outf);
3039 
 
3040 
  return 4;
3041 
}
3042 
 
3043 
static int
3044 
decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3045 
{
3046 
  /* dsp32mult
3047 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3048 
     | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3049 
     |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3050 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
3051 
  int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3052 
  int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3053 
  int MM   = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
3054 
  int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
3055 
  int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
3056 
  int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3057 
  int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
3058 
  int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3059 
  int h10  = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3060 
  int h00  = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3061 
  int h11  = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3062 
  int h01  = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3063 
 
3064 
  if (w1 == 0 && w0 == 0)
3065 
    return 0;
3066 
 
3067 
  if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3068 
    return 0;
3069 
 
3070 
  if (w1)
3071 
    {
3072 
      OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3073 
      OUTS (outf, " = ");
3074 
      decode_multfunc (h01, h11, src0, src1, outf);
3075 
 
3076 
      if (w0)
3077 
        {
3078 
          if (MM)
3079 
            OUTS (outf, " (M)");
3080 
          MM = 0;
3081 
          OUTS (outf, ", ");
3082 
        }
3083 
    }
3084 
 
3085 
  if (w0)
3086 
    {
3087 
      OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3088 
      OUTS (outf, " = ");
3089 
      decode_multfunc (h00, h10, src0, src1, outf);
3090 
    }
3091 
 
3092 
  decode_optmode (mmod, MM, outf);
3093 
  return 4;
3094 
}
3095 
 
3096 
static int
3097 
decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3098 
{
3099 
  /* dsp32alu
3100 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3101 
     | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3102 
     |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3103 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
3104 
  int s    = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3105 
  int x    = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3106 
  int aop  = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3107 
  int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3108 
  int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3109 
  int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3110 
  int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3111 
  int HL   = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3112 
  int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3113 
 
3114 
  if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3115 
    {
3116 
      OUTS (outf, "A0.L = ");
3117 
      OUTS (outf, dregs_lo (src0));
3118 
    }
3119 
  else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3120 
    {
3121 
      OUTS (outf, "A1.H = ");
3122 
      OUTS (outf, dregs_hi (src0));
3123 
    }
3124 
  else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3125 
    {
3126 
      OUTS (outf, "A1.L = ");
3127 
      OUTS (outf, dregs_lo (src0));
3128 
    }
3129 
  else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3130 
    {
3131 
      OUTS (outf, "A0.H = ");
3132 
      OUTS (outf, dregs_hi (src0));
3133 
    }
3134 
  else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3135 
    {
3136 
      OUTS (outf, dregs_hi (dst0));
3137 
      OUTS (outf, " = ");
3138 
      OUTS (outf, dregs (src0));
3139 
      OUTS (outf, " - ");
3140 
      OUTS (outf, dregs (src1));
3141 
      OUTS (outf, " (RND20)");
3142 
    }
3143 
  else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3144 
    {
3145 
      OUTS (outf, dregs_hi (dst0));
3146 
      OUTS (outf, " = ");
3147 
      OUTS (outf, dregs (src0));
3148 
      OUTS (outf, " + ");
3149 
      OUTS (outf, dregs (src1));
3150 
      OUTS (outf, " (RND20)");
3151 
    }
3152 
  else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3153 
    {
3154 
      OUTS (outf, dregs_lo (dst0));
3155 
      OUTS (outf, " = ");
3156 
      OUTS (outf, dregs (src0));
3157 
      OUTS (outf, " - ");
3158 
      OUTS (outf, dregs (src1));
3159 
      OUTS (outf, " (RND12)");
3160 
    }
3161 
  else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3162 
    {
3163 
      OUTS (outf, dregs_lo (dst0));
3164 
      OUTS (outf, " = ");
3165 
      OUTS (outf, dregs (src0));
3166 
      OUTS (outf, " + ");
3167 
      OUTS (outf, dregs (src1));
3168 
      OUTS (outf, " (RND12)");
3169 
    }
3170 
  else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3171 
    {
3172 
      OUTS (outf, dregs_lo (dst0));
3173 
      OUTS (outf, " = ");
3174 
      OUTS (outf, dregs (src0));
3175 
      OUTS (outf, " - ");
3176 
      OUTS (outf, dregs (src1));
3177 
      OUTS (outf, " (RND20)");
3178 
    }
3179 
  else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3180 
    {
3181 
      OUTS (outf, dregs_hi (dst0));
3182 
      OUTS (outf, " = ");
3183 
      OUTS (outf, dregs (src0));
3184 
      OUTS (outf, " + ");
3185 
      OUTS (outf, dregs (src1));
3186 
      OUTS (outf, " (RND12)");
3187 
    }
3188 
  else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3189 
    {
3190 
      OUTS (outf, dregs_lo (dst0));
3191 
      OUTS (outf, " = ");
3192 
      OUTS (outf, dregs (src0));
3193 
      OUTS (outf, " + ");
3194 
      OUTS (outf, dregs (src1));
3195 
      OUTS (outf, " (RND20)");
3196 
    }
3197 
  else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3198 
    {
3199 
      OUTS (outf, dregs_hi (dst0));
3200 
      OUTS (outf, " = ");
3201 
      OUTS (outf, dregs (src0));
3202 
      OUTS (outf, " - ");
3203 
      OUTS (outf, dregs (src1));
3204 
      OUTS (outf, " (RND12)");
3205 
    }
3206 
  else if (HL == 1 && aop == 0 && aopcde == 2)
3207 
    {
3208 
      OUTS (outf, dregs_hi (dst0));
3209 
      OUTS (outf, " = ");
3210 
      OUTS (outf, dregs_lo (src0));
3211 
      OUTS (outf, " + ");
3212 
      OUTS (outf, dregs_lo (src1));
3213 
      amod1 (s, x, outf);
3214 
    }
3215 
  else if (HL == 1 && aop == 1 && aopcde == 2)
3216 
    {
3217 
      OUTS (outf, dregs_hi (dst0));
3218 
      OUTS (outf, " = ");
3219 
      OUTS (outf, dregs_lo (src0));
3220 
      OUTS (outf, " + ");
3221 
      OUTS (outf, dregs_hi (src1));
3222 
      amod1 (s, x, outf);
3223 
    }
3224 
  else if (HL == 1 && aop == 2 && aopcde == 2)
3225 
    {
3226 
      OUTS (outf, dregs_hi (dst0));
3227 
      OUTS (outf, " = ");
3228 
      OUTS (outf, dregs_hi (src0));
3229 
      OUTS (outf, " + ");
3230 
      OUTS (outf, dregs_lo (src1));
3231 
      amod1 (s, x, outf);
3232 
    }
3233 
  else if (HL == 1 && aop == 3 && aopcde == 2)
3234 
    {
3235 
      OUTS (outf, dregs_hi (dst0));
3236 
      OUTS (outf, " = ");
3237 
      OUTS (outf, dregs_hi (src0));
3238 
      OUTS (outf, " + ");
3239 
      OUTS (outf, dregs_hi (src1));
3240 
      amod1 (s, x, outf);
3241 
    }
3242 
  else if (HL == 0 && aop == 0 && aopcde == 3)
3243 
    {
3244 
      OUTS (outf, dregs_lo (dst0));
3245 
      OUTS (outf, " = ");
3246 
      OUTS (outf, dregs_lo (src0));
3247 
      OUTS (outf, " - ");
3248 
      OUTS (outf, dregs_lo (src1));
3249 
      amod1 (s, x, outf);
3250 
    }
3251 
  else if (HL == 0 && aop == 1 && aopcde == 3)
3252 
    {
3253 
      OUTS (outf, dregs_lo (dst0));
3254 
      OUTS (outf, " = ");
3255 
      OUTS (outf, dregs_lo (src0));
3256 
      OUTS (outf, " - ");
3257 
      OUTS (outf, dregs_hi (src1));
3258 
      amod1 (s, x, outf);
3259 
    }
3260 
  else if (HL == 0 && aop == 3 && aopcde == 2)
3261 
    {
3262 
      OUTS (outf, dregs_lo (dst0));
3263 
      OUTS (outf, " = ");
3264 
      OUTS (outf, dregs_hi (src0));
3265 
      OUTS (outf, " + ");
3266 
      OUTS (outf, dregs_hi (src1));
3267 
      amod1 (s, x, outf);
3268 
    }
3269 
  else if (HL == 1 && aop == 0 && aopcde == 3)
3270 
    {
3271 
      OUTS (outf, dregs_hi (dst0));
3272 
      OUTS (outf, " = ");
3273 
      OUTS (outf, dregs_lo (src0));
3274 
      OUTS (outf, " - ");
3275 
      OUTS (outf, dregs_lo (src1));
3276 
      amod1 (s, x, outf);
3277 
    }
3278 
  else if (HL == 1 && aop == 1 && aopcde == 3)
3279 
    {
3280 
      OUTS (outf, dregs_hi (dst0));
3281 
      OUTS (outf, " = ");
3282 
      OUTS (outf, dregs_lo (src0));
3283 
      OUTS (outf, " - ");
3284 
      OUTS (outf, dregs_hi (src1));
3285 
      amod1 (s, x, outf);
3286 
    }
3287 
  else if (HL == 1 && aop == 2 && aopcde == 3)
3288 
    {
3289 
      OUTS (outf, dregs_hi (dst0));
3290 
      OUTS (outf, " = ");
3291 
      OUTS (outf, dregs_hi (src0));
3292 
      OUTS (outf, " - ");
3293 
      OUTS (outf, dregs_lo (src1));
3294 
      amod1 (s, x, outf);
3295 
    }
3296 
  else if (HL == 1 && aop == 3 && aopcde == 3)
3297 
    {
3298 
      OUTS (outf, dregs_hi (dst0));
3299 
      OUTS (outf, " = ");
3300 
      OUTS (outf, dregs_hi (src0));
3301 
      OUTS (outf, " - ");
3302 
      OUTS (outf, dregs_hi (src1));
3303 
      amod1 (s, x, outf);
3304 
    }
3305 
  else if (HL == 0 && aop == 2 && aopcde == 2)
3306 
    {
3307 
      OUTS (outf, dregs_lo (dst0));
3308 
      OUTS (outf, " = ");
3309 
      OUTS (outf, dregs_hi (src0));
3310 
      OUTS (outf, " + ");
3311 
      OUTS (outf, dregs_lo (src1));
3312 
      amod1 (s, x, outf);
3313 
    }
3314 
  else if (HL == 0 && aop == 1 && aopcde == 2)
3315 
    {
3316 
      OUTS (outf, dregs_lo (dst0));
3317 
      OUTS (outf, " = ");
3318 
      OUTS (outf, dregs_lo (src0));
3319 
      OUTS (outf, " + ");
3320 
      OUTS (outf, dregs_hi (src1));
3321 
      amod1 (s, x, outf);
3322 
    }
3323 
  else if (HL == 0 && aop == 2 && aopcde == 3)
3324 
    {
3325 
      OUTS (outf, dregs_lo (dst0));
3326 
      OUTS (outf, " = ");
3327 
      OUTS (outf, dregs_hi (src0));
3328 
      OUTS (outf, " - ");
3329 
      OUTS (outf, dregs_lo (src1));
3330 
      amod1 (s, x, outf);
3331 
    }
3332 
  else if (HL == 0 && aop == 3 && aopcde == 3)
3333 
    {
3334 
      OUTS (outf, dregs_lo (dst0));
3335 
      OUTS (outf, " = ");
3336 
      OUTS (outf, dregs_hi (src0));
3337 
      OUTS (outf, " - ");
3338 
      OUTS (outf, dregs_hi (src1));
3339 
      amod1 (s, x, outf);
3340 
    }
3341 
  else if (HL == 0 && aop == 0 && aopcde == 2)
3342 
    {
3343 
      OUTS (outf, dregs_lo (dst0));
3344 
      OUTS (outf, " = ");
3345 
      OUTS (outf, dregs_lo (src0));
3346 
      OUTS (outf, " + ");
3347 
      OUTS (outf, dregs_lo (src1));
3348 
      amod1 (s, x, outf);
3349 
    }
3350 
  else if (aop == 0 && aopcde == 9 && s == 1)
3351 
    {
3352 
      OUTS (outf, "A0 = ");
3353 
      OUTS (outf, dregs (src0));
3354 
    }
3355 
  else if (aop == 3 && aopcde == 11 && s == 0)
3356 
    OUTS (outf, "A0 -= A1");
3357 
 
3358 
  else if (aop == 3 && aopcde == 11 && s == 1)
3359 
    OUTS (outf, "A0 -= A1 (W32)");
3360 
 
3361 
  else if (aop == 1 && aopcde == 22 && HL == 1)
3362 
    {
3363 
      OUTS (outf, dregs (dst0));
3364 
      OUTS (outf, " = BYTEOP2P (");
3365 
      OUTS (outf, dregs (src0 + 1));
3366 
      OUTS (outf, ":");
3367 
      OUTS (outf, imm5d (src0));
3368 
      OUTS (outf, ", ");
3369 
      OUTS (outf, dregs (src1 + 1));
3370 
      OUTS (outf, ":");
3371 
      OUTS (outf, imm5d (src1));
3372 
      OUTS (outf, ") (TH");
3373 
      if (s == 1)
3374 
        OUTS (outf, ", R)");
3375 
      else
3376 
        OUTS (outf, ")");
3377 
    }
3378 
  else if (aop == 1 && aopcde == 22 && HL == 0)
3379 
    {
3380 
      OUTS (outf, dregs (dst0));
3381 
      OUTS (outf, " = BYTEOP2P (");
3382 
      OUTS (outf, dregs (src0 + 1));
3383 
      OUTS (outf, ":");
3384 
      OUTS (outf, imm5d (src0));
3385 
      OUTS (outf, ", ");
3386 
      OUTS (outf, dregs (src1 + 1));
3387 
      OUTS (outf, ":");
3388 
      OUTS (outf, imm5d (src1));
3389 
      OUTS (outf, ") (TL");
3390 
      if (s == 1)
3391 
        OUTS (outf, ", R)");
3392 
      else
3393 
        OUTS (outf, ")");
3394 
    }
3395 
  else if (aop == 0 && aopcde == 22 && HL == 1)
3396 
    {
3397 
      OUTS (outf, dregs (dst0));
3398 
      OUTS (outf, " = BYTEOP2P (");
3399 
      OUTS (outf, dregs (src0 + 1));
3400 
      OUTS (outf, ":");
3401 
      OUTS (outf, imm5d (src0));
3402 
      OUTS (outf, ", ");
3403 
      OUTS (outf, dregs (src1 + 1));
3404 
      OUTS (outf, ":");
3405 
      OUTS (outf, imm5d (src1));
3406 
      OUTS (outf, ") (RNDH");
3407 
      if (s == 1)
3408 
        OUTS (outf, ", R)");
3409 
      else
3410 
        OUTS (outf, ")");
3411 
    }
3412 
  else if (aop == 0 && aopcde == 22 && HL == 0)
3413 
    {
3414 
      OUTS (outf, dregs (dst0));
3415 
      OUTS (outf, " = BYTEOP2P (");
3416 
      OUTS (outf, dregs (src0 + 1));
3417 
      OUTS (outf, ":");
3418 
      OUTS (outf, imm5d (src0));
3419 
      OUTS (outf, ", ");
3420 
      OUTS (outf, dregs (src1 + 1));
3421 
      OUTS (outf, ":");
3422 
      OUTS (outf, imm5d (src1));
3423 
      OUTS (outf, ") (RNDL");
3424 
      if (s == 1)
3425 
        OUTS (outf, ", R)");
3426 
      else
3427 
        OUTS (outf, ")");
3428 
    }
3429 
  else if (aop == 0 && s == 0 && aopcde == 8)
3430 
    OUTS (outf, "A0 = 0");
3431 
 
3432 
  else if (aop == 0 && s == 1 && aopcde == 8)
3433 
    OUTS (outf, "A0 = A0 (S)");
3434 
 
3435 
  else if (aop == 1 && s == 0 && aopcde == 8)
3436 
    OUTS (outf, "A1 = 0");
3437 
 
3438 
  else if (aop == 1 && s == 1 && aopcde == 8)
3439 
    OUTS (outf, "A1 = A1 (S)");
3440 
 
3441 
  else if (aop == 2 && s == 0 && aopcde == 8)
3442 
    OUTS (outf, "A1 = A0 = 0");
3443 
 
3444 
  else if (aop == 2 && s == 1 && aopcde == 8)
3445 
    OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3446 
 
3447 
  else if (aop == 3 && s == 0 && aopcde == 8)
3448 
    OUTS (outf, "A0 = A1");
3449 
 
3450 
  else if (aop == 3 && s == 1 && aopcde == 8)
3451 
    OUTS (outf, "A1 = A0");
3452 
 
3453 
  else if (aop == 1 && aopcde == 9 && s == 0)
3454 
    {
3455 
      OUTS (outf, "A0.X = ");
3456 
      OUTS (outf, dregs_lo (src0));
3457 
    }
3458 
  else if (aop == 1 && HL == 0 && aopcde == 11)
3459 
    {
3460 
      OUTS (outf, dregs_lo (dst0));
3461 
      OUTS (outf, " = (A0 += A1)");
3462 
    }
3463 
  else if (aop == 3 && HL == 0 && aopcde == 16)
3464 
    OUTS (outf, "A1 = ABS A1, A0 = ABS A0");
3465 
 
3466 
  else if (aop == 0 && aopcde == 23 && HL == 1)
3467 
    {
3468 
      OUTS (outf, dregs (dst0));
3469 
      OUTS (outf, " = BYTEOP3P (");
3470 
      OUTS (outf, dregs (src0 + 1));
3471 
      OUTS (outf, ":");
3472 
      OUTS (outf, imm5d (src0));
3473 
      OUTS (outf, ", ");
3474 
      OUTS (outf, dregs (src1 + 1));
3475 
      OUTS (outf, ":");
3476 
      OUTS (outf, imm5d (src1));
3477 
      OUTS (outf, ") (HI");
3478 
      if (s == 1)
3479 
        OUTS (outf, ", R)");
3480 
      else
3481 
        OUTS (outf, ")");
3482 
    }
3483 
  else if (aop == 3 && aopcde == 9 && s == 0)
3484 
    {
3485 
      OUTS (outf, "A1.X = ");
3486 
      OUTS (outf, dregs_lo (src0));
3487 
    }
3488 
  else if (aop == 1 && HL == 1 && aopcde == 16)
3489 
    OUTS (outf, "A1 = ABS A1");
3490 
 
3491 
  else if (aop == 0 && HL == 1 && aopcde == 16)
3492 
    OUTS (outf, "A1 = ABS A0");
3493 
 
3494 
  else if (aop == 2 && aopcde == 9 && s == 1)
3495 
    {
3496 
      OUTS (outf, "A1 = ");
3497 
      OUTS (outf, dregs (src0));
3498 
    }
3499 
  else if (HL == 0 && aop == 3 && aopcde == 12)
3500 
    {
3501 
      OUTS (outf, dregs_lo (dst0));
3502 
      OUTS (outf, " = ");
3503 
      OUTS (outf, dregs (src0));
3504 
      OUTS (outf, " (RND)");
3505 
    }
3506 
  else if (aop == 1 && HL == 0 && aopcde == 16)
3507 
    OUTS (outf, "A0 = ABS A1");
3508 
 
3509 
  else if (aop == 0 && HL == 0 && aopcde == 16)
3510 
    OUTS (outf, "A0 = ABS A0");
3511 
 
3512 
  else if (aop == 3 && HL == 0 && aopcde == 15)
3513 
    {
3514 
      OUTS (outf, dregs (dst0));
3515 
      OUTS (outf, " = -");
3516 
      OUTS (outf, dregs (src0));
3517 
      OUTS (outf, " (V)");
3518 
    }
3519 
  else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3520 
    {
3521 
      OUTS (outf, dregs (dst0));
3522 
      OUTS (outf, " = -");
3523 
      OUTS (outf, dregs (src0));
3524 
      OUTS (outf, " (S)");
3525 
    }
3526 
  else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3527 
    {
3528 
      OUTS (outf, dregs (dst0));
3529 
      OUTS (outf, " = -");
3530 
      OUTS (outf, dregs (src0));
3531 
      OUTS (outf, " (NS)");
3532 
    }
3533 
  else if (aop == 1 && HL == 1 && aopcde == 11)
3534 
    {
3535 
      OUTS (outf, dregs_hi (dst0));
3536 
      OUTS (outf, " = (A0 += A1)");
3537 
    }
3538 
  else if (aop == 2 && aopcde == 11 && s == 0)
3539 
    OUTS (outf, "A0 += A1");
3540 
 
3541 
  else if (aop == 2 && aopcde == 11 && s == 1)
3542 
    OUTS (outf, "A0 += A1 (W32)");
3543 
 
3544 
  else if (aop == 3 && HL == 0 && aopcde == 14)
3545 
    OUTS (outf, "A1 = -A1, A0 = -A0");
3546 
 
3547 
  else if (HL == 1 && aop == 3 && aopcde == 12)
3548 
    {
3549 
      OUTS (outf, dregs_hi (dst0));
3550 
      OUTS (outf, " = ");
3551 
      OUTS (outf, dregs (src0));
3552 
      OUTS (outf, " (RND)");
3553 
    }
3554 
  else if (aop == 0 && aopcde == 23 && HL == 0)
3555 
    {
3556 
      OUTS (outf, dregs (dst0));
3557 
      OUTS (outf, " = BYTEOP3P (");
3558 
      OUTS (outf, dregs (src0 + 1));
3559 
      OUTS (outf, ":");
3560 
      OUTS (outf, imm5d (src0));
3561 
      OUTS (outf, ", ");
3562 
      OUTS (outf, dregs (src1 + 1));
3563 
      OUTS (outf, ":");
3564 
      OUTS (outf, imm5d (src1));
3565 
      OUTS (outf, ") (LO");
3566 
      if (s == 1)
3567 
        OUTS (outf, ", R)");
3568 
      else
3569 
        OUTS (outf, ")");
3570 
    }
3571 
  else if (aop == 0 && HL == 0 && aopcde == 14)
3572 
    OUTS (outf, "A0 = -A0");
3573 
 
3574 
  else if (aop == 1 && HL == 0 && aopcde == 14)
3575 
    OUTS (outf, "A0 = -A1");
3576 
 
3577 
  else if (aop == 0 && HL == 1 && aopcde == 14)
3578 
    OUTS (outf, "A1 = -A0");
3579 
 
3580 
  else if (aop == 1 && HL == 1 && aopcde == 14)
3581 
    OUTS (outf, "A1 = -A1");
3582 
 
3583 
  else if (aop == 0 && aopcde == 12)
3584 
    {
3585 
      OUTS (outf, dregs_hi (dst0));
3586 
      OUTS (outf, " = ");
3587 
      OUTS (outf, dregs_lo (dst0));
3588 
      OUTS (outf, " = SIGN (");
3589 
      OUTS (outf, dregs_hi (src0));
3590 
      OUTS (outf, ") * ");
3591 
      OUTS (outf, dregs_hi (src1));
3592 
      OUTS (outf, " + SIGN (");
3593 
      OUTS (outf, dregs_lo (src0));
3594 
      OUTS (outf, ") * ");
3595 
      OUTS (outf, dregs_lo (src1));
3596 
    }
3597 
  else if (aop == 2 && aopcde == 0)
3598 
    {
3599 
      OUTS (outf, dregs (dst0));
3600 
      OUTS (outf, " = ");
3601 
      OUTS (outf, dregs (src0));
3602 
      OUTS (outf, " -|+ ");
3603 
      OUTS (outf, dregs (src1));
3604 
      amod0 (s, x, outf);
3605 
    }
3606 
  else if (aop == 1 && aopcde == 12)
3607 
    {
3608 
      OUTS (outf, dregs (dst1));
3609 
      OUTS (outf, " = A1.L + A1.H, ");
3610 
      OUTS (outf, dregs (dst0));
3611 
      OUTS (outf, " = A0.L + A0.H");
3612 
    }
3613 
  else if (aop == 2 && aopcde == 4)
3614 
    {
3615 
      OUTS (outf, dregs (dst1));
3616 
      OUTS (outf, " = ");
3617 
      OUTS (outf, dregs (src0));
3618 
      OUTS (outf, " + ");
3619 
      OUTS (outf, dregs (src1));
3620 
      OUTS (outf, ", ");
3621 
      OUTS (outf, dregs (dst0));
3622 
      OUTS (outf, " = ");
3623 
      OUTS (outf, dregs (src0));
3624 
      OUTS (outf, " - ");
3625 
      OUTS (outf, dregs (src1));
3626 
      amod1 (s, x, outf);
3627 
    }
3628 
  else if (HL == 0 && aopcde == 1)
3629 
    {
3630 
      OUTS (outf, dregs (dst1));
3631 
      OUTS (outf, " = ");
3632 
      OUTS (outf, dregs (src0));
3633 
      OUTS (outf, " +|+ ");
3634 
      OUTS (outf, dregs (src1));
3635 
      OUTS (outf, ", ");
3636 
      OUTS (outf, dregs (dst0));
3637 
      OUTS (outf, " = ");
3638 
      OUTS (outf, dregs (src0));
3639 
      OUTS (outf, " -|- ");
3640 
      OUTS (outf, dregs (src1));
3641 
      amod0amod2 (s, x, aop, outf);
3642 
    }
3643 
  else if (aop == 0 && aopcde == 11)
3644 
    {
3645 
      OUTS (outf, dregs (dst0));
3646 
      OUTS (outf, " = (A0 += A1)");
3647 
    }
3648 
  else if (aop == 0 && aopcde == 10)
3649 
    {
3650 
      OUTS (outf, dregs_lo (dst0));
3651 
      OUTS (outf, " = A0.X");
3652 
    }
3653 
  else if (aop == 1 && aopcde == 10)
3654 
    {
3655 
      OUTS (outf, dregs_lo (dst0));
3656 
      OUTS (outf, " = A1.X");
3657 
    }
3658 
  else if (aop == 1 && aopcde == 0)
3659 
    {
3660 
      OUTS (outf, dregs (dst0));
3661 
      OUTS (outf, " = ");
3662 
      OUTS (outf, dregs (src0));
3663 
      OUTS (outf, " +|- ");
3664 
      OUTS (outf, dregs (src1));
3665 
      amod0 (s, x, outf);
3666 
    }
3667 
  else if (aop == 3 && aopcde == 0)
3668 
    {
3669 
      OUTS (outf, dregs (dst0));
3670 
      OUTS (outf, " = ");
3671 
      OUTS (outf, dregs (src0));
3672 
      OUTS (outf, " -|- ");
3673 
      OUTS (outf, dregs (src1));
3674 
      amod0 (s, x, outf);
3675 
    }
3676 
  else if (aop == 1 && aopcde == 4)
3677 
    {
3678 
      OUTS (outf, dregs (dst0));
3679 
      OUTS (outf, " = ");
3680 
      OUTS (outf, dregs (src0));
3681 
      OUTS (outf, " - ");
3682 
      OUTS (outf, dregs (src1));
3683 
      amod1 (s, x, outf);
3684 
    }
3685 
  else if (aop == 0 && aopcde == 17)
3686 
    {
3687 
      OUTS (outf, dregs (dst1));
3688 
      OUTS (outf, " = A1 + A0, ");
3689 
      OUTS (outf, dregs (dst0));
3690 
      OUTS (outf, " = A1 - A0");
3691 
      amod1 (s, x, outf);
3692 
    }
3693 
  else if (aop == 1 && aopcde == 17)
3694 
    {
3695 
      OUTS (outf, dregs (dst1));
3696 
      OUTS (outf, " = A0 + A1, ");
3697 
      OUTS (outf, dregs (dst0));
3698 
      OUTS (outf, " = A0 - A1");
3699 
      amod1 (s, x, outf);
3700 
    }
3701 
  else if (aop == 0 && aopcde == 18)
3702 
    {
3703 
      OUTS (outf, "SAA (");
3704 
      OUTS (outf, dregs (src0 + 1));
3705 
      OUTS (outf, ":");
3706 
      OUTS (outf, imm5d (src0));
3707 
      OUTS (outf, ", ");
3708 
      OUTS (outf, dregs (src1 + 1));
3709 
      OUTS (outf, ":");
3710 
      OUTS (outf, imm5d (src1));
3711 
      OUTS (outf, ")");
3712 
      aligndir (s, outf);
3713 
    }
3714 
  else if (aop == 3 && aopcde == 18)
3715 
    OUTS (outf, "DISALGNEXCPT");
3716 
 
3717 
  else if (aop == 0 && aopcde == 20)
3718 
    {
3719 
      OUTS (outf, dregs (dst0));
3720 
      OUTS (outf, " = BYTEOP1P (");
3721 
      OUTS (outf, dregs (src0 + 1));
3722 
      OUTS (outf, ":");
3723 
      OUTS (outf, imm5d (src0));
3724 
      OUTS (outf, ", ");
3725 
      OUTS (outf, dregs (src1 + 1));
3726 
      OUTS (outf, ":");
3727 
      OUTS (outf, imm5d (src1));
3728 
      OUTS (outf, ")");
3729 
      aligndir (s, outf);
3730 
    }
3731 
  else if (aop == 1 && aopcde == 20)
3732 
    {
3733 
      OUTS (outf, dregs (dst0));
3734 
      OUTS (outf, " = BYTEOP1P (");
3735 
      OUTS (outf, dregs (src0 + 1));
3736 
      OUTS (outf, ":");
3737 
      OUTS (outf, imm5d (src0));
3738 
      OUTS (outf, ", ");
3739 
      OUTS (outf, dregs (src1 + 1));
3740 
      OUTS (outf, ":");
3741 
      OUTS (outf, imm5d (src1));
3742 
      OUTS (outf, ") (T");
3743 
      if (s == 1)
3744 
        OUTS (outf, ", R)");
3745 
      else
3746 
        OUTS (outf, ")");
3747 
    }
3748 
  else if (aop == 0 && aopcde == 21)
3749 
    {
3750 
      OUTS (outf, "(");
3751 
      OUTS (outf, dregs (dst1));
3752 
      OUTS (outf, ", ");
3753 
      OUTS (outf, dregs (dst0));
3754 
      OUTS (outf, ") = BYTEOP16P (");
3755 
      OUTS (outf, dregs (src0 + 1));
3756 
      OUTS (outf, ":");
3757 
      OUTS (outf, imm5d (src0));
3758 
      OUTS (outf, ", ");
3759 
      OUTS (outf, dregs (src1 + 1));
3760 
      OUTS (outf, ":");
3761 
      OUTS (outf, imm5d (src1));
3762 
      OUTS (outf, ")");
3763 
      aligndir (s, outf);
3764 
    }
3765 
  else if (aop == 1 && aopcde == 21)
3766 
    {
3767 
      OUTS (outf, "(");
3768 
      OUTS (outf, dregs (dst1));
3769 
      OUTS (outf, ", ");
3770 
      OUTS (outf, dregs (dst0));
3771 
      OUTS (outf, ") = BYTEOP16M (");
3772 
      OUTS (outf, dregs (src0 + 1));
3773 
      OUTS (outf, ":");
3774 
      OUTS (outf, imm5d (src0));
3775 
      OUTS (outf, ", ");
3776 
      OUTS (outf, dregs (src1 + 1));
3777 
      OUTS (outf, ":");
3778 
      OUTS (outf, imm5d (src1));
3779 
      OUTS (outf, ")");
3780 
      aligndir (s, outf);
3781 
    }
3782 
  else if (aop == 2 && aopcde == 7)
3783 
    {
3784 
      OUTS (outf, dregs (dst0));
3785 
      OUTS (outf, " = ABS ");
3786 
      OUTS (outf, dregs (src0));
3787 
    }
3788 
  else if (aop == 1 && aopcde == 7)
3789 
    {
3790 
      OUTS (outf, dregs (dst0));
3791 
      OUTS (outf, " = MIN (");
3792 
      OUTS (outf, dregs (src0));
3793 
      OUTS (outf, ", ");
3794 
      OUTS (outf, dregs (src1));
3795 
      OUTS (outf, ")");
3796 
    }
3797 
  else if (aop == 0 && aopcde == 7)
3798 
    {
3799 
      OUTS (outf, dregs (dst0));
3800 
      OUTS (outf, " = MAX (");
3801 
      OUTS (outf, dregs (src0));
3802 
      OUTS (outf, ", ");
3803 
      OUTS (outf, dregs (src1));
3804 
      OUTS (outf, ")");
3805 
    }
3806 
  else if (aop == 2 && aopcde == 6)
3807 
    {
3808 
      OUTS (outf, dregs (dst0));
3809 
      OUTS (outf, " = ABS ");
3810 
      OUTS (outf, dregs (src0));
3811 
      OUTS (outf, " (V)");
3812 
    }
3813 
  else if (aop == 1 && aopcde == 6)
3814 
    {
3815 
      OUTS (outf, dregs (dst0));
3816 
      OUTS (outf, " = MIN (");
3817 
      OUTS (outf, dregs (src0));
3818 
      OUTS (outf, ", ");
3819 
      OUTS (outf, dregs (src1));
3820 
      OUTS (outf, ") (V)");
3821 
    }
3822 
  else if (aop == 0 && aopcde == 6)
3823 
    {
3824 
      OUTS (outf, dregs (dst0));
3825 
      OUTS (outf, " = MAX (");
3826 
      OUTS (outf, dregs (src0));
3827 
      OUTS (outf, ", ");
3828 
      OUTS (outf, dregs (src1));
3829 
      OUTS (outf, ") (V)");
3830 
    }
3831 
  else if (HL == 1 && aopcde == 1)
3832 
    {
3833 
      OUTS (outf, dregs (dst1));
3834 
      OUTS (outf, " = ");
3835 
      OUTS (outf, dregs (src0));
3836 
      OUTS (outf, " +|- ");
3837 
      OUTS (outf, dregs (src1));
3838 
      OUTS (outf, ", ");
3839 
      OUTS (outf, dregs (dst0));
3840 
      OUTS (outf, " = ");
3841 
      OUTS (outf, dregs (src0));
3842 
      OUTS (outf, " -|+ ");
3843 
      OUTS (outf, dregs (src1));
3844 
      amod0amod2 (s, x, aop, outf);
3845 
    }
3846 
  else if (aop == 0 && aopcde == 4)
3847 
    {
3848 
      OUTS (outf, dregs (dst0));
3849 
      OUTS (outf, " = ");
3850 
      OUTS (outf, dregs (src0));
3851 
      OUTS (outf, " + ");
3852 
      OUTS (outf, dregs (src1));
3853 
      amod1 (s, x, outf);
3854 
    }
3855 
  else if (aop == 0 && aopcde == 0)
3856 
    {
3857 
      OUTS (outf, dregs (dst0));
3858 
      OUTS (outf, " = ");
3859 
      OUTS (outf, dregs (src0));
3860 
      OUTS (outf, " +|+ ");
3861 
      OUTS (outf, dregs (src1));
3862 
      amod0 (s, x, outf);
3863 
    }
3864 
  else if (aop == 0 && aopcde == 24)
3865 
    {
3866 
      OUTS (outf, dregs (dst0));
3867 
      OUTS (outf, " = BYTEPACK (");
3868 
      OUTS (outf, dregs (src0));
3869 
      OUTS (outf, ", ");
3870 
      OUTS (outf, dregs (src1));
3871 
      OUTS (outf, ")");
3872 
    }
3873 
  else if (aop == 1 && aopcde == 24)
3874 
    {
3875 
      OUTS (outf, "(");
3876 
      OUTS (outf, dregs (dst1));
3877 
      OUTS (outf, ", ");
3878 
      OUTS (outf, dregs (dst0));
3879 
      OUTS (outf, ") = BYTEUNPACK ");
3880 
      OUTS (outf, dregs (src0 + 1));
3881 
      OUTS (outf, ":");
3882 
      OUTS (outf, imm5d (src0));
3883 
      aligndir (s, outf);
3884 
    }
3885 
  else if (aopcde == 13)
3886 
    {
3887 
      OUTS (outf, "(");
3888 
      OUTS (outf, dregs (dst1));
3889 
      OUTS (outf, ", ");
3890 
      OUTS (outf, dregs (dst0));
3891 
      OUTS (outf, ") = SEARCH ");
3892 
      OUTS (outf, dregs (src0));
3893 
      OUTS (outf, " (");
3894 
      searchmod (aop, outf);
3895 
      OUTS (outf, ")");
3896 
    }
3897 
  else
3898 
    return 0;
3899 
 
3900 
  return 4;
3901 
}
3902 
 
3903 
static int
3904 
decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3905 
{
3906 
  /* dsp32shift
3907 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3908 
     | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3909 
     |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3910 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
3911 
  int HLs  = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3912 
  int sop  = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3913 
  int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3914 
  int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3915 
  int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3916 
  int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3917 
  const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3918 
 
3919 
  if (HLs == 0 && sop == 0 && sopcde == 0)
3920 
    {
3921 
      OUTS (outf, dregs_lo (dst0));
3922 
      OUTS (outf, " = ASHIFT ");
3923 
      OUTS (outf, dregs_lo (src1));
3924 
      OUTS (outf, " BY ");
3925 
      OUTS (outf, dregs_lo (src0));
3926 
    }
3927 
  else if (HLs == 1 && sop == 0 && sopcde == 0)
3928 
    {
3929 
      OUTS (outf, dregs_lo (dst0));
3930 
      OUTS (outf, " = ASHIFT ");
3931 
      OUTS (outf, dregs_hi (src1));
3932 
      OUTS (outf, " BY ");
3933 
      OUTS (outf, dregs_lo (src0));
3934 
    }
3935 
  else if (HLs == 2 && sop == 0 && sopcde == 0)
3936 
    {
3937 
      OUTS (outf, dregs_hi (dst0));
3938 
      OUTS (outf, " = ASHIFT ");
3939 
      OUTS (outf, dregs_lo (src1));
3940 
      OUTS (outf, " BY ");
3941 
      OUTS (outf, dregs_lo (src0));
3942 
    }
3943 
  else if (HLs == 3 && sop == 0 && sopcde == 0)
3944 
    {
3945 
      OUTS (outf, dregs_hi (dst0));
3946 
      OUTS (outf, " = ASHIFT ");
3947 
      OUTS (outf, dregs_hi (src1));
3948 
      OUTS (outf, " BY ");
3949 
      OUTS (outf, dregs_lo (src0));
3950 
    }
3951 
  else if (HLs == 0 && sop == 1 && sopcde == 0)
3952 
    {
3953 
      OUTS (outf, dregs_lo (dst0));
3954 
      OUTS (outf, " = ASHIFT ");
3955 
      OUTS (outf, dregs_lo (src1));
3956 
      OUTS (outf, " BY ");
3957 
      OUTS (outf, dregs_lo (src0));
3958 
      OUTS (outf, " (S)");
3959 
    }
3960 
  else if (HLs == 1 && sop == 1 && sopcde == 0)
3961 
    {
3962 
      OUTS (outf, dregs_lo (dst0));
3963 
      OUTS (outf, " = ASHIFT ");
3964 
      OUTS (outf, dregs_hi (src1));
3965 
      OUTS (outf, " BY ");
3966 
      OUTS (outf, dregs_lo (src0));
3967 
      OUTS (outf, " (S)");
3968 
    }
3969 
  else if (HLs == 2 && sop == 1 && sopcde == 0)
3970 
    {
3971 
      OUTS (outf, dregs_hi (dst0));
3972 
      OUTS (outf, " = ASHIFT ");
3973 
      OUTS (outf, dregs_lo (src1));
3974 
      OUTS (outf, " BY ");
3975 
      OUTS (outf, dregs_lo (src0));
3976 
      OUTS (outf, " (S)");
3977 
    }
3978 
  else if (HLs == 3 && sop == 1 && sopcde == 0)
3979 
    {
3980 
      OUTS (outf, dregs_hi (dst0));
3981 
      OUTS (outf, " = ASHIFT ");
3982 
      OUTS (outf, dregs_hi (src1));
3983 
      OUTS (outf, " BY ");
3984 
      OUTS (outf, dregs_lo (src0));
3985 
      OUTS (outf, " (S)");
3986 
    }
3987 
  else if (sop == 2 && sopcde == 0)
3988 
    {
3989 
      OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
3990 
      OUTS (outf, " = LSHIFT ");
3991 
      OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
3992 
      OUTS (outf, " BY ");
3993 
      OUTS (outf, dregs_lo (src0));
3994 
    }
3995 
  else if (sop == 0 && sopcde == 3)
3996 
    {
3997 
      OUTS (outf, acc01);
3998 
      OUTS (outf, " = ASHIFT ");
3999 
      OUTS (outf, acc01);
4000 
      OUTS (outf, " BY ");
4001 
      OUTS (outf, dregs_lo (src0));
4002 
    }
4003 
  else if (sop == 1 && sopcde == 3)
4004 
    {
4005 
      OUTS (outf, acc01);
4006 
      OUTS (outf, " = LSHIFT ");
4007 
      OUTS (outf, acc01);
4008 
      OUTS (outf, " BY ");
4009 
      OUTS (outf, dregs_lo (src0));
4010 
    }
4011 
  else if (sop == 2 && sopcde == 3)
4012 
    {
4013 
      OUTS (outf, acc01);
4014 
      OUTS (outf, " = ROT ");
4015 
      OUTS (outf, acc01);
4016 
      OUTS (outf, " BY ");
4017 
      OUTS (outf, dregs_lo (src0));
4018 
    }
4019 
  else if (sop == 3 && sopcde == 3)
4020 
    {
4021 
      OUTS (outf, dregs (dst0));
4022 
      OUTS (outf, " = ROT ");
4023 
      OUTS (outf, dregs (src1));
4024 
      OUTS (outf, " BY ");
4025 
      OUTS (outf, dregs_lo (src0));
4026 
    }
4027 
  else if (sop == 1 && sopcde == 1)
4028 
    {
4029 
      OUTS (outf, dregs (dst0));
4030 
      OUTS (outf, " = ASHIFT ");
4031 
      OUTS (outf, dregs (src1));
4032 
      OUTS (outf, " BY ");
4033 
      OUTS (outf, dregs_lo (src0));
4034 
      OUTS (outf, " (V, S)");
4035 
    }
4036 
  else if (sop == 0 && sopcde == 1)
4037 
    {
4038 
      OUTS (outf, dregs (dst0));
4039 
      OUTS (outf, " = ASHIFT ");
4040 
      OUTS (outf, dregs (src1));
4041 
      OUTS (outf, " BY ");
4042 
      OUTS (outf, dregs_lo (src0));
4043 
      OUTS (outf, " (V)");
4044 
    }
4045 
  else if (sop == 0 && sopcde == 2)
4046 
    {
4047 
      OUTS (outf, dregs (dst0));
4048 
      OUTS (outf, " = ASHIFT ");
4049 
      OUTS (outf, dregs (src1));
4050 
      OUTS (outf, " BY ");
4051 
      OUTS (outf, dregs_lo (src0));
4052 
    }
4053 
  else if (sop == 1 && sopcde == 2)
4054 
    {
4055 
      OUTS (outf, dregs (dst0));
4056 
      OUTS (outf, " = ASHIFT ");
4057 
      OUTS (outf, dregs (src1));
4058 
      OUTS (outf, " BY ");
4059 
      OUTS (outf, dregs_lo (src0));
4060 
      OUTS (outf, " (S)");
4061 
    }
4062 
  else if (sop == 2 && sopcde == 2)
4063 
    {
4064 
      OUTS (outf, dregs (dst0));
4065 
      OUTS (outf, " = LSHIFT ");
4066 
      OUTS (outf, dregs (src1));
4067 
      OUTS (outf, " BY ");
4068 
      OUTS (outf, dregs_lo (src0));
4069 
    }
4070 
  else if (sop == 3 && sopcde == 2)
4071 
    {
4072 
      OUTS (outf, dregs (dst0));
4073 
      OUTS (outf, " = ROT ");
4074 
      OUTS (outf, dregs (src1));
4075 
      OUTS (outf, " BY ");
4076 
      OUTS (outf, dregs_lo (src0));
4077 
    }
4078 
  else if (sop == 2 && sopcde == 1)
4079 
    {
4080 
      OUTS (outf, dregs (dst0));
4081 
      OUTS (outf, " = LSHIFT ");
4082 
      OUTS (outf, dregs (src1));
4083 
      OUTS (outf, " BY ");
4084 
      OUTS (outf, dregs_lo (src0));
4085 
      OUTS (outf, " (V)");
4086 
    }
4087 
  else if (sop == 0 && sopcde == 4)
4088 
    {
4089 
      OUTS (outf, dregs (dst0));
4090 
      OUTS (outf, " = PACK (");
4091 
      OUTS (outf, dregs_lo (src1));
4092 
      OUTS (outf, ", ");
4093 
      OUTS (outf, dregs_lo (src0));
4094 
      OUTS (outf, ")");
4095 
    }
4096 
  else if (sop == 1 && sopcde == 4)
4097 
    {
4098 
      OUTS (outf, dregs (dst0));
4099 
      OUTS (outf, " = PACK (");
4100 
      OUTS (outf, dregs_lo (src1));
4101 
      OUTS (outf, ", ");
4102 
      OUTS (outf, dregs_hi (src0));
4103 
      OUTS (outf, ")");
4104 
    }
4105 
  else if (sop == 2 && sopcde == 4)
4106 
    {
4107 
      OUTS (outf, dregs (dst0));
4108 
      OUTS (outf, " = PACK (");
4109 
      OUTS (outf, dregs_hi (src1));
4110 
      OUTS (outf, ", ");
4111 
      OUTS (outf, dregs_lo (src0));
4112 
      OUTS (outf, ")");
4113 
    }
4114 
  else if (sop == 3 && sopcde == 4)
4115 
    {
4116 
      OUTS (outf, dregs (dst0));
4117 
      OUTS (outf, " = PACK (");
4118 
      OUTS (outf, dregs_hi (src1));
4119 
      OUTS (outf, ", ");
4120 
      OUTS (outf, dregs_hi (src0));
4121 
      OUTS (outf, ")");
4122 
    }
4123 
  else if (sop == 0 && sopcde == 5)
4124 
    {
4125 
      OUTS (outf, dregs_lo (dst0));
4126 
      OUTS (outf, " = SIGNBITS ");
4127 
      OUTS (outf, dregs (src1));
4128 
    }
4129 
  else if (sop == 1 && sopcde == 5)
4130 
    {
4131 
      OUTS (outf, dregs_lo (dst0));
4132 
      OUTS (outf, " = SIGNBITS ");
4133 
      OUTS (outf, dregs_lo (src1));
4134 
    }
4135 
  else if (sop == 2 && sopcde == 5)
4136 
    {
4137 
      OUTS (outf, dregs_lo (dst0));
4138 
      OUTS (outf, " = SIGNBITS ");
4139 
      OUTS (outf, dregs_hi (src1));
4140 
    }
4141 
  else if (sop == 0 && sopcde == 6)
4142 
    {
4143 
      OUTS (outf, dregs_lo (dst0));
4144 
      OUTS (outf, " = SIGNBITS A0");
4145 
    }
4146 
  else if (sop == 1 && sopcde == 6)
4147 
    {
4148 
      OUTS (outf, dregs_lo (dst0));
4149 
      OUTS (outf, " = SIGNBITS A1");
4150 
    }
4151 
  else if (sop == 3 && sopcde == 6)
4152 
    {
4153 
      OUTS (outf, dregs_lo (dst0));
4154 
      OUTS (outf, " = ONES ");
4155 
      OUTS (outf, dregs (src1));
4156 
    }
4157 
  else if (sop == 0 && sopcde == 7)
4158 
    {
4159 
      OUTS (outf, dregs_lo (dst0));
4160 
      OUTS (outf, " = EXPADJ (");
4161 
      OUTS (outf, dregs (src1));
4162 
      OUTS (outf, ", ");
4163 
      OUTS (outf, dregs_lo (src0));
4164 
      OUTS (outf, ")");
4165 
    }
4166 
  else if (sop == 1 && sopcde == 7)
4167 
    {
4168 
      OUTS (outf, dregs_lo (dst0));
4169 
      OUTS (outf, " = EXPADJ (");
4170 
      OUTS (outf, dregs (src1));
4171 
      OUTS (outf, ", ");
4172 
      OUTS (outf, dregs_lo (src0));
4173 
      OUTS (outf, ") (V)");
4174 
    }
4175 
  else if (sop == 2 && sopcde == 7)
4176 
    {
4177 
      OUTS (outf, dregs_lo (dst0));
4178 
      OUTS (outf, " = EXPADJ (");
4179 
      OUTS (outf, dregs_lo (src1));
4180 
      OUTS (outf, ", ");
4181 
      OUTS (outf, dregs_lo (src0));
4182 
      OUTS (outf, ")");
4183 
    }
4184 
  else if (sop == 3 && sopcde == 7)
4185 
    {
4186 
      OUTS (outf, dregs_lo (dst0));
4187 
      OUTS (outf, " = EXPADJ (");
4188 
      OUTS (outf, dregs_hi (src1));
4189 
      OUTS (outf, ", ");
4190 
      OUTS (outf, dregs_lo (src0));
4191 
      OUTS (outf, ")");
4192 
    }
4193 
  else if (sop == 0 && sopcde == 8)
4194 
    {
4195 
      OUTS (outf, "BITMUX (");
4196 
      OUTS (outf, dregs (src0));
4197 
      OUTS (outf, ", ");
4198 
      OUTS (outf, dregs (src1));
4199 
      OUTS (outf, ", A0) (ASR)");
4200 
    }
4201 
  else if (sop == 1 && sopcde == 8)
4202 
    {
4203 
      OUTS (outf, "BITMUX (");
4204 
      OUTS (outf, dregs (src0));
4205 
      OUTS (outf, ", ");
4206 
      OUTS (outf, dregs (src1));
4207 
      OUTS (outf, ", A0) (ASL)");
4208 
    }
4209 
  else if (sop == 0 && sopcde == 9)
4210 
    {
4211 
      OUTS (outf, dregs_lo (dst0));
4212 
      OUTS (outf, " = VIT_MAX (");
4213 
      OUTS (outf, dregs (src1));
4214 
      OUTS (outf, ") (ASL)");
4215 
    }
4216 
  else if (sop == 1 && sopcde == 9)
4217 
    {
4218 
      OUTS (outf, dregs_lo (dst0));
4219 
      OUTS (outf, " = VIT_MAX (");
4220 
      OUTS (outf, dregs (src1));
4221 
      OUTS (outf, ") (ASR)");
4222 
    }
4223 
  else if (sop == 2 && sopcde == 9)
4224 
    {
4225 
      OUTS (outf, dregs (dst0));
4226 
      OUTS (outf, " = VIT_MAX (");
4227 
      OUTS (outf, dregs (src1));
4228 
      OUTS (outf, ", ");
4229 
      OUTS (outf, dregs (src0));
4230 
      OUTS (outf, ") (ASL)");
4231 
    }
4232 
  else if (sop == 3 && sopcde == 9)
4233 
    {
4234 
      OUTS (outf, dregs (dst0));
4235 
      OUTS (outf, " = VIT_MAX (");
4236 
      OUTS (outf, dregs (src1));
4237 
      OUTS (outf, ", ");
4238 
      OUTS (outf, dregs (src0));
4239 
      OUTS (outf, ") (ASR)");
4240 
    }
4241 
  else if (sop == 0 && sopcde == 10)
4242 
    {
4243 
      OUTS (outf, dregs (dst0));
4244 
      OUTS (outf, " = EXTRACT (");
4245 
      OUTS (outf, dregs (src1));
4246 
      OUTS (outf, ", ");
4247 
      OUTS (outf, dregs_lo (src0));
4248 
      OUTS (outf, ") (Z)");
4249 
    }
4250 
  else if (sop == 1 && sopcde == 10)
4251 
    {
4252 
      OUTS (outf, dregs (dst0));
4253 
      OUTS (outf, " = EXTRACT (");
4254 
      OUTS (outf, dregs (src1));
4255 
      OUTS (outf, ", ");
4256 
      OUTS (outf, dregs_lo (src0));
4257 
      OUTS (outf, ") (X)");
4258 
    }
4259 
  else if (sop == 2 && sopcde == 10)
4260 
    {
4261 
      OUTS (outf, dregs (dst0));
4262 
      OUTS (outf, " = DEPOSIT (");
4263 
      OUTS (outf, dregs (src1));
4264 
      OUTS (outf, ", ");
4265 
      OUTS (outf, dregs (src0));
4266 
      OUTS (outf, ")");
4267 
    }
4268 
  else if (sop == 3 && sopcde == 10)
4269 
    {
4270 
      OUTS (outf, dregs (dst0));
4271 
      OUTS (outf, " = DEPOSIT (");
4272 
      OUTS (outf, dregs (src1));
4273 
      OUTS (outf, ", ");
4274 
      OUTS (outf, dregs (src0));
4275 
      OUTS (outf, ") (X)");
4276 
    }
4277 
  else if (sop == 0 && sopcde == 11)
4278 
    {
4279 
      OUTS (outf, dregs_lo (dst0));
4280 
      OUTS (outf, " = CC = BXORSHIFT (A0, ");
4281 
      OUTS (outf, dregs (src0));
4282 
      OUTS (outf, ")");
4283 
    }
4284 
  else if (sop == 1 && sopcde == 11)
4285 
    {
4286 
      OUTS (outf, dregs_lo (dst0));
4287 
      OUTS (outf, " = CC = BXOR (A0, ");
4288 
      OUTS (outf, dregs (src0));
4289 
      OUTS (outf, ")");
4290 
    }
4291 
  else if (sop == 0 && sopcde == 12)
4292 
    OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4293 
 
4294 
  else if (sop == 1 && sopcde == 12)
4295 
    {
4296 
      OUTS (outf, dregs_lo (dst0));
4297 
      OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4298 
    }
4299 
  else if (sop == 0 && sopcde == 13)
4300 
    {
4301 
      OUTS (outf, dregs (dst0));
4302 
      OUTS (outf, " = ALIGN8 (");
4303 
      OUTS (outf, dregs (src1));
4304 
      OUTS (outf, ", ");
4305 
      OUTS (outf, dregs (src0));
4306 
      OUTS (outf, ")");
4307 
    }
4308 
  else if (sop == 1 && sopcde == 13)
4309 
    {
4310 
      OUTS (outf, dregs (dst0));
4311 
      OUTS (outf, " = ALIGN16 (");
4312 
      OUTS (outf, dregs (src1));
4313 
      OUTS (outf, ", ");
4314 
      OUTS (outf, dregs (src0));
4315 
      OUTS (outf, ")");
4316 
    }
4317 
  else if (sop == 2 && sopcde == 13)
4318 
    {
4319 
      OUTS (outf, dregs (dst0));
4320 
      OUTS (outf, " = ALIGN24 (");
4321 
      OUTS (outf, dregs (src1));
4322 
      OUTS (outf, ", ");
4323 
      OUTS (outf, dregs (src0));
4324 
      OUTS (outf, ")");
4325 
    }
4326 
  else
4327 
    return 0;
4328 
 
4329 
  return 4;
4330 
}
4331 
 
4332 
static int
4333 
decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4334 
{
4335 
  /* dsp32shiftimm
4336 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4337 
     | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4338 
     |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4339 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
4340 
  int src1     = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4341 
  int sop      = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4342 
  int bit8     = ((iw1 >> 8) & 0x1);
4343 
  int immag    = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4344 
  int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4345 
  int dst0     = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4346 
  int sopcde   = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4347 
  int HLs      = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4348 
 
4349 
  if (sop == 0 && sopcde == 0)
4350 
    {
4351 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4352 
      OUTS (outf, " = ");
4353 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4354 
      OUTS (outf, " >>> ");
4355 
      OUTS (outf, uimm4 (newimmag));
4356 
    }
4357 
  else if (sop == 1 && sopcde == 0 && bit8 == 0)
4358 
    {
4359 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4360 
      OUTS (outf, " = ");
4361 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4362 
      OUTS (outf, " << ");
4363 
      OUTS (outf, uimm4 (immag));
4364 
      OUTS (outf, " (S)");
4365 
    }
4366 
  else if (sop == 1 && sopcde == 0 && bit8 == 1)
4367 
    {
4368 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4369 
      OUTS (outf, " = ");
4370 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4371 
      OUTS (outf, " >>> ");
4372 
      OUTS (outf, uimm4 (newimmag));
4373 
      OUTS (outf, " (S)");
4374 
    }
4375 
  else if (sop == 2 && sopcde == 0 && bit8 == 0)
4376 
    {
4377 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4378 
      OUTS (outf, " = ");
4379 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4380 
      OUTS (outf, " << ");
4381 
      OUTS (outf, uimm4 (immag));
4382 
    }
4383 
  else if (sop == 2 && sopcde == 0 && bit8 == 1)
4384 
    {
4385 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4386 
      OUTS (outf, " = ");
4387 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4388 
      OUTS (outf, " >> ");
4389 
      OUTS (outf, uimm4 (newimmag));
4390 
    }
4391 
  else if (sop == 2 && sopcde == 3 && HLs == 1)
4392 
    {
4393 
      OUTS (outf, "A1 = ROT A1 BY ");
4394 
      OUTS (outf, imm6 (immag));
4395 
    }
4396 
  else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4397 
    {
4398 
      OUTS (outf, "A0 = A0 << ");
4399 
      OUTS (outf, uimm5 (immag));
4400 
    }
4401 
  else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4402 
    {
4403 
      OUTS (outf, "A0 = A0 >>> ");
4404 
      OUTS (outf, uimm5 (newimmag));
4405 
    }
4406 
  else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4407 
    {
4408 
      OUTS (outf, "A1 = A1 << ");
4409 
      OUTS (outf, uimm5 (immag));
4410 
    }
4411 
  else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4412 
    {
4413 
      OUTS (outf, "A1 = A1 >>> ");
4414 
      OUTS (outf, uimm5 (newimmag));
4415 
    }
4416 
  else if (sop == 1 && sopcde == 3 && HLs == 0)
4417 
    {
4418 
      OUTS (outf, "A0 = A0 >> ");
4419 
      OUTS (outf, uimm5 (newimmag));
4420 
    }
4421 
  else if (sop == 1 && sopcde == 3 && HLs == 1)
4422 
    {
4423 
      OUTS (outf, "A1 = A1 >> ");
4424 
      OUTS (outf, uimm5 (newimmag));
4425 
    }
4426 
  else if (sop == 2 && sopcde == 3 && HLs == 0)
4427 
    {
4428 
      OUTS (outf, "A0 = ROT A0 BY ");
4429 
      OUTS (outf, imm6 (immag));
4430 
    }
4431 
  else if (sop == 1 && sopcde == 1 && bit8 == 0)
4432 
    {
4433 
      OUTS (outf, dregs (dst0));
4434 
      OUTS (outf, " = ");
4435 
      OUTS (outf, dregs (src1));
4436 
      OUTS (outf, " << ");
4437 
      OUTS (outf, uimm5 (immag));
4438 
      OUTS (outf, " (V, S)");
4439 
    }
4440 
  else if (sop == 1 && sopcde == 1 && bit8 == 1)
4441 
    {
4442 
      OUTS (outf, dregs (dst0));
4443 
      OUTS (outf, " = ");
4444 
      OUTS (outf, dregs (src1));
4445 
      OUTS (outf, " >>> ");
4446 
      OUTS (outf, imm5 (-immag));
4447 
      OUTS (outf, " (V, S)");
4448 
    }
4449 
  else if (sop == 2 && sopcde == 1 && bit8 == 1)
4450 
    {
4451 
      OUTS (outf, dregs (dst0));
4452 
      OUTS (outf, " = ");
4453 
      OUTS (outf, dregs (src1));
4454 
      OUTS (outf, " >> ");
4455 
      OUTS (outf, uimm5 (newimmag));
4456 
      OUTS (outf, " (V)");
4457 
    }
4458 
  else if (sop == 2 && sopcde == 1 && bit8 == 0)
4459 
    {
4460 
      OUTS (outf, dregs (dst0));
4461 
      OUTS (outf, " = ");
4462 
      OUTS (outf, dregs (src1));
4463 
      OUTS (outf, " << ");
4464 
      OUTS (outf, imm5 (immag));
4465 
      OUTS (outf, " (V)");
4466 
    }
4467 
  else if (sop == 0 && sopcde == 1)
4468 
    {
4469 
      OUTS (outf, dregs (dst0));
4470 
      OUTS (outf, " = ");
4471 
      OUTS (outf, dregs (src1));
4472 
      OUTS (outf, " >>> ");
4473 
      OUTS (outf, uimm5 (newimmag));
4474 
      OUTS (outf, " (V)");
4475 
    }
4476 
  else if (sop == 1 && sopcde == 2)
4477 
    {
4478 
      OUTS (outf, dregs (dst0));
4479 
      OUTS (outf, " = ");
4480 
      OUTS (outf, dregs (src1));
4481 
      OUTS (outf, " << ");
4482 
      OUTS (outf, uimm5 (immag));
4483 
      OUTS (outf, " (S)");
4484 
    }
4485 
  else if (sop == 2 && sopcde == 2 && bit8 == 1)
4486 
    {
4487 
      OUTS (outf, dregs (dst0));
4488 
      OUTS (outf, " = ");
4489 
      OUTS (outf, dregs (src1));
4490 
      OUTS (outf, " >> ");
4491 
      OUTS (outf, uimm5 (newimmag));
4492 
    }
4493 
  else if (sop == 2 && sopcde == 2 && bit8 == 0)
4494 
    {
4495 
      OUTS (outf, dregs (dst0));
4496 
      OUTS (outf, " = ");
4497 
      OUTS (outf, dregs (src1));
4498 
      OUTS (outf, " << ");
4499 
      OUTS (outf, uimm5 (immag));
4500 
    }
4501 
  else if (sop == 3 && sopcde == 2)
4502 
    {
4503 
      OUTS (outf, dregs (dst0));
4504 
      OUTS (outf, " = ROT ");
4505 
      OUTS (outf, dregs (src1));
4506 
      OUTS (outf, " BY ");
4507 
      OUTS (outf, imm6 (immag));
4508 
    }
4509 
  else if (sop == 0 && sopcde == 2)
4510 
    {
4511 
      OUTS (outf, dregs (dst0));
4512 
      OUTS (outf, " = ");
4513 
      OUTS (outf, dregs (src1));
4514 
      OUTS (outf, " >>> ");
4515 
      OUTS (outf, uimm5 (newimmag));
4516 
    }
4517 
  else
4518 
    return 0;
4519 
 
4520 
  return 4;
4521 
}
4522 
 
4523 
static int
4524 
decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4525 
{
4526 
  /* pseudoDEBUG
4527 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4528 
     | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4529 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
4530 
  int fn  = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4531 
  int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4532 
  int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4533 
 
4534 
  if (parallel)
4535 
    return 0;
4536 
 
4537 
  if (reg == 0 && fn == 3)
4538 
    OUTS (outf, "DBG A0");
4539 
 
4540 
  else if (reg == 1 && fn == 3)
4541 
    OUTS (outf, "DBG A1");
4542 
 
4543 
  else if (reg == 3 && fn == 3)
4544 
    OUTS (outf, "ABORT");
4545 
 
4546 
  else if (reg == 4 && fn == 3)
4547 
    OUTS (outf, "HLT");
4548 
 
4549 
  else if (reg == 5 && fn == 3)
4550 
    OUTS (outf, "DBGHALT");
4551 
 
4552 
  else if (reg == 6 && fn == 3)
4553 
    {
4554 
      OUTS (outf, "DBGCMPLX (");
4555 
      OUTS (outf, dregs (grp));
4556 
      OUTS (outf, ")");
4557 
    }
4558 
  else if (reg == 7 && fn == 3)
4559 
    OUTS (outf, "DBG");
4560 
 
4561 
  else if (grp == 0 && fn == 2)
4562 
    {
4563 
      OUTS (outf, "OUTC ");
4564 
      OUTS (outf, dregs (reg));
4565 
    }
4566 
  else if (fn == 0)
4567 
    {
4568 
      OUTS (outf, "DBG ");
4569 
      OUTS (outf, allregs (reg, grp));
4570 
    }
4571 
  else if (fn == 1)
4572 
    {
4573 
      OUTS (outf, "PRNT ");
4574 
      OUTS (outf, allregs (reg, grp));
4575 
    }
4576 
  else
4577 
    return 0;
4578 
 
4579 
  return 2;
4580 
}
4581 
 
4582 
static int
4583 
decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4584 
{
4585 
  /* psedoOChar
4586 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4587 
     | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4588 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
4589 
  int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4590 
 
4591 
  if (parallel)
4592 
    return 0;
4593 
 
4594 
  OUTS (outf, "OUTC ");
4595 
  OUTS (outf, uimm8 (ch));
4596 
 
4597 
  return 2;
4598 
}
4599 
 
4600 
static int
4601 
decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4602 
{
4603 
  /* pseudodbg_assert
4604 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4605 
     | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4606 
     |.expected......................................................|
4607 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
4608 
  int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4609 
  int dbgop    = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4610 
  int grp      = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
4611 
  int regtest  = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4612 
 
4613 
  if (parallel)
4614 
    return 0;
4615 
 
4616 
  if (dbgop == 0)
4617 
    {
4618 
      OUTS (outf, "DBGA (");
4619 
      OUTS (outf, regs_lo (regtest, grp));
4620 
      OUTS (outf, ", ");
4621 
      OUTS (outf, uimm16 (expected));
4622 
      OUTS (outf, ")");
4623 
    }
4624 
  else if (dbgop == 1)
4625 
    {
4626 
      OUTS (outf, "DBGA (");
4627 
      OUTS (outf, regs_hi (regtest, grp));
4628 
      OUTS (outf, ", ");
4629 
      OUTS (outf, uimm16 (expected));
4630 
      OUTS (outf, ")");
4631 
    }
4632 
  else if (dbgop == 2)
4633 
    {
4634 
      OUTS (outf, "DBGAL (");
4635 
      OUTS (outf, allregs (regtest, grp));
4636 
      OUTS (outf, ", ");
4637 
      OUTS (outf, uimm16 (expected));
4638 
      OUTS (outf, ")");
4639 
    }
4640 
  else if (dbgop == 3)
4641 
    {
4642 
      OUTS (outf, "DBGAH (");
4643 
      OUTS (outf, allregs (regtest, grp));
4644 
      OUTS (outf, ", ");
4645 
      OUTS (outf, uimm16 (expected));
4646 
      OUTS (outf, ")");
4647 
    }
4648 
  else
4649 
    return 0;
4650 
  return 4;
4651 
}
4652 
 
4653 
static int
4654 
_print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4655 
{
4656 
  bfd_byte buf[4];
4657 
  TIword iw0;
4658 
  TIword iw1;
4659 
  int status;
4660 
  int rv = 0;
4661 
 
4662 
  status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
4663 
  /* FIXME */
4664 
  (void) status;
4665 
  status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
4666 
  /* FIXME */
4667 
  (void) status;
4668 
 
4669 
  iw0 = bfd_getl16 (buf);
4670 
  iw1 = bfd_getl16 (buf + 2);
4671 
 
4672 
  if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4673 
    {
4674 
      if (parallel)
4675 
        {
4676 
          OUTS (outf, "ILLEGAL");
4677 
          return 0;
4678 
        }
4679 
      OUTS (outf, "MNOP");
4680 
      return 4;
4681 
    }
4682 
  else if ((iw0 & 0xff00) == 0x0000)
4683 
    rv = decode_ProgCtrl_0 (iw0, outf);
4684 
  else if ((iw0 & 0xffc0) == 0x0240)
4685 
    rv = decode_CaCTRL_0 (iw0, outf);
4686 
  else if ((iw0 & 0xff80) == 0x0100)
4687 
    rv = decode_PushPopReg_0 (iw0, outf);
4688 
  else if ((iw0 & 0xfe00) == 0x0400)
4689 
    rv = decode_PushPopMultiple_0 (iw0, outf);
4690 
  else if ((iw0 & 0xfe00) == 0x0600)
4691 
    rv = decode_ccMV_0 (iw0, outf);
4692 
  else if ((iw0 & 0xf800) == 0x0800)
4693 
    rv = decode_CCflag_0 (iw0, outf);
4694 
  else if ((iw0 & 0xffe0) == 0x0200)
4695 
    rv = decode_CC2dreg_0 (iw0, outf);
4696 
  else if ((iw0 & 0xff00) == 0x0300)
4697 
    rv = decode_CC2stat_0 (iw0, outf);
4698 
  else if ((iw0 & 0xf000) == 0x1000)
4699 
    rv = decode_BRCC_0 (iw0, pc, outf);
4700 
  else if ((iw0 & 0xf000) == 0x2000)
4701 
    rv = decode_UJUMP_0 (iw0, pc, outf);
4702 
  else if ((iw0 & 0xf000) == 0x3000)
4703 
    rv = decode_REGMV_0 (iw0, outf);
4704 
  else if ((iw0 & 0xfc00) == 0x4000)
4705 
    rv = decode_ALU2op_0 (iw0, outf);
4706 
  else if ((iw0 & 0xfe00) == 0x4400)
4707 
    rv = decode_PTR2op_0 (iw0, outf);
4708 
  else if ((iw0 & 0xf800) == 0x4800)
4709 
    rv = decode_LOGI2op_0 (iw0, outf);
4710 
  else if ((iw0 & 0xf000) == 0x5000)
4711 
    rv = decode_COMP3op_0 (iw0, outf);
4712 
  else if ((iw0 & 0xf800) == 0x6000)
4713 
    rv = decode_COMPI2opD_0 (iw0, outf);
4714 
  else if ((iw0 & 0xf800) == 0x6800)
4715 
    rv = decode_COMPI2opP_0 (iw0, outf);
4716 
  else if ((iw0 & 0xf000) == 0x8000)
4717 
    rv = decode_LDSTpmod_0 (iw0, outf);
4718 
  else if ((iw0 & 0xff60) == 0x9e60)
4719 
    rv = decode_dagMODim_0 (iw0, outf);
4720 
  else if ((iw0 & 0xfff0) == 0x9f60)
4721 
    rv = decode_dagMODik_0 (iw0, outf);
4722 
  else if ((iw0 & 0xfc00) == 0x9c00)
4723 
    rv = decode_dspLDST_0 (iw0, outf);
4724 
  else if ((iw0 & 0xf000) == 0x9000)
4725 
    rv = decode_LDST_0 (iw0, outf);
4726 
  else if ((iw0 & 0xfc00) == 0xb800)
4727 
    rv = decode_LDSTiiFP_0 (iw0, outf);
4728 
  else if ((iw0 & 0xe000) == 0xA000)
4729 
    rv = decode_LDSTii_0 (iw0, outf);
4730 
  else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4731 
    rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4732 
  else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4733 
    rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4734 
  else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4735 
    rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4736 
  else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4737 
    rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4738 
  else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4739 
    rv = decode_linkage_0 (iw0, iw1, outf);
4740 
  else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4741 
    rv = decode_dsp32mac_0 (iw0, iw1, outf);
4742 
  else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4743 
    rv = decode_dsp32mult_0 (iw0, iw1, outf);
4744 
  else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4745 
    rv = decode_dsp32alu_0 (iw0, iw1, outf);
4746 
  else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4747 
    rv = decode_dsp32shift_0 (iw0, iw1, outf);
4748 
  else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4749 
    rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4750 
  else if ((iw0 & 0xff00) == 0xf800)
4751 
    rv = decode_pseudoDEBUG_0 (iw0, outf);
4752 
  else if ((iw0 & 0xFF00) == 0xF900)
4753 
    rv = decode_pseudoOChar_0 (iw0, outf);
4754 
  else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4755 
    rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4756 
 
4757 
  if (rv == 0)
4758 
    OUTS (outf, "ILLEGAL");
4759 
 
4760 
  return rv;
4761 
}
4762 
 
4763 
int
4764 
print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4765 
{
4766 
  bfd_byte buf[2];
4767 
  unsigned short iw0;
4768 
  int status;
4769 
  int count = 0;
4770 
 
4771 
  status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
4772 
  /* FIXME */
4773 
  (void) status;
4774 
  iw0 = bfd_getl16 (buf);
4775 
 
4776 
  count += _print_insn_bfin (pc, outf);
4777 
 
4778 
  /* Proper display of multiple issue instructions.  */
4779 
 
4780 
  if (count == 4 && (iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
4781 
      && ((iw0 & 0xe800) != 0xe800 /* Not Linkage.  */ ))
4782 
    {
4783 
      int legal = 1;
4784 
      int len;
4785 
 
4786 
      parallel = 1;
4787 
      OUTS (outf, " || ");
4788 
      len = _print_insn_bfin (pc + 4, outf);
4789 
      OUTS (outf, " || ");
4790 
      if (len != 2)
4791 
        legal = 0;
4792 
      len = _print_insn_bfin (pc + 6, outf);
4793 
      if (len != 2)
4794 
        legal = 0;
4795 
 
4796 
      if (legal)
4797 
        count = 8;
4798 
      else
4799 
        {
4800 
          OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
4801 
          comment = 1;
4802 
          count = 0;
4803 
        }
4804 
      parallel = 0;
4805 
    }
4806 
 
4807 
  if (!comment)
4808 
    OUTS (outf, ";");
4809 
 
4810 
  if (count == 0)
4811 
    return 2;
4812 
 
4813 
  comment = 0;
4814 
 
4815 
  return count;
4816 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.