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/* Print i386 instructions for GDB, the GNU debugger.

   Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,

   2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011

   Free Software Foundation, Inc.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3, or (at your option)

   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT

   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public

   License for more details.

   You should have received a copy of the GNU General Public License

   along with this program; if not, write to the Free Software

   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,

   MA 02110-1301, USA.  */

/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)

   July 1988

    modified by John Hassey (hassey@dg-rtp.dg.com)

    x86-64 support added by Jan Hubicka (jh@suse.cz)

    VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */

/* The main tables describing the instructions is essentially a copy

   of the "Opcode Map" chapter (Appendix A) of the Intel 80386

   Programmers Manual.  Usually, there is a capital letter, followed

   by a small letter.  The capital letter tell the addressing mode,

   and the small letter tells about the operand size.  Refer to

   the Intel manual for details.  */

#include "sysdep.h"

#include "dis-asm.h"

#include "opintl.h"

#include "opcode/i386.h"

#include "libiberty.h"

#include <setjmp.h>

static int print_insn (bfd_vma, disassemble_info *);

static void dofloat (int);

static void OP_ST (int, int);

static void OP_STi (int, int);

static int putop (const char *, int);

static void oappend (const char *);

static void append_seg (void);

static void OP_indirE (int, int);

static void print_operand_value (char *, int, bfd_vma);

static void OP_E_register (int, int);

static void OP_E_memory (int, int);

static void print_displacement (char *, bfd_vma);

static void OP_E (int, int);

static void OP_G (int, int);

static bfd_vma get64 (void);

static bfd_signed_vma get32 (void);

static bfd_signed_vma get32s (void);

static int get16 (void);

static void set_op (bfd_vma, int);

static void OP_Skip_MODRM (int, int);

static void OP_REG (int, int);

static void OP_IMREG (int, int);

static void OP_I (int, int);

static void OP_I64 (int, int);

static void OP_sI (int, int);

static void OP_J (int, int);

static void OP_SEG (int, int);

static void OP_DIR (int, int);

static void OP_OFF (int, int);

static void OP_OFF64 (int, int);

static void ptr_reg (int, int);

static void OP_ESreg (int, int);

static void OP_DSreg (int, int);

static void OP_C (int, int);

static void OP_D (int, int);

static void OP_T (int, int);

static void OP_R (int, int);

static void OP_MMX (int, int);

static void OP_XMM (int, int);

static void OP_EM (int, int);

static void OP_EX (int, int);

static void OP_EMC (int,int);

static void OP_MXC (int,int);

static void OP_MS (int, int);

static void OP_XS (int, int);

static void OP_M (int, int);

static void OP_VEX (int, int);

static void OP_EX_Vex (int, int);

static void OP_EX_VexW (int, int);

static void OP_EX_VexImmW (int, int);

static void OP_XMM_Vex (int, int);

static void OP_XMM_VexW (int, int);

static void OP_REG_VexI4 (int, int);

static void PCLMUL_Fixup (int, int);

static void VEXI4_Fixup (int, int);

static void VZERO_Fixup (int, int);

static void VCMP_Fixup (int, int);

static void OP_0f07 (int, int);

static void OP_Monitor (int, int);

static void OP_Mwait (int, int);

static void NOP_Fixup1 (int, int);

static void NOP_Fixup2 (int, int);

static void OP_3DNowSuffix (int, int);

static void CMP_Fixup (int, int);

static void BadOp (void);

static void REP_Fixup (int, int);

static void CMPXCHG8B_Fixup (int, int);

static void XMM_Fixup (int, int);

static void CRC32_Fixup (int, int);

static void FXSAVE_Fixup (int, int);

static void OP_LWPCB_E (int, int);

static void OP_LWP_E (int, int);

static void OP_Vex_2src_1 (int, int);

static void OP_Vex_2src_2 (int, int);

static void MOVBE_Fixup (int, int);

struct dis_private {

  /* Points to first byte not fetched.  */

  bfd_byte *max_fetched;

  bfd_byte the_buffer[MAX_MNEM_SIZE];

  bfd_vma insn_start;

  int orig_sizeflag;

  jmp_buf bailout;

};

enum address_mode

{

  mode_16bit,

  mode_32bit,

  mode_64bit

};

enum address_mode address_mode;

/* Flags for the prefixes for the current instruction.  See below.  */

static int prefixes;

/* REX prefix the current instruction.  See below.  */

static int rex;

/* Bits of REX we've already used.  */

static int rex_used;

/* REX bits in original REX prefix ignored.  */

static int rex_ignored;

/* Mark parts used in the REX prefix.  When we are testing for

   empty prefix (for 8bit register REX extension), just mask it

   out.  Otherwise test for REX bit is excuse for existence of REX

   only in case value is nonzero.  */

#define USED_REX(value)                                 \

  {                                                     \

    if (value)                                          \

      {                                                 \

        if ((rex & value))                              \

          rex_used |= (value) | REX_OPCODE;             \

      }                                                 \

    else                                                \

      rex_used |= REX_OPCODE;                           \

  }

/* Flags for prefixes which we somehow handled when printing the

   current instruction.  */

static int used_prefixes;

/* Flags stored in PREFIXES.  */

#define PREFIX_REPZ 1

#define PREFIX_REPNZ 2

#define PREFIX_LOCK 4

#define PREFIX_CS 8

#define PREFIX_SS 0x10

#define PREFIX_DS 0x20

#define PREFIX_ES 0x40

#define PREFIX_FS 0x80

#define PREFIX_GS 0x100

#define PREFIX_DATA 0x200

#define PREFIX_ADDR 0x400

#define PREFIX_FWAIT 0x800

/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)

   to ADDR (exclusive) are valid.  Returns 1 for success, longjmps

   on error.  */

#define FETCH_DATA(info, addr) \

  ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \

   ? 1 : fetch_data ((info), (addr)))

static int

fetch_data (struct disassemble_info *info, bfd_byte *addr)

{

  int status;

  struct dis_private *priv = (struct dis_private *) info->private_data;

  bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);

  if (addr <= priv->the_buffer + MAX_MNEM_SIZE)

    status = (*info->read_memory_func) (start,

                                        priv->max_fetched,

                                        addr - priv->max_fetched,

                                        info);

  else

    status = -1;

  if (status != 0)

    {

      /* If we did manage to read at least one byte, then

         print_insn_i386 will do something sensible.  Otherwise, print

         an error.  We do that here because this is where we know

         STATUS.  */

      if (priv->max_fetched == priv->the_buffer)

        (*info->memory_error_func) (status, start, info);

      longjmp (priv->bailout, 1);

    }

  else

    priv->max_fetched = addr;

  return 1;

}

#define XX { NULL, 0 }

#define Bad_Opcode NULL, { { NULL, 0 } }

#define Eb { OP_E, b_mode }

#define EbS { OP_E, b_swap_mode }

#define Ev { OP_E, v_mode }

#define EvS { OP_E, v_swap_mode }

#define Ed { OP_E, d_mode }

#define Edq { OP_E, dq_mode }

#define Edqw { OP_E, dqw_mode }

#define Edqb { OP_E, dqb_mode }

#define Edqd { OP_E, dqd_mode }

#define Eq { OP_E, q_mode }

#define indirEv { OP_indirE, stack_v_mode }

#define indirEp { OP_indirE, f_mode }

#define stackEv { OP_E, stack_v_mode }

#define Em { OP_E, m_mode }

#define Ew { OP_E, w_mode }

#define M { OP_M, 0 }           /* lea, lgdt, etc. */

#define Ma { OP_M, a_mode }

#define Mb { OP_M, b_mode }

#define Md { OP_M, d_mode }

#define Mo { OP_M, o_mode }

#define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */

#define Mq { OP_M, q_mode }

#define Mx { OP_M, x_mode }

#define Mxmm { OP_M, xmm_mode }

#define Gb { OP_G, b_mode }

#define Gv { OP_G, v_mode }

#define Gd { OP_G, d_mode }

#define Gdq { OP_G, dq_mode }

#define Gm { OP_G, m_mode }

#define Gw { OP_G, w_mode }

#define Rd { OP_R, d_mode }

#define Rm { OP_R, m_mode }

#define Ib { OP_I, b_mode }

#define sIb { OP_sI, b_mode }   /* sign extened byte */

#define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */

#define Iv { OP_I, v_mode }

#define sIv { OP_sI, v_mode } 

#define Iq { OP_I, q_mode }

#define Iv64 { OP_I64, v_mode }

#define Iw { OP_I, w_mode }

#define I1 { OP_I, const_1_mode }

#define Jb { OP_J, b_mode }

#define Jv { OP_J, v_mode }

#define Cm { OP_C, m_mode }

#define Dm { OP_D, m_mode }

#define Td { OP_T, d_mode }

#define Skip_MODRM { OP_Skip_MODRM, 0 }

#define RMeAX { OP_REG, eAX_reg }

#define RMeBX { OP_REG, eBX_reg }

#define RMeCX { OP_REG, eCX_reg }

#define RMeDX { OP_REG, eDX_reg }

#define RMeSP { OP_REG, eSP_reg }

#define RMeBP { OP_REG, eBP_reg }

#define RMeSI { OP_REG, eSI_reg }

#define RMeDI { OP_REG, eDI_reg }

#define RMrAX { OP_REG, rAX_reg }

#define RMrBX { OP_REG, rBX_reg }

#define RMrCX { OP_REG, rCX_reg }

#define RMrDX { OP_REG, rDX_reg }

#define RMrSP { OP_REG, rSP_reg }

#define RMrBP { OP_REG, rBP_reg }

#define RMrSI { OP_REG, rSI_reg }

#define RMrDI { OP_REG, rDI_reg }

#define RMAL { OP_REG, al_reg }

#define RMCL { OP_REG, cl_reg }

#define RMDL { OP_REG, dl_reg }

#define RMBL { OP_REG, bl_reg }

#define RMAH { OP_REG, ah_reg }

#define RMCH { OP_REG, ch_reg }

#define RMDH { OP_REG, dh_reg }

#define RMBH { OP_REG, bh_reg }

#define RMAX { OP_REG, ax_reg }

#define RMDX { OP_REG, dx_reg }

#define eAX { OP_IMREG, eAX_reg }

#define eBX { OP_IMREG, eBX_reg }

#define eCX { OP_IMREG, eCX_reg }

#define eDX { OP_IMREG, eDX_reg }

#define eSP { OP_IMREG, eSP_reg }

#define eBP { OP_IMREG, eBP_reg }

#define eSI { OP_IMREG, eSI_reg }

#define eDI { OP_IMREG, eDI_reg }

#define AL { OP_IMREG, al_reg }

#define CL { OP_IMREG, cl_reg }

#define DL { OP_IMREG, dl_reg }

#define BL { OP_IMREG, bl_reg }

#define AH { OP_IMREG, ah_reg }

#define CH { OP_IMREG, ch_reg }

#define DH { OP_IMREG, dh_reg }

#define BH { OP_IMREG, bh_reg }

#define AX { OP_IMREG, ax_reg }

#define DX { OP_IMREG, dx_reg }

#define zAX { OP_IMREG, z_mode_ax_reg }

#define indirDX { OP_IMREG, indir_dx_reg }

#define Sw { OP_SEG, w_mode }

#define Sv { OP_SEG, v_mode }

#define Ap { OP_DIR, 0 }

#define Ob { OP_OFF64, b_mode }

#define Ov { OP_OFF64, v_mode }

#define Xb { OP_DSreg, eSI_reg }

#define Xv { OP_DSreg, eSI_reg }

#define Xz { OP_DSreg, eSI_reg }

#define Yb { OP_ESreg, eDI_reg }

#define Yv { OP_ESreg, eDI_reg }

#define DSBX { OP_DSreg, eBX_reg }

#define es { OP_REG, es_reg }

#define ss { OP_REG, ss_reg }

#define cs { OP_REG, cs_reg }

#define ds { OP_REG, ds_reg }

#define fs { OP_REG, fs_reg }

#define gs { OP_REG, gs_reg }

#define MX { OP_MMX, 0 }

#define XM { OP_XMM, 0 }

#define XMScalar { OP_XMM, scalar_mode }

#define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }

#define XMM { OP_XMM, xmm_mode }

#define EM { OP_EM, v_mode }

#define EMS { OP_EM, v_swap_mode }

#define EMd { OP_EM, d_mode }

#define EMx { OP_EM, x_mode }

#define EXw { OP_EX, w_mode }

#define EXd { OP_EX, d_mode }

#define EXdScalar { OP_EX, d_scalar_mode }

#define EXdS { OP_EX, d_swap_mode }

#define EXq { OP_EX, q_mode }

#define EXqScalar { OP_EX, q_scalar_mode }

#define EXqScalarS { OP_EX, q_scalar_swap_mode }

#define EXqS { OP_EX, q_swap_mode }

#define EXx { OP_EX, x_mode }

#define EXxS { OP_EX, x_swap_mode }

#define EXxmm { OP_EX, xmm_mode }

#define EXxmmq { OP_EX, xmmq_mode }

#define EXxmm_mb { OP_EX, xmm_mb_mode }

#define EXxmm_mw { OP_EX, xmm_mw_mode }

#define EXxmm_md { OP_EX, xmm_md_mode }

#define EXxmm_mq { OP_EX, xmm_mq_mode }

#define EXxmmdw { OP_EX, xmmdw_mode }

#define EXxmmqd { OP_EX, xmmqd_mode }

#define EXymmq { OP_EX, ymmq_mode }

#define EXVexWdq { OP_EX, vex_w_dq_mode }

#define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }

#define MS { OP_MS, v_mode }

#define XS { OP_XS, v_mode }

#define EMCq { OP_EMC, q_mode }

#define MXC { OP_MXC, 0 }

#define OPSUF { OP_3DNowSuffix, 0 }

#define CMP { CMP_Fixup, 0 }

#define XMM0 { XMM_Fixup, 0 }

#define FXSAVE { FXSAVE_Fixup, 0 }

#define Vex_2src_1 { OP_Vex_2src_1, 0 }

#define Vex_2src_2 { OP_Vex_2src_2, 0 }

#define Vex { OP_VEX, vex_mode }

#define VexScalar { OP_VEX, vex_scalar_mode }

#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }

#define Vex128 { OP_VEX, vex128_mode }

#define Vex256 { OP_VEX, vex256_mode }

#define VexGdq { OP_VEX, dq_mode }

#define VexI4 { VEXI4_Fixup, 0}

#define EXdVex { OP_EX_Vex, d_mode }

#define EXdVexS { OP_EX_Vex, d_swap_mode }

#define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }

#define EXqVex { OP_EX_Vex, q_mode }

#define EXqVexS { OP_EX_Vex, q_swap_mode }

#define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }

#define EXVexW { OP_EX_VexW, x_mode }

#define EXdVexW { OP_EX_VexW, d_mode }

#define EXqVexW { OP_EX_VexW, q_mode }

#define EXVexImmW { OP_EX_VexImmW, x_mode }

#define XMVex { OP_XMM_Vex, 0 }

#define XMVexScalar { OP_XMM_Vex, scalar_mode }

#define XMVexW { OP_XMM_VexW, 0 }

#define XMVexI4 { OP_REG_VexI4, x_mode }

#define PCLMUL { PCLMUL_Fixup, 0 }

#define VZERO { VZERO_Fixup, 0 }

#define VCMP { VCMP_Fixup, 0 }

#define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }

#define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }

/* Used handle "rep" prefix for string instructions.  */

#define Xbr { REP_Fixup, eSI_reg }

#define Xvr { REP_Fixup, eSI_reg }

#define Ybr { REP_Fixup, eDI_reg }

#define Yvr { REP_Fixup, eDI_reg }

#define Yzr { REP_Fixup, eDI_reg }

#define indirDXr { REP_Fixup, indir_dx_reg }

#define ALr { REP_Fixup, al_reg }

#define eAXr { REP_Fixup, eAX_reg }

#define cond_jump_flag { NULL, cond_jump_mode }

#define loop_jcxz_flag { NULL, loop_jcxz_mode }

/* bits in sizeflag */

#define SUFFIX_ALWAYS 4

#define AFLAG 2

#define DFLAG 1

enum

{

  /* byte operand */

  b_mode = 1,

  /* byte operand with operand swapped */

  b_swap_mode,

  /* byte operand, sign extend like 'T' suffix */

  b_T_mode,

  /* operand size depends on prefixes */

  v_mode,

  /* operand size depends on prefixes with operand swapped */

  v_swap_mode,

  /* word operand */

  w_mode,

  /* double word operand  */

  d_mode,

  /* double word operand with operand swapped */

  d_swap_mode,

  /* quad word operand */

  q_mode,

  /* quad word operand with operand swapped */

  q_swap_mode,

  /* ten-byte operand */

  t_mode,

  /* 16-byte XMM or 32-byte YMM operand */

  x_mode,

  /* 16-byte XMM or 32-byte YMM operand with operand swapped */

  x_swap_mode,

  /* 16-byte XMM operand */

  xmm_mode,

  /* 16-byte XMM or quad word operand */

  xmmq_mode,

  /* XMM register or byte memory operand */

  xmm_mb_mode,

  /* XMM register or word memory operand */

  xmm_mw_mode,

  /* XMM register or double word memory operand */

  xmm_md_mode,

  /* XMM register or quad word memory operand */

  xmm_mq_mode,

  /* 16-byte XMM, word or double word operand  */

  xmmdw_mode,

  /* 16-byte XMM, double word or quad word operand */

  xmmqd_mode,

  /* 32-byte YMM or quad word operand */

  ymmq_mode,

  /* 32-byte YMM or 16-byte word operand */

  ymmxmm_mode,

  /* d_mode in 32bit, q_mode in 64bit mode.  */

  m_mode,

  /* pair of v_mode operands */

  a_mode,

  cond_jump_mode,

  loop_jcxz_mode,

  /* operand size depends on REX prefixes.  */

  dq_mode,

  /* registers like dq_mode, memory like w_mode.  */

  dqw_mode,

  /* 4- or 6-byte pointer operand */

  f_mode,

  const_1_mode,

  /* v_mode for stack-related opcodes.  */

  stack_v_mode,

  /* non-quad operand size depends on prefixes */

  z_mode,

  /* 16-byte operand */

  o_mode,

  /* registers like dq_mode, memory like b_mode.  */

  dqb_mode,

  /* registers like dq_mode, memory like d_mode.  */

  dqd_mode,

  /* normal vex mode */

  vex_mode,

  /* 128bit vex mode */

  vex128_mode,

  /* 256bit vex mode */

  vex256_mode,

  /* operand size depends on the VEX.W bit.  */

  vex_w_dq_mode,

  /* Similar to vex_w_dq_mode, with VSIB dword indices.  */

  vex_vsib_d_w_dq_mode,

  /* Similar to vex_w_dq_mode, with VSIB qword indices.  */

  vex_vsib_q_w_dq_mode,

  /* scalar, ignore vector length.  */

  scalar_mode,

  /* like d_mode, ignore vector length.  */

  d_scalar_mode,

  /* like d_swap_mode, ignore vector length.  */

  d_scalar_swap_mode,

  /* like q_mode, ignore vector length.  */

  q_scalar_mode,

  /* like q_swap_mode, ignore vector length.  */

  q_scalar_swap_mode,

  /* like vex_mode, ignore vector length.  */

  vex_scalar_mode,

  /* like vex_w_dq_mode, ignore vector length.  */

  vex_scalar_w_dq_mode,

  es_reg,

  cs_reg,

  ss_reg,

  ds_reg,

  fs_reg,

  gs_reg,

  eAX_reg,

  eCX_reg,

  eDX_reg,

  eBX_reg,

  eSP_reg,

  eBP_reg,

  eSI_reg,

  eDI_reg,

  al_reg,

  cl_reg,

  dl_reg,

  bl_reg,

  ah_reg,

  ch_reg,

  dh_reg,

  bh_reg,

  ax_reg,

  cx_reg,

  dx_reg,

  bx_reg,

  sp_reg,

  bp_reg,

  si_reg,

  di_reg,

  rAX_reg,

  rCX_reg,

  rDX_reg,

  rBX_reg,

  rSP_reg,

  rBP_reg,

  rSI_reg,

  rDI_reg,

  z_mode_ax_reg,

  indir_dx_reg

};

enum

{

  FLOATCODE = 1,

  USE_REG_TABLE,

  USE_MOD_TABLE,

  USE_RM_TABLE,

  USE_PREFIX_TABLE,

  USE_X86_64_TABLE,

  USE_3BYTE_TABLE,

  USE_XOP_8F_TABLE,

  USE_VEX_C4_TABLE,

  USE_VEX_C5_TABLE,

  USE_VEX_LEN_TABLE,

  USE_VEX_W_TABLE

};

#define FLOAT                   NULL, { { NULL, FLOATCODE } }

#define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }

#define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))

#define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))

#define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))

#define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))

#define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))

#define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))

#define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))

#define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))

#define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))

#define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))

#define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))

enum

{

  REG_80 = 0,

  REG_81,

  REG_82,

  REG_8F,

  REG_C0,

  REG_C1,

  REG_C6,

  REG_C7,

  REG_D0,

  REG_D1,

  REG_D2,

  REG_D3,

  REG_F6,

  REG_F7,

  REG_FE,

  REG_FF,

  REG_0F00,

  REG_0F01,

  REG_0F0D,

  REG_0F18,

  REG_0F71,

  REG_0F72,

  REG_0F73,

  REG_0FA6,

  REG_0FA7,

  REG_0FAE,

  REG_0FBA,

  REG_0FC7,

  REG_VEX_0F71,

  REG_VEX_0F72,

  REG_VEX_0F73,

  REG_VEX_0FAE,

  REG_VEX_0F38F3,

  REG_XOP_LWPCB,

  REG_XOP_LWP,

  REG_XOP_TBM_01,

  REG_XOP_TBM_02

};

enum

{

  MOD_8D = 0,

  MOD_0F01_REG_0,

  MOD_0F01_REG_1,

  MOD_0F01_REG_2,

  MOD_0F01_REG_3,

  MOD_0F01_REG_7,

  MOD_0F12_PREFIX_0,

  MOD_0F13,

  MOD_0F16_PREFIX_0,

  MOD_0F17,

  MOD_0F18_REG_0,

  MOD_0F18_REG_1,

  MOD_0F18_REG_2,

  MOD_0F18_REG_3,

  MOD_0F20,

  MOD_0F21,

  MOD_0F22,

  MOD_0F23,

  MOD_0F24,

  MOD_0F26,

  MOD_0F2B_PREFIX_0,

  MOD_0F2B_PREFIX_1,

  MOD_0F2B_PREFIX_2,

  MOD_0F2B_PREFIX_3,

  MOD_0F51,

  MOD_0F71_REG_2,

  MOD_0F71_REG_4,

  MOD_0F71_REG_6,

  MOD_0F72_REG_2,

  MOD_0F72_REG_4,

  MOD_0F72_REG_6,

  MOD_0F73_REG_2,

  MOD_0F73_REG_3,

  MOD_0F73_REG_6,

  MOD_0F73_REG_7,

  MOD_0FAE_REG_0,

  MOD_0FAE_REG_1,

  MOD_0FAE_REG_2,

  MOD_0FAE_REG_3,

  MOD_0FAE_REG_4,

  MOD_0FAE_REG_5,

  MOD_0FAE_REG_6,

  MOD_0FAE_REG_7,

  MOD_0FB2,

  MOD_0FB4,

  MOD_0FB5,

  MOD_0FC7_REG_6,

  MOD_0FC7_REG_7,

  MOD_0FD7,

  MOD_0FE7_PREFIX_2,

  MOD_0FF0_PREFIX_3,

  MOD_0F382A_PREFIX_2,

  MOD_62_32BIT,

  MOD_C4_32BIT,

  MOD_C5_32BIT,

  MOD_VEX_0F12_PREFIX_0,

  MOD_VEX_0F13,

  MOD_VEX_0F16_PREFIX_0,

  MOD_VEX_0F17,

  MOD_VEX_0F2B,

  MOD_VEX_0F50,

  MOD_VEX_0F71_REG_2,

  MOD_VEX_0F71_REG_4,

  MOD_VEX_0F71_REG_6,

  MOD_VEX_0F72_REG_2,

  MOD_VEX_0F72_REG_4,

  MOD_VEX_0F72_REG_6,

  MOD_VEX_0F73_REG_2,

  MOD_VEX_0F73_REG_3,

  MOD_VEX_0F73_REG_6,

  MOD_VEX_0F73_REG_7,

  MOD_VEX_0FAE_REG_2,

  MOD_VEX_0FAE_REG_3,

  MOD_VEX_0FD7_PREFIX_2,

  MOD_VEX_0FE7_PREFIX_2,

  MOD_VEX_0FF0_PREFIX_3,

  MOD_VEX_0F381A_PREFIX_2,

  MOD_VEX_0F382A_PREFIX_2,

  MOD_VEX_0F382C_PREFIX_2,

  MOD_VEX_0F382D_PREFIX_2,

  MOD_VEX_0F382E_PREFIX_2,

  MOD_VEX_0F382F_PREFIX_2,

  MOD_VEX_0F385A_PREFIX_2,

  MOD_VEX_0F388C_PREFIX_2,

  MOD_VEX_0F388E_PREFIX_2,

};

enum

{

  RM_0F01_REG_0 = 0,

  RM_0F01_REG_1,

  RM_0F01_REG_2,

  RM_0F01_REG_3,

  RM_0F01_REG_7,

  RM_0FAE_REG_5,

  RM_0FAE_REG_6,

  RM_0FAE_REG_7

};

enum

{

  PREFIX_90 = 0,

  PREFIX_0F10,

  PREFIX_0F11,

  PREFIX_0F12,

  PREFIX_0F16,

  PREFIX_0F2A,

  PREFIX_0F2B,