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/* m68hc11-opc.c -- Motorola 68HC11 & 68HC12 opcode list
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Copyright 1999, 2000, 2002, 2005, 2007 Free Software Foundation, Inc.
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Written by Stephane Carrez (stcarrez@nerim.fr)
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include <stdio.h>
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#include "ansidecl.h"
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#include "opcode/m68hc11.h"
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#define TABLE_SIZE(X) (sizeof(X) / sizeof(X[0]))
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/* Combination of CCR flags. */
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#define M6811_ZC_BIT M6811_Z_BIT|M6811_C_BIT
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#define M6811_NZ_BIT M6811_N_BIT|M6811_Z_BIT
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#define M6811_NZV_BIT M6811_N_BIT|M6811_Z_BIT|M6811_V_BIT
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#define M6811_NZC_BIT M6811_N_BIT|M6811_Z_BIT|M6811_C_BIT
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#define M6811_NVC_BIT M6811_N_BIT|M6811_V_BIT|M6811_C_BIT
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#define M6811_ZVC_BIT M6811_Z_BIT|M6811_V_BIT|M6811_C_BIT
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#define M6811_NZVC_BIT M6811_ZVC_BIT|M6811_N_BIT
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#define M6811_HNZVC_BIT M6811_NZVC_BIT|M6811_H_BIT
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#define M6811_HNVC_BIT M6811_NVC_BIT|M6811_H_BIT
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#define M6811_VC_BIT M6811_V_BIT|M6811_C_BIT
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/* Flags when the insn only changes some CCR flags. */
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#define CHG_NONE 0,0,0
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#define CHG_Z 0,0,M6811_Z_BIT
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#define CHG_C 0,0,M6811_C_BIT
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#define CHG_ZVC 0,0,M6811_ZVC_BIT
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#define CHG_NZC 0,0,M6811_NZC_BIT
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#define CHG_NZV 0,0,M6811_NZV_BIT
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#define CHG_NZVC 0,0,M6811_NZVC_BIT
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#define CHG_HNZVC 0,0,M6811_HNZVC_BIT
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#define CHG_ALL 0,0,0xff
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/* The insn clears and changes some flags. */
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#define CLR_I 0,M6811_I_BIT,0
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#define CLR_C 0,M6811_C_BIT,0
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#define CLR_V 0,M6811_V_BIT,0
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#define CLR_V_CHG_ZC 0,M6811_V_BIT,M6811_ZC_BIT
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#define CLR_V_CHG_NZ 0,M6811_V_BIT,M6811_NZ_BIT
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#define CLR_V_CHG_ZVC 0,M6811_V_BIT,M6811_ZVC_BIT
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#define CLR_N_CHG_ZVC 0,M6811_N_BIT,M6811_ZVC_BIT /* Used by lsr */
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#define CLR_VC_CHG_NZ 0,M6811_VC_BIT,M6811_NZ_BIT
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/* The insn sets some flags. */
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#define SET_I M6811_I_BIT,0,0
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#define SET_C M6811_C_BIT,0,0
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#define SET_V M6811_V_BIT,0,0
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#define SET_Z_CLR_NVC M6811_Z_BIT,M6811_NVC_BIT,0
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#define SET_C_CLR_V_CHG_NZ M6811_C_BIT,M6811_V_BIT,M6811_NZ_BIT
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#define SET_Z_CHG_HNVC M6811_Z_BIT,0,M6811_HNVC_BIT
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#define _M 0xff
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#define OP_NONE M6811_OP_NONE
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#define OP_PAGE2 M6811_OP_PAGE2
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#define OP_PAGE3 M6811_OP_PAGE3
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#define OP_PAGE4 M6811_OP_PAGE4
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#define OP_IMM8 M6811_OP_IMM8
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#define OP_IMM16 M6811_OP_IMM16
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#define OP_IX M6811_OP_IX
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#define OP_IY M6811_OP_IY
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#define OP_IND16 M6811_OP_IND16
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#define OP_PAGE M6812_OP_PAGE
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#define OP_IDX M6812_OP_IDX
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#define OP_IDX_1 M6812_OP_IDX_1
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#define OP_IDX_2 M6812_OP_IDX_2
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#define OP_D_IDX M6812_OP_D_IDX
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#define OP_D_IDX_2 M6812_OP_D_IDX_2
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#define OP_DIRECT M6811_OP_DIRECT
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#define OP_BITMASK M6811_OP_BITMASK
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#define OP_BRANCH M6811_OP_BRANCH
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#define OP_JUMP_REL (M6811_OP_JUMP_REL|OP_BRANCH)
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#define OP_JUMP_REL16 (M6812_OP_JUMP_REL16|OP_BRANCH)
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#define OP_REG M6812_OP_REG
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#define OP_REG_1 M6812_OP_REG
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#define OP_REG_2 M6812_OP_REG_2
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#define OP_IDX_p2 M6812_OP_IDX_P2
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#define OP_IND16_p2 M6812_OP_IND16_P2
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#define OP_TRAP_ID M6812_OP_TRAP_ID
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#define OP_EXG_MARKER M6812_OP_EXG_MARKER
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#define OP_TFR_MARKER M6812_OP_TFR_MARKER
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#define OP_DBEQ_MARKER (M6812_OP_DBCC_MARKER|M6812_OP_EQ_MARKER)
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#define OP_DBNE_MARKER (M6812_OP_DBCC_MARKER)
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#define OP_TBEQ_MARKER (M6812_OP_TBCC_MARKER|M6812_OP_EQ_MARKER)
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#define OP_TBNE_MARKER (M6812_OP_TBCC_MARKER)
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#define OP_IBEQ_MARKER (M6812_OP_IBCC_MARKER|M6812_OP_EQ_MARKER)
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#define OP_IBNE_MARKER (M6812_OP_IBCC_MARKER)
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/*
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{ "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 },
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+-- cpu
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Name -+ +------- Insn CCR changes
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Format ------+ +----------- Max # cycles
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Size --------------------+ +--------------- Min # cycles
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+--------------------- Opcode
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*/
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const struct m68hc11_opcode m68hc11_opcodes[] = {
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{ "aba", OP_NONE, 1, 0x1b, 2, 2, CHG_HNZVC, cpu6811 },
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{ "aba", OP_NONE | OP_PAGE2,2, 0x06, 2, 2, CHG_HNZVC, cpu6812 },
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{ "abx", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6811 },
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{ "aby", OP_NONE | OP_PAGE2,2, 0x3a, 4, 4, CHG_NONE, cpu6811 },
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{ "adca", OP_IMM8, 2, 0x89, 1, 1, CHG_HNZVC, cpu6811|cpu6812 },
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{ "adca", OP_DIRECT, 2, 0x99, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
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{ "adca", OP_IND16, 3, 0xb9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
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{ "adca", OP_IX, 2, 0xa9, 4, 4, CHG_HNZVC, cpu6811 },
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{ "adca", OP_IY | OP_PAGE2, 3, 0xa9, 5, 5, CHG_HNZVC, cpu6811 },
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{ "adca", OP_IDX, 2, 0xa9, 3, 3, CHG_HNZVC, cpu6812 },
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{ "adca", OP_IDX_1, 3, 0xa9, 3, 3, CHG_HNZVC, cpu6812 },
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{ "adca", OP_IDX_2, 4, 0xa9, 4, 4, CHG_HNZVC, cpu6812 },
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{ "adca", OP_D_IDX, 2, 0xa9, 6, 6, CHG_HNZVC, cpu6812 },
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{ "adca", OP_D_IDX_2, 4, 0xa9, 6, 6, CHG_HNZVC, cpu6812 },
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{ "adcb", OP_IMM8, 2, 0xc9, 1, 1, CHG_HNZVC, cpu6811|cpu6812 },
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{ "adcb", OP_DIRECT, 2, 0xd9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
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{ "adcb", OP_IND16, 3, 0xf9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
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{ "adcb", OP_IX, 2, 0xe9, 4, 4, CHG_HNZVC, cpu6811 },
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{ "adcb", OP_IY | OP_PAGE2, 3, 0xe9, 5, 5, CHG_HNZVC, cpu6811 },
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{ "adcb", OP_IDX, 2, 0xe9, 3, 3, CHG_HNZVC, cpu6812 },
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{ "adcb", OP_IDX_1, 3, 0xe9, 3, 3, CHG_HNZVC, cpu6812 },
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{ "adcb", OP_IDX_2, 4, 0xe9, 4, 4, CHG_HNZVC, cpu6812 },
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{ "adcb", OP_D_IDX, 2, 0xe9, 6, 6, CHG_HNZVC, cpu6812 },
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{ "adcb", OP_D_IDX_2, 4, 0xe9, 6, 6, CHG_HNZVC, cpu6812 },
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{ "adda", OP_IMM8, 2, 0x8b, 1, 1, CHG_HNZVC, cpu6811|cpu6812 },
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{ "adda", OP_DIRECT, 2, 0x9b, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
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{ "adda", OP_IND16, 3, 0xbb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
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{ "adda", OP_IX, 2, 0xab, 4, 4, CHG_HNZVC, cpu6811 },
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{ "adda", OP_IY | OP_PAGE2, 3, 0xab, 5, 5, CHG_HNZVC, cpu6811 },
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{ "adda", OP_IDX, 2, 0xab, 3, 3, CHG_HNZVC, cpu6812 },
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{ "adda", OP_IDX_1, 3, 0xab, 3, 3, CHG_HNZVC, cpu6812 },
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{ "adda", OP_IDX_2, 4, 0xab, 4, 4, CHG_HNZVC, cpu6812 },
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{ "adda", OP_D_IDX, 2, 0xab, 6, 6, CHG_HNZVC, cpu6812 },
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{ "adda", OP_D_IDX_2, 4, 0xab, 6, 6, CHG_HNZVC, cpu6812 },
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{ "addb", OP_IMM8, 2, 0xcb, 1, 1, CHG_HNZVC, cpu6811|cpu6812 },
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{ "addb", OP_DIRECT, 2, 0xdb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
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{ "addb", OP_IND16, 3, 0xfb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
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{ "addb", OP_IX, 2, 0xeb, 4, 4, CHG_HNZVC, cpu6811 },
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{ "addb", OP_IY | OP_PAGE2, 3, 0xeb, 5, 5, CHG_HNZVC, cpu6811 },
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{ "addb", OP_IDX, 2, 0xeb, 3, 3, CHG_HNZVC, cpu6812 },
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{ "addb", OP_IDX_1, 3, 0xeb, 3, 3, CHG_HNZVC, cpu6812 },
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{ "addb", OP_IDX_2, 4, 0xeb, 4, 4, CHG_HNZVC, cpu6812 },
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| 160 |
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{ "addb", OP_D_IDX, 2, 0xeb, 6, 6, CHG_HNZVC, cpu6812 },
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| 161 |
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{ "addb", OP_D_IDX_2, 4, 0xeb, 6, 6, CHG_HNZVC, cpu6812 },
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| 162 |
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| 163 |
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{ "addd", OP_IMM16, 3, 0xc3, 2, 2, CHG_NZVC, cpu6811|cpu6812 },
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{ "addd", OP_DIRECT, 2, 0xd3, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
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{ "addd", OP_IND16, 3, 0xf3, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
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{ "addd", OP_IX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6811 },
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{ "addd", OP_IY | OP_PAGE2, 3, 0xe3, 7, 7, CHG_NZVC, cpu6811 },
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{ "addd", OP_IDX, 2, 0xe3, 3, 3, CHG_NZVC, cpu6812 },
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{ "addd", OP_IDX_1, 3, 0xe3, 3, 3, CHG_NZVC, cpu6812 },
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| 170 |
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{ "addd", OP_IDX_2, 4, 0xe3, 4, 4, CHG_NZVC, cpu6812 },
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| 171 |
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{ "addd", OP_D_IDX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6812 },
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| 172 |
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{ "addd", OP_D_IDX_2, 4, 0xe3, 6, 6, CHG_NZVC, cpu6812 },
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| 173 |
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| 174 |
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{ "anda", OP_IMM8, 2, 0x84, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
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| 175 |
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{ "anda", OP_DIRECT, 2, 0x94, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
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| 176 |
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{ "anda", OP_IND16, 3, 0xb4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
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| 177 |
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{ "anda", OP_IX, 2, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6811 },
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| 178 |
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{ "anda", OP_IY | OP_PAGE2, 3, 0xa4, 5, 5, CLR_V_CHG_NZ, cpu6811 },
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| 179 |
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{ "anda", OP_IDX, 2, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 },
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| 180 |
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{ "anda", OP_IDX_1, 3, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 },
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| 181 |
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{ "anda", OP_IDX_2, 4, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6812 },
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| 182 |
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{ "anda", OP_D_IDX, 2, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 },
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| 183 |
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{ "anda", OP_D_IDX_2, 4, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 },
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| 184 |
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| 185 |
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{ "andb", OP_IMM8, 2, 0xc4, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
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| 186 |
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{ "andb", OP_DIRECT, 2, 0xd4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
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| 187 |
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{ "andb", OP_IND16, 3, 0xf4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
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| 188 |
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{ "andb", OP_IX, 2, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6811 },
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| 189 |
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{ "andb", OP_IY | OP_PAGE2, 3, 0xe4, 5, 5, CLR_V_CHG_NZ, cpu6811 },
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| 190 |
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{ "andb", OP_IDX, 2, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 },
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| 191 |
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{ "andb", OP_IDX_1, 3, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 },
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| 192 |
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{ "andb", OP_IDX_2, 4, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6812 },
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| 193 |
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{ "andb", OP_D_IDX, 2, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 },
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| 194 |
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{ "andb", OP_D_IDX_2, 4, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 },
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| 195 |
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| 196 |
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{ "andcc", OP_IMM8, 2, 0x10, 1, 1, CHG_ALL, cpu6812 },
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| 197 |
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| 198 |
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{ "asl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812 },
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| 199 |
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{ "asl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 },
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| 200 |
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{ "asl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 },
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| 201 |
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{ "asl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 },
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| 202 |
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{ "asl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 },
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| 203 |
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{ "asl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 },
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| 204 |
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{ "asl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 },
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| 205 |
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{ "asl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 },
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| 206 |
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| 207 |
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{ "asla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
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| 208 |
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{ "aslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
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| 209 |
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{ "asld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 },
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| 210 |
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{ "asld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 },
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| 211 |
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| 212 |
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{ "asr", OP_IND16, 3, 0x77, 4, 4, CHG_NZVC, cpu6811|cpu6812 },
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| 213 |
|
|
{ "asr", OP_IX, 2, 0x67, 6, 6, CHG_NZVC, cpu6811 },
|
| 214 |
|
|
{ "asr", OP_IY | OP_PAGE2, 3, 0x67, 7, 7, CHG_NZVC, cpu6811 },
|
| 215 |
|
|
{ "asr", OP_IDX, 2, 0x67, 3, 3, CHG_NZVC, cpu6812 },
|
| 216 |
|
|
{ "asr", OP_IDX_1, 3, 0x67, 4, 4, CHG_NZVC, cpu6812 },
|
| 217 |
|
|
{ "asr", OP_IDX_2, 4, 0x67, 5, 5, CHG_NZVC, cpu6812 },
|
| 218 |
|
|
{ "asr", OP_D_IDX, 2, 0x67, 6, 6, CHG_NZVC, cpu6812 },
|
| 219 |
|
|
{ "asr", OP_D_IDX_2, 4, 0x67, 6, 6, CHG_NZVC, cpu6812 },
|
| 220 |
|
|
|
| 221 |
|
|
{ "asra", OP_NONE, 1, 0x47, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
|
| 222 |
|
|
{ "asrb", OP_NONE, 1, 0x57, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
|
| 223 |
|
|
|
| 224 |
|
|
{ "bcc", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811|cpu6812 },
|
| 225 |
|
|
|
| 226 |
|
|
{ "bclr", OP_BITMASK|OP_DIRECT, 3, 0x15, 6, 6, CLR_V_CHG_NZ, cpu6811 },
|
| 227 |
|
|
{ "bclr", OP_BITMASK|OP_IX, 3, 0x1d, 7, 7, CLR_V_CHG_NZ, cpu6811 },
|
| 228 |
|
|
{ "bclr", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1d, 8, 8, CLR_V_CHG_NZ, cpu6811},
|
| 229 |
|
|
{ "bclr", OP_BITMASK|OP_DIRECT, 3, 0x4d, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 230 |
|
|
{ "bclr", OP_BITMASK|OP_IND16, 4, 0x1d, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 231 |
|
|
{ "bclr", OP_BITMASK|OP_IDX, 3, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 232 |
|
|
{ "bclr", OP_BITMASK|OP_IDX_1, 4, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 233 |
|
|
{ "bclr", OP_BITMASK|OP_IDX_2, 5, 0x0d, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 234 |
|
|
|
| 235 |
|
|
{ "bcs", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
|
| 236 |
|
|
{ "beq", OP_JUMP_REL, 2, 0x27, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
|
| 237 |
|
|
{ "bge", OP_JUMP_REL, 2, 0x2c, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
|
| 238 |
|
|
|
| 239 |
|
|
{ "bgnd", OP_NONE, 1, 0x00, 5, 5, CHG_NONE, cpu6811 | cpu6812 },
|
| 240 |
|
|
|
| 241 |
|
|
{ "bgt", OP_JUMP_REL, 2, 0x2e, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
|
| 242 |
|
|
{ "bhi", OP_JUMP_REL, 2, 0x22, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
|
| 243 |
|
|
{ "bhs", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
|
| 244 |
|
|
|
| 245 |
|
|
{ "bita", OP_IMM8, 2, 0x85, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 246 |
|
|
{ "bita", OP_DIRECT, 2, 0x95, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 247 |
|
|
{ "bita", OP_IND16, 3, 0xb5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 248 |
|
|
{ "bita", OP_IX, 2, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6811 },
|
| 249 |
|
|
{ "bita", OP_IY | OP_PAGE2, 3, 0xa5, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 250 |
|
|
{ "bita", OP_IDX, 2, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 251 |
|
|
{ "bita", OP_IDX_1, 3, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 252 |
|
|
{ "bita", OP_IDX_2, 4, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 253 |
|
|
{ "bita", OP_D_IDX, 2, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 254 |
|
|
{ "bita", OP_D_IDX_2, 4, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 255 |
|
|
|
| 256 |
|
|
{ "bitb", OP_IMM8, 2, 0xc5, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 257 |
|
|
{ "bitb", OP_DIRECT, 2, 0xd5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 258 |
|
|
{ "bitb", OP_IND16, 3, 0xf5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 259 |
|
|
{ "bitb", OP_IX, 2, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6811 },
|
| 260 |
|
|
{ "bitb", OP_IY | OP_PAGE2, 3, 0xe5, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 261 |
|
|
{ "bitb", OP_IDX, 2, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 262 |
|
|
{ "bitb", OP_IDX_1, 3, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 263 |
|
|
{ "bitb", OP_IDX_2, 4, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 264 |
|
|
{ "bitb", OP_D_IDX, 2, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 265 |
|
|
{ "bitb", OP_D_IDX_2, 4, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 266 |
|
|
|
| 267 |
|
|
{ "ble", OP_JUMP_REL, 2, 0x2f, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
|
| 268 |
|
|
{ "blo", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
|
| 269 |
|
|
{ "bls", OP_JUMP_REL, 2, 0x23, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
|
| 270 |
|
|
{ "blt", OP_JUMP_REL, 2, 0x2d, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
|
| 271 |
|
|
{ "bmi", OP_JUMP_REL, 2, 0x2b, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
|
| 272 |
|
|
{ "bne", OP_JUMP_REL, 2, 0x26, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
|
| 273 |
|
|
{ "bpl", OP_JUMP_REL, 2, 0x2a, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
|
| 274 |
|
|
{ "bra", OP_JUMP_REL, 2, 0x20, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
|
| 275 |
|
|
|
| 276 |
|
|
{ "brclr", OP_BITMASK | OP_JUMP_REL
|
| 277 |
|
|
| OP_DIRECT, 4, 0x13, 6, 6, CHG_NONE, cpu6811 },
|
| 278 |
|
|
{ "brclr", OP_BITMASK | OP_JUMP_REL
|
| 279 |
|
|
| OP_IX, 4, 0x1f, 7, 7, CHG_NONE, cpu6811 },
|
| 280 |
|
|
{ "brclr", OP_BITMASK | OP_JUMP_REL
|
| 281 |
|
|
| OP_IY | OP_PAGE2, 5, 0x1f, 8, 8, CHG_NONE, cpu6811 },
|
| 282 |
|
|
{ "brclr", OP_BITMASK | OP_JUMP_REL
|
| 283 |
|
|
| OP_DIRECT, 4, 0x4f, 4, 4, CHG_NONE, cpu6812 },
|
| 284 |
|
|
{ "brclr", OP_BITMASK | OP_JUMP_REL
|
| 285 |
|
|
| OP_IND16, 5, 0x1f, 5, 5, CHG_NONE, cpu6812 },
|
| 286 |
|
|
{ "brclr", OP_BITMASK | OP_JUMP_REL
|
| 287 |
|
|
| OP_IDX, 4, 0x0f, 4, 4, CHG_NONE, cpu6812 },
|
| 288 |
|
|
{ "brclr", OP_BITMASK | OP_JUMP_REL
|
| 289 |
|
|
| OP_IDX_1, 5, 0x0f, 6, 6, CHG_NONE, cpu6812 },
|
| 290 |
|
|
{ "brclr", OP_BITMASK
|
| 291 |
|
|
| OP_JUMP_REL
|
| 292 |
|
|
| OP_IDX_2, 6, 0x0f, 8, 8, CHG_NONE, cpu6812 },
|
| 293 |
|
|
|
| 294 |
|
|
{ "brn", OP_JUMP_REL, 2, 0x21, 1, 3, CHG_NONE, cpu6811|cpu6812 },
|
| 295 |
|
|
|
| 296 |
|
|
{ "brset", OP_BITMASK | OP_JUMP_REL
|
| 297 |
|
|
| OP_DIRECT, 4, 0x12, 6, 6, CHG_NONE, cpu6811 },
|
| 298 |
|
|
{ "brset", OP_BITMASK
|
| 299 |
|
|
| OP_JUMP_REL
|
| 300 |
|
|
| OP_IX, 4, 0x1e, 7, 7, CHG_NONE, cpu6811 },
|
| 301 |
|
|
{ "brset", OP_BITMASK | OP_JUMP_REL
|
| 302 |
|
|
| OP_IY | OP_PAGE2, 5, 0x1e, 8, 8, CHG_NONE, cpu6811 },
|
| 303 |
|
|
{ "brset", OP_BITMASK | OP_JUMP_REL
|
| 304 |
|
|
| OP_DIRECT, 4, 0x4e, 4, 4, CHG_NONE, cpu6812 },
|
| 305 |
|
|
{ "brset", OP_BITMASK | OP_JUMP_REL
|
| 306 |
|
|
| OP_IND16, 5, 0x1e, 5, 5, CHG_NONE, cpu6812 },
|
| 307 |
|
|
{ "brset", OP_BITMASK | OP_JUMP_REL
|
| 308 |
|
|
| OP_IDX, 4, 0x0e, 4, 4, CHG_NONE, cpu6812 },
|
| 309 |
|
|
{ "brset", OP_BITMASK | OP_JUMP_REL
|
| 310 |
|
|
| OP_IDX_1, 5, 0x0e, 6, 6, CHG_NONE, cpu6812 },
|
| 311 |
|
|
{ "brset", OP_BITMASK | OP_JUMP_REL
|
| 312 |
|
|
| OP_IDX_2, 6, 0x0e, 8, 8, CHG_NONE, cpu6812 },
|
| 313 |
|
|
|
| 314 |
|
|
|
| 315 |
|
|
{ "bset", OP_BITMASK | OP_DIRECT, 3, 0x14, 6, 6, CLR_V_CHG_NZ, cpu6811 },
|
| 316 |
|
|
{ "bset", OP_BITMASK | OP_IX, 3, 0x1c, 7, 7, CLR_V_CHG_NZ, cpu6811 },
|
| 317 |
|
|
{ "bset", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1c, 8, 8, CLR_V_CHG_NZ, cpu6811 },
|
| 318 |
|
|
{ "bset", OP_BITMASK|OP_DIRECT, 3, 0x4c, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 319 |
|
|
{ "bset", OP_BITMASK|OP_IND16, 4, 0x1c, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 320 |
|
|
{ "bset", OP_BITMASK|OP_IDX, 3, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 321 |
|
|
{ "bset", OP_BITMASK|OP_IDX_1, 4, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 322 |
|
|
{ "bset", OP_BITMASK|OP_IDX_2, 5, 0x0c, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 323 |
|
|
|
| 324 |
|
|
{ "bsr", OP_JUMP_REL, 2, 0x8d, 6, 6, CHG_NONE, cpu6811 },
|
| 325 |
|
|
{ "bsr", OP_JUMP_REL, 2, 0x07, 4, 4, CHG_NONE, cpu6812 },
|
| 326 |
|
|
|
| 327 |
|
|
{ "bvc", OP_JUMP_REL, 2, 0x28, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
|
| 328 |
|
|
{ "bvs", OP_JUMP_REL, 2, 0x29, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
|
| 329 |
|
|
|
| 330 |
|
|
{ "call", OP_IND16 | OP_PAGE
|
| 331 |
|
|
| OP_BRANCH, 4, 0x4a, 8, 8, CHG_NONE, cpu6812 },
|
| 332 |
|
|
{ "call", OP_IDX | OP_PAGE
|
| 333 |
|
|
| OP_BRANCH, 3, 0x4b, 8, 8, CHG_NONE, cpu6812 },
|
| 334 |
|
|
{ "call", OP_IDX_1 | OP_PAGE
|
| 335 |
|
|
| OP_BRANCH, 4, 0x4b, 8, 8, CHG_NONE, cpu6812 },
|
| 336 |
|
|
{ "call", OP_IDX_2 | OP_PAGE
|
| 337 |
|
|
| OP_BRANCH, 5, 0x4b, 9, 9, CHG_NONE, cpu6812 },
|
| 338 |
|
|
{ "call", OP_D_IDX
|
| 339 |
|
|
| OP_BRANCH, 2, 0x4b, 10, 10, CHG_NONE, cpu6812 },
|
| 340 |
|
|
{ "call", OP_D_IDX_2
|
| 341 |
|
|
| OP_BRANCH, 4, 0x4b, 10, 10, CHG_NONE, cpu6812 },
|
| 342 |
|
|
|
| 343 |
|
|
{ "cba", OP_NONE, 1, 0x11, 2, 2, CHG_NZVC, cpu6811 },
|
| 344 |
|
|
{ "cba", OP_NONE | OP_PAGE2,2, 0x17, 2, 2, CHG_NZVC, cpu6812 },
|
| 345 |
|
|
|
| 346 |
|
|
{ "clc", OP_NONE, 1, 0x0c, 2, 2, CLR_C, cpu6811 },
|
| 347 |
|
|
{ "cli", OP_NONE, 1, 0x0e, 2, 2, CLR_I, cpu6811 },
|
| 348 |
|
|
|
| 349 |
|
|
{ "clr", OP_IND16, 3, 0x7f, 6, 6, SET_Z_CLR_NVC, cpu6811 },
|
| 350 |
|
|
{ "clr", OP_IX, 2, 0x6f, 6, 6, SET_Z_CLR_NVC, cpu6811 },
|
| 351 |
|
|
{ "clr", OP_IY | OP_PAGE2, 3, 0x6f, 7, 7, SET_Z_CLR_NVC, cpu6811 },
|
| 352 |
|
|
{ "clr", OP_IND16, 3, 0x79, 3, 3, SET_Z_CLR_NVC, cpu6812 },
|
| 353 |
|
|
{ "clr", OP_IDX, 2, 0x69, 2, 2, SET_Z_CLR_NVC, cpu6812 },
|
| 354 |
|
|
{ "clr", OP_IDX_1, 3, 0x69, 3, 3, SET_Z_CLR_NVC, cpu6812 },
|
| 355 |
|
|
{ "clr", OP_IDX_2, 4, 0x69, 4, 4, SET_Z_CLR_NVC, cpu6812 },
|
| 356 |
|
|
{ "clr", OP_D_IDX, 2, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 },
|
| 357 |
|
|
{ "clr", OP_D_IDX_2, 4, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 },
|
| 358 |
|
|
|
| 359 |
|
|
{ "clra", OP_NONE, 1, 0x4f, 2, 2, SET_Z_CLR_NVC, cpu6811 },
|
| 360 |
|
|
{ "clrb", OP_NONE, 1, 0x5f, 2, 2, SET_Z_CLR_NVC, cpu6811 },
|
| 361 |
|
|
{ "clra", OP_NONE, 1, 0x87, 1, 1, SET_Z_CLR_NVC, cpu6812 },
|
| 362 |
|
|
{ "clrb", OP_NONE, 1, 0xc7, 1, 1, SET_Z_CLR_NVC, cpu6812 },
|
| 363 |
|
|
|
| 364 |
|
|
{ "clv", OP_NONE, 1, 0x0a, 2, 2, CLR_V, cpu6811 },
|
| 365 |
|
|
|
| 366 |
|
|
{ "cmpa", OP_IMM8, 2, 0x81, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
|
| 367 |
|
|
{ "cmpa", OP_DIRECT, 2, 0x91, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
|
| 368 |
|
|
{ "cmpa", OP_IND16, 3, 0xb1, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
|
| 369 |
|
|
{ "cmpa", OP_IX, 2, 0xa1, 4, 4, CHG_NZVC, cpu6811 },
|
| 370 |
|
|
{ "cmpa", OP_IY | OP_PAGE2, 3, 0xa1, 5, 5, CHG_NZVC, cpu6811 },
|
| 371 |
|
|
{ "cmpa", OP_IDX, 2, 0xa1, 3, 3, CHG_NZVC, cpu6812 },
|
| 372 |
|
|
{ "cmpa", OP_IDX_1, 3, 0xa1, 3, 3, CHG_NZVC, cpu6812 },
|
| 373 |
|
|
{ "cmpa", OP_IDX_2, 4, 0xa1, 4, 4, CHG_NZVC, cpu6812 },
|
| 374 |
|
|
{ "cmpa", OP_D_IDX, 2, 0xa1, 6, 6, CHG_NZVC, cpu6812 },
|
| 375 |
|
|
{ "cmpa", OP_D_IDX_2, 4, 0xa1, 6, 6, CHG_NZVC, cpu6812 },
|
| 376 |
|
|
|
| 377 |
|
|
{ "cmpb", OP_IMM8, 2, 0xc1, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
|
| 378 |
|
|
{ "cmpb", OP_DIRECT, 2, 0xd1, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
|
| 379 |
|
|
{ "cmpb", OP_IND16, 3, 0xf1, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
|
| 380 |
|
|
{ "cmpb", OP_IX, 2, 0xe1, 4, 4, CHG_NZVC, cpu6811 },
|
| 381 |
|
|
{ "cmpb", OP_IY | OP_PAGE2, 3, 0xe1, 5, 5, CHG_NZVC, cpu6811 },
|
| 382 |
|
|
{ "cmpb", OP_IDX, 2, 0xe1, 3, 3, CHG_NZVC, cpu6812 },
|
| 383 |
|
|
{ "cmpb", OP_IDX_1, 3, 0xe1, 3, 3, CHG_NZVC, cpu6812 },
|
| 384 |
|
|
{ "cmpb", OP_IDX_2, 4, 0xe1, 4, 4, CHG_NZVC, cpu6812 },
|
| 385 |
|
|
{ "cmpb", OP_D_IDX, 2, 0xe1, 6, 6, CHG_NZVC, cpu6812 },
|
| 386 |
|
|
{ "cmpb", OP_D_IDX_2, 4, 0xe1, 6, 6, CHG_NZVC, cpu6812 },
|
| 387 |
|
|
|
| 388 |
|
|
{ "com", OP_IND16, 3, 0x73, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 },
|
| 389 |
|
|
{ "com", OP_IX, 2, 0x63, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 },
|
| 390 |
|
|
{ "com", OP_IY | OP_PAGE2, 3, 0x63, 7, 7, SET_C_CLR_V_CHG_NZ, cpu6811 },
|
| 391 |
|
|
{ "com", OP_IND16, 3, 0x71, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 },
|
| 392 |
|
|
{ "com", OP_IDX, 2, 0x61, 3, 3, SET_C_CLR_V_CHG_NZ, cpu6812 },
|
| 393 |
|
|
{ "com", OP_IDX_1, 3, 0x61, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 },
|
| 394 |
|
|
{ "com", OP_IDX_2, 4, 0x61, 5, 5, SET_C_CLR_V_CHG_NZ, cpu6812 },
|
| 395 |
|
|
{ "com", OP_D_IDX, 2, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 },
|
| 396 |
|
|
{ "com", OP_D_IDX_2, 4, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 },
|
| 397 |
|
|
|
| 398 |
|
|
{ "coma", OP_NONE, 1, 0x43, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 },
|
| 399 |
|
|
{ "coma", OP_NONE, 1, 0x41, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 },
|
| 400 |
|
|
{ "comb", OP_NONE, 1, 0x53, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 },
|
| 401 |
|
|
{ "comb", OP_NONE, 1, 0x51, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 },
|
| 402 |
|
|
|
| 403 |
|
|
{ "cpd", OP_IMM16 | OP_PAGE3, 4, 0x83, 5, 5, CHG_NZVC, cpu6811 },
|
| 404 |
|
|
{ "cpd", OP_DIRECT | OP_PAGE3, 3, 0x93, 6, 6, CHG_NZVC, cpu6811 },
|
| 405 |
|
|
{ "cpd", OP_IND16 | OP_PAGE3, 4, 0xb3, 7, 7, CHG_NZVC, cpu6811 },
|
| 406 |
|
|
{ "cpd", OP_IX | OP_PAGE3, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 },
|
| 407 |
|
|
{ "cpd", OP_IY | OP_PAGE4, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 },
|
| 408 |
|
|
{ "cpd", OP_IMM16, 3, 0x8c, 2, 2, CHG_NZVC, cpu6812 },
|
| 409 |
|
|
{ "cpd", OP_DIRECT, 2, 0x9c, 3, 3, CHG_NZVC, cpu6812 },
|
| 410 |
|
|
{ "cpd", OP_IND16, 3, 0xbc, 3, 3, CHG_NZVC, cpu6812 },
|
| 411 |
|
|
{ "cpd", OP_IDX, 2, 0xac, 3, 3, CHG_NZVC, cpu6812 },
|
| 412 |
|
|
{ "cpd", OP_IDX_1, 3, 0xac, 3, 3, CHG_NZVC, cpu6812 },
|
| 413 |
|
|
{ "cpd", OP_IDX_2, 4, 0xac, 4, 4, CHG_NZVC, cpu6812 },
|
| 414 |
|
|
{ "cpd", OP_D_IDX, 2, 0xac, 6, 6, CHG_NZVC, cpu6812 },
|
| 415 |
|
|
{ "cpd", OP_D_IDX_2, 4, 0xac, 6, 6, CHG_NZVC, cpu6812 },
|
| 416 |
|
|
|
| 417 |
|
|
{ "cps", OP_IMM16, 3, 0x8f, 2, 2, CHG_NZVC, cpu6812 },
|
| 418 |
|
|
{ "cps", OP_DIRECT, 2, 0x9f, 3, 3, CHG_NZVC, cpu6812 },
|
| 419 |
|
|
{ "cps", OP_IND16, 3, 0xbf, 3, 3, CHG_NZVC, cpu6812 },
|
| 420 |
|
|
{ "cps", OP_IDX, 2, 0xaf, 3, 3, CHG_NZVC, cpu6812 },
|
| 421 |
|
|
{ "cps", OP_IDX_1, 3, 0xaf, 3, 3, CHG_NZVC, cpu6812 },
|
| 422 |
|
|
{ "cps", OP_IDX_2, 4, 0xaf, 4, 4, CHG_NZVC, cpu6812 },
|
| 423 |
|
|
{ "cps", OP_D_IDX, 2, 0xaf, 6, 6, CHG_NZVC, cpu6812 },
|
| 424 |
|
|
{ "cps", OP_D_IDX_2, 4, 0xaf, 6, 6, CHG_NZVC, cpu6812 },
|
| 425 |
|
|
|
| 426 |
|
|
{ "cpx", OP_IMM16, 3, 0x8c, 4, 4, CHG_NZVC, cpu6811 },
|
| 427 |
|
|
{ "cpx", OP_DIRECT, 2, 0x9c, 5, 5, CHG_NZVC, cpu6811 },
|
| 428 |
|
|
{ "cpx", OP_IND16, 3, 0xbc, 5, 5, CHG_NZVC, cpu6811 },
|
| 429 |
|
|
{ "cpx", OP_IX, 2, 0xac, 6, 6, CHG_NZVC, cpu6811 },
|
| 430 |
|
|
{ "cpx", OP_IY | OP_PAGE4, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 },
|
| 431 |
|
|
{ "cpx", OP_IMM16, 3, 0x8e, 2, 2, CHG_NZVC, cpu6812 },
|
| 432 |
|
|
{ "cpx", OP_DIRECT, 2, 0x9e, 3, 3, CHG_NZVC, cpu6812 },
|
| 433 |
|
|
{ "cpx", OP_IND16, 3, 0xbe, 3, 3, CHG_NZVC, cpu6812 },
|
| 434 |
|
|
{ "cpx", OP_IDX, 2, 0xae, 3, 3, CHG_NZVC, cpu6812 },
|
| 435 |
|
|
{ "cpx", OP_IDX_1, 3, 0xae, 3, 3, CHG_NZVC, cpu6812 },
|
| 436 |
|
|
{ "cpx", OP_IDX_2, 4, 0xae, 4, 4, CHG_NZVC, cpu6812 },
|
| 437 |
|
|
{ "cpx", OP_D_IDX, 2, 0xae, 6, 6, CHG_NZVC, cpu6812 },
|
| 438 |
|
|
{ "cpx", OP_D_IDX_2, 4, 0xae, 6, 6, CHG_NZVC, cpu6812 },
|
| 439 |
|
|
|
| 440 |
|
|
{ "cpy", OP_PAGE2 | OP_IMM16, 4, 0x8c, 5, 5, CHG_NZVC, cpu6811 },
|
| 441 |
|
|
{ "cpy", OP_PAGE2 | OP_DIRECT, 3, 0x9c, 6, 6, CHG_NZVC, cpu6811 },
|
| 442 |
|
|
{ "cpy", OP_PAGE2 | OP_IY, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 },
|
| 443 |
|
|
{ "cpy", OP_PAGE2 | OP_IND16, 4, 0xbc, 7, 7, CHG_NZVC, cpu6811 },
|
| 444 |
|
|
{ "cpy", OP_PAGE3 | OP_IX, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 },
|
| 445 |
|
|
{ "cpy", OP_IMM16, 3, 0x8d, 2, 2, CHG_NZVC, cpu6812 },
|
| 446 |
|
|
{ "cpy", OP_DIRECT, 2, 0x9d, 3, 3, CHG_NZVC, cpu6812 },
|
| 447 |
|
|
{ "cpy", OP_IND16, 3, 0xbd, 3, 3, CHG_NZVC, cpu6812 },
|
| 448 |
|
|
{ "cpy", OP_IDX, 2, 0xad, 3, 3, CHG_NZVC, cpu6812 },
|
| 449 |
|
|
{ "cpy", OP_IDX_1, 3, 0xad, 3, 3, CHG_NZVC, cpu6812 },
|
| 450 |
|
|
{ "cpy", OP_IDX_2, 4, 0xad, 4, 4, CHG_NZVC, cpu6812 },
|
| 451 |
|
|
{ "cpy", OP_D_IDX, 2, 0xad, 6, 6, CHG_NZVC, cpu6812 },
|
| 452 |
|
|
{ "cpy", OP_D_IDX_2, 4, 0xad, 6, 6, CHG_NZVC, cpu6812 },
|
| 453 |
|
|
|
| 454 |
|
|
/* After 'daa', the Z flag is undefined. Mark it as changed. */
|
| 455 |
|
|
{ "daa", OP_NONE, 1, 0x19, 2, 2, CHG_NZVC, cpu6811 },
|
| 456 |
|
|
{ "daa", OP_NONE | OP_PAGE2, 2, 0x07, 3, 3, CHG_NZVC, cpu6812 },
|
| 457 |
|
|
|
| 458 |
|
|
{ "dbeq", OP_DBEQ_MARKER
|
| 459 |
|
|
| OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 },
|
| 460 |
|
|
{ "dbne", OP_DBNE_MARKER
|
| 461 |
|
|
| OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 },
|
| 462 |
|
|
|
| 463 |
|
|
{ "dec", OP_IX, 2, 0x6a, 6, 6, CHG_NZV, cpu6811 },
|
| 464 |
|
|
{ "dec", OP_IND16, 3, 0x7a, 6, 6, CHG_NZV, cpu6811 },
|
| 465 |
|
|
{ "dec", OP_IY | OP_PAGE2, 3, 0x6a, 7, 7, CHG_NZV, cpu6811 },
|
| 466 |
|
|
{ "dec", OP_IND16, 3, 0x73, 4, 4, CHG_NZV, cpu6812 },
|
| 467 |
|
|
{ "dec", OP_IDX, 2, 0x63, 3, 3, CHG_NZV, cpu6812 },
|
| 468 |
|
|
{ "dec", OP_IDX_1, 3, 0x63, 4, 4, CHG_NZV, cpu6812 },
|
| 469 |
|
|
{ "dec", OP_IDX_2, 4, 0x63, 5, 5, CHG_NZV, cpu6812 },
|
| 470 |
|
|
{ "dec", OP_D_IDX, 2, 0x63, 6, 6, CHG_NZV, cpu6812 },
|
| 471 |
|
|
{ "dec", OP_D_IDX_2, 4, 0x63, 6, 6, CHG_NZV, cpu6812 },
|
| 472 |
|
|
|
| 473 |
|
|
{ "des", OP_NONE, 1, 0x34, 3, 3, CHG_NONE, cpu6811 },
|
| 474 |
|
|
|
| 475 |
|
|
{ "deca", OP_NONE, 1, 0x4a, 2, 2, CHG_NZV, cpu6811 },
|
| 476 |
|
|
{ "deca", OP_NONE, 1, 0x43, 1, 1, CHG_NZV, cpu6812 },
|
| 477 |
|
|
{ "decb", OP_NONE, 1, 0x5a, 2, 2, CHG_NZV, cpu6811 },
|
| 478 |
|
|
{ "decb", OP_NONE, 1, 0x53, 1, 1, CHG_NZV, cpu6812 },
|
| 479 |
|
|
|
| 480 |
|
|
{ "dex", OP_NONE, 1, 0x09, 1, 1, CHG_Z, cpu6812|cpu6811 },
|
| 481 |
|
|
{ "dey", OP_NONE | OP_PAGE2, 2, 0x09, 4, 4, CHG_Z, cpu6811 },
|
| 482 |
|
|
{ "dey", OP_NONE, 1, 0x03, 1, 1, CHG_Z, cpu6812 },
|
| 483 |
|
|
|
| 484 |
|
|
{ "ediv", OP_NONE, 1, 0x11, 11, 11, CHG_NZVC, cpu6812 },
|
| 485 |
|
|
{ "edivs", OP_NONE | OP_PAGE2, 2, 0x14, 12, 12, CHG_NZVC, cpu6812 },
|
| 486 |
|
|
{ "emacs", OP_IND16 | OP_PAGE2, 4, 0x12, 13, 13, CHG_NZVC, cpu6812 },
|
| 487 |
|
|
|
| 488 |
|
|
{ "emaxd", OP_IDX | OP_PAGE2, 3, 0x1a, 4, 4, CHG_NZVC, cpu6812 },
|
| 489 |
|
|
{ "emaxd", OP_IDX_1 | OP_PAGE2, 4, 0x1a, 4, 4, CHG_NZVC, cpu6812 },
|
| 490 |
|
|
{ "emaxd", OP_IDX_2 | OP_PAGE2, 5, 0x1a, 5, 5, CHG_NZVC, cpu6812 },
|
| 491 |
|
|
{ "emaxd", OP_D_IDX | OP_PAGE2, 3, 0x1a, 7, 7, CHG_NZVC, cpu6812 },
|
| 492 |
|
|
{ "emaxd", OP_D_IDX_2 | OP_PAGE2, 5, 0x1a, 7, 7, CHG_NZVC, cpu6812 },
|
| 493 |
|
|
|
| 494 |
|
|
{ "emaxm", OP_IDX | OP_PAGE2, 3, 0x1e, 4, 4, CHG_NZVC, cpu6812 },
|
| 495 |
|
|
{ "emaxm", OP_IDX_1 | OP_PAGE2, 4, 0x1e, 5, 5, CHG_NZVC, cpu6812 },
|
| 496 |
|
|
{ "emaxm", OP_IDX_2 | OP_PAGE2, 5, 0x1e, 6, 6, CHG_NZVC, cpu6812 },
|
| 497 |
|
|
{ "emaxm", OP_D_IDX | OP_PAGE2, 3, 0x1e, 7, 7, CHG_NZVC, cpu6812 },
|
| 498 |
|
|
{ "emaxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1e, 7, 7, CHG_NZVC, cpu6812 },
|
| 499 |
|
|
|
| 500 |
|
|
{ "emind", OP_IDX | OP_PAGE2, 3, 0x1b, 4, 4, CHG_NZVC, cpu6812 },
|
| 501 |
|
|
{ "emind", OP_IDX_1 | OP_PAGE2, 4, 0x1b, 4, 4, CHG_NZVC, cpu6812 },
|
| 502 |
|
|
{ "emind", OP_IDX_2 | OP_PAGE2, 5, 0x1b, 5, 5, CHG_NZVC, cpu6812 },
|
| 503 |
|
|
{ "emind", OP_D_IDX | OP_PAGE2, 3, 0x1b, 7, 7, CHG_NZVC, cpu6812 },
|
| 504 |
|
|
{ "emind", OP_D_IDX_2 | OP_PAGE2, 5, 0x1b, 7, 7, CHG_NZVC, cpu6812 },
|
| 505 |
|
|
|
| 506 |
|
|
{ "eminm", OP_IDX | OP_PAGE2, 3, 0x1f, 4, 4, CHG_NZVC, cpu6812 },
|
| 507 |
|
|
{ "eminm", OP_IDX_1 | OP_PAGE2, 4, 0x1f, 5, 5, CHG_NZVC, cpu6812 },
|
| 508 |
|
|
{ "eminm", OP_IDX_2 | OP_PAGE2, 5, 0x1f, 6, 6, CHG_NZVC, cpu6812 },
|
| 509 |
|
|
{ "eminm", OP_D_IDX | OP_PAGE2, 3, 0x1f, 7, 7, CHG_NZVC, cpu6812 },
|
| 510 |
|
|
{ "eminm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1f, 7, 7, CHG_NZVC, cpu6812 },
|
| 511 |
|
|
|
| 512 |
|
|
{ "emul", OP_NONE, 1, 0x13, 3, 3, CHG_NZC, cpu6812 },
|
| 513 |
|
|
{ "emuls", OP_NONE | OP_PAGE2, 2, 0x13, 3, 3, CHG_NZC, cpu6812 },
|
| 514 |
|
|
|
| 515 |
|
|
{ "eora", OP_IMM8, 2, 0x88, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 516 |
|
|
{ "eora", OP_DIRECT, 2, 0x98, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 517 |
|
|
{ "eora", OP_IND16, 3, 0xb8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 518 |
|
|
{ "eora", OP_IX, 2, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6811 },
|
| 519 |
|
|
{ "eora", OP_IY | OP_PAGE2, 3, 0xa8, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 520 |
|
|
{ "eora", OP_IDX, 2, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 521 |
|
|
{ "eora", OP_IDX_1, 3, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 522 |
|
|
{ "eora", OP_IDX_2, 4, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 523 |
|
|
{ "eora", OP_D_IDX, 2, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 524 |
|
|
{ "eora", OP_D_IDX_2, 4, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 525 |
|
|
|
| 526 |
|
|
{ "eorb", OP_IMM8, 2, 0xc8, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 527 |
|
|
{ "eorb", OP_DIRECT, 2, 0xd8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 528 |
|
|
{ "eorb", OP_IND16, 3, 0xf8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 529 |
|
|
{ "eorb", OP_IX, 2, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6811 },
|
| 530 |
|
|
{ "eorb", OP_IY | OP_PAGE2, 3, 0xe8, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 531 |
|
|
{ "eorb", OP_IDX, 2, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 532 |
|
|
{ "eorb", OP_IDX_1, 3, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 533 |
|
|
{ "eorb", OP_IDX_2, 4, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 534 |
|
|
{ "eorb", OP_D_IDX, 2, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 535 |
|
|
{ "eorb", OP_D_IDX_2, 4, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 536 |
|
|
|
| 537 |
|
|
{ "etbl", OP_IDX | OP_PAGE2,3, 0x3f, 10, 10, CHG_NZC, cpu6812 },
|
| 538 |
|
|
|
| 539 |
|
|
{ "exg", OP_EXG_MARKER
|
| 540 |
|
|
| OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 },
|
| 541 |
|
|
|
| 542 |
|
|
{ "fdiv", OP_NONE, 1, 0x03, 3, 41, CHG_ZVC, cpu6811},
|
| 543 |
|
|
{ "fdiv", OP_NONE | OP_PAGE2, 2, 0x11, 12, 12, CHG_ZVC, cpu6812 },
|
| 544 |
|
|
|
| 545 |
|
|
{ "ibeq", OP_IBEQ_MARKER
|
| 546 |
|
|
| OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 },
|
| 547 |
|
|
{ "ibne", OP_IBNE_MARKER
|
| 548 |
|
|
| OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 },
|
| 549 |
|
|
|
| 550 |
|
|
{ "idiv", OP_NONE, 1, 0x02, 3, 41, CLR_V_CHG_ZC, cpu6811},
|
| 551 |
|
|
{ "idiv", OP_NONE | OP_PAGE2, 2, 0x10, 12, 12, CLR_V_CHG_ZC, cpu6812 },
|
| 552 |
|
|
{ "idivs", OP_NONE | OP_PAGE2, 2, 0x15, 12, 12, CHG_NZVC, cpu6812 },
|
| 553 |
|
|
|
| 554 |
|
|
{ "inc", OP_IX, 2, 0x6c, 6, 6, CHG_NZV, cpu6811 },
|
| 555 |
|
|
{ "inc", OP_IND16, 3, 0x7c, 6, 6, CHG_NZV, cpu6811 },
|
| 556 |
|
|
{ "inc", OP_IY | OP_PAGE2, 3, 0x6c, 7, 7, CHG_NZV, cpu6811 },
|
| 557 |
|
|
{ "inc", OP_IND16, 3, 0x72, 4, 4, CHG_NZV, cpu6812 },
|
| 558 |
|
|
{ "inc", OP_IDX, 2, 0x62, 3, 3, CHG_NZV, cpu6812 },
|
| 559 |
|
|
{ "inc", OP_IDX_1, 3, 0x62, 4, 4, CHG_NZV, cpu6812 },
|
| 560 |
|
|
{ "inc", OP_IDX_2, 4, 0x62, 5, 5, CHG_NZV, cpu6812 },
|
| 561 |
|
|
{ "inc", OP_D_IDX, 2, 0x62, 6, 6, CHG_NZV, cpu6812 },
|
| 562 |
|
|
{ "inc", OP_D_IDX_2, 4, 0x62, 6, 6, CHG_NZV, cpu6812 },
|
| 563 |
|
|
|
| 564 |
|
|
{ "inca", OP_NONE, 1, 0x4c, 2, 2, CHG_NZV, cpu6811 },
|
| 565 |
|
|
{ "inca", OP_NONE, 1, 0x42, 1, 1, CHG_NZV, cpu6812 },
|
| 566 |
|
|
{ "incb", OP_NONE, 1, 0x5c, 2, 2, CHG_NZV, cpu6811 },
|
| 567 |
|
|
{ "incb", OP_NONE, 1, 0x52, 1, 1, CHG_NZV, cpu6812 },
|
| 568 |
|
|
|
| 569 |
|
|
{ "ins", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6811 },
|
| 570 |
|
|
|
| 571 |
|
|
{ "inx", OP_NONE, 1, 0x08, 1, 1, CHG_Z, cpu6811|cpu6812 },
|
| 572 |
|
|
{ "iny", OP_NONE |OP_PAGE2, 2, 0x08, 4, 4, CHG_Z, cpu6811 },
|
| 573 |
|
|
{ "iny", OP_NONE, 1, 0x02, 1, 1, CHG_Z, cpu6812 },
|
| 574 |
|
|
|
| 575 |
|
|
{ "jmp", OP_IND16 | OP_BRANCH, 3, 0x7e, 3, 3, CHG_NONE, cpu6811 },
|
| 576 |
|
|
{ "jmp", OP_IX, 2, 0x6e, 3, 3, CHG_NONE, cpu6811 },
|
| 577 |
|
|
{ "jmp", OP_IY | OP_PAGE2, 3, 0x6e, 4, 4, CHG_NONE, cpu6811 },
|
| 578 |
|
|
{ "jmp", OP_IND16 | OP_BRANCH, 3, 0x06, 3, 3, CHG_NONE, cpu6812 },
|
| 579 |
|
|
{ "jmp", OP_IDX, 2, 0x05, 3, 3, CHG_NONE, cpu6812 },
|
| 580 |
|
|
{ "jmp", OP_IDX_1, 3, 0x05, 3, 3, CHG_NONE, cpu6812 },
|
| 581 |
|
|
{ "jmp", OP_IDX_2, 4, 0x05, 4, 4, CHG_NONE, cpu6812 },
|
| 582 |
|
|
{ "jmp", OP_D_IDX, 2, 0x05, 6, 6, CHG_NONE, cpu6812 },
|
| 583 |
|
|
{ "jmp", OP_D_IDX_2, 4, 0x05, 6, 6, CHG_NONE, cpu6812 },
|
| 584 |
|
|
|
| 585 |
|
|
{ "jsr", OP_DIRECT | OP_BRANCH, 2, 0x9d, 5, 5, CHG_NONE, cpu6811 },
|
| 586 |
|
|
{ "jsr", OP_IND16 | OP_BRANCH, 3, 0xbd, 6, 6, CHG_NONE, cpu6811 },
|
| 587 |
|
|
{ "jsr", OP_IX, 2, 0xad, 6, 6, CHG_NONE, cpu6811 },
|
| 588 |
|
|
{ "jsr", OP_IY | OP_PAGE2, 3, 0xad, 6, 6, CHG_NONE, cpu6811 },
|
| 589 |
|
|
{ "jsr", OP_DIRECT | OP_BRANCH, 2, 0x17, 4, 4, CHG_NONE, cpu6812 },
|
| 590 |
|
|
{ "jsr", OP_IND16 | OP_BRANCH, 3, 0x16, 4, 3, CHG_NONE, cpu6812 },
|
| 591 |
|
|
{ "jsr", OP_IDX, 2, 0x15, 4, 4, CHG_NONE, cpu6812 },
|
| 592 |
|
|
{ "jsr", OP_IDX_1, 3, 0x15, 4, 4, CHG_NONE, cpu6812 },
|
| 593 |
|
|
{ "jsr", OP_IDX_2, 4, 0x15, 5, 5, CHG_NONE, cpu6812 },
|
| 594 |
|
|
{ "jsr", OP_D_IDX, 2, 0x15, 7, 7, CHG_NONE, cpu6812 },
|
| 595 |
|
|
{ "jsr", OP_D_IDX_2, 4, 0x15, 7, 7, CHG_NONE, cpu6812 },
|
| 596 |
|
|
|
| 597 |
|
|
{ "lbcc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 },
|
| 598 |
|
|
{ "lbcs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 },
|
| 599 |
|
|
{ "lbeq", OP_JUMP_REL16 | OP_PAGE2, 4, 0x27, 3, 4, CHG_NONE, cpu6812 },
|
| 600 |
|
|
{ "lbge", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2c, 3, 4, CHG_NONE, cpu6812 },
|
| 601 |
|
|
{ "lbgt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2e, 3, 4, CHG_NONE, cpu6812 },
|
| 602 |
|
|
{ "lbhi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x22, 3, 4, CHG_NONE, cpu6812 },
|
| 603 |
|
|
{ "lbhs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 },
|
| 604 |
|
|
{ "lble", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2f, 3, 4, CHG_NONE, cpu6812 },
|
| 605 |
|
|
{ "lblo", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 },
|
| 606 |
|
|
{ "lbls", OP_JUMP_REL16 | OP_PAGE2, 4, 0x23, 3, 4, CHG_NONE, cpu6812 },
|
| 607 |
|
|
{ "lblt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2d, 3, 4, CHG_NONE, cpu6812 },
|
| 608 |
|
|
{ "lbmi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2b, 3, 4, CHG_NONE, cpu6812 },
|
| 609 |
|
|
{ "lbne", OP_JUMP_REL16 | OP_PAGE2, 4, 0x26, 3, 4, CHG_NONE, cpu6812 },
|
| 610 |
|
|
{ "lbpl", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2a, 3, 4, CHG_NONE, cpu6812 },
|
| 611 |
|
|
{ "lbra", OP_JUMP_REL16 | OP_PAGE2, 4, 0x20, 4, 4, CHG_NONE, cpu6812 },
|
| 612 |
|
|
{ "lbrn", OP_JUMP_REL16 | OP_PAGE2, 4, 0x21, 3, 3, CHG_NONE, cpu6812 },
|
| 613 |
|
|
{ "lbvc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x28, 3, 4, CHG_NONE, cpu6812 },
|
| 614 |
|
|
{ "lbvs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x29, 3, 4, CHG_NONE, cpu6812 },
|
| 615 |
|
|
|
| 616 |
|
|
{ "ldaa", OP_IMM8, 2, 0x86, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 617 |
|
|
{ "ldaa", OP_DIRECT, 2, 0x96, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 618 |
|
|
{ "ldaa", OP_IND16, 3, 0xb6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 619 |
|
|
{ "ldaa", OP_IX, 2, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6811 },
|
| 620 |
|
|
{ "ldaa", OP_IY | OP_PAGE2, 3, 0xa6, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 621 |
|
|
{ "ldaa", OP_IDX, 2, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 622 |
|
|
{ "ldaa", OP_IDX_1, 3, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 623 |
|
|
{ "ldaa", OP_IDX_2, 4, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 624 |
|
|
{ "ldaa", OP_D_IDX, 2, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 625 |
|
|
{ "ldaa", OP_D_IDX_2, 4, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 626 |
|
|
|
| 627 |
|
|
{ "ldab", OP_IMM8, 2, 0xc6, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 628 |
|
|
{ "ldab", OP_DIRECT, 2, 0xd6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 629 |
|
|
{ "ldab", OP_IND16, 3, 0xf6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 630 |
|
|
{ "ldab", OP_IX, 2, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6811 },
|
| 631 |
|
|
{ "ldab", OP_IY | OP_PAGE2, 3, 0xe6, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 632 |
|
|
{ "ldab", OP_IDX, 2, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 633 |
|
|
{ "ldab", OP_IDX_1, 3, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 634 |
|
|
{ "ldab", OP_IDX_2, 4, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 635 |
|
|
{ "ldab", OP_D_IDX, 2, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 636 |
|
|
{ "ldab", OP_D_IDX_2, 4, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 637 |
|
|
|
| 638 |
|
|
{ "ldd", OP_IMM16, 3, 0xcc, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 639 |
|
|
{ "ldd", OP_DIRECT, 2, 0xdc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 640 |
|
|
{ "ldd", OP_IND16, 3, 0xfc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 641 |
|
|
{ "ldd", OP_IX, 2, 0xec, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 642 |
|
|
{ "ldd", OP_IY | OP_PAGE2, 3, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6811 },
|
| 643 |
|
|
{ "ldd", OP_IDX, 2, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 644 |
|
|
{ "ldd", OP_IDX_1, 3, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 645 |
|
|
{ "ldd", OP_IDX_2, 4, 0xec, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 646 |
|
|
{ "ldd", OP_D_IDX, 2, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 647 |
|
|
{ "ldd", OP_D_IDX_2, 4, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 648 |
|
|
|
| 649 |
|
|
{ "lds", OP_IMM16, 3, 0x8e, 3, 3, CLR_V_CHG_NZ, cpu6811 },
|
| 650 |
|
|
{ "lds", OP_DIRECT, 2, 0x9e, 4, 4, CLR_V_CHG_NZ, cpu6811 },
|
| 651 |
|
|
{ "lds", OP_IND16, 3, 0xbe, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 652 |
|
|
{ "lds", OP_IX, 2, 0xae, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 653 |
|
|
{ "lds", OP_IY | OP_PAGE2, 3, 0xae, 6, 6, CLR_V_CHG_NZ, cpu6811 },
|
| 654 |
|
|
{ "lds", OP_IMM16, 3, 0xcf, 2, 2, CLR_V_CHG_NZ, cpu6812 },
|
| 655 |
|
|
{ "lds", OP_DIRECT, 2, 0xdf, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 656 |
|
|
{ "lds", OP_IND16, 3, 0xff, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 657 |
|
|
{ "lds", OP_IDX, 2, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 658 |
|
|
{ "lds", OP_IDX_1, 3, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 659 |
|
|
{ "lds", OP_IDX_2, 4, 0xef, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 660 |
|
|
{ "lds", OP_D_IDX, 2, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 661 |
|
|
{ "lds", OP_D_IDX_2, 4, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 662 |
|
|
|
| 663 |
|
|
{ "ldx", OP_IMM16, 3, 0xce, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 664 |
|
|
{ "ldx", OP_DIRECT, 2, 0xde, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 665 |
|
|
{ "ldx", OP_IND16, 3, 0xfe, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 666 |
|
|
{ "ldx", OP_IX, 2, 0xee, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 667 |
|
|
{ "ldx", OP_IY | OP_PAGE4, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 },
|
| 668 |
|
|
{ "ldx", OP_IDX, 2, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 669 |
|
|
{ "ldx", OP_IDX_1, 3, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 670 |
|
|
{ "ldx", OP_IDX_2, 4, 0xee, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 671 |
|
|
{ "ldx", OP_D_IDX, 2, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 672 |
|
|
{ "ldx", OP_D_IDX_2, 4, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 673 |
|
|
|
| 674 |
|
|
{ "ldy", OP_IMM16 | OP_PAGE2, 4, 0xce, 4, 4, CLR_V_CHG_NZ, cpu6811 },
|
| 675 |
|
|
{ "ldy", OP_DIRECT | OP_PAGE2, 3, 0xde, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 676 |
|
|
{ "ldy", OP_IND16 | OP_PAGE2, 4, 0xfe, 6, 6, CLR_V_CHG_NZ, cpu6811 },
|
| 677 |
|
|
{ "ldy", OP_IX | OP_PAGE3, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 },
|
| 678 |
|
|
{ "ldy", OP_IY | OP_PAGE2, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 },
|
| 679 |
|
|
{ "ldy", OP_IMM16, 3, 0xcd, 2, 2, CLR_V_CHG_NZ, cpu6812 },
|
| 680 |
|
|
{ "ldy", OP_DIRECT, 2, 0xdd, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 681 |
|
|
{ "ldy", OP_IND16, 3, 0xfd, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 682 |
|
|
{ "ldy", OP_IDX, 2, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 683 |
|
|
{ "ldy", OP_IDX_1, 3, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 684 |
|
|
{ "ldy", OP_IDX_2, 4, 0xed, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 685 |
|
|
{ "ldy", OP_D_IDX, 2, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 686 |
|
|
{ "ldy", OP_D_IDX_2, 4, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 687 |
|
|
|
| 688 |
|
|
{ "leas", OP_IDX, 2, 0x1b, 2, 2, CHG_NONE, cpu6812 },
|
| 689 |
|
|
{ "leas", OP_IDX_1, 3, 0x1b, 2, 2, CHG_NONE, cpu6812 },
|
| 690 |
|
|
{ "leas", OP_IDX_2, 4, 0x1b, 2, 2, CHG_NONE, cpu6812 },
|
| 691 |
|
|
|
| 692 |
|
|
{ "leax", OP_IDX, 2, 0x1a, 2, 2, CHG_NONE, cpu6812 },
|
| 693 |
|
|
{ "leax", OP_IDX_1, 3, 0x1a, 2, 2, CHG_NONE, cpu6812 },
|
| 694 |
|
|
{ "leax", OP_IDX_2, 4, 0x1a, 2, 2, CHG_NONE, cpu6812 },
|
| 695 |
|
|
|
| 696 |
|
|
{ "leay", OP_IDX, 2, 0x19, 2, 2, CHG_NONE, cpu6812 },
|
| 697 |
|
|
{ "leay", OP_IDX_1, 3, 0x19, 2, 2, CHG_NONE, cpu6812 },
|
| 698 |
|
|
{ "leay", OP_IDX_2, 4, 0x19, 2, 2, CHG_NONE, cpu6812 },
|
| 699 |
|
|
|
| 700 |
|
|
{ "lsl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812 },
|
| 701 |
|
|
{ "lsl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 },
|
| 702 |
|
|
{ "lsl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 },
|
| 703 |
|
|
{ "lsl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 },
|
| 704 |
|
|
{ "lsl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 },
|
| 705 |
|
|
{ "lsl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 },
|
| 706 |
|
|
{ "lsl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 },
|
| 707 |
|
|
{ "lsl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 },
|
| 708 |
|
|
|
| 709 |
|
|
{ "lsla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
|
| 710 |
|
|
{ "lslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
|
| 711 |
|
|
{ "lsld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 },
|
| 712 |
|
|
{ "lsld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 },
|
| 713 |
|
|
|
| 714 |
|
|
{ "lsr", OP_IND16, 3, 0x74, 4, 4, CLR_N_CHG_ZVC, cpu6811|cpu6812},
|
| 715 |
|
|
{ "lsr", OP_IX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6811 },
|
| 716 |
|
|
{ "lsr", OP_IY | OP_PAGE2, 3, 0x64, 7, 7, CLR_V_CHG_ZVC, cpu6811 },
|
| 717 |
|
|
{ "lsr", OP_IDX, 2, 0x64, 3, 3, CLR_N_CHG_ZVC, cpu6812 },
|
| 718 |
|
|
{ "lsr", OP_IDX_1, 3, 0x64, 4, 4, CLR_N_CHG_ZVC, cpu6812 },
|
| 719 |
|
|
{ "lsr", OP_IDX_2, 4, 0x64, 5, 5, CLR_N_CHG_ZVC, cpu6812 },
|
| 720 |
|
|
{ "lsr", OP_D_IDX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 },
|
| 721 |
|
|
{ "lsr", OP_D_IDX_2, 4, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 },
|
| 722 |
|
|
|
| 723 |
|
|
{ "lsra", OP_NONE, 1, 0x44, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812},
|
| 724 |
|
|
{ "lsrb", OP_NONE, 1, 0x54, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812},
|
| 725 |
|
|
{ "lsrd", OP_NONE, 1, 0x04, 3, 3, CLR_N_CHG_ZVC, cpu6811 },
|
| 726 |
|
|
{ "lsrd", OP_NONE, 1, 0x49, 1, 1, CLR_N_CHG_ZVC, cpu6812 },
|
| 727 |
|
|
|
| 728 |
|
|
{ "maxa", OP_IDX | OP_PAGE2, 3, 0x18, 4, 4, CHG_NZVC, cpu6812 },
|
| 729 |
|
|
{ "maxa", OP_IDX_1 | OP_PAGE2, 4, 0x18, 4, 4, CHG_NZVC, cpu6812 },
|
| 730 |
|
|
{ "maxa", OP_IDX_2 | OP_PAGE2, 5, 0x18, 5, 5, CHG_NZVC, cpu6812 },
|
| 731 |
|
|
{ "maxa", OP_D_IDX | OP_PAGE2, 3, 0x18, 7, 7, CHG_NZVC, cpu6812 },
|
| 732 |
|
|
{ "maxa", OP_D_IDX_2 | OP_PAGE2, 5, 0x18, 7, 7, CHG_NZVC, cpu6812 },
|
| 733 |
|
|
|
| 734 |
|
|
{ "maxm", OP_IDX | OP_PAGE2, 3, 0x1c, 4, 4, CHG_NZVC, cpu6812 },
|
| 735 |
|
|
{ "maxm", OP_IDX_1 | OP_PAGE2, 4, 0x1c, 5, 5, CHG_NZVC, cpu6812 },
|
| 736 |
|
|
{ "maxm", OP_IDX_2 | OP_PAGE2, 5, 0x1c, 6, 6, CHG_NZVC, cpu6812 },
|
| 737 |
|
|
{ "maxm", OP_D_IDX | OP_PAGE2, 3, 0x1c, 7, 7, CHG_NZVC, cpu6812 },
|
| 738 |
|
|
{ "maxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1c, 7, 7, CHG_NZVC, cpu6812 },
|
| 739 |
|
|
|
| 740 |
|
|
{ "mem", OP_NONE, 1, 0x01, 5, 5, CHG_HNZVC, cpu6812 },
|
| 741 |
|
|
|
| 742 |
|
|
{ "mina", OP_IDX | OP_PAGE2, 3, 0x19, 4, 4, CHG_NZVC, cpu6812 },
|
| 743 |
|
|
{ "mina", OP_IDX_1 | OP_PAGE2, 4, 0x19, 4, 4, CHG_NZVC, cpu6812 },
|
| 744 |
|
|
{ "mina", OP_IDX_2 | OP_PAGE2, 5, 0x19, 5, 5, CHG_NZVC, cpu6812 },
|
| 745 |
|
|
{ "mina", OP_D_IDX | OP_PAGE2, 3, 0x19, 7, 7, CHG_NZVC, cpu6812 },
|
| 746 |
|
|
{ "mina", OP_D_IDX_2 | OP_PAGE2, 5, 0x19, 7, 7, CHG_NZVC, cpu6812 },
|
| 747 |
|
|
|
| 748 |
|
|
{ "minm", OP_IDX | OP_PAGE2, 3, 0x1d, 4, 4, CHG_NZVC, cpu6812 },
|
| 749 |
|
|
{ "minm", OP_IDX_1 | OP_PAGE2, 4, 0x1d, 5, 5, CHG_NZVC, cpu6812 },
|
| 750 |
|
|
{ "minm", OP_IDX_2 | OP_PAGE2, 5, 0x1d, 6, 6, CHG_NZVC, cpu6812 },
|
| 751 |
|
|
{ "minm", OP_D_IDX | OP_PAGE2, 3, 0x1d, 7, 7, CHG_NZVC, cpu6812 },
|
| 752 |
|
|
{ "minm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1d, 7, 7, CHG_NZVC, cpu6812 },
|
| 753 |
|
|
|
| 754 |
|
|
{ "movb", OP_IMM8|OP_IND16_p2|OP_PAGE2, 5, 0x0b, 4, 4, CHG_NONE, cpu6812 },
|
| 755 |
|
|
{ "movb", OP_IMM8|OP_IDX_p2|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu6812 },
|
| 756 |
|
|
{ "movb", OP_IND16|OP_IND16_p2|OP_PAGE2, 6, 0x0c, 6, 6, CHG_NONE, cpu6812 },
|
| 757 |
|
|
{ "movb", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu6812 },
|
| 758 |
|
|
{ "movb", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu6812 },
|
| 759 |
|
|
{ "movb", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu6812 },
|
| 760 |
|
|
|
| 761 |
|
|
{ "movw", OP_IMM16 | OP_IND16_p2 | OP_PAGE2, 6, 0x03, 5, 5, CHG_NONE, cpu6812 },
|
| 762 |
|
|
{ "movw", OP_IMM16 | OP_IDX_p2 | OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, cpu6812 },
|
| 763 |
|
|
{ "movw", OP_IND16 | OP_IND16_p2 | OP_PAGE2, 6, 0x04, 6, 6, CHG_NONE, cpu6812 },
|
| 764 |
|
|
{ "movw", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu6812 },
|
| 765 |
|
|
{ "movw", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu6812 },
|
| 766 |
|
|
{ "movw", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu6812 },
|
| 767 |
|
|
|
| 768 |
|
|
{ "mul", OP_NONE, 1, 0x3d, 3, 10, CHG_C, cpu6811 },
|
| 769 |
|
|
{ "mul", OP_NONE, 1, 0x12, 3, 3, CHG_C, cpu6812 },
|
| 770 |
|
|
|
| 771 |
|
|
{ "neg", OP_IND16, 3, 0x70, 4, 4, CHG_NZVC, cpu6811|cpu6812 },
|
| 772 |
|
|
{ "neg", OP_IX, 2, 0x60, 6, 6, CHG_NZVC, cpu6811 },
|
| 773 |
|
|
{ "neg", OP_IY | OP_PAGE2, 3, 0x60, 7, 7, CHG_NZVC, cpu6811 },
|
| 774 |
|
|
{ "neg", OP_IDX, 2, 0x60, 3, 3, CHG_NZVC, cpu6812 },
|
| 775 |
|
|
{ "neg", OP_IDX_1, 3, 0x60, 4, 4, CHG_NZVC, cpu6812 },
|
| 776 |
|
|
{ "neg", OP_IDX_2, 4, 0x60, 5, 5, CHG_NZVC, cpu6812 },
|
| 777 |
|
|
{ "neg", OP_D_IDX, 2, 0x60, 6, 6, CHG_NZVC, cpu6812 },
|
| 778 |
|
|
{ "neg", OP_D_IDX_2, 4, 0x60, 6, 6, CHG_NZVC, cpu6812 },
|
| 779 |
|
|
|
| 780 |
|
|
{ "nega", OP_NONE, 1, 0x40, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
|
| 781 |
|
|
{ "negb", OP_NONE, 1, 0x50, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
|
| 782 |
|
|
{ "nop", OP_NONE, 1, 0x01, 2, 2, CHG_NONE, cpu6811 },
|
| 783 |
|
|
{ "nop", OP_NONE, 1, 0xa7, 1, 1, CHG_NONE, cpu6812 },
|
| 784 |
|
|
|
| 785 |
|
|
{ "oraa", OP_IMM8, 2, 0x8a, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 786 |
|
|
{ "oraa", OP_DIRECT, 2, 0x9a, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 787 |
|
|
{ "oraa", OP_IND16, 3, 0xba, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 788 |
|
|
{ "oraa", OP_IX, 2, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6811 },
|
| 789 |
|
|
{ "oraa", OP_IY | OP_PAGE2, 3, 0xaa, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 790 |
|
|
{ "oraa", OP_IDX, 2, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 791 |
|
|
{ "oraa", OP_IDX_1, 3, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 792 |
|
|
{ "oraa", OP_IDX_2, 4, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 793 |
|
|
{ "oraa", OP_D_IDX, 2, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 794 |
|
|
{ "oraa", OP_D_IDX_2, 4, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 795 |
|
|
|
| 796 |
|
|
{ "orab", OP_IMM8, 2, 0xca, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 797 |
|
|
{ "orab", OP_DIRECT, 2, 0xda, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 798 |
|
|
{ "orab", OP_IND16, 3, 0xfa, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
|
| 799 |
|
|
{ "orab", OP_IX, 2, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6811 },
|
| 800 |
|
|
{ "orab", OP_IY | OP_PAGE2, 3, 0xea, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 801 |
|
|
{ "orab", OP_IDX, 2, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 802 |
|
|
{ "orab", OP_IDX_1, 3, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 803 |
|
|
{ "orab", OP_IDX_2, 4, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6812 },
|
| 804 |
|
|
{ "orab", OP_D_IDX, 2, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 805 |
|
|
{ "orab", OP_D_IDX_2, 4, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 },
|
| 806 |
|
|
|
| 807 |
|
|
{ "orcc", OP_IMM8, 2, 0x14, 1, 1, CHG_ALL, cpu6812 },
|
| 808 |
|
|
|
| 809 |
|
|
{ "psha", OP_NONE, 1, 0x36, 2, 2, CHG_NONE, cpu6811|cpu6812 },
|
| 810 |
|
|
{ "pshb", OP_NONE, 1, 0x37, 2, 2, CHG_NONE, cpu6811|cpu6812 },
|
| 811 |
|
|
{ "pshc", OP_NONE, 1, 0x39, 2, 2, CHG_NONE, cpu6812 },
|
| 812 |
|
|
{ "pshd", OP_NONE, 1, 0x3b, 2, 2, CHG_NONE, cpu6812 },
|
| 813 |
|
|
{ "pshx", OP_NONE, 1, 0x3c, 4, 4, CHG_NONE, cpu6811 },
|
| 814 |
|
|
{ "pshx", OP_NONE, 1, 0x34, 2, 2, CHG_NONE, cpu6812 },
|
| 815 |
|
|
{ "pshy", OP_NONE | OP_PAGE2,2, 0x3c, 5, 5, CHG_NONE, cpu6811 },
|
| 816 |
|
|
{ "pshy", OP_NONE, 1, 0x35, 2, 2, CHG_NONE, cpu6812 },
|
| 817 |
|
|
|
| 818 |
|
|
{ "pula", OP_NONE, 1, 0x32, 3, 3, CHG_NONE, cpu6811|cpu6812 },
|
| 819 |
|
|
{ "pulb", OP_NONE, 1, 0x33, 3, 3, CHG_NONE, cpu6811|cpu6812 },
|
| 820 |
|
|
{ "pulc", OP_NONE, 1, 0x38, 3, 3, CHG_NONE, cpu6812 },
|
| 821 |
|
|
{ "puld", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6812 },
|
| 822 |
|
|
{ "pulx", OP_NONE, 1, 0x38, 5, 5, CHG_NONE, cpu6811 },
|
| 823 |
|
|
{ "pulx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6812 },
|
| 824 |
|
|
{ "puly", OP_NONE | OP_PAGE2,2, 0x38, 6, 6, CHG_NONE, cpu6811 },
|
| 825 |
|
|
{ "puly", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6812 },
|
| 826 |
|
|
|
| 827 |
|
|
{ "rev", OP_NONE | OP_PAGE2, 2, 0x3a, _M, _M, CHG_HNZVC, cpu6812 },
|
| 828 |
|
|
{ "revw", OP_NONE | OP_PAGE2, 2, 0x3b, _M, _M, CHG_HNZVC, cpu6812 },
|
| 829 |
|
|
|
| 830 |
|
|
{ "rol", OP_IND16, 3, 0x79, 6, 6, CHG_NZVC, cpu6811 },
|
| 831 |
|
|
{ "rol", OP_IX, 2, 0x69, 6, 6, CHG_NZVC, cpu6811 },
|
| 832 |
|
|
{ "rol", OP_IY | OP_PAGE2, 3, 0x69, 7, 7, CHG_NZVC, cpu6811 },
|
| 833 |
|
|
{ "rol", OP_IND16, 3, 0x75, 4, 4, CHG_NZVC, cpu6812 },
|
| 834 |
|
|
{ "rol", OP_IDX, 2, 0x65, 3, 3, CHG_NZVC, cpu6812 },
|
| 835 |
|
|
{ "rol", OP_IDX_1, 3, 0x65, 4, 4, CHG_NZVC, cpu6812 },
|
| 836 |
|
|
{ "rol", OP_IDX_2, 4, 0x65, 5, 5, CHG_NZVC, cpu6812 },
|
| 837 |
|
|
{ "rol", OP_D_IDX, 2, 0x65, 6, 6, CHG_NZVC, cpu6812 },
|
| 838 |
|
|
{ "rol", OP_D_IDX_2, 4, 0x65, 6, 6, CHG_NZVC, cpu6812 },
|
| 839 |
|
|
|
| 840 |
|
|
{ "rola", OP_NONE, 1, 0x49, 2, 2, CHG_NZVC, cpu6811 },
|
| 841 |
|
|
{ "rola", OP_NONE, 1, 0x45, 1, 1, CHG_NZVC, cpu6812 },
|
| 842 |
|
|
{ "rolb", OP_NONE, 1, 0x59, 2, 2, CHG_NZVC, cpu6811 },
|
| 843 |
|
|
{ "rolb", OP_NONE, 1, 0x55, 1, 1, CHG_NZVC, cpu6812 },
|
| 844 |
|
|
|
| 845 |
|
|
{ "ror", OP_IND16, 3, 0x76, 4, 4, CHG_NZVC, cpu6811|cpu6812 },
|
| 846 |
|
|
{ "ror", OP_IX, 2, 0x66, 6, 6, CHG_NZVC, cpu6811 },
|
| 847 |
|
|
{ "ror", OP_IY | OP_PAGE2, 3, 0x66, 7, 7, CHG_NZVC, cpu6811 },
|
| 848 |
|
|
{ "ror", OP_IDX, 2, 0x66, 3, 3, CHG_NZVC, cpu6812 },
|
| 849 |
|
|
{ "ror", OP_IDX_1, 3, 0x66, 4, 4, CHG_NZVC, cpu6812 },
|
| 850 |
|
|
{ "ror", OP_IDX_2, 4, 0x66, 5, 5, CHG_NZVC, cpu6812 },
|
| 851 |
|
|
{ "ror", OP_D_IDX, 2, 0x66, 6, 6, CHG_NZVC, cpu6812 },
|
| 852 |
|
|
{ "ror", OP_D_IDX_2, 4, 0x66, 6, 6, CHG_NZVC, cpu6812 },
|
| 853 |
|
|
|
| 854 |
|
|
{ "rora", OP_NONE, 1, 0x46, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
|
| 855 |
|
|
{ "rorb", OP_NONE, 1, 0x56, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
|
| 856 |
|
|
|
| 857 |
|
|
{ "rtc", OP_NONE, 1, 0x0a, 6, 6, CHG_NONE, cpu6812 },
|
| 858 |
|
|
{ "rti", OP_NONE, 1, 0x3b, 12, 12, CHG_ALL, cpu6811},
|
| 859 |
|
|
{ "rti", OP_NONE, 1, 0x0b, 8, 10, CHG_ALL, cpu6812},
|
| 860 |
|
|
{ "rts", OP_NONE, 1, 0x39, 5, 5, CHG_NONE, cpu6811 },
|
| 861 |
|
|
{ "rts", OP_NONE, 1, 0x3d, 5, 5, CHG_NONE, cpu6812 },
|
| 862 |
|
|
|
| 863 |
|
|
{ "sba", OP_NONE, 1, 0x10, 2, 2, CHG_NZVC, cpu6811 },
|
| 864 |
|
|
{ "sba", OP_NONE | OP_PAGE2, 2, 0x16, 2, 2, CHG_NZVC, cpu6812 },
|
| 865 |
|
|
|
| 866 |
|
|
{ "sbca", OP_IMM8, 2, 0x82, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
|
| 867 |
|
|
{ "sbca", OP_DIRECT, 2, 0x92, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
|
| 868 |
|
|
{ "sbca", OP_IND16, 3, 0xb2, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
|
| 869 |
|
|
{ "sbca", OP_IX, 2, 0xa2, 4, 4, CHG_NZVC, cpu6811 },
|
| 870 |
|
|
{ "sbca", OP_IY | OP_PAGE2, 3, 0xa2, 5, 5, CHG_NZVC, cpu6811 },
|
| 871 |
|
|
{ "sbca", OP_IDX, 2, 0xa2, 3, 3, CHG_NZVC, cpu6812 },
|
| 872 |
|
|
{ "sbca", OP_IDX_1, 3, 0xa2, 3, 3, CHG_NZVC, cpu6812 },
|
| 873 |
|
|
{ "sbca", OP_IDX_2, 4, 0xa2, 4, 4, CHG_NZVC, cpu6812 },
|
| 874 |
|
|
{ "sbca", OP_D_IDX, 2, 0xa2, 6, 6, CHG_NZVC, cpu6812 },
|
| 875 |
|
|
{ "sbca", OP_D_IDX_2, 4, 0xa2, 6, 6, CHG_NZVC, cpu6812 },
|
| 876 |
|
|
|
| 877 |
|
|
{ "sbcb", OP_IMM8, 2, 0xc2, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
|
| 878 |
|
|
{ "sbcb", OP_DIRECT, 2, 0xd2, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
|
| 879 |
|
|
{ "sbcb", OP_IND16, 3, 0xf2, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
|
| 880 |
|
|
{ "sbcb", OP_IX, 2, 0xe2, 4, 4, CHG_NZVC, cpu6811 },
|
| 881 |
|
|
{ "sbcb", OP_IY | OP_PAGE2, 3, 0xe2, 5, 5, CHG_NZVC, cpu6811 },
|
| 882 |
|
|
{ "sbcb", OP_IDX, 2, 0xe2, 3, 3, CHG_NZVC, cpu6812 },
|
| 883 |
|
|
{ "sbcb", OP_IDX_1, 3, 0xe2, 3, 3, CHG_NZVC, cpu6812 },
|
| 884 |
|
|
{ "sbcb", OP_IDX_2, 4, 0xe2, 4, 4, CHG_NZVC, cpu6812 },
|
| 885 |
|
|
{ "sbcb", OP_D_IDX, 2, 0xe2, 6, 6, CHG_NZVC, cpu6812 },
|
| 886 |
|
|
{ "sbcb", OP_D_IDX_2, 4, 0xe2, 6, 6, CHG_NZVC, cpu6812 },
|
| 887 |
|
|
|
| 888 |
|
|
{ "sec", OP_NONE, 1, 0x0d, 2, 2, SET_C, cpu6811 },
|
| 889 |
|
|
{ "sei", OP_NONE, 1, 0x0f, 2, 2, SET_I, cpu6811 },
|
| 890 |
|
|
{ "sev", OP_NONE, 1, 0x0b, 2, 2, SET_V, cpu6811 },
|
| 891 |
|
|
|
| 892 |
|
|
{ "sex", M6812_OP_SEX_MARKER
|
| 893 |
|
|
| OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 },
|
| 894 |
|
|
|
| 895 |
|
|
{ "staa", OP_IND16, 3, 0xb7, 4, 4, CLR_V_CHG_NZ, cpu6811 },
|
| 896 |
|
|
{ "staa", OP_DIRECT, 2, 0x97, 3, 3, CLR_V_CHG_NZ, cpu6811 },
|
| 897 |
|
|
{ "staa", OP_IX, 2, 0xa7, 4, 4, CLR_V_CHG_NZ, cpu6811 },
|
| 898 |
|
|
{ "staa", OP_IY | OP_PAGE2, 3, 0xa7, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 899 |
|
|
{ "staa", OP_DIRECT, 2, 0x5a, 2, 2, CLR_V_CHG_NZ, cpu6812 },
|
| 900 |
|
|
{ "staa", OP_IND16, 3, 0x7a, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 901 |
|
|
{ "staa", OP_IDX, 2, 0x6a, 2, 2, CLR_V_CHG_NZ, cpu6812 },
|
| 902 |
|
|
{ "staa", OP_IDX_1, 3, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 903 |
|
|
{ "staa", OP_IDX_2, 4, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 904 |
|
|
{ "staa", OP_D_IDX, 2, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 },
|
| 905 |
|
|
{ "staa", OP_D_IDX_2, 4, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 },
|
| 906 |
|
|
|
| 907 |
|
|
{ "stab", OP_IND16, 3, 0xf7, 4, 4, CLR_V_CHG_NZ, cpu6811 },
|
| 908 |
|
|
{ "stab", OP_DIRECT, 2, 0xd7, 3, 3, CLR_V_CHG_NZ, cpu6811 },
|
| 909 |
|
|
{ "stab", OP_IX, 2, 0xe7, 4, 4, CLR_V_CHG_NZ, cpu6811 },
|
| 910 |
|
|
{ "stab", OP_IY | OP_PAGE2, 3, 0xe7, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 911 |
|
|
{ "stab", OP_DIRECT, 2, 0x5b, 2, 2, CLR_V_CHG_NZ, cpu6812 },
|
| 912 |
|
|
{ "stab", OP_IND16, 3, 0x7b, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 913 |
|
|
{ "stab", OP_IDX, 2, 0x6b, 2, 2, CLR_V_CHG_NZ, cpu6812 },
|
| 914 |
|
|
{ "stab", OP_IDX_1, 3, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 915 |
|
|
{ "stab", OP_IDX_2, 4, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 916 |
|
|
{ "stab", OP_D_IDX, 2, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 },
|
| 917 |
|
|
{ "stab", OP_D_IDX_2, 4, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 },
|
| 918 |
|
|
|
| 919 |
|
|
{ "std", OP_IND16, 3, 0xfd, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 920 |
|
|
{ "std", OP_DIRECT, 2, 0xdd, 4, 4, CLR_V_CHG_NZ, cpu6811 },
|
| 921 |
|
|
{ "std", OP_IX, 2, 0xed, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 922 |
|
|
{ "std", OP_IY | OP_PAGE2, 3, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6811 },
|
| 923 |
|
|
{ "std", OP_DIRECT, 2, 0x5c, 2, 2, CLR_V_CHG_NZ, cpu6812 },
|
| 924 |
|
|
{ "std", OP_IND16, 3, 0x7c, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 925 |
|
|
{ "std", OP_IDX, 2, 0x6c, 2, 2, CLR_V_CHG_NZ, cpu6812 },
|
| 926 |
|
|
{ "std", OP_IDX_1, 3, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 927 |
|
|
{ "std", OP_IDX_2, 4, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 928 |
|
|
{ "std", OP_D_IDX, 2, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 },
|
| 929 |
|
|
{ "std", OP_D_IDX_2, 4, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 },
|
| 930 |
|
|
|
| 931 |
|
|
{ "stop", OP_NONE, 1, 0xcf, 2, 2, CHG_NONE, cpu6811 },
|
| 932 |
|
|
{ "stop", OP_NONE | OP_PAGE2,2, 0x3e, 2, 9, CHG_NONE, cpu6812 },
|
| 933 |
|
|
|
| 934 |
|
|
{ "sts", OP_IND16, 3, 0xbf, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 935 |
|
|
{ "sts", OP_DIRECT, 2, 0x9f, 4, 4, CLR_V_CHG_NZ, cpu6811 },
|
| 936 |
|
|
{ "sts", OP_IX, 2, 0xaf, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 937 |
|
|
{ "sts", OP_IY | OP_PAGE2, 3, 0xaf, 6, 6, CLR_V_CHG_NZ, cpu6811 },
|
| 938 |
|
|
{ "sts", OP_DIRECT, 2, 0x5f, 2, 2, CLR_V_CHG_NZ, cpu6812 },
|
| 939 |
|
|
{ "sts", OP_IND16, 3, 0x7f, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 940 |
|
|
{ "sts", OP_IDX, 2, 0x6f, 2, 2, CLR_V_CHG_NZ, cpu6812 },
|
| 941 |
|
|
{ "sts", OP_IDX_1, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 942 |
|
|
{ "sts", OP_IDX_2, 4, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 943 |
|
|
{ "sts", OP_D_IDX, 2, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 },
|
| 944 |
|
|
{ "sts", OP_D_IDX_2, 4, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 },
|
| 945 |
|
|
|
| 946 |
|
|
{ "stx", OP_IND16, 3, 0xff, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 947 |
|
|
{ "stx", OP_DIRECT, 2, 0xdf, 4, 4, CLR_V_CHG_NZ, cpu6811 },
|
| 948 |
|
|
{ "stx", OP_IX, 2, 0xef, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 949 |
|
|
{ "stx", OP_IY | OP_PAGE4, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 },
|
| 950 |
|
|
{ "stx", OP_DIRECT, 2, 0x5e, 2, 2, CLR_V_CHG_NZ, cpu6812 },
|
| 951 |
|
|
{ "stx", OP_IND16, 3, 0x7e, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 952 |
|
|
{ "stx", OP_IDX, 2, 0x6e, 2, 2, CLR_V_CHG_NZ, cpu6812 },
|
| 953 |
|
|
{ "stx", OP_IDX_1, 3, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 954 |
|
|
{ "stx", OP_IDX_2, 4, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 955 |
|
|
{ "stx", OP_D_IDX, 2, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 },
|
| 956 |
|
|
{ "stx", OP_D_IDX_2, 4, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 },
|
| 957 |
|
|
|
| 958 |
|
|
{ "sty", OP_IND16 | OP_PAGE2, 4, 0xff, 6, 6, CLR_V_CHG_NZ, cpu6811 },
|
| 959 |
|
|
{ "sty", OP_DIRECT | OP_PAGE2, 3, 0xdf, 5, 5, CLR_V_CHG_NZ, cpu6811 },
|
| 960 |
|
|
{ "sty", OP_IY | OP_PAGE2, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 },
|
| 961 |
|
|
{ "sty", OP_IX | OP_PAGE3, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 },
|
| 962 |
|
|
{ "sty", OP_DIRECT, 2, 0x5d, 2, 2, CLR_V_CHG_NZ, cpu6812 },
|
| 963 |
|
|
{ "sty", OP_IND16, 3, 0x7d, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 964 |
|
|
{ "sty", OP_IDX, 2, 0x6d, 2, 2, CLR_V_CHG_NZ, cpu6812 },
|
| 965 |
|
|
{ "sty", OP_IDX_1, 3, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 966 |
|
|
{ "sty", OP_IDX_2, 4, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 },
|
| 967 |
|
|
{ "sty", OP_D_IDX, 2, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 },
|
| 968 |
|
|
{ "sty", OP_D_IDX_2, 4, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 },
|
| 969 |
|
|
|
| 970 |
|
|
{ "suba", OP_IMM8, 2, 0x80, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
|
| 971 |
|
|
{ "suba", OP_DIRECT, 2, 0x90, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
|
| 972 |
|
|
{ "suba", OP_IND16, 3, 0xb0, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
|
| 973 |
|
|
{ "suba", OP_IX, 2, 0xa0, 4, 4, CHG_NZVC, cpu6811 },
|
| 974 |
|
|
{ "suba", OP_IY | OP_PAGE2, 3, 0xa0, 5, 5, CHG_NZVC, cpu6811 },
|
| 975 |
|
|
{ "suba", OP_IDX, 2, 0xa0, 3, 3, CHG_NZVC, cpu6812 },
|
| 976 |
|
|
{ "suba", OP_IDX_1, 3, 0xa0, 3, 3, CHG_NZVC, cpu6812 },
|
| 977 |
|
|
{ "suba", OP_IDX_2, 4, 0xa0, 4, 4, CHG_NZVC, cpu6812 },
|
| 978 |
|
|
{ "suba", OP_D_IDX, 2, 0xa0, 6, 6, CHG_NZVC, cpu6812 },
|
| 979 |
|
|
{ "suba", OP_D_IDX_2, 4, 0xa0, 6, 6, CHG_NZVC, cpu6812 },
|
| 980 |
|
|
|
| 981 |
|
|
{ "subb", OP_IMM8, 2, 0xc0, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
|
| 982 |
|
|
{ "subb", OP_DIRECT, 2, 0xd0, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
|
| 983 |
|
|
{ "subb", OP_IND16, 3, 0xf0, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
|
| 984 |
|
|
{ "subb", OP_IX, 2, 0xe0, 4, 4, CHG_NZVC, cpu6811 },
|
| 985 |
|
|
{ "subb", OP_IY | OP_PAGE2, 3, 0xe0, 5, 5, CHG_NZVC, cpu6811 },
|
| 986 |
|
|
{ "subb", OP_IDX, 2, 0xe0, 3, 3, CHG_NZVC, cpu6812 },
|
| 987 |
|
|
{ "subb", OP_IDX_1, 3, 0xe0, 3, 3, CHG_NZVC, cpu6812 },
|
| 988 |
|
|
{ "subb", OP_IDX_2, 4, 0xe0, 4, 4, CHG_NZVC, cpu6812 },
|
| 989 |
|
|
{ "subb", OP_D_IDX, 2, 0xe0, 6, 6, CHG_NZVC, cpu6812 },
|
| 990 |
|
|
{ "subb", OP_D_IDX_2, 4, 0xe0, 6, 6, CHG_NZVC, cpu6812 },
|
| 991 |
|
|
|
| 992 |
|
|
{ "subd", OP_IMM16, 3, 0x83, 2, 2, CHG_NZVC, cpu6811|cpu6812 },
|
| 993 |
|
|
{ "subd", OP_DIRECT, 2, 0x93, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
|
| 994 |
|
|
{ "subd", OP_IND16, 3, 0xb3, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
|
| 995 |
|
|
{ "subd", OP_IX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6811 },
|
| 996 |
|
|
{ "subd", OP_IY | OP_PAGE2, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 },
|
| 997 |
|
|
{ "subd", OP_IDX, 2, 0xa3, 3, 3, CHG_NZVC, cpu6812 },
|
| 998 |
|
|
{ "subd", OP_IDX_1, 3, 0xa3, 3, 3, CHG_NZVC, cpu6812 },
|
| 999 |
|
|
{ "subd", OP_IDX_2, 4, 0xa3, 4, 4, CHG_NZVC, cpu6812 },
|
| 1000 |
|
|
{ "subd", OP_D_IDX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6812 },
|
| 1001 |
|
|
{ "subd", OP_D_IDX_2, 4, 0xa3, 6, 6, CHG_NZVC, cpu6812 },
|
| 1002 |
|
|
|
| 1003 |
|
|
{ "swi", OP_NONE, 1, 0x3f, 9, 9, CHG_NONE, cpu6811|cpu6812 },
|
| 1004 |
|
|
|
| 1005 |
|
|
{ "tab", OP_NONE, 1, 0x16, 2, 2, CLR_V_CHG_NZ, cpu6811 },
|
| 1006 |
|
|
{ "tab", OP_NONE | OP_PAGE2,2, 0x0e, 2, 2, CLR_V_CHG_NZ, cpu6812 },
|
| 1007 |
|
|
|
| 1008 |
|
|
{ "tap", OP_NONE, 1, 0x06, 2, 2, CHG_ALL, cpu6811 },
|
| 1009 |
|
|
|
| 1010 |
|
|
{ "tba", OP_NONE, 1, 0x17, 2, 2, CLR_V_CHG_NZ, cpu6811 },
|
| 1011 |
|
|
{ "tba", OP_NONE | OP_PAGE2,2, 0x0f, 2, 2, CLR_V_CHG_NZ, cpu6812 },
|
| 1012 |
|
|
|
| 1013 |
|
|
{ "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 },
|
| 1014 |
|
|
|
| 1015 |
|
|
{ "tpa", OP_NONE, 1, 0x07, 2, 2, CHG_NONE, cpu6811 },
|
| 1016 |
|
|
|
| 1017 |
|
|
{ "tbeq", OP_TBEQ_MARKER
|
| 1018 |
|
|
| OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 },
|
| 1019 |
|
|
|
| 1020 |
|
|
{ "tbl", OP_IDX | OP_PAGE2, 3, 0x3d, 8, 8, CHG_NZC, cpu6812 },
|
| 1021 |
|
|
|
| 1022 |
|
|
{ "tbne", OP_TBNE_MARKER
|
| 1023 |
|
|
| OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 },
|
| 1024 |
|
|
|
| 1025 |
|
|
{ "tfr", OP_TFR_MARKER
|
| 1026 |
|
|
| OP_REG_1 | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 },
|
| 1027 |
|
|
|
| 1028 |
|
|
{ "trap", OP_IMM8 | OP_TRAP_ID, 2, 0x18, 11, 11, SET_I, cpu6812 },
|
| 1029 |
|
|
|
| 1030 |
|
|
{ "tst", OP_IND16, 3, 0x7d, 6, 6, CLR_VC_CHG_NZ, cpu6811 },
|
| 1031 |
|
|
{ "tst", OP_IX, 2, 0x6d, 6, 6, CLR_VC_CHG_NZ, cpu6811 },
|
| 1032 |
|
|
{ "tst", OP_IY | OP_PAGE2, 3, 0x6d, 7, 7, CLR_VC_CHG_NZ, cpu6811 },
|
| 1033 |
|
|
{ "tst", OP_IND16, 3, 0xf7, 3, 3, CLR_VC_CHG_NZ, cpu6812 },
|
| 1034 |
|
|
{ "tst", OP_IDX, 2, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 },
|
| 1035 |
|
|
{ "tst", OP_IDX_1, 3, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 },
|
| 1036 |
|
|
{ "tst", OP_IDX_2, 4, 0xe7, 4, 4, CLR_VC_CHG_NZ, cpu6812 },
|
| 1037 |
|
|
{ "tst", OP_D_IDX, 2, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 },
|
| 1038 |
|
|
{ "tst", OP_D_IDX_2, 4, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 },
|
| 1039 |
|
|
|
| 1040 |
|
|
{ "tsta", OP_NONE, 1, 0x4d, 2, 2, CLR_VC_CHG_NZ, cpu6811 },
|
| 1041 |
|
|
{ "tsta", OP_NONE, 1, 0x97, 1, 1, CLR_VC_CHG_NZ, cpu6812 },
|
| 1042 |
|
|
{ "tstb", OP_NONE, 1, 0x5d, 2, 2, CLR_VC_CHG_NZ, cpu6811 },
|
| 1043 |
|
|
{ "tstb", OP_NONE, 1, 0xd7, 1, 1, CLR_VC_CHG_NZ, cpu6812 },
|
| 1044 |
|
|
|
| 1045 |
|
|
{ "tsx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6811 },
|
| 1046 |
|
|
{ "tsy", OP_NONE | OP_PAGE2,2, 0x30, 4, 4, CHG_NONE, cpu6811 },
|
| 1047 |
|
|
{ "txs", OP_NONE, 1, 0x35, 3, 3, CHG_NONE, cpu6811 },
|
| 1048 |
|
|
{ "tys", OP_NONE | OP_PAGE2,2, 0x35, 4, 4, CHG_NONE, cpu6811 },
|
| 1049 |
|
|
|
| 1050 |
|
|
{ "wai", OP_NONE, 1, 0x3e, 5, _M, CHG_NONE, cpu6811|cpu6812 },
|
| 1051 |
|
|
|
| 1052 |
|
|
{ "wav", OP_NONE | OP_PAGE2, 2, 0x3c, 8, _M, SET_Z_CHG_HNVC, cpu6812 },
|
| 1053 |
|
|
|
| 1054 |
|
|
{ "xgdx", OP_NONE, 1, 0x8f, 3, 3, CHG_NONE, cpu6811 },
|
| 1055 |
|
|
{ "xgdy", OP_NONE | OP_PAGE2,2, 0x8f, 4, 4, CHG_NONE, cpu6811 }
|
| 1056 |
|
|
};
|
| 1057 |
|
|
|
| 1058 |
|
|
const int m68hc11_num_opcodes = TABLE_SIZE (m68hc11_opcodes);
|
| 1059 |
|
|
|
| 1060 |
|
|
/* The following alias table provides source compatibility to
|
| 1061 |
|
|
move from 68HC11 assembly to 68HC12. */
|
| 1062 |
|
|
const struct m68hc12_opcode_alias m68hc12_alias[] = {
|
| 1063 |
|
|
{ "abx", "leax b,x", 2, 0x1a, 0xe5 },
|
| 1064 |
|
|
{ "aby", "leay b,y", 2, 0x19, 0xed },
|
| 1065 |
|
|
{ "clc", "andcc #$fe", 2, 0x10, 0xfe },
|
| 1066 |
|
|
{ "cli", "andcc #$ef", 2, 0x10, 0xef },
|
| 1067 |
|
|
{ "clv", "andcc #$fd", 2, 0x10, 0xfd },
|
| 1068 |
|
|
{ "des", "leas -1,sp", 2, 0x1b, 0x9f },
|
| 1069 |
|
|
{ "ins", "leas 1,sp", 2, 0x1b, 0x81 },
|
| 1070 |
|
|
{ "sec", "orcc #$01", 2, 0x14, 0x01 },
|
| 1071 |
|
|
{ "sei", "orcc #$10", 2, 0x14, 0x10 },
|
| 1072 |
|
|
{ "sev", "orcc #$02", 2, 0x14, 0x02 },
|
| 1073 |
|
|
{ "tap", "tfr a,ccr", 2, 0xb7, 0x02 },
|
| 1074 |
|
|
{ "tpa", "tfr ccr,a", 2, 0xb7, 0x20 },
|
| 1075 |
|
|
{ "tsx", "tfr sp,x", 2, 0xb7, 0x75 },
|
| 1076 |
|
|
{ "tsy", "tfr sp,y", 2, 0xb7, 0x76 },
|
| 1077 |
|
|
{ "txs", "tfr x,sp", 2, 0xb7, 0x57 },
|
| 1078 |
|
|
{ "tys", "tfr y,sp", 2, 0xb7, 0x67 },
|
| 1079 |
|
|
{ "xgdx","exg d,x", 2, 0xb7, 0xc5 },
|
| 1080 |
|
|
{ "xgdy","exg d,y", 2, 0xb7, 0xc6 }
|
| 1081 |
|
|
};
|
| 1082 |
|
|
const int m68hc12_num_alias = TABLE_SIZE (m68hc12_alias);
|
