OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [opcodes/] [mips-dis.c] - Blame information for rev 53

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 18 khays 
/* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 
   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 
   2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009
4 
   Free Software Foundation, Inc.
5 
   Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6 
 
7 
   This file is part of the GNU opcodes library.
8 
 
9 
   This library is free software; you can redistribute it and/or modify
10 
   it under the terms of the GNU General Public License as published by
11 
   the Free Software Foundation; either version 3, or (at your option)
12 
   any later version.
13 
 
14 
   It is distributed in the hope that it will be useful, but WITHOUT
15 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17 
   License for more details.
18 
 
19 
   You should have received a copy of the GNU General Public License
20 
   along with this program; if not, write to the Free Software
21 
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 
   MA 02110-1301, USA.  */
23 
 
24 
#include "sysdep.h"
25 
#include "dis-asm.h"
26 
#include "libiberty.h"
27 
#include "opcode/mips.h"
28 
#include "opintl.h"
29 
 
30 
/* FIXME: These are needed to figure out if the code is mips16 or
31 
   not. The low bit of the address is often a good indicator.  No
32 
   symbol table is available when this code runs out in an embedded
33 
   system as when it is used for disassembler support in a monitor.  */
34 
 
35 
#if !defined(EMBEDDED_ENV)
36 
#define SYMTAB_AVAILABLE 1
37 
#include "elf-bfd.h"
38 
#include "elf/mips.h"
39 
#endif
40 
 
41 
/* Mips instructions are at maximum this many bytes long.  */
42 
#define INSNLEN 4
43 
 
44 
 
45 
/* FIXME: These should be shared with gdb somehow.  */
46 
 
47 
struct mips_cp0sel_name
48 
{
49 
  unsigned int cp0reg;
50 
  unsigned int sel;
51 
  const char * const name;
52 
};
53 
 
54 
/* The mips16 registers.  */
55 
static const unsigned int mips16_to_32_reg_map[] =
56 
{
57 
  16, 17, 2, 3, 4, 5, 6, 7
58 
};
59 
 
60 
#define mips16_reg_names(rn)    mips_gpr_names[mips16_to_32_reg_map[rn]]
61 
 
62 
 
63 
static const char * const mips_gpr_names_numeric[32] =
64 
{
65 
  "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
66 
  "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
67 
  "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
68 
  "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
69 
};
70 
 
71 
static const char * const mips_gpr_names_oldabi[32] =
72 
{
73 
  "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
74 
  "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",
75 
  "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
76 
  "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
77 
};
78 
 
79 
static const char * const mips_gpr_names_newabi[32] =
80 
{
81 
  "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
82 
  "a4",   "a5",   "a6",   "a7",   "t0",   "t1",   "t2",   "t3",
83 
  "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
84 
  "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
85 
};
86 
 
87 
static const char * const mips_fpr_names_numeric[32] =
88 
{
89 
  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
90 
  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 
  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 
  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
93 
};
94 
 
95 
static const char * const mips_fpr_names_32[32] =
96 
{
97 
  "fv0",  "fv0f", "fv1",  "fv1f", "ft0",  "ft0f", "ft1",  "ft1f",
98 
  "ft2",  "ft2f", "ft3",  "ft3f", "fa0",  "fa0f", "fa1",  "fa1f",
99 
  "ft4",  "ft4f", "ft5",  "ft5f", "fs0",  "fs0f", "fs1",  "fs1f",
100 
  "fs2",  "fs2f", "fs3",  "fs3f", "fs4",  "fs4f", "fs5",  "fs5f"
101 
};
102 
 
103 
static const char * const mips_fpr_names_n32[32] =
104 
{
105 
  "fv0",  "ft14", "fv1",  "ft15", "ft0",  "ft1",  "ft2",  "ft3",
106 
  "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
107 
  "fa4",  "fa5",  "fa6",  "fa7",  "fs0",  "ft8",  "fs1",  "ft9",
108 
  "fs2",  "ft10", "fs3",  "ft11", "fs4",  "ft12", "fs5",  "ft13"
109 
};
110 
 
111 
static const char * const mips_fpr_names_64[32] =
112 
{
113 
  "fv0",  "ft12", "fv1",  "ft13", "ft0",  "ft1",  "ft2",  "ft3",
114 
  "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
115 
  "fa4",  "fa5",  "fa6",  "fa7",  "ft8",  "ft9",  "ft10", "ft11",
116 
  "fs0",  "fs1",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7"
117 
};
118 
 
119 
static const char * const mips_cp0_names_numeric[32] =
120 
{
121 
  "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
122 
  "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
123 
  "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
124 
  "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
125 
};
126 
 
127 
static const char * const mips_cp0_names_r3000[32] =
128 
{
129 
  "c0_index",     "c0_random",    "c0_entrylo",   "$3",
130 
  "c0_context",   "$5",           "$6",           "$7",
131 
  "c0_badvaddr",  "$9",           "c0_entryhi",   "$11",
132 
  "c0_sr",        "c0_cause",     "c0_epc",       "c0_prid",
133 
  "$16",          "$17",          "$18",          "$19",
134 
  "$20",          "$21",          "$22",          "$23",
135 
  "$24",          "$25",          "$26",          "$27",
136 
  "$28",          "$29",          "$30",          "$31",
137 
};
138 
 
139 
static const char * const mips_cp0_names_r4000[32] =
140 
{
141 
  "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
142 
  "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
143 
  "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
144 
  "c0_sr",        "c0_cause",     "c0_epc",       "c0_prid",
145 
  "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
146 
  "c0_xcontext",  "$21",          "$22",          "$23",
147 
  "$24",          "$25",          "c0_ecc",       "c0_cacheerr",
148 
  "c0_taglo",     "c0_taghi",     "c0_errorepc",  "$31",
149 
};
150 
 
151 
static const char * const mips_cp0_names_mips3264[32] =
152 
{
153 
  "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
154 
  "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
155 
  "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
156 
  "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
157 
  "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
158 
  "c0_xcontext",  "$21",          "$22",          "c0_debug",
159 
  "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
160 
  "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
161 
};
162 
 
163 
static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
164 
{
165 
  { 16, 1, "c0_config1"         },
166 
  { 16, 2, "c0_config2"         },
167 
  { 16, 3, "c0_config3"         },
168 
  { 18, 1, "c0_watchlo,1"       },
169 
  { 18, 2, "c0_watchlo,2"       },
170 
  { 18, 3, "c0_watchlo,3"       },
171 
  { 18, 4, "c0_watchlo,4"       },
172 
  { 18, 5, "c0_watchlo,5"       },
173 
  { 18, 6, "c0_watchlo,6"       },
174 
  { 18, 7, "c0_watchlo,7"       },
175 
  { 19, 1, "c0_watchhi,1"       },
176 
  { 19, 2, "c0_watchhi,2"       },
177 
  { 19, 3, "c0_watchhi,3"       },
178 
  { 19, 4, "c0_watchhi,4"       },
179 
  { 19, 5, "c0_watchhi,5"       },
180 
  { 19, 6, "c0_watchhi,6"       },
181 
  { 19, 7, "c0_watchhi,7"       },
182 
  { 25, 1, "c0_perfcnt,1"       },
183 
  { 25, 2, "c0_perfcnt,2"       },
184 
  { 25, 3, "c0_perfcnt,3"       },
185 
  { 25, 4, "c0_perfcnt,4"       },
186 
  { 25, 5, "c0_perfcnt,5"       },
187 
  { 25, 6, "c0_perfcnt,6"       },
188 
  { 25, 7, "c0_perfcnt,7"       },
189 
  { 27, 1, "c0_cacheerr,1"      },
190 
  { 27, 2, "c0_cacheerr,2"      },
191 
  { 27, 3, "c0_cacheerr,3"      },
192 
  { 28, 1, "c0_datalo"          },
193 
  { 29, 1, "c0_datahi"          }
194 
};
195 
 
196 
static const char * const mips_cp0_names_mips3264r2[32] =
197 
{
198 
  "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
199 
  "c0_context",   "c0_pagemask",  "c0_wired",     "c0_hwrena",
200 
  "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
201 
  "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
202 
  "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
203 
  "c0_xcontext",  "$21",          "$22",          "c0_debug",
204 
  "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
205 
  "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
206 
};
207 
 
208 
static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
209 
{
210 
  {  4, 1, "c0_contextconfig"   },
211 
  {  0, 1, "c0_mvpcontrol"       },
212 
  {  0, 2, "c0_mvpconf0" },
213 
  {  0, 3, "c0_mvpconf1" },
214 
  {  1, 1, "c0_vpecontrol"      },
215 
  {  1, 2, "c0_vpeconf0"        },
216 
  {  1, 3, "c0_vpeconf1"        },
217 
  {  1, 4, "c0_yqmask"          },
218 
  {  1, 5, "c0_vpeschedule"     },
219 
  {  1, 6, "c0_vpeschefback"    },
220 
  {  2, 1, "c0_tcstatus"        },
221 
  {  2, 2, "c0_tcbind"          },
222 
  {  2, 3, "c0_tcrestart"       },
223 
  {  2, 4, "c0_tchalt"          },
224 
  {  2, 5, "c0_tccontext"       },
225 
  {  2, 6, "c0_tcschedule"      },
226 
  {  2, 7, "c0_tcschefback"     },
227 
  {  5, 1, "c0_pagegrain"       },
228 
  {  6, 1, "c0_srsconf0"        },
229 
  {  6, 2, "c0_srsconf1"        },
230 
  {  6, 3, "c0_srsconf2"        },
231 
  {  6, 4, "c0_srsconf3"        },
232 
  {  6, 5, "c0_srsconf4"        },
233 
  { 12, 1, "c0_intctl"          },
234 
  { 12, 2, "c0_srsctl"          },
235 
  { 12, 3, "c0_srsmap"          },
236 
  { 15, 1, "c0_ebase"           },
237 
  { 16, 1, "c0_config1"         },
238 
  { 16, 2, "c0_config2"         },
239 
  { 16, 3, "c0_config3"         },
240 
  { 18, 1, "c0_watchlo,1"       },
241 
  { 18, 2, "c0_watchlo,2"       },
242 
  { 18, 3, "c0_watchlo,3"       },
243 
  { 18, 4, "c0_watchlo,4"       },
244 
  { 18, 5, "c0_watchlo,5"       },
245 
  { 18, 6, "c0_watchlo,6"       },
246 
  { 18, 7, "c0_watchlo,7"       },
247 
  { 19, 1, "c0_watchhi,1"       },
248 
  { 19, 2, "c0_watchhi,2"       },
249 
  { 19, 3, "c0_watchhi,3"       },
250 
  { 19, 4, "c0_watchhi,4"       },
251 
  { 19, 5, "c0_watchhi,5"       },
252 
  { 19, 6, "c0_watchhi,6"       },
253 
  { 19, 7, "c0_watchhi,7"       },
254 
  { 23, 1, "c0_tracecontrol"    },
255 
  { 23, 2, "c0_tracecontrol2"   },
256 
  { 23, 3, "c0_usertracedata"   },
257 
  { 23, 4, "c0_tracebpc"        },
258 
  { 25, 1, "c0_perfcnt,1"       },
259 
  { 25, 2, "c0_perfcnt,2"       },
260 
  { 25, 3, "c0_perfcnt,3"       },
261 
  { 25, 4, "c0_perfcnt,4"       },
262 
  { 25, 5, "c0_perfcnt,5"       },
263 
  { 25, 6, "c0_perfcnt,6"       },
264 
  { 25, 7, "c0_perfcnt,7"       },
265 
  { 27, 1, "c0_cacheerr,1"      },
266 
  { 27, 2, "c0_cacheerr,2"      },
267 
  { 27, 3, "c0_cacheerr,3"      },
268 
  { 28, 1, "c0_datalo"          },
269 
  { 28, 2, "c0_taglo1"          },
270 
  { 28, 3, "c0_datalo1"         },
271 
  { 28, 4, "c0_taglo2"          },
272 
  { 28, 5, "c0_datalo2"         },
273 
  { 28, 6, "c0_taglo3"          },
274 
  { 28, 7, "c0_datalo3"         },
275 
  { 29, 1, "c0_datahi"          },
276 
  { 29, 2, "c0_taghi1"          },
277 
  { 29, 3, "c0_datahi1"         },
278 
  { 29, 4, "c0_taghi2"          },
279 
  { 29, 5, "c0_datahi2"         },
280 
  { 29, 6, "c0_taghi3"          },
281 
  { 29, 7, "c0_datahi3"         },
282 
};
283 
 
284 
/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods.  */
285 
static const char * const mips_cp0_names_sb1[32] =
286 
{
287 
  "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
288 
  "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
289 
  "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
290 
  "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
291 
  "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
292 
  "c0_xcontext",  "$21",          "$22",          "c0_debug",
293 
  "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr_i",
294 
  "c0_taglo_i",   "c0_taghi_i",   "c0_errorepc",  "c0_desave",
295 
};
296 
 
297 
static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
298 
{
299 
  { 16, 1, "c0_config1"         },
300 
  { 18, 1, "c0_watchlo,1"       },
301 
  { 19, 1, "c0_watchhi,1"       },
302 
  { 22, 0, "c0_perftrace"        },
303 
  { 23, 3, "c0_edebug"          },
304 
  { 25, 1, "c0_perfcnt,1"       },
305 
  { 25, 2, "c0_perfcnt,2"       },
306 
  { 25, 3, "c0_perfcnt,3"       },
307 
  { 25, 4, "c0_perfcnt,4"       },
308 
  { 25, 5, "c0_perfcnt,5"       },
309 
  { 25, 6, "c0_perfcnt,6"       },
310 
  { 25, 7, "c0_perfcnt,7"       },
311 
  { 26, 1, "c0_buserr_pa"       },
312 
  { 27, 1, "c0_cacheerr_d"      },
313 
  { 27, 3, "c0_cacheerr_d_pa"   },
314 
  { 28, 1, "c0_datalo_i"        },
315 
  { 28, 2, "c0_taglo_d"         },
316 
  { 28, 3, "c0_datalo_d"        },
317 
  { 29, 1, "c0_datahi_i"        },
318 
  { 29, 2, "c0_taghi_d"         },
319 
  { 29, 3, "c0_datahi_d"        },
320 
};
321 
 
322 
/* Xlr cop0 register names.  */
323 
static const char * const mips_cp0_names_xlr[32] = {
324 
  "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
325 
  "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
326 
  "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
327 
  "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
328 
  "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
329 
  "c0_xcontext",  "$21",          "$22",          "c0_debug",
330 
  "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr_i",
331 
  "c0_taglo_i",   "c0_taghi_i",   "c0_errorepc",  "c0_desave",
332 
};
333 
 
334 
/* XLR's CP0 Select Registers.  */
335 
 
336 
static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = {
337 
  {  9, 6, "c0_extintreq"       },
338 
  {  9, 7, "c0_extintmask"      },
339 
  { 15, 1, "c0_ebase"           },
340 
  { 16, 1, "c0_config1"         },
341 
  { 16, 2, "c0_config2"         },
342 
  { 16, 3, "c0_config3"         },
343 
  { 16, 7, "c0_procid2"         },
344 
  { 18, 1, "c0_watchlo,1"       },
345 
  { 18, 2, "c0_watchlo,2"       },
346 
  { 18, 3, "c0_watchlo,3"       },
347 
  { 18, 4, "c0_watchlo,4"       },
348 
  { 18, 5, "c0_watchlo,5"       },
349 
  { 18, 6, "c0_watchlo,6"       },
350 
  { 18, 7, "c0_watchlo,7"       },
351 
  { 19, 1, "c0_watchhi,1"       },
352 
  { 19, 2, "c0_watchhi,2"       },
353 
  { 19, 3, "c0_watchhi,3"       },
354 
  { 19, 4, "c0_watchhi,4"       },
355 
  { 19, 5, "c0_watchhi,5"       },
356 
  { 19, 6, "c0_watchhi,6"       },
357 
  { 19, 7, "c0_watchhi,7"       },
358 
  { 25, 1, "c0_perfcnt,1"       },
359 
  { 25, 2, "c0_perfcnt,2"       },
360 
  { 25, 3, "c0_perfcnt,3"       },
361 
  { 25, 4, "c0_perfcnt,4"       },
362 
  { 25, 5, "c0_perfcnt,5"       },
363 
  { 25, 6, "c0_perfcnt,6"       },
364 
  { 25, 7, "c0_perfcnt,7"       },
365 
  { 27, 1, "c0_cacheerr,1"      },
366 
  { 27, 2, "c0_cacheerr,2"      },
367 
  { 27, 3, "c0_cacheerr,3"      },
368 
  { 28, 1, "c0_datalo"          },
369 
  { 29, 1, "c0_datahi"          }
370 
};
371 
 
372 
static const char * const mips_hwr_names_numeric[32] =
373 
{
374 
  "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
375 
  "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
376 
  "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
377 
  "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
378 
};
379 
 
380 
static const char * const mips_hwr_names_mips3264r2[32] =
381 
{
382 
  "hwr_cpunum",   "hwr_synci_step", "hwr_cc",     "hwr_ccres",
383 
  "$4",          "$5",            "$6",           "$7",
384 
  "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
385 
  "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
386 
  "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
387 
};
388 
 
389 
struct mips_abi_choice
390 
{
391 
  const char * name;
392 
  const char * const *gpr_names;
393 
  const char * const *fpr_names;
394 
};
395 
 
396 
struct mips_abi_choice mips_abi_choices[] =
397 
{
398 
  { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
399 
  { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
400 
  { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
401 
  { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
402 
};
403 
 
404 
struct mips_arch_choice
405 
{
406 
  const char *name;
407 
  int bfd_mach_valid;
408 
  unsigned long bfd_mach;
409 
  int processor;
410 
  int isa;
411 
  const char * const *cp0_names;
412 
  const struct mips_cp0sel_name *cp0sel_names;
413 
  unsigned int cp0sel_names_len;
414 
  const char * const *hwr_names;
415 
};
416 
 
417 
const struct mips_arch_choice mips_arch_choices[] =
418 
{
419 
  { "numeric",  0, 0, 0, 0,
420 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
421 
 
422 
  { "r3000",    1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
423 
    mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
424 
  { "r3900",    1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
425 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
426 
  { "r4000",    1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
427 
    mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
428 
  { "r4010",    1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
429 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
430 
  { "vr4100",   1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
431 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
432 
  { "vr4111",   1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
433 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
434 
  { "vr4120",   1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
435 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
436 
  { "r4300",    1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
437 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
438 
  { "r4400",    1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
439 
    mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
440 
  { "r4600",    1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
441 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
442 
  { "r4650",    1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
443 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
444 
  { "r5000",    1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
445 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
446 
  { "vr5400",   1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
447 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
448 
  { "vr5500",   1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
449 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
450 
  { "r6000",    1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
451 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
452 
  { "rm7000",   1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
453 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
454 
  { "rm9000",   1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
455 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
456 
  { "r8000",    1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
457 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
458 
  { "r10000",   1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
459 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
460 
  { "r12000",   1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
461 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
462 
  { "r14000",   1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4,
463 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
464 
  { "r16000",   1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4,
465 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
466 
  { "mips5",    1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
467 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
468 
 
469 
  /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
470 
     Note that MIPS-3D and MDMX are not applicable to MIPS32.  (See
471 
     _MIPS32 Architecture For Programmers Volume I: Introduction to the
472 
     MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
473 
     page 1.  */
474 
  { "mips32",   1, bfd_mach_mipsisa32, CPU_MIPS32,
475 
    ISA_MIPS32 | INSN_SMARTMIPS,
476 
    mips_cp0_names_mips3264,
477 
    mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
478 
    mips_hwr_names_numeric },
479 
 
480 
  { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
481 
    (ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
482 
     | INSN_MIPS3D | INSN_MT),
483 
    mips_cp0_names_mips3264r2,
484 
    mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
485 
    mips_hwr_names_mips3264r2 },
486 
 
487 
  /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs.  */
488 
  { "mips64",   1, bfd_mach_mipsisa64, CPU_MIPS64,
489 
    ISA_MIPS64 | INSN_MIPS3D | INSN_MDMX,
490 
    mips_cp0_names_mips3264,
491 
    mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
492 
    mips_hwr_names_numeric },
493 
 
494 
  { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
495 
    (ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
496 
     | INSN_DSP64 | INSN_MT | INSN_MDMX),
497 
    mips_cp0_names_mips3264r2,
498 
    mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
499 
    mips_hwr_names_mips3264r2 },
500 
 
501 
  { "sb1",      1, bfd_mach_mips_sb1, CPU_SB1,
502 
    ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
503 
    mips_cp0_names_sb1,
504 
    mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
505 
    mips_hwr_names_numeric },
506 
 
507 
  { "loongson2e",   1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
508 
    ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric,
509 
    NULL, 0, mips_hwr_names_numeric },
510 
 
511 
  { "loongson2f",   1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
512 
    ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric,
513 
    NULL, 0, mips_hwr_names_numeric },
514 
 
515 
  { "loongson3a",   1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
516 
    ISA_MIPS64 | INSN_LOONGSON_3A, mips_cp0_names_numeric,
517 
    NULL, 0, mips_hwr_names_numeric },
518 
 
519 
  { "octeon",   1, bfd_mach_mips_octeon, CPU_OCTEON,
520 
    ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
521 
    mips_hwr_names_numeric },
522 
 
523 
  { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
524 
    ISA_MIPS64 | INSN_XLR,
525 
    mips_cp0_names_xlr,
526 
    mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
527 
    mips_hwr_names_numeric },
528 
 
529 
  /* This entry, mips16, is here only for ISA/processor selection; do
530 
     not print its name.  */
531 
  { "",         1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3,
532 
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
533 
};
534 
 
535 
/* ISA and processor type to disassemble for, and register names to use.
536 
   set_default_mips_dis_options and parse_mips_dis_options fill in these
537 
   values.  */
538 
static int mips_processor;
539 
static int mips_isa;
540 
static const char * const *mips_gpr_names;
541 
static const char * const *mips_fpr_names;
542 
static const char * const *mips_cp0_names;
543 
static const struct mips_cp0sel_name *mips_cp0sel_names;
544 
static int mips_cp0sel_names_len;
545 
static const char * const *mips_hwr_names;
546 
 
547 
/* Other options */
548 
static int no_aliases;  /* If set disassemble as most general inst.  */
549 
 
550 
static const struct mips_abi_choice *
551 
choose_abi_by_name (const char *name, unsigned int namelen)
552 
{
553 
  const struct mips_abi_choice *c;
554 
  unsigned int i;
555 
 
556 
  for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
557 
    if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
558 
        && strlen (mips_abi_choices[i].name) == namelen)
559 
      c = &mips_abi_choices[i];
560 
 
561 
  return c;
562 
}
563 
 
564 
static const struct mips_arch_choice *
565 
choose_arch_by_name (const char *name, unsigned int namelen)
566 
{
567 
  const struct mips_arch_choice *c = NULL;
568 
  unsigned int i;
569 
 
570 
  for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
571 
    if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
572 
        && strlen (mips_arch_choices[i].name) == namelen)
573 
      c = &mips_arch_choices[i];
574 
 
575 
  return c;
576 
}
577 
 
578 
static const struct mips_arch_choice *
579 
choose_arch_by_number (unsigned long mach)
580 
{
581 
  static unsigned long hint_bfd_mach;
582 
  static const struct mips_arch_choice *hint_arch_choice;
583 
  const struct mips_arch_choice *c;
584 
  unsigned int i;
585 
 
586 
  /* We optimize this because even if the user specifies no
587 
     flags, this will be done for every instruction!  */
588 
  if (hint_bfd_mach == mach
589 
      && hint_arch_choice != NULL
590 
      && hint_arch_choice->bfd_mach == hint_bfd_mach)
591 
    return hint_arch_choice;
592 
 
593 
  for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
594 
    {
595 
      if (mips_arch_choices[i].bfd_mach_valid
596 
          && mips_arch_choices[i].bfd_mach == mach)
597 
        {
598 
          c = &mips_arch_choices[i];
599 
          hint_bfd_mach = mach;
600 
          hint_arch_choice = c;
601 
        }
602 
    }
603 
  return c;
604 
}
605 
 
606 
/* Check if the object uses NewABI conventions.  */
607 
 
608 
static int
609 
is_newabi (Elf_Internal_Ehdr *header)
610 
{
611 
  /* There are no old-style ABIs which use 64-bit ELF.  */
612 
  if (header->e_ident[EI_CLASS] == ELFCLASS64)
613 
    return 1;
614 
 
615 
  /* If a 32-bit ELF file, n32 is a new-style ABI.  */
616 
  if ((header->e_flags & EF_MIPS_ABI2) != 0)
617 
    return 1;
618 
 
619 
  return 0;
620 
}
621 
 
622 
static void
623 
set_default_mips_dis_options (struct disassemble_info *info)
624 
{
625 
  const struct mips_arch_choice *chosen_arch;
626 
 
627 
  /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
628 
     and numeric FPR, CP0 register, and HWR names.  */
629 
  mips_isa = ISA_MIPS3;
630 
  mips_processor =  CPU_R3000;
631 
  mips_gpr_names = mips_gpr_names_oldabi;
632 
  mips_fpr_names = mips_fpr_names_numeric;
633 
  mips_cp0_names = mips_cp0_names_numeric;
634 
  mips_cp0sel_names = NULL;
635 
  mips_cp0sel_names_len = 0;
636 
  mips_hwr_names = mips_hwr_names_numeric;
637 
  no_aliases = 0;
638 
 
639 
  /* If an ELF "newabi" binary, use the n32/(n)64 GPR names.  */
640 
  if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
641 
    {
642 
      Elf_Internal_Ehdr *header;
643 
 
644 
      header = elf_elfheader (info->section->owner);
645 
      if (is_newabi (header))
646 
        mips_gpr_names = mips_gpr_names_newabi;
647 
    }
648 
 
649 
  /* Set ISA, architecture, and cp0 register names as best we can.  */
650 
#if ! SYMTAB_AVAILABLE
651 
  /* This is running out on a target machine, not in a host tool.
652 
     FIXME: Where does mips_target_info come from?  */
653 
  target_processor = mips_target_info.processor;
654 
  mips_isa = mips_target_info.isa;
655 
#else
656 
  chosen_arch = choose_arch_by_number (info->mach);
657 
  if (chosen_arch != NULL)
658 
    {
659 
      mips_processor = chosen_arch->processor;
660 
      mips_isa = chosen_arch->isa;
661 
      mips_cp0_names = chosen_arch->cp0_names;
662 
      mips_cp0sel_names = chosen_arch->cp0sel_names;
663 
      mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
664 
      mips_hwr_names = chosen_arch->hwr_names;
665 
    }
666 
#endif
667 
}
668 
 
669 
static void
670 
parse_mips_dis_option (const char *option, unsigned int len)
671 
{
672 
  unsigned int i, optionlen, vallen;
673 
  const char *val;
674 
  const struct mips_abi_choice *chosen_abi;
675 
  const struct mips_arch_choice *chosen_arch;
676 
 
677 
  /* Try to match options that are simple flags */
678 
  if (CONST_STRNEQ (option, "no-aliases"))
679 
    {
680 
      no_aliases = 1;
681 
      return;
682 
    }
683 
 
684 
  /* Look for the = that delimits the end of the option name.  */
685 
  for (i = 0; i < len; i++)
686 
    if (option[i] == '=')
687 
      break;
688 
 
689 
  if (i == 0)            /* Invalid option: no name before '='.  */
690 
    return;
691 
  if (i == len)         /* Invalid option: no '='.  */
692 
    return;
693 
  if (i == (len - 1))   /* Invalid option: no value after '='.  */
694 
    return;
695 
 
696 
  optionlen = i;
697 
  val = option + (optionlen + 1);
698 
  vallen = len - (optionlen + 1);
699 
 
700 
  if (strncmp ("gpr-names", option, optionlen) == 0
701 
      && strlen ("gpr-names") == optionlen)
702 
    {
703 
      chosen_abi = choose_abi_by_name (val, vallen);
704 
      if (chosen_abi != NULL)
705 
        mips_gpr_names = chosen_abi->gpr_names;
706 
      return;
707 
    }
708 
 
709 
  if (strncmp ("fpr-names", option, optionlen) == 0
710 
      && strlen ("fpr-names") == optionlen)
711 
    {
712 
      chosen_abi = choose_abi_by_name (val, vallen);
713 
      if (chosen_abi != NULL)
714 
        mips_fpr_names = chosen_abi->fpr_names;
715 
      return;
716 
    }
717 
 
718 
  if (strncmp ("cp0-names", option, optionlen) == 0
719 
      && strlen ("cp0-names") == optionlen)
720 
    {
721 
      chosen_arch = choose_arch_by_name (val, vallen);
722 
      if (chosen_arch != NULL)
723 
        {
724 
          mips_cp0_names = chosen_arch->cp0_names;
725 
          mips_cp0sel_names = chosen_arch->cp0sel_names;
726 
          mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
727 
        }
728 
      return;
729 
    }
730 
 
731 
  if (strncmp ("hwr-names", option, optionlen) == 0
732 
      && strlen ("hwr-names") == optionlen)
733 
    {
734 
      chosen_arch = choose_arch_by_name (val, vallen);
735 
      if (chosen_arch != NULL)
736 
        mips_hwr_names = chosen_arch->hwr_names;
737 
      return;
738 
    }
739 
 
740 
  if (strncmp ("reg-names", option, optionlen) == 0
741 
      && strlen ("reg-names") == optionlen)
742 
    {
743 
      /* We check both ABI and ARCH here unconditionally, so
744 
         that "numeric" will do the desirable thing: select
745 
         numeric register names for all registers.  Other than
746 
         that, a given name probably won't match both.  */
747 
      chosen_abi = choose_abi_by_name (val, vallen);
748 
      if (chosen_abi != NULL)
749 
        {
750 
          mips_gpr_names = chosen_abi->gpr_names;
751 
          mips_fpr_names = chosen_abi->fpr_names;
752 
        }
753 
      chosen_arch = choose_arch_by_name (val, vallen);
754 
      if (chosen_arch != NULL)
755 
        {
756 
          mips_cp0_names = chosen_arch->cp0_names;
757 
          mips_cp0sel_names = chosen_arch->cp0sel_names;
758 
          mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
759 
          mips_hwr_names = chosen_arch->hwr_names;
760 
        }
761 
      return;
762 
    }
763 
 
764 
  /* Invalid option.  */
765 
}
766 
 
767 
static void
768 
parse_mips_dis_options (const char *options)
769 
{
770 
  const char *option_end;
771 
 
772 
  if (options == NULL)
773 
    return;
774 
 
775 
  while (*options != '\0')
776 
    {
777 
      /* Skip empty options.  */
778 
      if (*options == ',')
779 
        {
780 
          options++;
781 
          continue;
782 
        }
783 
 
784 
      /* We know that *options is neither NUL or a comma.  */
785 
      option_end = options + 1;
786 
      while (*option_end != ',' && *option_end != '\0')
787 
        option_end++;
788 
 
789 
      parse_mips_dis_option (options, option_end - options);
790 
 
791 
      /* Go on to the next one.  If option_end points to a comma, it
792 
         will be skipped above.  */
793 
      options = option_end;
794 
    }
795 
}
796 
 
797 
static const struct mips_cp0sel_name *
798 
lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
799 
                         unsigned int len,
800 
                         unsigned int cp0reg,
801 
                         unsigned int sel)
802 
{
803 
  unsigned int i;
804 
 
805 
  for (i = 0; i < len; i++)
806 
    if (names[i].cp0reg == cp0reg && names[i].sel == sel)
807 
      return &names[i];
808 
  return NULL;
809 
}
810 
 
811 
/* Print insn arguments for 32/64-bit code.  */
812 
 
813 
static void
814 
print_insn_args (const char *d,
815 
                 register unsigned long int l,
816 
                 bfd_vma pc,
817 
                 struct disassemble_info *info,
818 
                 const struct mips_opcode *opp)
819 
{
820 
  int op, delta;
821 
  unsigned int lsb, msb, msbd;
822 
 
823 
  lsb = 0;
824 
 
825 
  for (; *d != '\0'; d++)
826 
    {
827 
      switch (*d)
828 
        {
829 
        case ',':
830 
        case '(':
831 
        case ')':
832 
        case '[':
833 
        case ']':
834 
          (*info->fprintf_func) (info->stream, "%c", *d);
835 
          break;
836 
 
837 
        case '+':
838 
          /* Extension character; switch for second char.  */
839 
          d++;
840 
          switch (*d)
841 
            {
842 
            case '\0':
843 
              /* xgettext:c-format */
844 
              (*info->fprintf_func) (info->stream,
845 
                                     _("# internal error, incomplete extension sequence (+)"));
846 
              return;
847 
 
848 
            case 'A':
849 
              lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
850 
              (*info->fprintf_func) (info->stream, "0x%x", lsb);
851 
              break;
852 
 
853 
            case 'B':
854 
              msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
855 
              (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
856 
              break;
857 
 
858 
            case '1':
859 
              (*info->fprintf_func) (info->stream, "0x%lx",
860 
                                     (l >> OP_SH_UDI1) & OP_MASK_UDI1);
861 
              break;
862 
 
863 
            case '2':
864 
              (*info->fprintf_func) (info->stream, "0x%lx",
865 
                                     (l >> OP_SH_UDI2) & OP_MASK_UDI2);
866 
              break;
867 
 
868 
            case '3':
869 
              (*info->fprintf_func) (info->stream, "0x%lx",
870 
                                     (l >> OP_SH_UDI3) & OP_MASK_UDI3);
871 
              break;
872 
 
873 
            case '4':
874 
              (*info->fprintf_func) (info->stream, "0x%lx",
875 
                                     (l >> OP_SH_UDI4) & OP_MASK_UDI4);
876 
              break;
877 
 
878 
            case 'C':
879 
            case 'H':
880 
              msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
881 
              (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
882 
              break;
883 
 
884 
            case 'D':
885 
              {
886 
                const struct mips_cp0sel_name *n;
887 
                unsigned int cp0reg, sel;
888 
 
889 
                cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
890 
                sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
891 
 
892 
                /* CP0 register including 'sel' code for mtcN (et al.), to be
893 
                   printed textually if known.  If not known, print both
894 
                   CP0 register name and sel numerically since CP0 register
895 
                   with sel 0 may have a name unrelated to register being
896 
                   printed.  */
897 
                n = lookup_mips_cp0sel_name(mips_cp0sel_names,
898 
                                            mips_cp0sel_names_len, cp0reg, sel);
899 
                if (n != NULL)
900 
                  (*info->fprintf_func) (info->stream, "%s", n->name);
901 
                else
902 
                  (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
903 
                break;
904 
              }
905 
 
906 
            case 'E':
907 
              lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
908 
              (*info->fprintf_func) (info->stream, "0x%x", lsb);
909 
              break;
910 
 
911 
            case 'F':
912 
              msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
913 
              (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
914 
              break;
915 
 
916 
            case 'G':
917 
              msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
918 
              (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
919 
              break;
920 
 
921 
            case 't': /* Coprocessor 0 reg name */
922 
              (*info->fprintf_func) (info->stream, "%s",
923 
                                     mips_cp0_names[(l >> OP_SH_RT) &
924 
                                                     OP_MASK_RT]);
925 
              break;
926 
 
927 
            case 'T': /* Coprocessor 0 reg name */
928 
              {
929 
                const struct mips_cp0sel_name *n;
930 
                unsigned int cp0reg, sel;
931 
 
932 
                cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
933 
                sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
934 
 
935 
                /* CP0 register including 'sel' code for mftc0, to be
936 
                   printed textually if known.  If not known, print both
937 
                   CP0 register name and sel numerically since CP0 register
938 
                   with sel 0 may have a name unrelated to register being
939 
                   printed.  */
940 
                n = lookup_mips_cp0sel_name(mips_cp0sel_names,
941 
                                            mips_cp0sel_names_len, cp0reg, sel);
942 
                if (n != NULL)
943 
                  (*info->fprintf_func) (info->stream, "%s", n->name);
944 
                else
945 
                  (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
946 
                break;
947 
              }
948 
 
949 
            case 'x':           /* bbit bit index */
950 
              (*info->fprintf_func) (info->stream, "0x%lx",
951 
                                     (l >> OP_SH_BBITIND) & OP_MASK_BBITIND);
952 
              break;
953 
 
954 
            case 'p':           /* cins, cins32, exts and exts32 position */
955 
              (*info->fprintf_func) (info->stream, "0x%lx",
956 
                                     (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS);
957 
              break;
958 
 
959 
            case 's':           /* cins and exts length-minus-one */
960 
              (*info->fprintf_func) (info->stream, "0x%lx",
961 
                                     (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
962 
              break;
963 
 
964 
            case 'S':           /* cins32 and exts32 length-minus-one field */
965 
              (*info->fprintf_func) (info->stream, "0x%lx",
966 
                                     (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
967 
              break;
968 
 
969 
            case 'Q':           /* seqi/snei immediate field */
970 
              op = (l >> OP_SH_SEQI) & OP_MASK_SEQI;
971 
              /* Sign-extend it.  */
972 
              op = (op ^ 512) - 512;
973 
              (*info->fprintf_func) (info->stream, "%d", op);
974 
              break;
975 
 
976 
            case 'a':           /* 8-bit signed offset in bit 6 */
977 
              delta = (l >> OP_SH_OFFSET_A) & OP_MASK_OFFSET_A;
978 
              if (delta & 0x80)
979 
                delta |= ~OP_MASK_OFFSET_A;
980 
              (*info->fprintf_func) (info->stream, "%d", delta);
981 
              break;
982 
 
983 
            case 'b':           /* 8-bit signed offset in bit 3 */
984 
              delta = (l >> OP_SH_OFFSET_B) & OP_MASK_OFFSET_B;
985 
              if (delta & 0x80)
986 
                delta |= ~OP_MASK_OFFSET_B;
987 
              (*info->fprintf_func) (info->stream, "%d", delta);
988 
              break;
989 
 
990 
            case 'c':           /* 9-bit signed offset in bit 6 */
991 
              delta = (l >> OP_SH_OFFSET_C) & OP_MASK_OFFSET_C;
992 
              if (delta & 0x100)
993 
                delta |= ~OP_MASK_OFFSET_C;
994 
              /* Left shift 4 bits to print the real offset.  */
995 
              (*info->fprintf_func) (info->stream, "%d", delta << 4);
996 
              break;
997 
 
998 
            case 'z':
999 
              (*info->fprintf_func) (info->stream, "%s",
1000 
                                     mips_gpr_names[(l >> OP_SH_RZ) & OP_MASK_RZ]);
1001 
              break;
1002 
 
1003 
            case 'Z':
1004 
              (*info->fprintf_func) (info->stream, "%s",
1005 
                                     mips_fpr_names[(l >> OP_SH_FZ) & OP_MASK_FZ]);
1006 
              break;
1007 
 
1008 
            default:
1009 
              /* xgettext:c-format */
1010 
              (*info->fprintf_func) (info->stream,
1011 
                                     _("# internal error, undefined extension sequence (+%c)"),
1012 
                                     *d);
1013 
              return;
1014 
            }
1015 
          break;
1016 
 
1017 
        case '2':
1018 
          (*info->fprintf_func) (info->stream, "0x%lx",
1019 
                                 (l >> OP_SH_BP) & OP_MASK_BP);
1020 
          break;
1021 
 
1022 
        case '3':
1023 
          (*info->fprintf_func) (info->stream, "0x%lx",
1024 
                                 (l >> OP_SH_SA3) & OP_MASK_SA3);
1025 
          break;
1026 
 
1027 
        case '4':
1028 
          (*info->fprintf_func) (info->stream, "0x%lx",
1029 
                                 (l >> OP_SH_SA4) & OP_MASK_SA4);
1030 
          break;
1031 
 
1032 
        case '5':
1033 
          (*info->fprintf_func) (info->stream, "0x%lx",
1034 
                                 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
1035 
          break;
1036 
 
1037 
        case '6':
1038 
          (*info->fprintf_func) (info->stream, "0x%lx",
1039 
                                 (l >> OP_SH_RS) & OP_MASK_RS);
1040 
          break;
1041 
 
1042 
        case '7':
1043 
          (*info->fprintf_func) (info->stream, "$ac%ld",
1044 
                                 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
1045 
          break;
1046 
 
1047 
        case '8':
1048 
          (*info->fprintf_func) (info->stream, "0x%lx",
1049 
                                 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
1050 
          break;
1051 
 
1052 
        case '9':
1053 
          (*info->fprintf_func) (info->stream, "$ac%ld",
1054 
                                 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
1055 
          break;
1056 
 
1057 
        case '0': /* dsp 6-bit signed immediate in bit 20 */
1058 
          delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
1059 
          if (delta & 0x20) /* test sign bit */
1060 
            delta |= ~OP_MASK_DSPSFT;
1061 
          (*info->fprintf_func) (info->stream, "%d", delta);
1062 
          break;
1063 
 
1064 
        case ':': /* dsp 7-bit signed immediate in bit 19 */
1065 
          delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
1066 
          if (delta & 0x40) /* test sign bit */
1067 
            delta |= ~OP_MASK_DSPSFT_7;
1068 
          (*info->fprintf_func) (info->stream, "%d", delta);
1069 
          break;
1070 
 
1071 
        case '\'':
1072 
          (*info->fprintf_func) (info->stream, "0x%lx",
1073 
                                 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
1074 
          break;
1075 
 
1076 
        case '@': /* dsp 10-bit signed immediate in bit 16 */
1077 
          delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
1078 
          if (delta & 0x200) /* test sign bit */
1079 
            delta |= ~OP_MASK_IMM10;
1080 
          (*info->fprintf_func) (info->stream, "%d", delta);
1081 
          break;
1082 
 
1083 
        case '!':
1084 
          (*info->fprintf_func) (info->stream, "%ld",
1085 
                                 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
1086 
          break;
1087 
 
1088 
        case '$':
1089 
          (*info->fprintf_func) (info->stream, "%ld",
1090 
                                 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
1091 
          break;
1092 
 
1093 
        case '*':
1094 
          (*info->fprintf_func) (info->stream, "$ac%ld",
1095 
                                 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
1096 
          break;
1097 
 
1098 
        case '&':
1099 
          (*info->fprintf_func) (info->stream, "$ac%ld",
1100 
                                 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
1101 
          break;
1102 
 
1103 
        case 'g':
1104 
          /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2.  */
1105 
          (*info->fprintf_func) (info->stream, "$%ld",
1106 
                                 (l >> OP_SH_RD) & OP_MASK_RD);
1107 
          break;
1108 
 
1109 
        case 's':
1110 
        case 'b':
1111 
        case 'r':
1112 
        case 'v':
1113 
          (*info->fprintf_func) (info->stream, "%s",
1114 
                                 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
1115 
          break;
1116 
 
1117 
        case 't':
1118 
        case 'w':
1119 
          (*info->fprintf_func) (info->stream, "%s",
1120 
                                 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1121 
          break;
1122 
 
1123 
        case 'i':
1124 
        case 'u':
1125 
          (*info->fprintf_func) (info->stream, "0x%lx",
1126 
                                 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
1127 
          break;
1128 
 
1129 
        case 'j': /* Same as i, but sign-extended.  */
1130 
        case 'o':
1131 
          delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1132 
          if (delta & 0x8000)
1133 
            delta |= ~0xffff;
1134 
          (*info->fprintf_func) (info->stream, "%d",
1135 
                                 delta);
1136 
          break;
1137 
 
1138 
        case 'h':
1139 
          (*info->fprintf_func) (info->stream, "0x%x",
1140 
                                 (unsigned int) ((l >> OP_SH_PREFX)
1141 
                                                 & OP_MASK_PREFX));
1142 
          break;
1143 
 
1144 
        case 'k':
1145 
          (*info->fprintf_func) (info->stream, "0x%x",
1146 
                                 (unsigned int) ((l >> OP_SH_CACHE)
1147 
                                                 & OP_MASK_CACHE));
1148 
          break;
1149 
 
1150 
        case 'a':
1151 
          info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1152 
                          | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
1153 
          /* For gdb disassembler, force odd address on jalx.  */
1154 
          if (info->flavour == bfd_target_unknown_flavour
1155 
              && strcmp (opp->name, "jalx") == 0)
1156 
            info->target |= 1;
1157 
          (*info->print_address_func) (info->target, info);
1158 
          break;
1159 
 
1160 
        case 'p':
1161 
          /* Sign extend the displacement.  */
1162 
          delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1163 
          if (delta & 0x8000)
1164 
            delta |= ~0xffff;
1165 
          info->target = (delta << 2) + pc + INSNLEN;
1166 
          (*info->print_address_func) (info->target, info);
1167 
          break;
1168 
 
1169 
        case 'd':
1170 
          (*info->fprintf_func) (info->stream, "%s",
1171 
                                 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1172 
          break;
1173 
 
1174 
        case 'U':
1175 
          {
1176 
            /* First check for both rd and rt being equal.  */
1177 
            unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1178 
            if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
1179 
              (*info->fprintf_func) (info->stream, "%s",
1180 
                                     mips_gpr_names[reg]);
1181 
            else
1182 
              {
1183 
                /* If one is zero use the other.  */
1184 
                if (reg == 0)
1185 
                  (*info->fprintf_func) (info->stream, "%s",
1186 
                                         mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1187 
                else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
1188 
                  (*info->fprintf_func) (info->stream, "%s",
1189 
                                         mips_gpr_names[reg]);
1190 
                else /* Bogus, result depends on processor.  */
1191 
                  (*info->fprintf_func) (info->stream, "%s or %s",
1192 
                                         mips_gpr_names[reg],
1193 
                                         mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1194 
              }
1195 
          }
1196 
          break;
1197 
 
1198 
        case 'z':
1199 
          (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1200 
          break;
1201 
 
1202 
        case '<':
1203 
        case '1':
1204 
          (*info->fprintf_func) (info->stream, "0x%lx",
1205 
                                 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1206 
          break;
1207 
 
1208 
        case 'c':
1209 
          (*info->fprintf_func) (info->stream, "0x%lx",
1210 
                                 (l >> OP_SH_CODE) & OP_MASK_CODE);
1211 
          break;
1212 
 
1213 
        case 'q':
1214 
          (*info->fprintf_func) (info->stream, "0x%lx",
1215 
                                 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
1216 
          break;
1217 
 
1218 
        case 'C':
1219 
          (*info->fprintf_func) (info->stream, "0x%lx",
1220 
                                 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1221 
          break;
1222 
 
1223 
        case 'B':
1224 
          (*info->fprintf_func) (info->stream, "0x%lx",
1225 
 
1226 
                                 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1227 
          break;
1228 
 
1229 
        case 'J':
1230 
          (*info->fprintf_func) (info->stream, "0x%lx",
1231 
                                 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1232 
          break;
1233 
 
1234 
        case 'S':
1235 
        case 'V':
1236 
          (*info->fprintf_func) (info->stream, "%s",
1237 
                                 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1238 
          break;
1239 
 
1240 
        case 'T':
1241 
        case 'W':
1242 
          (*info->fprintf_func) (info->stream, "%s",
1243 
                                 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
1244 
          break;
1245 
 
1246 
        case 'D':
1247 
          (*info->fprintf_func) (info->stream, "%s",
1248 
                                 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1249 
          break;
1250 
 
1251 
        case 'R':
1252 
          (*info->fprintf_func) (info->stream, "%s",
1253 
                                 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1254 
          break;
1255 
 
1256 
        case 'E':
1257 
          /* Coprocessor register for lwcN instructions, et al.
1258 
 
1259 
             Note that there is no load/store cp0 instructions, and
1260 
             that FPU (cp1) instructions disassemble this field using
1261 
             'T' format.  Therefore, until we gain understanding of
1262 
             cp2 register names, we can simply print the register
1263 
             numbers.  */
1264 
          (*info->fprintf_func) (info->stream, "$%ld",
1265 
                                 (l >> OP_SH_RT) & OP_MASK_RT);
1266 
          break;
1267 
 
1268 
        case 'G':
1269 
          /* Coprocessor register for mtcN instructions, et al.  Note
1270 
             that FPU (cp1) instructions disassemble this field using
1271 
             'S' format.  Therefore, we only need to worry about cp0,
1272 
             cp2, and cp3.  */
1273 
          op = (l >> OP_SH_OP) & OP_MASK_OP;
1274 
          if (op == OP_OP_COP0)
1275 
            (*info->fprintf_func) (info->stream, "%s",
1276 
                                   mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1277 
          else
1278 
            (*info->fprintf_func) (info->stream, "$%ld",
1279 
                                   (l >> OP_SH_RD) & OP_MASK_RD);
1280 
          break;
1281 
 
1282 
        case 'K':
1283 
          (*info->fprintf_func) (info->stream, "%s",
1284 
                                 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1285 
          break;
1286 
 
1287 
        case 'N':
1288 
          (*info->fprintf_func) (info->stream,
1289 
                                 ((opp->pinfo & (FP_D | FP_S)) != 0
1290 
                                  ? "$fcc%ld" : "$cc%ld"),
1291 
                                 (l >> OP_SH_BCC) & OP_MASK_BCC);
1292 
          break;
1293 
 
1294 
        case 'M':
1295 
          (*info->fprintf_func) (info->stream, "$fcc%ld",
1296 
                                 (l >> OP_SH_CCC) & OP_MASK_CCC);
1297 
          break;
1298 
 
1299 
        case 'P':
1300 
          (*info->fprintf_func) (info->stream, "%ld",
1301 
                                 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1302 
          break;
1303 
 
1304 
        case 'e':
1305 
          (*info->fprintf_func) (info->stream, "%ld",
1306 
                                 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1307 
          break;
1308 
 
1309 
        case '%':
1310 
          (*info->fprintf_func) (info->stream, "%ld",
1311 
                                 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1312 
          break;
1313 
 
1314 
        case 'H':
1315 
          (*info->fprintf_func) (info->stream, "%ld",
1316 
                                 (l >> OP_SH_SEL) & OP_MASK_SEL);
1317 
          break;
1318 
 
1319 
        case 'O':
1320 
          (*info->fprintf_func) (info->stream, "%ld",
1321 
                                 (l >> OP_SH_ALN) & OP_MASK_ALN);
1322 
          break;
1323 
 
1324 
        case 'Q':
1325 
          {
1326 
            unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
1327 
 
1328 
            if ((vsel & 0x10) == 0)
1329 
              {
1330 
                int fmt;
1331 
 
1332 
                vsel &= 0x0f;
1333 
                for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1334 
                  if ((vsel & 1) == 0)
1335 
                    break;
1336 
                (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1337 
                                       (l >> OP_SH_FT) & OP_MASK_FT,
1338 
                                       vsel >> 1);
1339 
              }
1340 
            else if ((vsel & 0x08) == 0)
1341 
              {
1342 
                (*info->fprintf_func) (info->stream, "$v%ld",
1343 
                                       (l >> OP_SH_FT) & OP_MASK_FT);
1344 
              }
1345 
            else
1346 
              {
1347 
                (*info->fprintf_func) (info->stream, "0x%lx",
1348 
                                       (l >> OP_SH_FT) & OP_MASK_FT);
1349 
              }
1350 
          }
1351 
          break;
1352 
 
1353 
        case 'X':
1354 
          (*info->fprintf_func) (info->stream, "$v%ld",
1355 
                                 (l >> OP_SH_FD) & OP_MASK_FD);
1356 
          break;
1357 
 
1358 
        case 'Y':
1359 
          (*info->fprintf_func) (info->stream, "$v%ld",
1360 
                                 (l >> OP_SH_FS) & OP_MASK_FS);
1361 
          break;
1362 
 
1363 
        case 'Z':
1364 
          (*info->fprintf_func) (info->stream, "$v%ld",
1365 
                                 (l >> OP_SH_FT) & OP_MASK_FT);
1366 
          break;
1367 
 
1368 
        default:
1369 
          /* xgettext:c-format */
1370 
          (*info->fprintf_func) (info->stream,
1371 
                                 _("# internal error, undefined modifier (%c)"),
1372 
                                 *d);
1373 
          return;
1374 
        }
1375 
    }
1376 
}
1377 
 
1378 
/* Print the mips instruction at address MEMADDR in debugged memory,
1379 
   on using INFO.  Returns length of the instruction, in bytes, which is
1380 
   always INSNLEN.  BIGENDIAN must be 1 if this is big-endian code, 0 if
1381 
   this is little-endian code.  */
1382 
 
1383 
static int
1384 
print_insn_mips (bfd_vma memaddr,
1385 
                 unsigned long int word,
1386 
                 struct disassemble_info *info)
1387 
{
1388 
  const struct mips_opcode *op;
1389 
  static bfd_boolean init = 0;
1390 
  static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1391 
 
1392 
  /* Build a hash table to shorten the search time.  */
1393 
  if (! init)
1394 
    {
1395 
      unsigned int i;
1396 
 
1397 
      for (i = 0; i <= OP_MASK_OP; i++)
1398 
        {
1399 
          for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1400 
            {
1401 
              if (op->pinfo == INSN_MACRO
1402 
                  || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1403 
                continue;
1404 
              if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1405 
                {
1406 
                  mips_hash[i] = op;
1407 
                  break;
1408 
                }
1409 
            }
1410 
        }
1411 
 
1412 
      init = 1;
1413 
    }
1414 
 
1415 
  info->bytes_per_chunk = INSNLEN;
1416 
  info->display_endian = info->endian;
1417 
  info->insn_info_valid = 1;
1418 
  info->branch_delay_insns = 0;
1419 
  info->data_size = 0;
1420 
  info->insn_type = dis_nonbranch;
1421 
  info->target = 0;
1422 
  info->target2 = 0;
1423 
 
1424 
  op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1425 
  if (op != NULL)
1426 
    {
1427 
      for (; op < &mips_opcodes[NUMOPCODES]; op++)
1428 
        {
1429 
          if (op->pinfo != INSN_MACRO
1430 
              && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1431 
              && (word & op->mask) == op->match)
1432 
            {
1433 
              const char *d;
1434 
 
1435 
              /* We always allow to disassemble the jalx instruction.  */
1436 
              if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1437 
                  && strcmp (op->name, "jalx"))
1438 
                continue;
1439 
 
1440 
              /* Figure out instruction type and branch delay information.  */
1441 
              if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1442 
                {
1443 
                  if ((op->pinfo & (INSN_WRITE_GPR_31
1444 
                                    | INSN_WRITE_GPR_D)) != 0)
1445 
                    info->insn_type = dis_jsr;
1446 
                  else
1447 
                    info->insn_type = dis_branch;
1448 
                  info->branch_delay_insns = 1;
1449 
                }
1450 
              else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1451 
                                     | INSN_COND_BRANCH_LIKELY)) != 0)
1452 
                {
1453 
                  if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
1454 
                    info->insn_type = dis_condjsr;
1455 
                  else
1456 
                    info->insn_type = dis_condbranch;
1457 
                  info->branch_delay_insns = 1;
1458 
                }
1459 
              else if ((op->pinfo & (INSN_STORE_MEMORY
1460 
                                     | INSN_LOAD_MEMORY_DELAY)) != 0)
1461 
                info->insn_type = dis_dref;
1462 
 
1463 
              (*info->fprintf_func) (info->stream, "%s", op->name);
1464 
 
1465 
              d = op->args;
1466 
              if (d != NULL && *d != '\0')
1467 
                {
1468 
                  (*info->fprintf_func) (info->stream, "\t");
1469 
                  print_insn_args (d, word, memaddr, info, op);
1470 
                }
1471 
 
1472 
              return INSNLEN;
1473 
            }
1474 
        }
1475 
    }
1476 
 
1477 
  /* Handle undefined instructions.  */
1478 
  info->insn_type = dis_noninsn;
1479 
  (*info->fprintf_func) (info->stream, "0x%lx", word);
1480 
  return INSNLEN;
1481 
}
1482 
 
1483 
/* Disassemble an operand for a mips16 instruction.  */
1484 
 
1485 
static void
1486 
print_mips16_insn_arg (char type,
1487 
                       const struct mips_opcode *op,
1488 
                       int l,
1489 
                       bfd_boolean use_extend,
1490 
                       int extend,
1491 
                       bfd_vma memaddr,
1492 
                       struct disassemble_info *info)
1493 
{
1494 
  switch (type)
1495 
    {
1496 
    case ',':
1497 
    case '(':
1498 
    case ')':
1499 
      (*info->fprintf_func) (info->stream, "%c", type);
1500 
      break;
1501 
 
1502 
    case 'y':
1503 
    case 'w':
1504 
      (*info->fprintf_func) (info->stream, "%s",
1505 
                             mips16_reg_names(((l >> MIPS16OP_SH_RY)
1506 
                                               & MIPS16OP_MASK_RY)));
1507 
      break;
1508 
 
1509 
    case 'x':
1510 
    case 'v':
1511 
      (*info->fprintf_func) (info->stream, "%s",
1512 
                             mips16_reg_names(((l >> MIPS16OP_SH_RX)
1513 
                                               & MIPS16OP_MASK_RX)));
1514 
      break;
1515 
 
1516 
    case 'z':
1517 
      (*info->fprintf_func) (info->stream, "%s",
1518 
                             mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1519 
                                               & MIPS16OP_MASK_RZ)));
1520 
      break;
1521 
 
1522 
    case 'Z':
1523 
      (*info->fprintf_func) (info->stream, "%s",
1524 
                             mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1525 
                                               & MIPS16OP_MASK_MOVE32Z)));
1526 
      break;
1527 
 
1528 
    case '0':
1529 
      (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1530 
      break;
1531 
 
1532 
    case 'S':
1533 
      (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1534 
      break;
1535 
 
1536 
    case 'P':
1537 
      (*info->fprintf_func) (info->stream, "$pc");
1538 
      break;
1539 
 
1540 
    case 'R':
1541 
      (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1542 
      break;
1543 
 
1544 
    case 'X':
1545 
      (*info->fprintf_func) (info->stream, "%s",
1546 
                             mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1547 
                                            & MIPS16OP_MASK_REGR32)]);
1548 
      break;
1549 
 
1550 
    case 'Y':
1551 
      (*info->fprintf_func) (info->stream, "%s",
1552 
                             mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1553 
      break;
1554 
 
1555 
    case '<':
1556 
    case '>':
1557 
    case '[':
1558 
    case ']':
1559 
    case '4':
1560 
    case '5':
1561 
    case 'H':
1562 
    case 'W':
1563 
    case 'D':
1564 
    case 'j':
1565 
    case '6':
1566 
    case '8':
1567 
    case 'V':
1568 
    case 'C':
1569 
    case 'U':
1570 
    case 'k':
1571 
    case 'K':
1572 
    case 'p':
1573 
    case 'q':
1574 
    case 'A':
1575 
    case 'B':
1576 
    case 'E':
1577 
      {
1578 
        int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1579 
 
1580 
        shift = 0;
1581 
        signedp = 0;
1582 
        extbits = 16;
1583 
        pcrel = 0;
1584 
        extu = 0;
1585 
        branch = 0;
1586 
        switch (type)
1587 
          {
1588 
          case '<':
1589 
            nbits = 3;
1590 
            immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1591 
            extbits = 5;
1592 
            extu = 1;
1593 
            break;
1594 
          case '>':
1595 
            nbits = 3;
1596 
            immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1597 
            extbits = 5;
1598 
            extu = 1;
1599 
            break;
1600 
          case '[':
1601 
            nbits = 3;
1602 
            immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1603 
            extbits = 6;
1604 
            extu = 1;
1605 
            break;
1606 
          case ']':
1607 
            nbits = 3;
1608 
            immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1609 
            extbits = 6;
1610 
            extu = 1;
1611 
            break;
1612 
          case '4':
1613 
            nbits = 4;
1614 
            immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1615 
            signedp = 1;
1616 
            extbits = 15;
1617 
            break;
1618 
          case '5':
1619 
            nbits = 5;
1620 
            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1621 
            info->insn_type = dis_dref;
1622 
            info->data_size = 1;
1623 
            break;
1624 
          case 'H':
1625 
            nbits = 5;
1626 
            shift = 1;
1627 
            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1628 
            info->insn_type = dis_dref;
1629 
            info->data_size = 2;
1630 
            break;
1631 
          case 'W':
1632 
            nbits = 5;
1633 
            shift = 2;
1634 
            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1635 
            if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1636 
                && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1637 
              {
1638 
                info->insn_type = dis_dref;
1639 
                info->data_size = 4;
1640 
              }
1641 
            break;
1642 
          case 'D':
1643 
            nbits = 5;
1644 
            shift = 3;
1645 
            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1646 
            info->insn_type = dis_dref;
1647 
            info->data_size = 8;
1648 
            break;
1649 
          case 'j':
1650 
            nbits = 5;
1651 
            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1652 
            signedp = 1;
1653 
            break;
1654 
          case '6':
1655 
            nbits = 6;
1656 
            immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1657 
            break;
1658 
          case '8':
1659 
            nbits = 8;
1660 
            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1661 
            break;
1662 
          case 'V':
1663 
            nbits = 8;
1664 
            shift = 2;
1665 
            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1666 
            /* FIXME: This might be lw, or it might be addiu to $sp or
1667 
               $pc.  We assume it's load.  */
1668 
            info->insn_type = dis_dref;
1669 
            info->data_size = 4;
1670 
            break;
1671 
          case 'C':
1672 
            nbits = 8;
1673 
            shift = 3;
1674 
            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1675 
            info->insn_type = dis_dref;
1676 
            info->data_size = 8;
1677 
            break;
1678 
          case 'U':
1679 
            nbits = 8;
1680 
            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1681 
            extu = 1;
1682 
            break;
1683 
          case 'k':
1684 
            nbits = 8;
1685 
            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1686 
            signedp = 1;
1687 
            break;
1688 
          case 'K':
1689 
            nbits = 8;
1690 
            shift = 3;
1691 
            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1692 
            signedp = 1;
1693 
            break;
1694 
          case 'p':
1695 
            nbits = 8;
1696 
            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1697 
            signedp = 1;
1698 
            pcrel = 1;
1699 
            branch = 1;
1700 
            break;
1701 
          case 'q':
1702 
            nbits = 11;
1703 
            immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1704 
            signedp = 1;
1705 
            pcrel = 1;
1706 
            branch = 1;
1707 
            break;
1708 
          case 'A':
1709 
            nbits = 8;
1710 
            shift = 2;
1711 
            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1712 
            pcrel = 1;
1713 
            /* FIXME: This can be lw or la.  We assume it is lw.  */
1714 
            info->insn_type = dis_dref;
1715 
            info->data_size = 4;
1716 
            break;
1717 
          case 'B':
1718 
            nbits = 5;
1719 
            shift = 3;
1720 
            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1721 
            pcrel = 1;
1722 
            info->insn_type = dis_dref;
1723 
            info->data_size = 8;
1724 
            break;
1725 
          case 'E':
1726 
            nbits = 5;
1727 
            shift = 2;
1728 
            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1729 
            pcrel = 1;
1730 
            break;
1731 
          default:
1732 
            abort ();
1733 
          }
1734 
 
1735 
        if (! use_extend)
1736 
          {
1737 
            if (signedp && immed >= (1 << (nbits - 1)))
1738 
              immed -= 1 << nbits;
1739 
            immed <<= shift;
1740 
            if ((type == '<' || type == '>' || type == '[' || type == ']')
1741 
                && immed == 0)
1742 
              immed = 8;
1743 
          }
1744 
        else
1745 
          {
1746 
            if (extbits == 16)
1747 
              immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1748 
            else if (extbits == 15)
1749 
              immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1750 
            else
1751 
              immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1752 
            immed &= (1 << extbits) - 1;
1753 
            if (! extu && immed >= (1 << (extbits - 1)))
1754 
              immed -= 1 << extbits;
1755 
          }
1756 
 
1757 
        if (! pcrel)
1758 
          (*info->fprintf_func) (info->stream, "%d", immed);
1759 
        else
1760 
          {
1761 
            bfd_vma baseaddr;
1762 
 
1763 
            if (branch)
1764 
              {
1765 
                immed *= 2;
1766 
                baseaddr = memaddr + 2;
1767 
              }
1768 
            else if (use_extend)
1769 
              baseaddr = memaddr - 2;
1770 
            else
1771 
              {
1772 
                int status;
1773 
                bfd_byte buffer[2];
1774 
 
1775 
                baseaddr = memaddr;
1776 
 
1777 
                /* If this instruction is in the delay slot of a jr
1778 
                   instruction, the base address is the address of the
1779 
                   jr instruction.  If it is in the delay slot of jalr
1780 
                   instruction, the base address is the address of the
1781 
                   jalr instruction.  This test is unreliable: we have
1782 
                   no way of knowing whether the previous word is
1783 
                   instruction or data.  */
1784 
                status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1785 
                                                    info);
1786 
                if (status == 0
1787 
                    && (((info->endian == BFD_ENDIAN_BIG
1788 
                          ? bfd_getb16 (buffer)
1789 
                          : bfd_getl16 (buffer))
1790 
                         & 0xf800) == 0x1800))
1791 
                  baseaddr = memaddr - 4;
1792 
                else
1793 
                  {
1794 
                    status = (*info->read_memory_func) (memaddr - 2, buffer,
1795 
                                                        2, info);
1796 
                    if (status == 0
1797 
                        && (((info->endian == BFD_ENDIAN_BIG
1798 
                              ? bfd_getb16 (buffer)
1799 
                              : bfd_getl16 (buffer))
1800 
                             & 0xf81f) == 0xe800))
1801 
                      baseaddr = memaddr - 2;
1802 
                  }
1803 
              }
1804 
            info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1805 
            if (pcrel && branch
1806 
                && info->flavour == bfd_target_unknown_flavour)
1807 
              /* For gdb disassembler, maintain odd address.  */
1808 
              info->target |= 1;
1809 
            (*info->print_address_func) (info->target, info);
1810 
          }
1811 
      }
1812 
      break;
1813 
 
1814 
    case 'a':
1815 
      {
1816 
        int jalx = l & 0x400;
1817 
 
1818 
        if (! use_extend)
1819 
          extend = 0;
1820 
        l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1821 
        if (!jalx && info->flavour == bfd_target_unknown_flavour)
1822 
          /* For gdb disassembler, maintain odd address.  */
1823 
          l |= 1;
1824 
      }
1825 
      info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1826 
      (*info->print_address_func) (info->target, info);
1827 
      break;
1828 
 
1829 
    case 'l':
1830 
    case 'L':
1831 
      {
1832 
        int need_comma, amask, smask;
1833 
 
1834 
        need_comma = 0;
1835 
 
1836 
        l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1837 
 
1838 
        amask = (l >> 3) & 7;
1839 
 
1840 
        if (amask > 0 && amask < 5)
1841 
          {
1842 
            (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1843 
            if (amask > 1)
1844 
              (*info->fprintf_func) (info->stream, "-%s",
1845 
                                     mips_gpr_names[amask + 3]);
1846 
            need_comma = 1;
1847 
          }
1848 
 
1849 
        smask = (l >> 1) & 3;
1850 
        if (smask == 3)
1851 
          {
1852 
            (*info->fprintf_func) (info->stream, "%s??",
1853 
                                   need_comma ? "," : "");
1854 
            need_comma = 1;
1855 
          }
1856 
        else if (smask > 0)
1857 
          {
1858 
            (*info->fprintf_func) (info->stream, "%s%s",
1859 
                                   need_comma ? "," : "",
1860 
                                   mips_gpr_names[16]);
1861 
            if (smask > 1)
1862 
              (*info->fprintf_func) (info->stream, "-%s",
1863 
                                     mips_gpr_names[smask + 15]);
1864 
            need_comma = 1;
1865 
          }
1866 
 
1867 
        if (l & 1)
1868 
          {
1869 
            (*info->fprintf_func) (info->stream, "%s%s",
1870 
                                   need_comma ? "," : "",
1871 
                                   mips_gpr_names[31]);
1872 
            need_comma = 1;
1873 
          }
1874 
 
1875 
        if (amask == 5 || amask == 6)
1876 
          {
1877 
            (*info->fprintf_func) (info->stream, "%s$f0",
1878 
                                   need_comma ? "," : "");
1879 
            if (amask == 6)
1880 
              (*info->fprintf_func) (info->stream, "-$f1");
1881 
          }
1882 
      }
1883 
      break;
1884 
 
1885 
    case 'm':
1886 
    case 'M':
1887 
      /* MIPS16e save/restore.  */
1888 
      {
1889 
      int need_comma = 0;
1890 
      int amask, args, statics;
1891 
      int nsreg, smask;
1892 
      int framesz;
1893 
      int i, j;
1894 
 
1895 
      l = l & 0x7f;
1896 
      if (use_extend)
1897 
        l |= extend << 16;
1898 
 
1899 
      amask = (l >> 16) & 0xf;
1900 
      if (amask == MIPS16_ALL_ARGS)
1901 
        {
1902 
          args = 4;
1903 
          statics = 0;
1904 
        }
1905 
      else if (amask == MIPS16_ALL_STATICS)
1906 
        {
1907 
          args = 0;
1908 
          statics = 4;
1909 
        }
1910 
      else
1911 
        {
1912 
          args = amask >> 2;
1913 
          statics = amask & 3;
1914 
        }
1915 
 
1916 
      if (args > 0) {
1917 
          (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1918 
          if (args > 1)
1919 
            (*info->fprintf_func) (info->stream, "-%s",
1920 
                                   mips_gpr_names[4 + args - 1]);
1921 
          need_comma = 1;
1922 
      }
1923 
 
1924 
      framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1925 
      if (framesz == 0 && !use_extend)
1926 
        framesz = 128;
1927 
 
1928 
      (*info->fprintf_func) (info->stream, "%s%d",
1929 
                             need_comma ? "," : "",
1930 
                             framesz);
1931 
 
1932 
      if (l & 0x40)                   /* $ra */
1933 
        (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1934 
 
1935 
      nsreg = (l >> 24) & 0x7;
1936 
      smask = 0;
1937 
      if (l & 0x20)                   /* $s0 */
1938 
        smask |= 1 << 0;
1939 
      if (l & 0x10)                   /* $s1 */
1940 
        smask |= 1 << 1;
1941 
      if (nsreg > 0)                  /* $s2-$s8 */
1942 
        smask |= ((1 << nsreg) - 1) << 2;
1943 
 
1944 
      /* Find first set static reg bit.  */
1945 
      for (i = 0; i < 9; i++)
1946 
        {
1947 
          if (smask & (1 << i))
1948 
            {
1949 
              (*info->fprintf_func) (info->stream, ",%s",
1950 
                                     mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1951 
              /* Skip over string of set bits.  */
1952 
              for (j = i; smask & (2 << j); j++)
1953 
                continue;
1954 
              if (j > i)
1955 
                (*info->fprintf_func) (info->stream, "-%s",
1956 
                                       mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1957 
              i = j + 1;
1958 
            }
1959 
        }
1960 
 
1961 
      /* Statics $ax - $a3.  */
1962 
      if (statics == 1)
1963 
        (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1964 
      else if (statics > 0)
1965 
        (*info->fprintf_func) (info->stream, ",%s-%s",
1966 
                               mips_gpr_names[7 - statics + 1],
1967 
                               mips_gpr_names[7]);
1968 
      }
1969 
      break;
1970 
 
1971 
    default:
1972 
      /* xgettext:c-format */
1973 
      (*info->fprintf_func)
1974 
        (info->stream,
1975 
         _("# internal disassembler error, unrecognised modifier (%c)"),
1976 
         type);
1977 
      abort ();
1978 
    }
1979 
}
1980 
 
1981 
/* Disassemble mips16 instructions.  */
1982 
 
1983 
static int
1984 
print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1985 
{
1986 
  int status;
1987 
  bfd_byte buffer[2];
1988 
  int length;
1989 
  int insn;
1990 
  bfd_boolean use_extend;
1991 
  int extend = 0;
1992 
  const struct mips_opcode *op, *opend;
1993 
 
1994 
  info->bytes_per_chunk = 2;
1995 
  info->display_endian = info->endian;
1996 
  info->insn_info_valid = 1;
1997 
  info->branch_delay_insns = 0;
1998 
  info->data_size = 0;
1999 
  info->insn_type = dis_nonbranch;
2000 
  info->target = 0;
2001 
  info->target2 = 0;
2002 
 
2003 
  status = (*info->read_memory_func) (memaddr, buffer, 2, info);
2004 
  if (status != 0)
2005 
    {
2006 
      (*info->memory_error_func) (status, memaddr, info);
2007 
      return -1;
2008 
    }
2009 
 
2010 
  length = 2;
2011 
 
2012 
  if (info->endian == BFD_ENDIAN_BIG)
2013 
    insn = bfd_getb16 (buffer);
2014 
  else
2015 
    insn = bfd_getl16 (buffer);
2016 
 
2017 
  /* Handle the extend opcode specially.  */
2018 
  use_extend = FALSE;
2019 
  if ((insn & 0xf800) == 0xf000)
2020 
    {
2021 
      use_extend = TRUE;
2022 
      extend = insn & 0x7ff;
2023 
 
2024 
      memaddr += 2;
2025 
 
2026 
      status = (*info->read_memory_func) (memaddr, buffer, 2, info);
2027 
      if (status != 0)
2028 
        {
2029 
          (*info->fprintf_func) (info->stream, "extend 0x%x",
2030 
                                 (unsigned int) extend);
2031 
          (*info->memory_error_func) (status, memaddr, info);
2032 
          return -1;
2033 
        }
2034 
 
2035 
      if (info->endian == BFD_ENDIAN_BIG)
2036 
        insn = bfd_getb16 (buffer);
2037 
      else
2038 
        insn = bfd_getl16 (buffer);
2039 
 
2040 
      /* Check for an extend opcode followed by an extend opcode.  */
2041 
      if ((insn & 0xf800) == 0xf000)
2042 
        {
2043 
          (*info->fprintf_func) (info->stream, "extend 0x%x",
2044 
                                 (unsigned int) extend);
2045 
          info->insn_type = dis_noninsn;
2046 
          return length;
2047 
        }
2048 
 
2049 
      length += 2;
2050 
    }
2051 
 
2052 
  /* FIXME: Should probably use a hash table on the major opcode here.  */
2053 
 
2054 
  opend = mips16_opcodes + bfd_mips16_num_opcodes;
2055 
  for (op = mips16_opcodes; op < opend; op++)
2056 
    {
2057 
      if (op->pinfo != INSN_MACRO
2058 
          && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
2059 
          && (insn & op->mask) == op->match)
2060 
        {
2061 
          const char *s;
2062 
 
2063 
          if (strchr (op->args, 'a') != NULL)
2064 
            {
2065 
              if (use_extend)
2066 
                {
2067 
                  (*info->fprintf_func) (info->stream, "extend 0x%x",
2068 
                                         (unsigned int) extend);
2069 
                  info->insn_type = dis_noninsn;
2070 
                  return length - 2;
2071 
                }
2072 
 
2073 
              use_extend = FALSE;
2074 
 
2075 
              memaddr += 2;
2076 
 
2077 
              status = (*info->read_memory_func) (memaddr, buffer, 2,
2078 
                                                  info);
2079 
              if (status == 0)
2080 
                {
2081 
                  use_extend = TRUE;
2082 
                  if (info->endian == BFD_ENDIAN_BIG)
2083 
                    extend = bfd_getb16 (buffer);
2084 
                  else
2085 
                    extend = bfd_getl16 (buffer);
2086 
                  length += 2;
2087 
                }
2088 
            }
2089 
 
2090 
          (*info->fprintf_func) (info->stream, "%s", op->name);
2091 
          if (op->args[0] != '\0')
2092 
            (*info->fprintf_func) (info->stream, "\t");
2093 
 
2094 
          for (s = op->args; *s != '\0'; s++)
2095 
            {
2096 
              if (*s == ','
2097 
                  && s[1] == 'w'
2098 
                  && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
2099 
                      == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
2100 
                {
2101 
                  /* Skip the register and the comma.  */
2102 
                  ++s;
2103 
                  continue;
2104 
                }
2105 
              if (*s == ','
2106 
                  && s[1] == 'v'
2107 
                  && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
2108 
                      == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
2109 
                {
2110 
                  /* Skip the register and the comma.  */
2111 
                  ++s;
2112 
                  continue;
2113 
                }
2114 
              print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
2115 
                                     info);
2116 
            }
2117 
 
2118 
          /* Figure out branch instruction type and delay slot information.  */
2119 
          if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2120 
            info->branch_delay_insns = 1;
2121 
          if ((op->pinfo & (INSN_UNCOND_BRANCH_DELAY
2122 
                            | MIPS16_INSN_UNCOND_BRANCH)) != 0)
2123 
            {
2124 
              if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
2125 
                info->insn_type = dis_jsr;
2126 
              else
2127 
                info->insn_type = dis_branch;
2128 
            }
2129 
          else if ((op->pinfo & MIPS16_INSN_COND_BRANCH) != 0)
2130 
            info->insn_type = dis_condbranch;
2131 
 
2132 
          return length;
2133 
        }
2134 
    }
2135 
 
2136 
  if (use_extend)
2137 
    (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
2138 
  (*info->fprintf_func) (info->stream, "0x%x", insn);
2139 
  info->insn_type = dis_noninsn;
2140 
 
2141 
  return length;
2142 
}
2143 
 
2144 
/* In an environment where we do not know the symbol type of the
2145 
   instruction we are forced to assume that the low order bit of the
2146 
   instructions' address may mark it as a mips16 instruction.  If we
2147 
   are single stepping, or the pc is within the disassembled function,
2148 
   this works.  Otherwise, we need a clue.  Sometimes.  */
2149 
 
2150 
static int
2151 
_print_insn_mips (bfd_vma memaddr,
2152 
                  struct disassemble_info *info,
2153 
                  enum bfd_endian endianness)
2154 
{
2155 
  bfd_byte buffer[INSNLEN];
2156 
  int status;
2157 
 
2158 
  set_default_mips_dis_options (info);
2159 
  parse_mips_dis_options (info->disassembler_options);
2160 
 
2161 
#if 1
2162 
  /* FIXME: If odd address, this is CLEARLY a mips 16 instruction.  */
2163 
  /* Only a few tools will work this way.  */
2164 
  if (memaddr & 0x01)
2165 
    return print_insn_mips16 (memaddr, info);
2166 
#endif
2167 
 
2168 
#if SYMTAB_AVAILABLE
2169 
  if (info->mach == bfd_mach_mips16
2170 
      || (info->symbols != NULL
2171 
          && bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
2172 
          && ELF_ST_IS_MIPS16 ((*(elf_symbol_type **) info->symbols)
2173 
                               ->internal_elf_sym.st_other)))
2174 
    return print_insn_mips16 (memaddr, info);
2175 
#endif
2176 
 
2177 
  status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2178 
  if (status == 0)
2179 
    {
2180 
      unsigned long insn;
2181 
 
2182 
      if (endianness == BFD_ENDIAN_BIG)
2183 
        insn = (unsigned long) bfd_getb32 (buffer);
2184 
      else
2185 
        insn = (unsigned long) bfd_getl32 (buffer);
2186 
 
2187 
      return print_insn_mips (memaddr, insn, info);
2188 
    }
2189 
  else
2190 
    {
2191 
      (*info->memory_error_func) (status, memaddr, info);
2192 
      return -1;
2193 
    }
2194 
}
2195 
 
2196 
int
2197 
print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2198 
{
2199 
  return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2200 
}
2201 
 
2202 
int
2203 
print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2204 
{
2205 
  return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2206 
}
2207 
 
2208 
void
2209 
print_mips_disassembler_options (FILE *stream)
2210 
{
2211 
  unsigned int i;
2212 
 
2213 
  fprintf (stream, _("\n\
2214 
The following MIPS specific disassembler options are supported for use\n\
2215 
with the -M switch (multiple options should be separated by commas):\n"));
2216 
 
2217 
  fprintf (stream, _("\n\
2218 
  gpr-names=ABI            Print GPR names according to  specified ABI.\n\
2219 
                           Default: based on binary being disassembled.\n"));
2220 
 
2221 
  fprintf (stream, _("\n\
2222 
  fpr-names=ABI            Print FPR names according to specified ABI.\n\
2223 
                           Default: numeric.\n"));
2224 
 
2225 
  fprintf (stream, _("\n\
2226 
  cp0-names=ARCH           Print CP0 register names according to\n\
2227 
                           specified architecture.\n\
2228 
                           Default: based on binary being disassembled.\n"));
2229 
 
2230 
  fprintf (stream, _("\n\
2231 
  hwr-names=ARCH           Print HWR names according to specified \n\
2232 
                           architecture.\n\
2233 
                           Default: based on binary being disassembled.\n"));
2234 
 
2235 
  fprintf (stream, _("\n\
2236 
  reg-names=ABI            Print GPR and FPR names according to\n\
2237 
                           specified ABI.\n"));
2238 
 
2239 
  fprintf (stream, _("\n\
2240 
  reg-names=ARCH           Print CP0 register and HWR names according to\n\
2241 
                           specified architecture.\n"));
2242 
 
2243 
  fprintf (stream, _("\n\
2244 
  For the options above, the following values are supported for \"ABI\":\n\
2245 
   "));
2246 
  for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
2247 
    fprintf (stream, " %s", mips_abi_choices[i].name);
2248 
  fprintf (stream, _("\n"));
2249 
 
2250 
  fprintf (stream, _("\n\
2251 
  For the options above, The following values are supported for \"ARCH\":\n\
2252 
   "));
2253 
  for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
2254 
    if (*mips_arch_choices[i].name != '\0')
2255 
      fprintf (stream, " %s", mips_arch_choices[i].name);
2256 
  fprintf (stream, _("\n"));
2257 
 
2258 
  fprintf (stream, _("\n"));
2259 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.