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[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [opcodes/] [mips-opc.c] - Blame information for rev 158

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1 18 khays
/* mips-opc.c -- MIPS opcode list.
2
   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3
   2003, 2004, 2005, 2006, 2007, 2008, 2009  Free Software Foundation, Inc.
4
   Contributed by Ralph Campbell and OSF
5
   Commented and modified by Ian Lance Taylor, Cygnus Support
6
   Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
7
   MIPS-3D, MDMX, and MIPS32 Release 2 support added by Broadcom
8
   Corporation (SiByte).
9
 
10
   This file is part of the GNU opcodes library.
11
 
12
   This library is free software; you can redistribute it and/or modify
13
   it under the terms of the GNU General Public License as published by
14
   the Free Software Foundation; either version 3, or (at your option)
15
   any later version.
16
 
17
   It is distributed in the hope that it will be useful, but WITHOUT
18
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
20
   License for more details.
21
 
22
   You should have received a copy of the GNU General Public License
23
   along with this file; see the file COPYING.  If not, write to the
24
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
25
   MA 02110-1301, USA.  */
26
 
27
#include <stdio.h>
28
#include "sysdep.h"
29
#include "opcode/mips.h"
30
 
31
/* Short hand so the lines aren't too long.  */
32
 
33
#define LDD     INSN_LOAD_MEMORY_DELAY
34
#define LCD     INSN_LOAD_COPROC_DELAY
35
#define UBD     INSN_UNCOND_BRANCH_DELAY
36
#define CBD     INSN_COND_BRANCH_DELAY
37
#define COD     INSN_COPROC_MOVE_DELAY
38
#define CLD     INSN_COPROC_MEMORY_DELAY
39
#define CBL     INSN_COND_BRANCH_LIKELY
40 158 khays
#define NODS    INSN_NO_DELAY_SLOT
41
#define TRAP    INSN_NO_DELAY_SLOT
42 18 khays
#define SM      INSN_STORE_MEMORY
43
 
44
#define WR_d    INSN_WRITE_GPR_D
45
#define WR_t    INSN_WRITE_GPR_T
46
#define WR_31   INSN_WRITE_GPR_31
47
#define WR_D    INSN_WRITE_FPR_D
48
#define WR_T    INSN_WRITE_FPR_T
49
#define WR_S    INSN_WRITE_FPR_S
50
#define RD_s    INSN_READ_GPR_S
51
#define RD_b    INSN_READ_GPR_S
52
#define RD_t    INSN_READ_GPR_T
53
#define RD_S    INSN_READ_FPR_S
54
#define RD_T    INSN_READ_FPR_T
55
#define RD_R    INSN_READ_FPR_R
56
#define WR_CC   INSN_WRITE_COND_CODE
57
#define RD_CC   INSN_READ_COND_CODE
58
#define RD_C0   INSN_COP
59
#define RD_C1   INSN_COP
60
#define RD_C2   INSN_COP
61
#define RD_C3   INSN_COP
62
#define WR_C0   INSN_COP
63
#define WR_C1   INSN_COP
64
#define WR_C2   INSN_COP
65
#define WR_C3   INSN_COP
66
#define CP      INSN_COP
67
 
68
#define WR_HI   INSN_WRITE_HI
69
#define RD_HI   INSN_READ_HI
70
#define MOD_HI  WR_HI|RD_HI
71
 
72
#define WR_LO   INSN_WRITE_LO
73
#define RD_LO   INSN_READ_LO
74
#define MOD_LO  WR_LO|RD_LO
75
 
76
#define WR_HILO WR_HI|WR_LO
77
#define RD_HILO RD_HI|RD_LO
78
#define MOD_HILO WR_HILO|RD_HILO
79
 
80
#define IS_M    INSN_MULT
81
 
82
#define WR_MACC INSN2_WRITE_MDMX_ACC
83
#define RD_MACC INSN2_READ_MDMX_ACC
84
 
85
#define I1      INSN_ISA1
86
#define I2      INSN_ISA2
87
#define I3      INSN_ISA3
88
#define I4      INSN_ISA4
89
#define I5      INSN_ISA5
90
#define I32     INSN_ISA32
91
#define I64     INSN_ISA64
92
#define I33     INSN_ISA32R2
93
#define I65     INSN_ISA64R2
94
#define I3_32   INSN_ISA3_32
95
#define I3_33   INSN_ISA3_32R2
96
#define I4_32   INSN_ISA4_32
97
#define I4_33   INSN_ISA4_32R2
98
#define I5_33   INSN_ISA5_32R2
99
 
100
/* MIPS64 MIPS-3D ASE support.  */
101
#define M3D     INSN_MIPS3D
102
 
103
/* MIPS32 SmartMIPS ASE support.  */
104
#define SMT     INSN_SMARTMIPS
105
 
106
/* MIPS64 MDMX ASE support.  */
107
#define MX      INSN_MDMX
108
 
109
#define IL2E    (INSN_LOONGSON_2E)
110
#define IL2F    (INSN_LOONGSON_2F)
111
#define IL3A    (INSN_LOONGSON_3A)
112
 
113
#define P3      INSN_4650
114
#define L1      INSN_4010
115
#define V1      (INSN_4100 | INSN_4111 | INSN_4120)
116
#define T3      INSN_3900
117
#define M1      INSN_10000
118
#define SB1     INSN_SB1
119
#define N411    INSN_4111
120
#define N412    INSN_4120
121
#define N5      (INSN_5400 | INSN_5500)
122
#define N54     INSN_5400
123
#define N55     INSN_5500
124
#define IOCT    INSN_OCTEON
125
#define XLR     INSN_XLR
126
 
127
#define G1      (T3             \
128
                 )
129
 
130
#define G2      (T3             \
131
                 )
132
 
133
#define G3      (I4             \
134
                 )
135
 
136
/* MIPS DSP ASE support.
137
   NOTE:
138
   1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3).  $ac0 is the pair
139
   of original HI and LO.  $ac1, $ac2 and $ac3 are new registers, and have
140
   the same structure as $ac0 (HI + LO).  For DSP instructions that write or
141
   read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a
142
   (RD_HILO) attributes, such that HILO dependencies are maintained
143
   conservatively.
144
 
145
   2. For some mul. instructions that use integer registers as destinations
146
   but destroy HI+LO as side-effect, we add WR_HILO to their attributes.
147
 
148
   3. MIPS DSP ASE includes a new DSP control register, which has 6 fields
149
   (ccond, outflag, EFI, c, scount, pos).  Many DSP instructions read or write
150
   certain fields of the DSP control register.  For simplicity, we decide not
151
   to track dependencies of these fields.
152
   However, "bposge32" is a branch instruction that depends on the "pos"
153
   field.  In order to make sure that GAS does not reorder DSP instructions
154 158 khays
   that writes the "pos" field and "bposge32", we add DSP_VOLA
155
   (INSN_NO_DELAY_SLOT) attribute to those instructions that write the "pos"
156
   field.  */
157 18 khays
 
158
#define WR_a    WR_HILO /* Write dsp accumulators (reuse WR_HILO)  */
159
#define RD_a    RD_HILO /* Read dsp accumulators (reuse RD_HILO)  */
160
#define MOD_a   WR_a|RD_a
161 158 khays
#define DSP_VOLA INSN_NO_DELAY_SLOT
162 18 khays
#define D32     INSN_DSP
163
#define D33     INSN_DSPR2
164
#define D64     INSN_DSP64
165
 
166
/* MIPS MT ASE support.  */
167
#define MT32    INSN_MT
168
 
169
/* Loongson support.  */
170
#define WR_z    INSN2_WRITE_GPR_Z
171
#define WR_Z    INSN2_WRITE_FPR_Z
172
#define RD_z    INSN2_READ_GPR_Z
173
#define RD_Z    INSN2_READ_FPR_Z
174
#define RD_d    INSN2_READ_GPR_D
175
 
176 158 khays
/* MIPS MCU (MicroController) ASE support.  */
177
#define MC      INSN_MCU
178
 
179 18 khays
/* The order of overloaded instructions matters.  Label arguments and
180
   register arguments look the same. Instructions that can have either
181
   for arguments must apear in the correct order in this table for the
182
   assembler to pick the right one. In other words, entries with
183
   immediate operands must apear after the same instruction with
184
   registers.
185
 
186
   Because of the lookup algorithm used, entries with the same opcode
187
   name must be contiguous.
188
 
189
   Many instructions are short hand for other instructions (i.e., The
190
   jal <register> instruction is short for jalr <register>).  */
191
 
192
const struct mips_opcode mips_builtin_opcodes[] =
193
{
194
/* These instructions appear first so that the disassembler will find
195
   them first.  The assemblers uses a hash table based on the
196
   instruction name anyhow.  */
197
/* name,    args,       match,      mask,       pinfo,                  pinfo2,         membership */
198
{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                   0,               I4_32|G3        },
199
{"pref",    "k,A(b)",   0,    (int) M_PREF_AB,   INSN_MACRO,             0,               I4_32|G3        },
200
{"prefx",   "h,t(b)",   0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S,         0,               I4_33   },
201
{"nop",     "",         0x00000000, 0xffffffff, 0,               INSN2_ALIAS,    I1      }, /* sll */
202
{"ssnop",   "",         0x00000040, 0xffffffff, 0,               INSN2_ALIAS,    I1      }, /* sll */
203
{"ehb",     "",         0x000000c0, 0xffffffff, 0,               INSN2_ALIAS,    I1      }, /* sll */
204
{"li",      "t,j",      0x24000000, 0xffe00000, WR_t,                   INSN2_ALIAS,    I1      }, /* addiu */
205
{"li",      "t,i",      0x34000000, 0xffe00000, WR_t,                   INSN2_ALIAS,    I1      }, /* ori */
206
{"li",      "t,I",      0,    (int) M_LI,        INSN_MACRO,             0,               I1      },
207
{"move",    "d,s",      0,    (int) M_MOVE,      INSN_MACRO,             0,               I1      },
208
{"move",    "d,s",      0x0000002d, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I3      },/* daddu */
209
{"move",    "d,s",      0x00000021, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I1      },/* addu */
210
{"move",    "d,s",      0x00000025, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I1      },/* or */
211
{"b",       "p",        0x10000000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1      },/* beq 0,0 */
212
{"b",       "p",        0x04010000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1      },/* bgez 0 */
213
{"bal",     "p",        0x04110000, 0xffff0000, UBD|WR_31,              INSN2_ALIAS,    I1      },/* bgezal 0*/
214
 
215
/* Loongson specific instructions.  Loongson 3A redefines the Coprocessor 2
216
   instructions.  Put them here so that disassembler will find them first.
217
   The assemblers uses a hash table based on the instruction name anyhow.  */
218
{"campi",       "d,s",          0x70000075,     0xfc1f07ff,     WR_d|RD_s,      0,       IL3A    },
219
{"campv",       "d,s",          0x70000035,     0xfc1f07ff,     WR_d|RD_s,      0,       IL3A    },
220
{"camwi",       "d,s,t",        0x700000b5,     0xfc0007ff,     RD_s|RD_t,      RD_d,   IL3A    },
221
{"ramri",       "d,s",          0x700000f5,     0xfc1f07ff,     WR_d|RD_s,      0,       IL3A    },
222
{"gsle",        "s,t",          0x70000026,     0xfc00ffff,     RD_s|RD_t,      0,       IL3A    },
223
{"gsgt",        "s,t",          0x70000027,     0xfc00ffff,     RD_s|RD_t,      0,       IL3A    },
224
{"gslble",      "t,b,d",        0xc8000010,     0xfc0007ff,     WR_t|RD_b|LDD,  RD_d,   IL3A    },
225
{"gslbgt",      "t,b,d",        0xc8000011,     0xfc0007ff,     WR_t|RD_b|LDD,  RD_d,   IL3A    },
226
{"gslhle",      "t,b,d",        0xc8000012,     0xfc0007ff,     WR_t|RD_b|LDD,  RD_d,   IL3A    },
227
{"gslhgt",      "t,b,d",        0xc8000013,     0xfc0007ff,     WR_t|RD_b|LDD,  RD_d,   IL3A    },
228
{"gslwle",      "t,b,d",        0xc8000014,     0xfc0007ff,     WR_t|RD_b|LDD,  RD_d,   IL3A    },
229
{"gslwgt",      "t,b,d",        0xc8000015,     0xfc0007ff,     WR_t|RD_b|LDD,  RD_d,   IL3A    },
230
{"gsldle",      "t,b,d",        0xc8000016,     0xfc0007ff,     WR_t|RD_b|LDD,  RD_d,   IL3A    },
231
{"gsldgt",      "t,b,d",        0xc8000017,     0xfc0007ff,     WR_t|RD_b|LDD,  RD_d,   IL3A    },
232
{"gssble",      "t,b,d",        0xe8000010,     0xfc0007ff,     RD_t|RD_b|SM,   RD_d,   IL3A    },
233
{"gssbgt",      "t,b,d",        0xe8000011,     0xfc0007ff,     RD_t|RD_b|SM,   RD_d,   IL3A    },
234
{"gsshle",      "t,b,d",        0xe8000012,     0xfc0007ff,     RD_t|RD_b|SM,   RD_d,   IL3A    },
235
{"gsshgt",      "t,b,d",        0xe8000013,     0xfc0007ff,     RD_t|RD_b|SM,   RD_d,   IL3A    },
236
{"gsswle",      "t,b,d",        0xe8000014,     0xfc0007ff,     RD_t|RD_b|SM,   RD_d,   IL3A    },
237
{"gsswgt",      "t,b,d",        0xe8000015,     0xfc0007ff,     RD_t|RD_b|SM,   RD_d,   IL3A    },
238
{"gssdle",      "t,b,d",        0xe8000016,     0xfc0007ff,     RD_t|RD_b|SM,   RD_d,   IL3A    },
239
{"gssdgt",      "t,b,d",        0xe8000017,     0xfc0007ff,     RD_t|RD_b|SM,   RD_d,   IL3A    },
240
{"gslwlec1",    "T,b,d",        0xc8000018,     0xfc0007ff,     WR_T|RD_b|LDD,  RD_d,   IL3A    },
241
{"gslwgtc1",    "T,b,d",        0xc8000019,     0xfc0007ff,     WR_T|RD_b|LDD,  RD_d,   IL3A    },
242
{"gsldlec1",    "T,b,d",        0xc800001a,     0xfc0007ff,     WR_T|RD_b|LDD,  RD_d,   IL3A    },
243
{"gsldgtc1",    "T,b,d",        0xc800001b,     0xfc0007ff,     WR_T|RD_b|LDD,  RD_d,   IL3A    },
244
{"gsswlec1",    "T,b,d",        0xe800001c,     0xfc0007ff,     RD_T|RD_b|SM,   RD_d,   IL3A    },
245
{"gsswgtc1",    "T,b,d",        0xe800001d,     0xfc0007ff,     RD_T|RD_b|SM,   RD_d,   IL3A    },
246
{"gssdlec1",    "T,b,d",        0xe800001e,     0xfc0007ff,     RD_T|RD_b|SM,   RD_d,   IL3A    },
247
{"gssdgtc1",    "T,b,d",        0xe800001f,     0xfc0007ff,     RD_T|RD_b|SM,   RD_d,   IL3A    },
248
{"gslwlc1",     "T,+a(b)",      0xc8000004,     0xfc00c03f,     WR_T|RD_b|LDD,  0,       IL3A    },
249
{"gslwrc1",     "T,+a(b)",      0xc8000005,     0xfc00c03f,     WR_T|RD_b|LDD,  0,       IL3A    },
250
{"gsldlc1",     "T,+a(b)",      0xc8000006,     0xfc00c03f,     WR_T|RD_b|LDD,  0,       IL3A    },
251
{"gsldrc1",     "T,+a(b)",      0xc8000007,     0xfc00c03f,     WR_T|RD_b|LDD,  0,       IL3A    },
252
{"gsswlc1",     "T,+a(b)",      0xe8000004,     0xfc00c03f,     RD_T|RD_b|SM,   0,       IL3A    },
253
{"gsswrc1",     "T,+a(b)",      0xe8000005,     0xfc00c03f,     RD_T|RD_b|SM,   0,       IL3A    },
254
{"gssdlc1",     "T,+a(b)",      0xe8000006,     0xfc00c03f,     RD_T|RD_b|SM,   0,       IL3A    },
255
{"gssdrc1",     "T,+a(b)",      0xe8000007,     0xfc00c03f,     RD_T|RD_b|SM,   0,       IL3A    },
256
{"gslbx",       "t,+b(b,d)",    0xd8000000,     0xfc000007,     WR_t|RD_b|LDD,  RD_d,   IL3A    },
257
{"gslhx",       "t,+b(b,d)",    0xd8000001,     0xfc000007,     WR_t|RD_b|LDD,  RD_d,   IL3A    },
258
{"gslwx",       "t,+b(b,d)",    0xd8000002,     0xfc000007,     WR_t|RD_b|LDD,  RD_d,   IL3A    },
259
{"gsldx",       "t,+b(b,d)",    0xd8000003,     0xfc000007,     WR_t|RD_b|LDD,  RD_d,   IL3A    },
260
{"gssbx",       "t,+b(b,d)",    0xf8000000,     0xfc000007,     RD_t|RD_b|SM,   RD_d,   IL3A    },
261
{"gsshx",       "t,+b(b,d)",    0xf8000001,     0xfc000007,     RD_t|RD_b|SM,   RD_d,   IL3A    },
262
{"gsswx",       "t,+b(b,d)",    0xf8000002,     0xfc000007,     RD_t|RD_b|SM,   RD_d,   IL3A    },
263
{"gssdx",       "t,+b(b,d)",    0xf8000003,     0xfc000007,     RD_t|RD_b|SM,   RD_d,   IL3A    },
264
{"gslwxc1",     "T,+b(b,d)",    0xd8000006,     0xfc000007,     WR_T|RD_b|LDD,  RD_d,   IL3A    },
265
{"gsldxc1",     "T,+b(b,d)",    0xd8000007,     0xfc000007,     WR_T|RD_b|LDD,  RD_d,   IL3A    },
266
{"gsswxc1",     "T,+b(b,d)",    0xf8000006,     0xfc000007,     RD_T|RD_b|SM,   RD_d,   IL3A    },
267
{"gssdxc1",     "T,+b(b,d)",    0xf8000007,     0xfc000007,     RD_T|RD_b|SM,   RD_d,   IL3A    },
268
{"gslq",        "+z,t,+c(b)",   0xc8000020,     0xfc008020,     WR_t|RD_b|LDD,  WR_z,   IL3A    },
269
{"gssq",        "+z,t,+c(b)",   0xe8000020,     0xfc008020,     RD_t|RD_b|SM,   RD_z,   IL3A    },
270
{"gslqc1",      "+Z,T,+c(b)",   0xc8008020,     0xfc008020,     WR_T|RD_b|LDD,  WR_Z,   IL3A    },
271
{"gssqc1",      "+Z,T,+c(b)",   0xe8008020,     0xfc008020,     RD_T|RD_b|SM,   RD_Z,   IL3A    },
272
 
273
{"abs",     "d,v",      0,    (int) M_ABS,       INSN_MACRO,             0,               I1      },
274
{"abs.s",   "D,V",      0x46000005, 0xffff003f, WR_D|RD_S|FP_S,         0,               I1      },
275
{"abs.d",   "D,V",      0x46200005, 0xffff003f, WR_D|RD_S|FP_D,         0,               I1      },
276
{"abs.ps",  "D,V",      0x46c00005, 0xffff003f, WR_D|RD_S|FP_D,         0,               I5_33|IL2F      },
277
{"abs.ps",  "D,V",      0x45600005, 0xffff003f, WR_D|RD_S|FP_D,         0,               IL2E    },
278 158 khays
{"aclr",    "\\,~(b)",  0x04070000, 0xfc1f8000, SM|RD_b|NODS,           0,               MC      },
279
{"aclr",    "\\,o(b)",  0,    (int) M_ACLR_OB,   INSN_MACRO,             0,               MC      },
280
{"aclr",    "\\,A(b)",  0,    (int) M_ACLR_AB,   INSN_MACRO,             0,               MC      },
281 18 khays
{"add",     "d,v,t",    0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I1      },
282
{"add",     "t,r,I",    0,    (int) M_ADD_I,     INSN_MACRO,             0,               I1      },
283
{"add", "D,S,T",        0x45c00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2E    },
284
{"add", "D,S,T",        0x4b40000c,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2F|IL3A       },
285
{"add.s",   "D,V,T",    0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,               I1      },
286
{"add.d",   "D,V,T",    0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               I1      },
287
{"add.ob",  "X,Y,Q",    0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX|SB1  },
288
{"add.ob",  "D,S,T",    0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
289
{"add.ob",  "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T,         0,               N54     },
290
{"add.ob",  "D,S,k",    0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
291
{"add.ps",  "D,V,T",    0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               I5_33|IL2F      },
292
{"add.ps",  "D,V,T",    0x45600000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               IL2E    },
293
{"add.qh",  "X,Y,Q",    0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },
294
{"adda.ob", "Y,Q",      0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
295
{"adda.qh", "Y,Q",      0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
296
{"addi",    "t,r,j",    0x20000000, 0xfc000000, WR_t|RD_s,              0,               I1      },
297
{"addiu",   "t,r,j",    0x24000000, 0xfc000000, WR_t|RD_s,              0,               I1      },
298
{"addl.ob", "Y,Q",      0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
299
{"addl.qh", "Y,Q",      0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
300
{"addr.ps", "D,S,T",    0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               M3D     },
301
{"addu",    "d,v,t",    0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I1      },
302
{"addu",    "t,r,I",    0,    (int) M_ADDU_I,    INSN_MACRO,             0,               I1      },
303
{"addu",        "D,S,T",        0x45800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2E    },
304
{"addu",        "D,S,T",        0x4b00000c,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2F|IL3A       },
305
{"alni.ob", "X,Y,Z,O",  0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,               MX|SB1  },
306
{"alni.ob", "D,S,T,%",  0x48000018, 0xff00003f, WR_D|RD_S|RD_T,         0,               N54     },
307
{"alni.qh", "X,Y,Z,O",  0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },
308
{"alnv.ps", "D,V,T,s",  0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,             I5_33   },
309
{"alnv.ob", "X,Y,Z,s",  0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,             MX|SB1  },
310
{"alnv.qh", "X,Y,Z,s",  0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,             MX      },
311
{"and",     "d,v,t",    0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I1      },
312
{"and",     "t,r,I",    0,    (int) M_AND_I,     INSN_MACRO,             0,               I1      },
313
{"and", "D,S,T",        0x47c00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
314
{"and", "D,S,T",        0x4bc00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
315
{"and.ob",  "X,Y,Q",    0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX|SB1  },
316
{"and.ob",  "D,S,T",    0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
317
{"and.ob",  "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T,         0,               N54     },
318
{"and.ob",  "D,S,k",    0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
319
{"and.qh",  "X,Y,Q",    0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },
320
{"andi",    "t,r,i",    0x30000000, 0xfc000000, WR_t|RD_s,              0,               I1      },
321 158 khays
{"aset",    "\\,~(b)",  0x04078000, 0xfc1f8000, SM|RD_b|NODS,           0,               MC      },
322
{"aset",    "\\,o(b)",  0,    (int) M_ASET_OB,   INSN_MACRO,             0,               MC      },
323
{"aset",    "\\,A(b)",  0,    (int) M_ASET_AB,   INSN_MACRO,             0,               MC      },
324 18 khays
{"baddu",   "d,v,t",    0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               IOCT    },
325
/* b is at the top of the table.  */
326
/* bal is at the top of the table.  */
327
{"bbit032", "s,+x,p",   0xd8000000, 0xfc000000, RD_s|CBD,               0,               IOCT    },
328
{"bbit0",   "s,+X,p",   0xd8000000, 0xfc000000, RD_s|CBD,               0,               IOCT    }, /* bbit032 */
329
{"bbit0",   "s,+x,p",   0xc8000000, 0xfc000000, RD_s|CBD,               0,               IOCT    },
330
{"bbit132", "s,+x,p",   0xf8000000, 0xfc000000, RD_s|CBD,               0,               IOCT    },
331
{"bbit1",   "s,+X,p",   0xf8000000, 0xfc000000, RD_s|CBD,               0,               IOCT    }, /* bbit132 */
332
{"bbit1",   "s,+x,p",   0xe8000000, 0xfc000000, RD_s|CBD,               0,               IOCT    },
333
/* bc0[tf]l? are at the bottom of the table.  */
334
{"bc1any2f", "N,p",     0x45200000, 0xffe30000, CBD|RD_CC|FP_S,         0,               M3D     },
335
{"bc1any2t", "N,p",     0x45210000, 0xffe30000, CBD|RD_CC|FP_S,         0,               M3D     },
336
{"bc1any4f", "N,p",     0x45400000, 0xffe30000, CBD|RD_CC|FP_S,         0,               M3D     },
337
{"bc1any4t", "N,p",     0x45410000, 0xffe30000, CBD|RD_CC|FP_S,         0,               M3D     },
338
{"bc1f",    "p",        0x45000000, 0xffff0000, CBD|RD_CC|FP_S,         0,               I1      },
339
{"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S,         0,               I4_32   },
340
{"bc1fl",   "p",        0x45020000, 0xffff0000, CBL|RD_CC|FP_S,         0,               I2|T3   },
341
{"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S,         0,               I4_32   },
342
{"bc1t",    "p",        0x45010000, 0xffff0000, CBD|RD_CC|FP_S,         0,               I1      },
343
{"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S,         0,               I4_32   },
344
{"bc1tl",   "p",        0x45030000, 0xffff0000, CBL|RD_CC|FP_S,         0,               I2|T3   },
345
{"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S,         0,               I4_32   },
346
/* bc2* are at the bottom of the table.  */
347
/* bc3* are at the bottom of the table.  */
348
{"beqz",    "s,p",      0x10000000, 0xfc1f0000, CBD|RD_s,               0,               I1      },
349
{"beqzl",   "s,p",      0x50000000, 0xfc1f0000, CBL|RD_s,               0,               I2|T3   },
350
{"beq",     "s,t,p",    0x10000000, 0xfc000000, CBD|RD_s|RD_t,          0,               I1      },
351
{"beq",     "s,I,p",    0,    (int) M_BEQ_I,     INSN_MACRO,             0,               I1      },
352
{"beql",    "s,t,p",    0x50000000, 0xfc000000, CBL|RD_s|RD_t,          0,               I2|T3   },
353
{"beql",    "s,I,p",    0,    (int) M_BEQL_I,    INSN_MACRO,             0,               I2|T3   },
354
{"bge",     "s,t,p",    0,    (int) M_BGE,       INSN_MACRO,             0,               I1      },
355
{"bge",     "s,I,p",    0,    (int) M_BGE_I,     INSN_MACRO,             0,               I1      },
356
{"bgel",    "s,t,p",    0,    (int) M_BGEL,      INSN_MACRO,             0,               I2|T3   },
357
{"bgel",    "s,I,p",    0,    (int) M_BGEL_I,    INSN_MACRO,             0,               I2|T3   },
358
{"bgeu",    "s,t,p",    0,    (int) M_BGEU,      INSN_MACRO,             0,               I1      },
359
{"bgeu",    "s,I,p",    0,    (int) M_BGEU_I,    INSN_MACRO,             0,               I1      },
360
{"bgeul",   "s,t,p",    0,    (int) M_BGEUL,     INSN_MACRO,             0,               I2|T3   },
361
{"bgeul",   "s,I,p",    0,    (int) M_BGEUL_I,   INSN_MACRO,             0,               I2|T3   },
362
{"bgez",    "s,p",      0x04010000, 0xfc1f0000, CBD|RD_s,               0,               I1      },
363
{"bgezl",   "s,p",      0x04030000, 0xfc1f0000, CBL|RD_s,               0,               I2|T3   },
364
{"bgezal",  "s,p",      0x04110000, 0xfc1f0000, CBD|RD_s|WR_31,         0,               I1      },
365
{"bgezall", "s,p",      0x04130000, 0xfc1f0000, CBL|RD_s|WR_31,         0,               I2|T3   },
366
{"bgt",     "s,t,p",    0,    (int) M_BGT,       INSN_MACRO,             0,               I1      },
367
{"bgt",     "s,I,p",    0,    (int) M_BGT_I,     INSN_MACRO,             0,               I1      },
368
{"bgtl",    "s,t,p",    0,    (int) M_BGTL,      INSN_MACRO,             0,               I2|T3   },
369
{"bgtl",    "s,I,p",    0,    (int) M_BGTL_I,    INSN_MACRO,             0,               I2|T3   },
370
{"bgtu",    "s,t,p",    0,    (int) M_BGTU,      INSN_MACRO,             0,               I1      },
371
{"bgtu",    "s,I,p",    0,    (int) M_BGTU_I,    INSN_MACRO,             0,               I1      },
372
{"bgtul",   "s,t,p",    0,    (int) M_BGTUL,     INSN_MACRO,             0,               I2|T3   },
373
{"bgtul",   "s,I,p",    0,    (int) M_BGTUL_I,   INSN_MACRO,             0,               I2|T3   },
374
{"bgtz",    "s,p",      0x1c000000, 0xfc1f0000, CBD|RD_s,               0,               I1      },
375
{"bgtzl",   "s,p",      0x5c000000, 0xfc1f0000, CBL|RD_s,               0,               I2|T3   },
376
{"ble",     "s,t,p",    0,    (int) M_BLE,       INSN_MACRO,             0,               I1      },
377
{"ble",     "s,I,p",    0,    (int) M_BLE_I,     INSN_MACRO,             0,               I1      },
378
{"blel",    "s,t,p",    0,    (int) M_BLEL,      INSN_MACRO,             0,               I2|T3   },
379
{"blel",    "s,I,p",    0,    (int) M_BLEL_I,    INSN_MACRO,             0,               I2|T3   },
380
{"bleu",    "s,t,p",    0,    (int) M_BLEU,      INSN_MACRO,             0,               I1      },
381
{"bleu",    "s,I,p",    0,    (int) M_BLEU_I,    INSN_MACRO,             0,               I1      },
382
{"bleul",   "s,t,p",    0,    (int) M_BLEUL,     INSN_MACRO,             0,               I2|T3   },
383
{"bleul",   "s,I,p",    0,    (int) M_BLEUL_I,   INSN_MACRO,             0,               I2|T3   },
384
{"blez",    "s,p",      0x18000000, 0xfc1f0000, CBD|RD_s,               0,               I1      },
385
{"blezl",   "s,p",      0x58000000, 0xfc1f0000, CBL|RD_s,               0,               I2|T3   },
386
{"blt",     "s,t,p",    0,    (int) M_BLT,       INSN_MACRO,             0,               I1      },
387
{"blt",     "s,I,p",    0,    (int) M_BLT_I,     INSN_MACRO,             0,               I1      },
388
{"bltl",    "s,t,p",    0,    (int) M_BLTL,      INSN_MACRO,             0,               I2|T3   },
389
{"bltl",    "s,I,p",    0,    (int) M_BLTL_I,    INSN_MACRO,             0,               I2|T3   },
390
{"bltu",    "s,t,p",    0,    (int) M_BLTU,      INSN_MACRO,             0,               I1      },
391
{"bltu",    "s,I,p",    0,    (int) M_BLTU_I,    INSN_MACRO,             0,               I1      },
392
{"bltul",   "s,t,p",    0,    (int) M_BLTUL,     INSN_MACRO,             0,               I2|T3   },
393
{"bltul",   "s,I,p",    0,    (int) M_BLTUL_I,   INSN_MACRO,             0,               I2|T3   },
394
{"bltz",    "s,p",      0x04000000, 0xfc1f0000, CBD|RD_s,               0,               I1      },
395
{"bltzl",   "s,p",      0x04020000, 0xfc1f0000, CBL|RD_s,               0,               I2|T3   },
396
{"bltzal",  "s,p",      0x04100000, 0xfc1f0000, CBD|RD_s|WR_31,         0,               I1      },
397
{"bltzall", "s,p",      0x04120000, 0xfc1f0000, CBL|RD_s|WR_31,         0,               I2|T3   },
398
{"bnez",    "s,p",      0x14000000, 0xfc1f0000, CBD|RD_s,               0,               I1      },
399
{"bnezl",   "s,p",      0x54000000, 0xfc1f0000, CBL|RD_s,               0,               I2|T3   },
400
{"bne",     "s,t,p",    0x14000000, 0xfc000000, CBD|RD_s|RD_t,          0,               I1      },
401
{"bne",     "s,I,p",    0,    (int) M_BNE_I,     INSN_MACRO,             0,               I1      },
402
{"bnel",    "s,t,p",    0x54000000, 0xfc000000, CBL|RD_s|RD_t,          0,               I2|T3   },
403
{"bnel",    "s,I,p",    0,    (int) M_BNEL_I,    INSN_MACRO,             0,               I2|T3   },
404
{"break",   "",         0x0000000d, 0xffffffff, TRAP,                   0,               I1      },
405
{"break",   "c",        0x0000000d, 0xfc00ffff, TRAP,                   0,               I1      },
406
{"break",   "c,q",      0x0000000d, 0xfc00003f, TRAP,                   0,               I1      },
407
{"c.f.d",   "S,T",      0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },
408
{"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },
409
{"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },
410
{"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },
411
{"c.f.ps",  "S,T",      0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },
412
{"c.f.ps",  "S,T",      0x45600030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },
413
{"c.f.ps",  "M,S,T",    0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },
414
{"c.un.d",  "S,T",      0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },
415
{"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },
416
{"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },
417
{"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },
418
{"c.un.ps", "S,T",      0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },
419
{"c.un.ps", "S,T",      0x45600031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },
420
{"c.un.ps", "M,S,T",    0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },
421
{"c.eq.d",  "S,T",      0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },
422
{"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },
423
{"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },
424
{"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },
425
{"c.eq.ob", "Y,Q",      0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,               MX|SB1  },
426
{"c.eq.ob", "S,T",      0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,               N54     },
427
{"c.eq.ob", "S,T[e]",   0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,               N54     },
428
{"c.eq.ob", "S,k",      0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,               N54     },
429
{"c.eq.ps", "S,T",      0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },
430
{"c.eq.ps", "S,T",      0x45600032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },
431
{"c.eq.ps", "M,S,T",    0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },
432
{"c.eq.qh", "Y,Q",      0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,               MX      },
433
{"c.ueq.d", "S,T",      0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },
434
{"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },
435
{"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },
436
{"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },
437
{"c.ueq.ps","S,T",      0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },
438
{"c.ueq.ps","S,T",      0x45600033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },
439
{"c.ueq.ps","M,S,T",    0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },
440
{"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },
441
{"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },
442
{"c.olt.s", "S,T",      0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },
443
{"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },
444
{"c.olt.ps","S,T",      0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },
445
{"c.olt.ps","S,T",      0x45600034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },
446
{"c.olt.ps","M,S,T",    0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },
447
{"c.ult.d", "S,T",      0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },
448
{"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },
449
{"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },
450
{"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },
451
{"c.ult.ps","S,T",      0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },
452
{"c.ult.ps","S,T",      0x45600035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },
453
{"c.ult.ps","M,S,T",    0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },
454
{"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },
455
{"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },
456
{"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },
457
{"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },
458
{"c.ole.ps","S,T",      0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },
459
{"c.ole.ps","S,T",      0x45600036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },
460
{"c.ole.ps","M,S,T",    0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },
461
{"c.ule.d", "S,T",      0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },
462
{"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },
463
{"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },
464
{"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },
465
{"c.ule.ps","S,T",      0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },
466
{"c.ule.ps","S,T",      0x45600037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },
467
{"c.ule.ps","M,S,T",    0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },
468
{"c.sf.d",  "S,T",      0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },
469
{"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },
470
{"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },
471
{"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },
472
{"c.sf.ps", "S,T",      0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },
473
{"c.sf.ps", "S,T",      0x45600038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },
474
{"c.sf.ps", "M,S,T",    0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },
475
{"c.ngle.d","S,T",      0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },
476
{"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },
477
{"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },
478
{"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },
479
{"c.ngle.ps","S,T",     0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },
480
{"c.ngle.ps","S,T",     0x45600039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },
481
{"c.ngle.ps","M,S,T",   0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },
482
{"c.seq.d", "S,T",      0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },
483
{"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },
484
{"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },
485
{"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },
486
{"c.seq.ps","S,T",      0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },
487
{"c.seq.ps","S,T",      0x4560003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },
488
{"c.seq.ps","M,S,T",    0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },
489
{"c.ngl.d", "S,T",      0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },
490
{"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },
491
{"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },
492
{"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },
493
{"c.ngl.ps","S,T",      0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },
494
{"c.ngl.ps","S,T",      0x4560003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },
495
{"c.ngl.ps","M,S,T",    0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },
496
{"c.lt.d",  "S,T",      0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },
497
{"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },
498
{"c.lt.s",  "S,T",      0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },
499
{"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },
500
{"c.lt.ob", "Y,Q",      0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,               MX|SB1  },
501
{"c.lt.ob", "S,T",      0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,               N54     },
502
{"c.lt.ob", "S,T[e]",   0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,               N54     },
503
{"c.lt.ob", "S,k",      0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,               N54     },
504
{"c.lt.ps", "S,T",      0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },
505
{"c.lt.ps", "S,T",      0x4560003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },
506
{"c.lt.ps", "M,S,T",    0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },
507
{"c.lt.qh", "Y,Q",      0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,               MX      },
508
{"c.nge.d", "S,T",      0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },
509
{"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },
510
{"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },
511
{"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },
512
{"c.nge.ps","S,T",      0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },
513
{"c.nge.ps","S,T",      0x4560003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },
514
{"c.nge.ps","M,S,T",    0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },
515
{"c.le.d",  "S,T",      0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },
516
{"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },
517
{"c.le.s",  "S,T",      0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },
518
{"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },
519
{"c.le.ob", "Y,Q",      0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,               MX|SB1  },
520
{"c.le.ob", "S,T",      0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,               N54     },
521
{"c.le.ob", "S,T[e]",   0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,               N54     },
522
{"c.le.ob", "S,k",      0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,               N54     },
523
{"c.le.ps", "S,T",      0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },
524
{"c.le.ps", "S,T",      0x4560003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },
525
{"c.le.ps", "M,S,T",    0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },
526
{"c.le.qh", "Y,Q",      0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,               MX      },
527
{"c.ngt.d", "S,T",      0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },
528
{"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },
529
{"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },
530
{"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },
531
{"c.ngt.ps","S,T",      0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },
532
{"c.ngt.ps","S,T",      0x4560003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },
533
{"c.ngt.ps","M,S,T",    0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },
534
{"cabs.eq.d",  "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
535
{"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
536
{"cabs.eq.s",  "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               M3D     },
537
{"cabs.f.d",   "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
538
{"cabs.f.ps",  "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
539
{"cabs.f.s",   "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               M3D     },
540
{"cabs.le.d",  "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
541
{"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
542
{"cabs.le.s",  "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               M3D     },
543
{"cabs.lt.d",  "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
544
{"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
545
{"cabs.lt.s",  "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               M3D     },
546
{"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
547
{"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
548
{"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               M3D     },
549
{"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
550
{"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
551
{"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               M3D     },
552
{"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
553
{"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
554
{"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               M3D     },
555
{"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
556
{"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
557
{"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               M3D     },
558
{"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
559
{"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
560
{"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               M3D     },
561
{"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
562
{"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
563
{"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               M3D     },
564
{"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
565
{"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
566
{"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               M3D     },
567
{"cabs.sf.d",  "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
568
{"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
569
{"cabs.sf.s",  "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               M3D     },
570
{"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
571
{"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
572
{"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               M3D     },
573
{"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
574
{"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
575
{"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               M3D     },
576
{"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
577
{"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
578
{"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               M3D     },
579
{"cabs.un.d",  "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
580
{"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               M3D     },
581
{"cabs.un.s",  "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               M3D     },
582
/* CW4010 instructions which are aliases for the cache instruction.  */
583
{"flushi",  "",         0xbc010000, 0xffffffff, 0,                       0,               L1      },
584
{"flushd",  "",         0xbc020000, 0xffffffff, 0,                       0,               L1      },
585
{"flushid", "",         0xbc030000, 0xffffffff, 0,                       0,               L1      },
586
{"wb",      "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b,                0,               L1      },
587
{"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,                   0,               I3_32|T3},
588
{"cache",   "k,A(b)",   0,    (int) M_CACHE_AB, INSN_MACRO,              0,               I3_32|T3},
589
{"ceil.l.d", "D,S",     0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,         0,               I3_33   },
590
{"ceil.l.s", "D,S",     0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               I3_33   },
591
{"ceil.w.d", "D,S",     0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               I2      },
592
{"ceil.w.s", "D,S",     0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,         0,               I2      },
593
{"cfc0",    "t,G",      0x40400000, 0xffe007ff, LCD|WR_t|RD_C0,         0,               I1      },
594
{"cfc1",    "t,G",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,               I1      },
595
{"cfc1",    "t,S",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,               I1      },
596
/* cfc2 is at the bottom of the table.  */
597
/* cfc3 is at the bottom of the table.  */
598
{"cftc1",   "d,E",      0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,             MT32    },
599
{"cftc1",   "d,T",      0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,             MT32    },
600
{"cftc2",   "d,E",      0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,               MT32    },
601
{"cins32",  "t,r,+p,+S",0x70000033, 0xfc00003f, WR_t|RD_s,              0,               IOCT    },
602
{"cins",    "t,r,+P,+S",0x70000033, 0xfc00003f, WR_t|RD_s,              0,               IOCT    }, /* cins32 */
603
{"cins",    "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s,              0,               IOCT    },
604
{"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s,         0,               I32|N55 },
605
{"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s,         0,               I32|N55 },
606
{"ctc0",    "t,G",      0x40c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,               I1      },
607
{"ctc1",    "t,G",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,               I1      },
608
{"ctc1",    "t,S",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,               I1      },
609
/* ctc2 is at the bottom of the table.  */
610
/* ctc3 is at the bottom of the table.  */
611
{"cttc1",   "t,g",      0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,             MT32    },
612
{"cttc1",   "t,S",      0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,             MT32    },
613
{"cttc2",   "t,g",      0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC,    0,               MT32    },
614
{"cvt.d.l", "D,S",      0x46a00021, 0xffff003f, WR_D|RD_S|FP_D,         0,               I3_33   },
615
{"cvt.d.s", "D,S",      0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               I1      },
616
{"cvt.d.w", "D,S",      0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               I1      },
617
{"cvt.l.d", "D,S",      0x46200025, 0xffff003f, WR_D|RD_S|FP_D,         0,               I3_33   },
618
{"cvt.l.s", "D,S",      0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               I3_33   },
619
{"cvt.s.l", "D,S",      0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               I3_33   },
620
{"cvt.s.d", "D,S",      0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               I1      },
621
{"cvt.s.w", "D,S",      0x46800020, 0xffff003f, WR_D|RD_S|FP_S,         0,               I1      },
622
{"cvt.s.pl","D,S",      0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               I5_33   },
623
{"cvt.s.pu","D,S",      0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               I5_33   },
624
{"cvt.w.d", "D,S",      0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               I1      },
625
{"cvt.w.s", "D,S",      0x46000024, 0xffff003f, WR_D|RD_S|FP_S,         0,               I1      },
626
{"cvt.ps.pw", "D,S",    0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               M3D     },
627
{"cvt.ps.s","D,V,T",    0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0,             I5_33   },
628
{"cvt.pw.ps", "D,S",    0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               M3D     },
629
{"dabs",    "d,v",      0,    (int) M_DABS,      INSN_MACRO,             0,               I3      },
630
{"dadd",    "d,v,t",    0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I3      },
631
{"dadd",    "t,r,I",    0,    (int) M_DADD_I,    INSN_MACRO,             0,               I3      },
632
{"dadd",        "D,S,T",        0x45e00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
633
{"dadd",        "D,S,T",        0x4b60000c,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
634
{"daddi",   "t,r,j",    0x60000000, 0xfc000000, WR_t|RD_s,              0,               I3      },
635
{"daddiu",  "t,r,j",    0x64000000, 0xfc000000, WR_t|RD_s,              0,               I3      },
636
{"daddu",   "d,v,t",    0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I3      },
637
{"daddu",   "t,r,I",    0,    (int) M_DADDU_I,   INSN_MACRO,             0,               I3      },
638
{"daddwc",  "d,s,t",    0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0,     0,       XLR     },
639
{"dbreak",  "",         0x7000003f, 0xffffffff, 0,                       0,               N5      },
640
{"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t,         0,               I64|N55 },
641
{"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t,         0,               I64|N55 },
642
/* dctr and dctw are used on the r5000.  */
643
{"dctr",    "o(b)",     0xbc050000, 0xfc1f0000, RD_b,                   0,               I3      },
644
{"dctw",    "o(b)",     0xbc090000, 0xfc1f0000, RD_b,                   0,               I3      },
645 158 khays
{"deret",   "",         0x4200001f, 0xffffffff, NODS,                   0,               I32|G2  },
646 18 khays
{"dext",    "t,r,I,+I", 0,    (int) M_DEXT,      INSN_MACRO,             0,               I65     },
647
{"dext",    "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s,             0,               I65     },
648
{"dextm",   "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s,             0,               I65     },
649
{"dextu",   "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s,             0,               I65     },
650
/* For ddiv, see the comments about div.  */
651
{"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,               I3      },
652
{"ddiv",    "d,v,t",    0,    (int) M_DDIV_3,    INSN_MACRO,             0,               I3      },
653
{"ddiv",    "d,v,I",    0,    (int) M_DDIV_3I,   INSN_MACRO,             0,               I3      },
654
/* For ddivu, see the comments about div.  */
655
{"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,               I3      },
656
{"ddivu",   "d,v,t",    0,    (int) M_DDIVU_3,   INSN_MACRO,             0,               I3      },
657
{"ddivu",   "d,v,I",    0,    (int) M_DDIVU_3I,  INSN_MACRO,             0,               I3      },
658
{"di",      "",         0x41606000, 0xffffffff, WR_t|WR_C0,             0,               I33|IOCT},
659
{"di",      "t",        0x41606000, 0xffe0ffff, WR_t|WR_C0,             0,               I33|IOCT},
660
{"dins",    "t,r,I,+I", 0,    (int) M_DINS,      INSN_MACRO,             0,               I65     },
661
{"dins",    "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s,             0,               I65     },
662
{"dinsm",   "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s,             0,               I65     },
663
{"dinsu",   "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s,             0,               I65     },
664
/* The MIPS assembler treats the div opcode with two operands as
665
   though the first operand appeared twice (the first operand is both
666
   a source and a destination).  To get the div machine instruction,
667
   you must use an explicit destination of $0.  */
668
{"div",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,               I1      },
669
{"div",     "z,t",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,               I1      },
670
{"div",     "d,v,t",    0,    (int) M_DIV_3,     INSN_MACRO,             0,               I1      },
671
{"div",     "d,v,I",    0,    (int) M_DIV_3I,    INSN_MACRO,             0,               I1      },
672
{"div.d",   "D,V,T",    0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               I1      },
673
{"div.s",   "D,V,T",    0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,               I1      },
674
{"div.ps",  "D,V,T",    0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               SB1     },
675
/* For divu, see the comments about div.  */
676
{"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,               I1      },
677
{"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,               I1      },
678
{"divu",    "d,v,t",    0,    (int) M_DIVU_3,    INSN_MACRO,             0,               I1      },
679
{"divu",    "d,v,I",    0,    (int) M_DIVU_3I,   INSN_MACRO,             0,               I1      },
680
{"dla",     "t,A(b)",   0,    (int) M_DLA_AB,    INSN_MACRO,             0,               I3      },
681
{"dlca",    "t,A(b)",   0,    (int) M_DLCA_AB,   INSN_MACRO,             0,               I3      },
682
{"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,                   0,               I3      }, /* addiu */
683
{"dli",     "t,i",      0x34000000, 0xffe00000, WR_t,                   0,               I3      }, /* ori */
684
{"dli",     "t,I",      0,    (int) M_DLI,       INSN_MACRO,             0,               I3      },
685
{"dmacc",   "d,s,t",    0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,               N412    },
686
{"dmacchi", "d,s,t",    0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,               N412    },
687
{"dmacchis", "d,s,t",   0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,               N412    },
688
{"dmacchiu", "d,s,t",   0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,               N412    },
689
{"dmacchius", "d,s,t",  0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,               N412    },
690
{"dmaccs",  "d,s,t",    0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,               N412    },
691
{"dmaccu",  "d,s,t",    0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,               N412    },
692
{"dmaccus", "d,s,t",    0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,               N412    },
693
{"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       0,               N411    },
694
{"dmfc0",   "t,G",      0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,         0,               I3|IOCT },
695
{"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,               I64|IOCT},
696
{"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,               I64|IOCT},
697
{"dmt",     "",         0x41600bc1, 0xffffffff, TRAP,                   0,               MT32    },
698
{"dmt",     "t",        0x41600bc1, 0xffe0ffff, TRAP|WR_t,              0,               MT32    },
699
{"dmtc0",   "t,G",      0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,               I3|IOCT },
700
{"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,               I64|IOCT},
701
{"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,               I64|IOCT},
702
{"dmfc1",   "t,S",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,               I3      },
703
{"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,               I3      },
704
{"dmtc1",   "t,S",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,               I3      },
705
{"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,               I3      },
706
/* dmfc2 is at the bottom of the table.  */
707
/* dmtc2 is at the bottom of the table.  */
708
/* dmfc3 is at the bottom of the table.  */
709
/* dmtc3 is at the bottom of the table.  */
710
{"dmul",    "d,v,t",    0x70000003, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,               IOCT    },
711
{"dmul",    "d,v,t",    0,    (int) M_DMUL,      INSN_MACRO,             0,               I3      },
712
{"dmul",    "d,v,I",    0,    (int) M_DMUL_I,    INSN_MACRO,             0,               I3      },
713
{"dmulo",   "d,v,t",    0,    (int) M_DMULO,     INSN_MACRO,             0,               I3      },
714
{"dmulo",   "d,v,I",    0,    (int) M_DMULO_I,   INSN_MACRO,             0,               I3      },
715
{"dmulou",  "d,v,t",    0,    (int) M_DMULOU,    INSN_MACRO,             0,               I3      },
716
{"dmulou",  "d,v,I",    0,    (int) M_DMULOU_I,  INSN_MACRO,             0,               I3      },
717
{"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,               I3      },
718
{"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,               I3      },
719
{"dneg",    "d,w",      0x0000002e, 0xffe007ff, WR_d|RD_t,              0,               I3      }, /* dsub 0 */
720
{"dnegu",   "d,w",      0x0000002f, 0xffe007ff, WR_d|RD_t,              0,               I3      }, /* dsubu 0*/
721
{"dpop",    "d,v",      0x7000002d, 0xfc1f07ff, WR_d|RD_s,              0,               IOCT    },
722
{"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,               I3      },
723
{"drem",    "d,v,t",    0,    (int) M_DREM_3,    INSN_MACRO,             0,               I3      },
724
{"drem",    "d,v,I",    0,    (int) M_DREM_3I,   INSN_MACRO,             0,               I3      },
725
{"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,               I3      },
726
{"dremu",   "d,v,t",    0,    (int) M_DREMU_3,   INSN_MACRO,             0,               I3      },
727
{"dremu",   "d,v,I",    0,    (int) M_DREMU_3I,  INSN_MACRO,             0,               I3      },
728
{"dret",    "",         0x7000003e, 0xffffffff, 0,                       0,               N5      },
729
{"drol",    "d,v,t",    0,    (int) M_DROL,      INSN_MACRO,             0,               I3      },
730
{"drol",    "d,v,I",    0,    (int) M_DROL_I,    INSN_MACRO,             0,               I3      },
731
{"dror",    "d,v,t",    0,    (int) M_DROR,      INSN_MACRO,             0,               I3      },
732
{"dror",    "d,v,I",    0,    (int) M_DROR_I,    INSN_MACRO,             0,               I3      },
733
{"dror",    "d,w,<",    0x0020003a, 0xffe0003f, WR_d|RD_t,              0,               N5|I65  },
734
{"drorv",   "d,t,s",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         0,               N5|I65  },
735
{"dror32",  "d,w,<",    0x0020003e, 0xffe0003f, WR_d|RD_t,              0,               N5|I65  },
736
{"drotl",   "d,v,t",    0,    (int) M_DROL,      INSN_MACRO,             0,               I65     },
737
{"drotl",   "d,v,I",    0,    (int) M_DROL_I,    INSN_MACRO,             0,               I65     },
738
{"drotr",   "d,v,t",    0,    (int) M_DROR,      INSN_MACRO,             0,               I65     },
739
{"drotr",   "d,v,I",    0,    (int) M_DROR_I,    INSN_MACRO,             0,               I65     },
740
{"drotrv",  "d,t,s",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         0,               I65     },
741
{"drotr32", "d,w,<",    0x0020003e, 0xffe0003f, WR_d|RD_t,              0,               I65     },
742
{"dsbh",    "d,w",      0x7c0000a4, 0xffe007ff, WR_d|RD_t,              0,               I65     },
743
{"dshd",    "d,w",      0x7c000164, 0xffe007ff, WR_d|RD_t,              0,               I65     },
744
{"dsllv",   "d,t,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         0,               I3      },
745
{"dsll32",  "d,w,<",    0x0000003c, 0xffe0003f, WR_d|RD_t,              0,               I3      },
746
{"dsll",    "d,w,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         0,               I3      }, /* dsllv */
747
{"dsll",    "d,w,>",    0x0000003c, 0xffe0003f, WR_d|RD_t,              0,               I3      }, /* dsll32 */
748
{"dsll",    "d,w,<",    0x00000038, 0xffe0003f, WR_d|RD_t,              0,               I3      },
749
{"dsll",        "D,S,T",        0x45a00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
750
{"dsll",        "D,S,T",        0x4b20000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
751
{"dsrav",   "d,t,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,               I3      },
752
{"dsra32",  "d,w,<",    0x0000003f, 0xffe0003f, WR_d|RD_t,              0,               I3      },
753
{"dsra",    "d,w,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,               I3      }, /* dsrav */
754
{"dsra",    "d,w,>",    0x0000003f, 0xffe0003f, WR_d|RD_t,              0,               I3      }, /* dsra32 */
755
{"dsra",    "d,w,<",    0x0000003b, 0xffe0003f, WR_d|RD_t,              0,               I3      },
756
{"dsra",        "D,S,T",        0x45e00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
757
{"dsra",        "D,S,T",        0x4b60000f,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
758
{"dsrlv",   "d,t,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,               I3      },
759
{"dsrl32",  "d,w,<",    0x0000003e, 0xffe0003f, WR_d|RD_t,              0,               I3      },
760
{"dsrl",    "d,w,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,               I3      }, /* dsrlv */
761
{"dsrl",    "d,w,>",    0x0000003e, 0xffe0003f, WR_d|RD_t,              0,               I3      }, /* dsrl32 */
762
{"dsrl",    "d,w,<",    0x0000003a, 0xffe0003f, WR_d|RD_t,              0,               I3      },
763
{"dsrl",        "D,S,T",        0x45a00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
764
{"dsrl",        "D,S,T",        0x4b20000f,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
765
{"dsub",    "d,v,t",    0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I3      },
766
{"dsub",    "d,v,I",    0,    (int) M_DSUB_I,    INSN_MACRO,             0,               I3      },
767
{"dsub",        "D,S,T",        0x45e00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
768
{"dsub",        "D,S,T",        0x4b60000d,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
769
{"dsubu",   "d,v,t",    0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I3      },
770
{"dsubu",   "d,v,I",    0,    (int) M_DSUBU_I,   INSN_MACRO,             0,               I3      },
771
{"dvpe",    "",         0x41600001, 0xffffffff, TRAP,                   0,               MT32    },
772
{"dvpe",    "t",        0x41600001, 0xffe0ffff, TRAP|WR_t,              0,               MT32    },
773
{"ei",      "",         0x41606020, 0xffffffff, WR_t|WR_C0,             0,               I33|IOCT},
774
{"ei",      "t",        0x41606020, 0xffe0ffff, WR_t|WR_C0,             0,               I33|IOCT},
775
{"emt",     "",         0x41600be1, 0xffffffff, TRAP,                   0,               MT32    },
776
{"emt",     "t",        0x41600be1, 0xffe0ffff, TRAP|WR_t,              0,               MT32    },
777 158 khays
{"eret",    "",         0x42000018, 0xffffffff, NODS,                   0,               I3_32   },
778 18 khays
{"evpe",    "",         0x41600021, 0xffffffff, TRAP,                   0,               MT32    },
779
{"evpe",    "t",        0x41600021, 0xffe0ffff, TRAP|WR_t,              0,               MT32    },
780
{"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,             0,               I33     },
781
{"exts32",  "t,r,+p,+S",0x7000003b, 0xfc00003f, WR_t|RD_s,              0,               IOCT    },
782
{"exts",    "t,r,+P,+S",0x7000003b, 0xfc00003f, WR_t|RD_s,              0,               IOCT    }, /* exts32 */
783
{"exts",    "t,r,+p,+s",0x7000003a, 0xfc00003f, WR_t|RD_s,              0,               IOCT    },
784
{"floor.l.d", "D,S",    0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,         0,               I3_33   },
785
{"floor.l.s", "D,S",    0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               I3_33   },
786
{"floor.w.d", "D,S",    0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               I2      },
787
{"floor.w.s", "D,S",    0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,         0,               I2      },
788
{"hibernate","",        0x42000023, 0xffffffff, 0,                       0,               V1      },
789
{"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,             0,               I33     },
790 158 khays
{"iret",    "",         0x42000038, 0xffffffff, NODS,                   0,               MC      },
791 18 khays
{"jr",      "s",        0x00000008, 0xfc1fffff, UBD|RD_s,               0,               I1      },
792
/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
793
   the same hazard barrier effect.  */
794
{"jr.hb",   "s",        0x00000408, 0xfc1fffff, UBD|RD_s,               0,               I32     },
795
{"j",       "s",        0x00000008, 0xfc1fffff, UBD|RD_s,               0,               I1      }, /* jr */
796
/* SVR4 PIC code requires special handling for j, so it must be a
797
   macro.  */
798
{"j",       "a",        0,     (int) M_J_A,      INSN_MACRO,             0,               I1      },
799
/* This form of j is used by the disassembler and internally by the
800
   assembler, but will never match user input (because the line above
801
   will match first).  */
802
{"j",       "a",        0x08000000, 0xfc000000, UBD,                    0,               I1      },
803
{"jalr",    "s",        0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d,          0,               I1      },
804
{"jalr",    "d,s",      0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d,          0,               I1      },
805
/* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
806
   with the same hazard barrier effect.  */
807
{"jalr.hb", "s",        0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d,          0,               I32     },
808
{"jalr.hb", "d,s",      0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d,          0,               I32     },
809
/* SVR4 PIC code requires special handling for jal, so it must be a
810
   macro.  */
811
{"jal",     "d,s",      0,     (int) M_JAL_2,    INSN_MACRO,             0,               I1      },
812
{"jal",     "s",        0,     (int) M_JAL_1,    INSN_MACRO,             0,               I1      },
813
{"jal",     "a",        0,     (int) M_JAL_A,    INSN_MACRO,             0,               I1      },
814
/* This form of jal is used by the disassembler and internally by the
815
   assembler, but will never match user input (because the line above
816
   will match first).  */
817
{"jal",     "a",        0x0c000000, 0xfc000000, UBD|WR_31,              0,               I1      },
818
{"jalx",    "a",        0x74000000, 0xfc000000, UBD|WR_31,              0,               I1      },
819
{"la",      "t,A(b)",   0,    (int) M_LA_AB,     INSN_MACRO,             0,               I1      },
820
{"lb",      "t,o(b)",   0x80000000, 0xfc000000, LDD|RD_b|WR_t,          0,               I1      },
821
{"lb",      "t,A(b)",   0,    (int) M_LB_AB,     INSN_MACRO,             0,               I1      },
822
{"lbu",     "t,o(b)",   0x90000000, 0xfc000000, LDD|RD_b|WR_t,          0,               I1      },
823
{"lbu",     "t,A(b)",   0,    (int) M_LBU_AB,    INSN_MACRO,             0,               I1      },
824
{"lca",     "t,A(b)",   0,    (int) M_LCA_AB,    INSN_MACRO,             0,               I1      },
825
/* The macro has to be first to handle o32 correctly.  */
826
{"ld",      "t,o(b)",   0,    (int) M_LD_OB,     INSN_MACRO,             0,               I1      },
827
{"ld",      "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,              0,               I3      },
828
{"ld",      "t,A(b)",   0,    (int) M_LD_AB,     INSN_MACRO,             0,               I1      },
829
{"ldaddw",  "t,b",      0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,               XLR     },
830
{"ldaddwu", "t,b",      0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,               XLR     },
831
{"ldaddd",  "t,b",      0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,               XLR     },
832
{"ldc1",    "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,               I2      },
833
{"ldc1",    "E,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,               I2      },
834
{"ldc1",    "T,A(b)",   0,    (int) M_LDC1_AB,   INSN_MACRO,             INSN2_M_FP_D,   I2      },
835
{"ldc1",    "E,A(b)",   0,    (int) M_LDC1_AB,   INSN_MACRO,             INSN2_M_FP_D,   I2      },
836
{"l.d",     "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,               I2      }, /* ldc1 */
837
{"l.d",     "T,o(b)",   0,    (int) M_L_DOB,     INSN_MACRO,             INSN2_M_FP_D,   I1      },
838
{"l.d",     "T,A(b)",   0,    (int) M_L_DAB,     INSN_MACRO,             INSN2_M_FP_D,   I1      },
839
{"ldc2",    "E,o(b)",   0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,               I2      },
840
{"ldc2",    "E,A(b)",   0,    (int) M_LDC2_AB,   INSN_MACRO,             0,               I2      },
841
{"ldc3",    "E,o(b)",   0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,               I2      },
842
{"ldc3",    "E,A(b)",   0,    (int) M_LDC3_AB,   INSN_MACRO,             0,               I2      },
843
{"ldl",     "t,o(b)",   0x68000000, 0xfc000000, LDD|WR_t|RD_b,          0,               I3      },
844
{"ldl",     "t,A(b)",   0,    (int) M_LDL_AB,    INSN_MACRO,             0,               I3      },
845
{"ldr",     "t,o(b)",   0x6c000000, 0xfc000000, LDD|WR_t|RD_b,          0,               I3      },
846
{"ldr",     "t,A(b)",   0,    (int) M_LDR_AB,    INSN_MACRO,             0,               I3      },
847
{"ldxc1",   "D,t(b)",   0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,              I4_33   },
848
{"lh",      "t,o(b)",   0x84000000, 0xfc000000, LDD|RD_b|WR_t,          0,               I1      },
849
{"lh",      "t,A(b)",   0,    (int) M_LH_AB,     INSN_MACRO,             0,               I1      },
850
{"lhu",     "t,o(b)",   0x94000000, 0xfc000000, LDD|RD_b|WR_t,          0,               I1      },
851
{"lhu",     "t,A(b)",   0,    (int) M_LHU_AB,    INSN_MACRO,             0,               I1      },
852
/* li is at the start of the table.  */
853
{"li.d",    "t,F",      0,    (int) M_LI_D,      INSN_MACRO,             INSN2_M_FP_D,   I1      },
854
{"li.d",    "T,L",      0,    (int) M_LI_DD,     INSN_MACRO,             INSN2_M_FP_D,   I1      },
855
{"li.s",    "t,f",      0,    (int) M_LI_S,      INSN_MACRO,             INSN2_M_FP_S,   I1      },
856
{"li.s",    "T,l",      0,    (int) M_LI_SS,     INSN_MACRO,             INSN2_M_FP_S,   I1      },
857
{"ll",      "t,o(b)",   0xc0000000, 0xfc000000, LDD|RD_b|WR_t,          0,               I2      },
858
{"ll",      "t,A(b)",   0,    (int) M_LL_AB,     INSN_MACRO,             0,               I2      },
859
{"lld",     "t,o(b)",   0xd0000000, 0xfc000000, LDD|RD_b|WR_t,          0,               I3      },
860
{"lld",     "t,A(b)",   0,    (int) M_LLD_AB,    INSN_MACRO,             0,               I3      },
861
{"lui",     "t,u",      0x3c000000, 0xffe00000, WR_t,                   0,               I1      },
862
{"luxc1",   "D,t(b)",   0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,              I5_33|N55},
863
{"lw",      "t,o(b)",   0x8c000000, 0xfc000000, LDD|RD_b|WR_t,          0,               I1      },
864
{"lw",      "t,A(b)",   0,    (int) M_LW_AB,     INSN_MACRO,             0,               I1      },
865
{"lwc0",    "E,o(b)",   0xc0000000, 0xfc000000, CLD|RD_b|WR_CC,         0,               I1      },
866
{"lwc0",    "E,A(b)",   0,    (int) M_LWC0_AB,   INSN_MACRO,             0,               I1      },
867
{"lwc1",    "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,               I1      },
868
{"lwc1",    "E,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,               I1      },
869
{"lwc1",    "T,A(b)",   0,    (int) M_LWC1_AB,   INSN_MACRO,             INSN2_M_FP_S,   I1      },
870
{"lwc1",    "E,A(b)",   0,    (int) M_LWC1_AB,   INSN_MACRO,             INSN2_M_FP_S,   I1      },
871
{"l.s",     "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,               I1      }, /* lwc1 */
872
{"l.s",     "T,A(b)",   0,    (int) M_LWC1_AB,   INSN_MACRO,             INSN2_M_FP_S,   I1      },
873
{"lwc2",    "E,o(b)",   0xc8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,               I1      },
874
{"lwc2",    "E,A(b)",   0,    (int) M_LWC2_AB,   INSN_MACRO,             0,               I1      },
875
{"lwc3",    "E,o(b)",   0xcc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,               I1      },
876
{"lwc3",    "E,A(b)",   0,    (int) M_LWC3_AB,   INSN_MACRO,             0,               I1      },
877
{"lwl",     "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,               I1      },
878
{"lwl",     "t,A(b)",   0,    (int) M_LWL_AB,    INSN_MACRO,             0,               I1      },
879
{"lcache",  "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,               I2      }, /* same */
880
{"lcache",  "t,A(b)",   0,    (int) M_LWL_AB,    INSN_MACRO,             0,               I2      }, /* as lwl */
881
{"lwr",     "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t,          0,               I1      },
882
{"lwr",     "t,A(b)",   0,    (int) M_LWR_AB,    INSN_MACRO,             0,               I1      },
883
{"flush",   "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t,          0,               I2      }, /* same */
884
{"flush",   "t,A(b)",   0,    (int) M_LWR_AB,    INSN_MACRO,             0,               I2      }, /* as lwr */
885
{"fork",    "d,s,t",    0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t,    0,               MT32    },
886
{"lwu",     "t,o(b)",   0x9c000000, 0xfc000000, LDD|RD_b|WR_t,          0,               I3      },
887
{"lwu",     "t,A(b)",   0,    (int) M_LWU_AB,    INSN_MACRO,             0,               I3      },
888
{"lwxc1",   "D,t(b)",   0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_S, 0,              I4_33   },
889
{"lwxs",    "d,t(b)",   0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d,     0,               SMT     },
890
{"macc",    "d,s,t",    0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N412    },
891
{"macc",    "d,s,t",    0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N5      },
892
{"maccs",   "d,s,t",    0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N412    },
893
{"macchi",  "d,s,t",    0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N412    },
894
{"macchi",  "d,s,t",    0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N5      },
895
{"macchis", "d,s,t",    0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N412    },
896
{"macchiu", "d,s,t",    0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N412    },
897
{"macchiu", "d,s,t",    0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N5      },
898
{"macchius","d,s,t",    0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N412    },
899
{"maccu",   "d,s,t",    0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N412    },
900
{"maccu",   "d,s,t",    0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N5      },
901
{"maccus",  "d,s,t",    0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N412    },
902
{"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,               P3      },
903
{"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,               P3      },
904
{"madd.d",  "D,R,S,T",  0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,          I4_33   },
905
{"madd.d",      "D,S,T",        0x46200018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
906
{"madd.d",      "D,S,T",        0x72200018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F    },
907
{"madd.s",  "D,R,S,T",  0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,          I4_33   },
908
{"madd.s",      "D,S,T",        0x46000018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2E    },
909
{"madd.s",      "D,S,T",        0x72000018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2F    },
910
{"madd.ps", "D,R,S,T",  0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,          I5_33   },
911
{"madd.ps",     "D,S,T",        0x45600018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
912
{"madd.ps",     "D,S,T",        0x71600018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F    },
913
{"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,          L1      },
914
{"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,          I32|N55 },
915
{"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,          G1      },
916
{"madd",    "7,s,t",    0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D32      },
917
{"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,          G1      },
918
{"maddp",   "s,t",      0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,          SMT     },
919
{"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,          L1      },
920
{"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,          I32|N55 },
921
{"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,          G1      },
922
{"maddu",   "7,s,t",    0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D32      },
923
{"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,          G1      },
924
{"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,               N411    },
925
{"max.ob",  "X,Y,Q",    0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX|SB1  },
926
{"max.ob",  "D,S,T",    0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
927
{"max.ob",  "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T,         0,               N54     },
928
{"max.ob",  "D,S,k",    0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
929
{"max.qh",  "X,Y,Q",    0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },
930
{"mfpc",    "t,P",      0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0,         0,               M1|N5   },
931
{"mfps",    "t,P",      0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0,         0,               M1|N5   },
932
{"mftacx",  "d",        0x41020021, 0xffff07ff, TRAP|WR_d|RD_a,         0,               MT32    },
933
{"mftacx",  "d,*",      0x41020021, 0xfff307ff, TRAP|WR_d|RD_a,         0,               MT32    },
934
{"mftc0",   "d,+t",     0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0,    0,               MT32    },
935
{"mftc0",   "d,+T",     0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,               MT32    },
936
{"mftc0",   "d,E,H",    0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,               MT32    },
937
{"mftc1",   "d,T",      0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,              MT32    },
938
{"mftc1",   "d,E",      0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,              MT32    },
939
{"mftc2",   "d,E",      0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,               MT32    },
940
{"mftdsp",  "d",        0x41100021, 0xffff07ff, TRAP|WR_d,              0,               MT32    },
941
{"mftgpr",  "d,t",      0x41000020, 0xffe007ff, TRAP|WR_d|RD_t,         0,               MT32    },
942
{"mfthc1",  "d,T",      0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,              MT32    },
943
{"mfthc1",  "d,E",      0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,              MT32    },
944
{"mfthc2",  "d,E",      0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,               MT32    },
945
{"mfthi",   "d",        0x41010021, 0xffff07ff, TRAP|WR_d|RD_a,         0,               MT32    },
946
{"mfthi",   "d,*",      0x41010021, 0xfff307ff, TRAP|WR_d|RD_a,         0,               MT32    },
947
{"mftlo",   "d",        0x41000021, 0xffff07ff, TRAP|WR_d|RD_a,         0,               MT32    },
948
{"mftlo",   "d,*",      0x41000021, 0xfff307ff, TRAP|WR_d|RD_a,         0,               MT32    },
949
{"mftr",    "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d,             0,               MT32    },
950
{"mfc0",    "t,G",      0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         0,               I1|IOCT },
951
{"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,               I32|IOCT},
952
{"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,               I32|IOCT},
953
{"mfc1",    "t,S",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,               I1      },
954
{"mfc1",    "t,G",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,               I1      },
955
{"mfhc1",   "t,S",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,               I33     },
956
{"mfhc1",   "t,G",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,               I33     },
957
/* mfc2 is at the bottom of the table.  */
958
/* mfhc2 is at the bottom of the table.  */
959
/* mfc3 is at the bottom of the table.  */
960
{"mfdr",    "t,G",      0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0,         0,               N5      },
961
{"mfhi",    "d",        0x00000010, 0xffff07ff, WR_d|RD_HI,             0,               I1      },
962
{"mfhi",    "d,9",      0x00000010, 0xff9f07ff, WR_d|RD_HI,             0,               D32     },
963
{"mflo",    "d",        0x00000012, 0xffff07ff, WR_d|RD_LO,             0,               I1      },
964
{"mflo",    "d,9",      0x00000012, 0xff9f07ff, WR_d|RD_LO,             0,               D32     },
965
{"mflhxu",  "d",        0x00000052, 0xffff07ff, WR_d|MOD_HILO,          0,               SMT     },
966
{"mfcr",    "t,s",      0x70000018, 0xfc00ffff, WR_t,                   0,               XLR     },
967
{"min.ob",  "X,Y,Q",    0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX|SB1  },
968
{"min.ob",  "D,S,T",    0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
969
{"min.ob",  "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T,         0,               N54     },
970
{"min.ob",  "D,S,k",    0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
971
{"min.qh",  "X,Y,Q",    0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },
972
{"mov.d",   "D,S",      0x46200006, 0xffff003f, WR_D|RD_S|FP_D,         0,               I1      },
973
{"mov.s",   "D,S",      0x46000006, 0xffff003f, WR_D|RD_S|FP_S,         0,               I1      },
974
{"mov.ps",  "D,S",      0x46c00006, 0xffff003f, WR_D|RD_S|FP_D,         0,               I5_33|IL2F      },
975
{"mov.ps",  "D,S",      0x45600006, 0xffff003f, WR_D|RD_S|FP_D,         0,               IL2E    },
976
{"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,            I4_32  },
977
{"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,               I4_32   },
978
{"movf.l",  "D,S,N",    0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,               MX|SB1  },
979
{"movf.l",  "X,Y,N",    0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,               MX|SB1  },
980
{"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,               I4_32   },
981
{"movf.ps", "D,S,N",    0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,               I5_33   },
982
{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I4_32|IL2E|IL2F },
983
{"movnz",   "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               IL2E|IL2F|IL3A  },
984
{"ffc",     "d,v",      0x0000000b, 0xfc1f07ff, WR_d|RD_s,              0,               L1      },
985
{"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,               I4_32   },
986
{"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,               MX|SB1  },
987
{"movn.l",  "X,Y,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,               MX|SB1  },
988
{"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,               I4_32   },
989
{"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,               I5_33   },
990
{"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,            I4_32   },
991
{"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,               I4_32   },
992
{"movt.l",  "D,S,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,               MX|SB1  },
993
{"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,               MX|SB1  },
994
{"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,               I4_32   },
995
{"movt.ps", "D,S,N",    0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,               I5_33   },
996
{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I4_32|IL2E|IL2F },
997
{"ffs",     "d,v",      0x0000000a, 0xfc1f07ff, WR_d|RD_s,              0,               L1      },
998
{"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,               I4_32   },
999
{"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,               MX|SB1  },
1000
{"movz.l",  "X,Y,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,               MX|SB1  },
1001
{"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,               I4_32   },
1002
{"movz.ps", "D,S,t",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,               I5_33   },
1003
{"msac",    "d,s,t",    0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N5      },
1004
{"msacu",   "d,s,t",    0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N5      },
1005
{"msachi",  "d,s,t",    0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N5      },
1006
{"msachiu", "d,s,t",    0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N5      },
1007
/* move is at the top of the table.  */
1008
{"msgn.qh", "X,Y,Q",    0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },
1009
{"msgsnd",  "t",        0,    (int) M_MSGSND,    INSN_MACRO,             0,             XLR       },
1010
{"msgld",   "",         0,    (int) M_MSGLD,     INSN_MACRO,             0,             XLR       },
1011
{"msgld",   "t",        0,    (int) M_MSGLD_T,   INSN_MACRO,             0,             XLR       },
1012
{"msgwait", "",         0,    (int) M_MSGWAIT,   INSN_MACRO,             0,             XLR       },
1013
{"msgwait", "t",        0,    (int) M_MSGWAIT_T,INSN_MACRO,              0,             XLR       },
1014
{"msub.d",  "D,R,S,T",  0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,             I4_33   },
1015
{"msub.d",      "D,S,T",        0x46200019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1016
{"msub.d",      "D,S,T",        0x72200019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F    },
1017
{"msub.s",  "D,R,S,T",  0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,             I4_33   },
1018
{"msub.s",      "D,S,T",        0x46000019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2E    },
1019
{"msub.s",      "D,S,T",        0x72000019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2F    },
1020
{"msub.ps", "D,R,S,T",  0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,             I5_33   },
1021
{"msub.ps",     "D,S,T",        0x45600019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1022
{"msub.ps",     "D,S,T",        0x71600019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F    },
1023
{"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,               L1      },
1024
{"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,               I32|N55 },
1025
{"msub",    "7,s,t",    0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32      },
1026
{"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,               L1      },
1027
{"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,               I32|N55 },
1028
{"msubu",   "7,s,t",    0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32      },
1029
{"mtpc",    "t,P",      0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0,         0,               M1|N5   },
1030
{"mtps",    "t,P",      0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0,         0,               M1|N5   },
1031
{"mtc0",    "t,G",      0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,               I1|IOCT },
1032
{"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,               I32|IOCT},
1033
{"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,               I32|IOCT},
1034
{"mtc1",    "t,S",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,               I1      },
1035
{"mtc1",    "t,G",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,               I1      },
1036
{"mthc1",   "t,S",      0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,               I33     },
1037
{"mthc1",   "t,G",      0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,               I33     },
1038
/* mtc2 is at the bottom of the table.  */
1039
/* mthc2 is at the bottom of the table.  */
1040
/* mtc3 is at the bottom of the table.  */
1041
{"mtdr",    "t,G",      0x7080003d, 0xffe007ff, COD|RD_t|WR_C0,         0,               N5      },
1042
{"mthi",    "s",        0x00000011, 0xfc1fffff, RD_s|WR_HI,             0,               I1      },
1043
{"mthi",    "s,7",      0x00000011, 0xfc1fe7ff, RD_s|WR_HI,             0,               D32     },
1044
{"mtlo",    "s",        0x00000013, 0xfc1fffff, RD_s|WR_LO,             0,               I1      },
1045
{"mtlo",    "s,7",      0x00000013, 0xfc1fe7ff, RD_s|WR_LO,             0,               D32     },
1046
{"mtlhx",   "s",        0x00000053, 0xfc1fffff, RD_s|MOD_HILO,          0,               SMT     },
1047
{"mtcr",    "t,s",      0x70000019, 0xfc00ffff, RD_t,                   0,               XLR     },
1048
{"mtm0",    "s",        0x70000008, 0xfc1fffff, RD_s,                   0,               IOCT    },
1049
{"mtm1",    "s",        0x7000000c, 0xfc1fffff, RD_s,                   0,               IOCT    },
1050
{"mtm2",    "s",        0x7000000d, 0xfc1fffff, RD_s,                   0,               IOCT    },
1051
{"mtp0",    "s",        0x70000009, 0xfc1fffff, RD_s,                   0,               IOCT    },
1052
{"mtp1",    "s",        0x7000000a, 0xfc1fffff, RD_s,                   0,               IOCT    },
1053
{"mtp2",    "s",        0x7000000b, 0xfc1fffff, RD_s,                   0,               IOCT    },
1054
{"mttc0",   "t,G",      0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0,            MT32    },
1055
{"mttc0",   "t,+D",     0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,            MT32    },
1056
{"mttc0",   "t,G,H",    0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,            MT32    },
1057
{"mttc1",   "t,S",      0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,              MT32    },
1058
{"mttc1",   "t,G",      0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,              MT32    },
1059
{"mttc2",   "t,g",      0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,            MT32    },
1060
{"mttacx",  "t",        0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,               MT32    },
1061
{"mttacx",  "t,&",      0x41801021, 0xffe09fff, TRAP|WR_a|RD_t,         0,               MT32    },
1062
{"mttdsp",  "t",        0x41808021, 0xffe0ffff, TRAP|RD_t,              0,               MT32    },
1063
{"mttgpr",  "t,d",      0x41800020, 0xffe007ff, TRAP|WR_d|RD_t,         0,               MT32    },
1064
{"mtthc1",  "t,S",      0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,              MT32    },
1065
{"mtthc1",  "t,G",      0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,              MT32    },
1066
{"mtthc2",  "t,g",      0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,            MT32    },
1067
{"mtthi",   "t",        0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t,         0,               MT32    },
1068
{"mtthi",   "t,&",      0x41800821, 0xffe09fff, TRAP|WR_a|RD_t,         0,               MT32    },
1069
{"mttlo",   "t",        0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,               MT32    },
1070
{"mttlo",   "t,&",      0x41800021, 0xffe09fff, TRAP|WR_a|RD_t,         0,               MT32    },
1071
{"mttr",    "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t,             0,               MT32    },
1072
{"mul.d",   "D,V,T",    0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               I1      },
1073
{"mul.s",   "D,V,T",    0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,               I1      },
1074
{"mul.ob",  "X,Y,Q",    0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX|SB1  },
1075
{"mul.ob",  "D,S,T",    0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
1076
{"mul.ob",  "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T,         0,               N54     },
1077
{"mul.ob",  "D,S,k",    0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
1078
{"mul.ps",  "D,V,T",    0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               I5_33|IL2F      },
1079
{"mul.ps",  "D,V,T",    0x45600002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               IL2E    },
1080
{"mul.qh",  "X,Y,Q",    0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },
1081
{"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,               I32|P3|N55},
1082
{"mul",     "d,s,t",    0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N54     },
1083
{"mul",     "d,v,t",    0,    (int) M_MUL,       INSN_MACRO,             0,               I1      },
1084
{"mul",     "d,v,I",    0,    (int) M_MUL_I,     INSN_MACRO,             0,               I1      },
1085
{"mula.ob", "Y,Q",      0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1086
{"mula.ob", "S,T",      0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T,        0,               N54     },
1087
{"mula.ob", "S,T[e]",   0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,               N54     },
1088
{"mula.ob", "S,k",      0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T,        0,               N54     },
1089
{"mula.qh", "Y,Q",      0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1090
{"mulhi",   "d,s,t",    0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N5      },
1091
{"mulhiu",  "d,s,t",    0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N5      },
1092
{"mull.ob", "Y,Q",      0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1093
{"mull.ob", "S,T",      0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T,        0,               N54     },
1094
{"mull.ob", "S,T[e]",   0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,               N54     },
1095
{"mull.ob", "S,k",      0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T,        0,               N54     },
1096
{"mull.qh", "Y,Q",      0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1097
{"mulo",    "d,v,t",    0,    (int) M_MULO,      INSN_MACRO,             0,               I1      },
1098
{"mulo",    "d,v,I",    0,    (int) M_MULO_I,    INSN_MACRO,             0,               I1      },
1099
{"mulou",   "d,v,t",    0,    (int) M_MULOU,     INSN_MACRO,             0,               I1      },
1100
{"mulou",   "d,v,I",    0,    (int) M_MULOU_I,   INSN_MACRO,             0,               I1      },
1101
{"mulr.ps", "D,S,T",    0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               M3D     },
1102
{"muls",    "d,s,t",    0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N5      },
1103
{"mulsu",   "d,s,t",    0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N5      },
1104
{"mulshi",  "d,s,t",    0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N5      },
1105
{"mulshiu", "d,s,t",    0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N5      },
1106
{"muls.ob", "Y,Q",      0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1107
{"muls.ob", "S,T",      0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T,        0,               N54     },
1108
{"muls.ob", "S,T[e]",   0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,               N54     },
1109
{"muls.ob", "S,k",      0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T,        0,               N54     },
1110
{"muls.qh", "Y,Q",      0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1111
{"mulsl.ob", "Y,Q",     0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1112
{"mulsl.ob", "S,T",     0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T,        0,               N54     },
1113
{"mulsl.ob", "S,T[e]",  0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,               N54     },
1114
{"mulsl.ob", "S,k",     0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T,        0,               N54     },
1115
{"mulsl.qh", "Y,Q",     0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1116
{"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,               I1      },
1117
{"mult",    "7,s,t",    0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D32      },
1118
{"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,          G1      },
1119
{"multp",   "s,t",      0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,               SMT     },
1120
{"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,               I1      },
1121
{"multu",   "7,s,t",    0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D32      },
1122
{"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,          G1      },
1123
{"mulu",    "d,s,t",    0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,               N5      },
1124
{"neg",     "d,w",      0x00000022, 0xffe007ff, WR_d|RD_t,              0,               I1      }, /* sub 0 */
1125
{"negu",    "d,w",      0x00000023, 0xffe007ff, WR_d|RD_t,              0,               I1      }, /* subu 0 */
1126
{"neg.d",   "D,V",      0x46200007, 0xffff003f, WR_D|RD_S|FP_D,         0,               I1      },
1127
{"neg.s",   "D,V",      0x46000007, 0xffff003f, WR_D|RD_S|FP_S,         0,               I1      },
1128
{"neg.ps",  "D,V",      0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,         0,               I5_33|IL2F      },
1129
{"neg.ps",  "D,V",      0x45600007, 0xffff003f, WR_D|RD_S|FP_D,         0,               IL2E    },
1130
{"nmadd.d", "D,R,S,T",  0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,             I4_33   },
1131
{"nmadd.d",     "D,S,T",        0x4620001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1132
{"nmadd.d",     "D,S,T",        0x7220001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F    },
1133
{"nmadd.s", "D,R,S,T",  0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,             I4_33   },
1134
{"nmadd.s",     "D,S,T",        0x4600001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2E    },
1135
{"nmadd.s",     "D,S,T",        0x7200001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2F    },
1136
{"nmadd.ps","D,R,S,T",  0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,             I5_33   },
1137
{"nmadd.ps",    "D,S,T",        0x4560001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1138
{"nmadd.ps",    "D,S,T",        0x7160001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F    },
1139
{"nmsub.d", "D,R,S,T",  0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,             I4_33   },
1140
{"nmsub.d",     "D,S,T",        0x4620001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1141
{"nmsub.d",     "D,S,T",        0x7220001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F    },
1142
{"nmsub.s", "D,R,S,T",  0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,             I4_33   },
1143
{"nmsub.s",     "D,S,T",        0x4600001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2E    },
1144
{"nmsub.s",     "D,S,T",        0x7200001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2F    },
1145
{"nmsub.ps","D,R,S,T",  0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,             I5_33   },
1146
{"nmsub.ps",    "D,S,T",        0x4560001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1147
{"nmsub.ps",    "D,S,T",        0x7160001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F    },
1148
/* nop is at the start of the table.  */
1149
{"nor",     "d,v,t",    0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I1      },
1150
{"nor",     "t,r,I",    0,    (int) M_NOR_I,     INSN_MACRO,             0,               I1      },
1151
{"nor", "D,S,T",        0x47a00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1152
{"nor", "D,S,T",        0x4ba00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1153
{"nor.ob",  "X,Y,Q",    0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX|SB1  },
1154
{"nor.ob",  "D,S,T",    0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
1155
{"nor.ob",  "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T,         0,               N54     },
1156
{"nor.ob",  "D,S,k",    0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
1157
{"nor.qh",  "X,Y,Q",    0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },
1158
{"not",     "d,v",      0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t,         0,               I1      },/*nor d,s,0*/
1159
{"or",      "d,v,t",    0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I1      },
1160
{"or",      "t,r,I",    0,    (int) M_OR_I,      INSN_MACRO,             0,               I1      },
1161
{"or",  "D,S,T",        0x45a00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1162
{"or",  "D,S,T",        0x4b20000c,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1163
{"or.ob",   "X,Y,Q",    0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX|SB1  },
1164
{"or.ob",   "D,S,T",    0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
1165
{"or.ob",   "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T,         0,               N54     },
1166
{"or.ob",   "D,S,k",    0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
1167
{"or.qh",   "X,Y,Q",    0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },
1168
{"ori",     "t,r,i",    0x34000000, 0xfc000000, WR_t|RD_s,              0,               I1      },
1169
{"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               SB1     },
1170
{"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        SB1     },
1171
{"pavg.ob", "X,Y,Q",    0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               SB1     },
1172
{"pickf.ob", "X,Y,Q",   0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX|SB1  },
1173
{"pickf.ob", "D,S,T",   0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
1174
{"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T,         0,               N54     },
1175
{"pickf.ob", "D,S,k",   0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
1176
{"pickf.qh", "X,Y,Q",   0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },
1177
{"pickt.ob", "X,Y,Q",   0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX|SB1  },
1178
{"pickt.ob", "D,S,T",   0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
1179
{"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T,         0,               N54     },
1180
{"pickt.ob", "D,S,k",   0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
1181
{"pickt.qh", "X,Y,Q",   0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },
1182
{"pll.ps",  "D,V,T",    0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               I5_33   },
1183
{"plu.ps",  "D,V,T",    0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               I5_33   },
1184
{"pop",     "d,v",      0x7000002c, 0xfc1f07ff, WR_d|RD_s,              0,               IOCT    },
1185
  /* pref and prefx are at the start of the table.  */
1186
{"pul.ps",  "D,V,T",    0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               I5_33   },
1187
{"puu.ps",  "D,V,T",    0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               I5_33   },
1188
{"pperm",   "s,t",      0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t,     0,               SMT     },
1189
{"rach.ob", "X",        0x7a00003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
1190
{"rach.ob", "D",        0x4a00003f, 0xfffff83f, WR_D,                   0,               N54     },
1191
{"rach.qh", "X",        0x7a20003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
1192
{"racl.ob", "X",        0x7800003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
1193
{"racl.ob", "D",        0x4800003f, 0xfffff83f, WR_D,                   0,               N54     },
1194
{"racl.qh", "X",        0x7820003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
1195
{"racm.ob", "X",        0x7900003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
1196
{"racm.ob", "D",        0x4900003f, 0xfffff83f, WR_D,                   0,               N54     },
1197
{"racm.qh", "X",        0x7920003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
1198
{"recip.d", "D,S",      0x46200015, 0xffff003f, WR_D|RD_S|FP_D,         0,               I4_33   },
1199
{"recip.ps","D,S",      0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,         0,               SB1     },
1200
{"recip.s", "D,S",      0x46000015, 0xffff003f, WR_D|RD_S|FP_S,         0,               I4_33   },
1201
{"recip1.d",  "D,S",    0x4620001d, 0xffff003f, WR_D|RD_S|FP_D,         0,               M3D     },
1202
{"recip1.ps", "D,S",    0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S,         0,               M3D     },
1203
{"recip1.s",  "D,S",    0x4600001d, 0xffff003f, WR_D|RD_S|FP_S,         0,               M3D     },
1204
{"recip2.d",  "D,S,T",  0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               M3D     },
1205
{"recip2.ps", "D,S,T",  0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,               M3D     },
1206
{"recip2.s",  "D,S,T",  0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,               M3D     },
1207
{"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,               I1      },
1208
{"rem",     "d,v,t",    0,    (int) M_REM_3,     INSN_MACRO,             0,               I1      },
1209
{"rem",     "d,v,I",    0,    (int) M_REM_3I,    INSN_MACRO,             0,               I1      },
1210
{"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,               I1      },
1211
{"remu",    "d,v,t",    0,    (int) M_REMU_3,    INSN_MACRO,             0,               I1      },
1212
{"remu",    "d,v,I",    0,    (int) M_REMU_3I,   INSN_MACRO,             0,               I1      },
1213
{"rdhwr",   "t,K",      0x7c00003b, 0xffe007ff, WR_t,                   0,               I33     },
1214
{"rdpgpr",  "d,w",      0x41400000, 0xffe007ff, WR_d,                   0,               I33     },
1215
{"rfe",     "",         0x42000010, 0xffffffff, 0,                       0,               I1|T3   },
1216
{"rnas.qh", "X,Q",      0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
1217
{"rnau.ob", "X,Q",      0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
1218
{"rnau.qh", "X,Q",      0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
1219
{"rnes.qh", "X,Q",      0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
1220
{"rneu.ob", "X,Q",      0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
1221
{"rneu.qh", "X,Q",      0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
1222
{"rol",     "d,v,t",    0,    (int) M_ROL,       INSN_MACRO,             0,               I1      },
1223
{"rol",     "d,v,I",    0,    (int) M_ROL_I,     INSN_MACRO,             0,               I1      },
1224
{"ror",     "d,v,t",    0,    (int) M_ROR,       INSN_MACRO,             0,               I1      },
1225
{"ror",     "d,v,I",    0,    (int) M_ROR_I,     INSN_MACRO,             0,               I1      },
1226
{"ror",     "d,w,<",    0x00200002, 0xffe0003f, WR_d|RD_t,              0,               N5|I33|SMT },
1227
{"rorv",    "d,t,s",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,               N5|I33|SMT },
1228
{"rotl",    "d,v,t",    0,    (int) M_ROL,       INSN_MACRO,             0,               I33|SMT },
1229
{"rotl",    "d,v,I",    0,    (int) M_ROL_I,     INSN_MACRO,             0,               I33|SMT },
1230
{"rotr",    "d,v,t",    0,    (int) M_ROR,       INSN_MACRO,             0,               I33|SMT },
1231
{"rotr",    "d,v,I",    0,    (int) M_ROR_I,     INSN_MACRO,             0,               I33|SMT },
1232
{"rotrv",   "d,t,s",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,               I33|SMT },
1233
{"round.l.d", "D,S",    0x46200008, 0xffff003f, WR_D|RD_S|FP_D,         0,               I3_33   },
1234
{"round.l.s", "D,S",    0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               I3_33   },
1235
{"round.w.d", "D,S",    0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               I2      },
1236
{"round.w.s", "D,S",    0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,         0,               I2      },
1237
{"rsqrt.d", "D,S",      0x46200016, 0xffff003f, WR_D|RD_S|FP_D,         0,               I4_33   },
1238
{"rsqrt.ps","D,S",      0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,         0,               SB1     },
1239
{"rsqrt.s", "D,S",      0x46000016, 0xffff003f, WR_D|RD_S|FP_S,         0,               I4_33   },
1240
{"rsqrt1.d",  "D,S",    0x4620001e, 0xffff003f, WR_D|RD_S|FP_D,         0,               M3D     },
1241
{"rsqrt1.ps", "D,S",    0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S,         0,               M3D     },
1242
{"rsqrt1.s",  "D,S",    0x4600001e, 0xffff003f, WR_D|RD_S|FP_S,         0,               M3D     },
1243
{"rsqrt2.d",  "D,S,T",  0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               M3D     },
1244
{"rsqrt2.ps", "D,S,T",  0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,               M3D     },
1245
{"rsqrt2.s",  "D,S,T",  0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,               M3D     },
1246
{"rzs.qh",  "X,Q",      0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
1247
{"rzu.ob",  "X,Q",      0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
1248
{"rzu.ob",  "D,k",      0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T,         0,               N54     },
1249
{"rzu.qh",  "X,Q",      0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
1250
{"sb",      "t,o(b)",   0xa0000000, 0xfc000000, SM|RD_t|RD_b,           0,               I1      },
1251
{"sb",      "t,A(b)",   0,    (int) M_SB_AB,     INSN_MACRO,             0,               I1      },
1252
{"sc",      "t,o(b)",   0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,               I2      },
1253
{"sc",      "t,A(b)",   0,    (int) M_SC_AB,     INSN_MACRO,             0,               I2      },
1254
{"scd",     "t,o(b)",   0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,               I3      },
1255
{"scd",     "t,A(b)",   0,    (int) M_SCD_AB,    INSN_MACRO,             0,               I3      },
1256
/* The macro has to be first to handle o32 correctly.  */
1257
{"sd",      "t,o(b)",   0,    (int) M_SD_OB,     INSN_MACRO,             0,               I1      },
1258
{"sd",      "t,o(b)",   0xfc000000, 0xfc000000, SM|RD_t|RD_b,           0,               I3      },
1259
{"sd",      "t,A(b)",   0,    (int) M_SD_AB,     INSN_MACRO,             0,               I1      },
1260
{"sdbbp",   "",         0x0000000e, 0xffffffff, TRAP,                   0,               G2      },
1261
{"sdbbp",   "c",        0x0000000e, 0xfc00ffff, TRAP,                   0,               G2      },
1262
{"sdbbp",   "c,q",      0x0000000e, 0xfc00003f, TRAP,                   0,               G2      },
1263
{"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,                   0,               I32     },
1264
{"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,                   0,               I32     },
1265
{"sdc1",    "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,               I2      },
1266
{"sdc1",    "E,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,               I2      },
1267
{"sdc1",    "T,A(b)",   0,    (int) M_SDC1_AB,   INSN_MACRO,             INSN2_M_FP_D,   I2      },
1268
{"sdc1",    "E,A(b)",   0,    (int) M_SDC1_AB,   INSN_MACRO,             INSN2_M_FP_D,   I2      },
1269
{"sdc2",    "E,o(b)",   0xf8000000, 0xfc000000, SM|RD_C2|RD_b,          0,               I2      },
1270
{"sdc2",    "E,A(b)",   0,    (int) M_SDC2_AB,   INSN_MACRO,             0,               I2      },
1271
{"sdc3",    "E,o(b)",   0xfc000000, 0xfc000000, SM|RD_C3|RD_b,          0,               I2      },
1272
{"sdc3",    "E,A(b)",   0,    (int) M_SDC3_AB,   INSN_MACRO,             0,               I2      },
1273
{"s.d",     "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,               I2      },
1274
{"s.d",     "T,o(b)",   0,    (int) M_S_DOB,     INSN_MACRO,             INSN2_M_FP_D,   I1      },
1275
{"s.d",     "T,A(b)",   0,    (int) M_S_DAB,     INSN_MACRO,             INSN2_M_FP_D,   I1      },
1276
{"sdl",     "t,o(b)",   0xb0000000, 0xfc000000, SM|RD_t|RD_b,           0,               I3      },
1277
{"sdl",     "t,A(b)",   0,    (int) M_SDL_AB,    INSN_MACRO,             0,               I3      },
1278
{"sdr",     "t,o(b)",   0xb4000000, 0xfc000000, SM|RD_t|RD_b,           0,               I3      },
1279
{"sdr",     "t,A(b)",   0,    (int) M_SDR_AB,    INSN_MACRO,             0,               I3      },
1280
{"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0,               I4_33   },
1281
{"seb",     "d,w",      0x7c000420, 0xffe007ff, WR_d|RD_t,              0,               I33     },
1282
{"seh",     "d,w",      0x7c000620, 0xffe007ff, WR_d|RD_t,              0,               I33     },
1283
{"selsl",   "d,v,t",    0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               L1      },
1284
{"selsr",   "d,v,t",    0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               L1      },
1285
{"seq",     "d,v,t",    0x7000002a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               IOCT    },
1286
{"seq",     "d,v,t",    0,    (int) M_SEQ,       INSN_MACRO,             0,               I1      },
1287
{"seq",     "d,v,I",    0,    (int) M_SEQ_I,     INSN_MACRO,             0,               I1      },
1288
{"seq", "S,T",          0x46a00032,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,       IL2E    },
1289
{"seq", "S,T",          0x4ba0000c,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,       IL2F|IL3A       },
1290
{"seqi",    "t,r,+Q",   0x7000002e, 0xfc00003f, WR_t|RD_s,              0,               IOCT    },
1291
{"sge",     "d,v,t",    0,    (int) M_SGE,       INSN_MACRO,             0,               I1      },
1292
{"sge",     "d,v,I",    0,    (int) M_SGE_I,     INSN_MACRO,             0,               I1      },
1293
{"sgeu",    "d,v,t",    0,    (int) M_SGEU,      INSN_MACRO,             0,               I1      },
1294
{"sgeu",    "d,v,I",    0,    (int) M_SGEU_I,    INSN_MACRO,             0,               I1      },
1295
{"sgt",     "d,v,t",    0,    (int) M_SGT,       INSN_MACRO,             0,               I1      },
1296
{"sgt",     "d,v,I",    0,    (int) M_SGT_I,     INSN_MACRO,             0,               I1      },
1297
{"sgtu",    "d,v,t",    0,    (int) M_SGTU,      INSN_MACRO,             0,               I1      },
1298
{"sgtu",    "d,v,I",    0,    (int) M_SGTU_I,    INSN_MACRO,             0,               I1      },
1299
{"sh",      "t,o(b)",   0xa4000000, 0xfc000000, SM|RD_t|RD_b,           0,               I1      },
1300
{"sh",      "t,A(b)",   0,    (int) M_SH_AB,     INSN_MACRO,             0,               I1      },
1301
{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,               MX      },
1302
{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,               MX|SB1  },
1303
{"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,               N54     },
1304
{"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,               MX      },
1305
{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,               MX|SB1  },
1306
{"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,               N54     },
1307
{"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,               MX      },
1308
{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,               MX|SB1  },
1309
{"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,               N54     },
1310
{"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,               MX      },
1311
{"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,               N54     },
1312
{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,               MX      },
1313
{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,               MX      },
1314
{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,               MX|SB1  },
1315
{"sle",     "d,v,t",    0,    (int) M_SLE,       INSN_MACRO,             0,               I1      },
1316
{"sle",     "d,v,I",    0,    (int) M_SLE_I,     INSN_MACRO,             0,               I1      },
1317
{"sle", "S,T",          0x46a0003e,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,       IL2E    },
1318
{"sle", "S,T",          0x4ba0000e,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,       IL2F|IL3A       },
1319
{"sleu",    "d,v,t",    0,    (int) M_SLEU,      INSN_MACRO,             0,               I1      },
1320
{"sleu",    "d,v,I",    0,    (int) M_SLEU_I,    INSN_MACRO,             0,               I1      },
1321
{"sleu",        "S,T",          0x4680003e,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,       IL2E    },
1322
{"sleu",        "S,T",          0x4b80000e,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,       IL2F|IL3A       },
1323
{"sllv",    "d,t,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,               I1      },
1324
{"sll",     "d,w,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,               I1      }, /* sllv */
1325
{"sll",     "d,w,<",    0x00000000, 0xffe0003f, WR_d|RD_t,              0,               I1      },
1326
{"sll", "D,S,T",        0x45800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1327
{"sll", "D,S,T",        0x4b00000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1328
{"sll.ob",  "X,Y,Q",    0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX|SB1  },
1329
{"sll.ob",  "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T,         0,               N54     },
1330
{"sll.ob",  "D,S,k",    0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
1331
{"sll.qh",  "X,Y,Q",    0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },
1332
{"slt",     "d,v,t",    0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I1      },
1333
{"slt",     "d,v,I",    0,    (int) M_SLT_I,     INSN_MACRO,             0,               I1      },
1334
{"slt", "S,T",          0x46a0003c,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,       IL2E    },
1335
{"slt", "S,T",          0x4ba0000d,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,       IL2F|IL3A       },
1336
{"slti",    "t,r,j",    0x28000000, 0xfc000000, WR_t|RD_s,              0,               I1      },
1337
{"sltiu",   "t,r,j",    0x2c000000, 0xfc000000, WR_t|RD_s,              0,               I1      },
1338
{"sltu",    "d,v,t",    0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I1      },
1339
{"sltu",    "d,v,I",    0,    (int) M_SLTU_I,    INSN_MACRO,             0,               I1      },
1340
{"sltu",        "S,T",          0x4680003c,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,       IL2E    },
1341
{"sltu",        "S,T",          0x4b80000d,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,       IL2F|IL3A       },
1342
{"sne",     "d,v,t",    0x7000002b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               IOCT    },
1343
{"sne",     "d,v,t",    0,    (int) M_SNE,       INSN_MACRO,             0,               I1      },
1344
{"sne",     "d,v,I",    0,    (int) M_SNE_I,     INSN_MACRO,             0,               I1      },
1345
{"snei",    "t,r,+Q",   0x7000002f, 0xfc00003f, WR_t|RD_s,              0,               IOCT    },
1346
{"sqrt.d",  "D,S",      0x46200004, 0xffff003f, WR_D|RD_S|FP_D,         0,               I2      },
1347
{"sqrt.s",  "D,S",      0x46000004, 0xffff003f, WR_D|RD_S|FP_S,         0,               I2      },
1348
{"sqrt.ps", "D,S",      0x46c00004, 0xffff003f, WR_D|RD_S|FP_D,         0,               SB1     },
1349
{"srav",    "d,t,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,               I1      },
1350
{"sra",     "d,w,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,               I1      }, /* srav */
1351
{"sra",     "d,w,<",    0x00000003, 0xffe0003f, WR_d|RD_t,              0,               I1      },
1352
{"sra", "D,S,T",        0x45c00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1353
{"sra", "D,S,T",        0x4b40000f,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1354
{"sra.qh",  "X,Y,Q",    0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },
1355
{"srlv",    "d,t,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,               I1      },
1356
{"srl",     "d,w,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,               I1      }, /* srlv */
1357
{"srl",     "d,w,<",    0x00000002, 0xffe0003f, WR_d|RD_t,              0,               I1      },
1358
{"srl", "D,S,T",        0x45800003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1359
{"srl", "D,S,T",        0x4b00000f,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1360
{"srl.ob",  "X,Y,Q",    0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX|SB1  },
1361
{"srl.ob",  "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T,         0,               N54     },
1362
{"srl.ob",  "D,S,k",    0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
1363
{"srl.qh",  "X,Y,Q",    0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },
1364
/* ssnop is at the start of the table.  */
1365
{"standby", "",         0x42000021, 0xffffffff, 0,                       0,               V1      },
1366
{"sub",     "d,v,t",    0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I1      },
1367
{"sub",     "d,v,I",    0,    (int) M_SUB_I,     INSN_MACRO,             0,               I1      },
1368
{"sub", "D,S,T",        0x45c00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2E    },
1369
{"sub", "D,S,T",        0x4b40000d,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2F|IL3A       },
1370
{"sub.d",   "D,V,T",    0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               I1      },
1371
{"sub.s",   "D,V,T",    0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,               I1      },
1372
{"sub.ob",  "X,Y,Q",    0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX|SB1  },
1373
{"sub.ob",  "D,S,T",    0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
1374
{"sub.ob",  "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T,         0,               N54     },
1375
{"sub.ob",  "D,S,k",    0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
1376
{"sub.ps",  "D,V,T",    0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               I5_33|IL2F      },
1377
{"sub.ps",  "D,V,T",    0x45600001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               IL2E    },
1378
{"sub.qh",  "X,Y,Q",    0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },
1379
{"suba.ob", "Y,Q",      0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1380
{"suba.qh", "Y,Q",      0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1381
{"subl.ob", "Y,Q",      0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1382
{"subl.qh", "Y,Q",      0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1383
{"subu",    "d,v,t",    0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I1      },
1384
{"subu",    "d,v,I",    0,    (int) M_SUBU_I,    INSN_MACRO,             0,               I1      },
1385
{"subu",        "D,S,T",        0x45800001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2E    },
1386
{"subu",        "D,S,T",        0x4b00000d,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2F|IL3A       },
1387
{"suspend", "",         0x42000022, 0xffffffff, 0,                       0,               V1      },
1388
{"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0,               I5_33|N55},
1389
{"sw",      "t,o(b)",   0xac000000, 0xfc000000, SM|RD_t|RD_b,           0,               I1      },
1390
{"sw",      "t,A(b)",   0,    (int) M_SW_AB,     INSN_MACRO,             0,               I1      },
1391
{"swapw",   "t,b",      0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,               XLR     },
1392
{"swapwu",  "t,b",      0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,               XLR     },
1393
{"swapd",   "t,b",      0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,               XLR     },
1394
{"swc0",    "E,o(b)",   0xe0000000, 0xfc000000, SM|RD_C0|RD_b,          0,               I1      },
1395
{"swc0",    "E,A(b)",   0,    (int) M_SWC0_AB,   INSN_MACRO,             0,               I1      },
1396
{"swc1",    "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,               I1      },
1397
{"swc1",    "E,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,               I1      },
1398
{"swc1",    "T,A(b)",   0,    (int) M_SWC1_AB,   INSN_MACRO,             INSN2_M_FP_S,   I1      },
1399
{"swc1",    "E,A(b)",   0,    (int) M_SWC1_AB,   INSN_MACRO,             INSN2_M_FP_S,   I1      },
1400
{"s.s",     "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,               I1      }, /* swc1 */
1401
{"s.s",     "T,A(b)",   0,    (int) M_SWC1_AB,   INSN_MACRO,             INSN2_M_FP_S,   I1      },
1402
{"swc2",    "E,o(b)",   0xe8000000, 0xfc000000, SM|RD_C2|RD_b,          0,               I1      },
1403
{"swc2",    "E,A(b)",   0,    (int) M_SWC2_AB,   INSN_MACRO,             0,               I1      },
1404
{"swc3",    "E,o(b)",   0xec000000, 0xfc000000, SM|RD_C3|RD_b,          0,               I1      },
1405
{"swc3",    "E,A(b)",   0,    (int) M_SWC3_AB,   INSN_MACRO,             0,               I1      },
1406
{"swl",     "t,o(b)",   0xa8000000, 0xfc000000, SM|RD_t|RD_b,           0,               I1      },
1407
{"swl",     "t,A(b)",   0,    (int) M_SWL_AB,    INSN_MACRO,             0,               I1      },
1408
{"scache",  "t,o(b)",   0xa8000000, 0xfc000000, RD_t|RD_b,              0,               I2      }, /* same */
1409
{"scache",  "t,A(b)",   0,    (int) M_SWL_AB,    INSN_MACRO,             0,               I2      }, /* as swl */
1410
{"swr",     "t,o(b)",   0xb8000000, 0xfc000000, SM|RD_t|RD_b,           0,               I1      },
1411
{"swr",     "t,A(b)",   0,    (int) M_SWR_AB,    INSN_MACRO,             0,               I1      },
1412
{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b,              0,               I2      }, /* same */
1413
{"invalidate", "t,A(b)",0,    (int) M_SWR_AB,    INSN_MACRO,             0,               I2      }, /* as swr */
1414
{"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0,               I4_33   },
1415 158 khays
{"synciobdma", "",      0x0000008f, 0xffffffff, NODS,                   0,               IOCT    },
1416
{"syncs",   "",         0x0000018f, 0xffffffff, NODS,                   0,               IOCT    },
1417
{"syncw",   "",         0x0000010f, 0xffffffff, NODS,                   0,               IOCT    },
1418
{"syncws",  "",         0x0000014f, 0xffffffff, NODS,                   0,               IOCT    },
1419
{"sync_acquire", "",    0x0000044f, 0xffffffff, NODS,                   0,               I33     },
1420
{"sync_mb", "",         0x0000040f, 0xffffffff, NODS,                   0,               I33     },
1421
{"sync_release", "",    0x0000048f, 0xffffffff, NODS,                   0,               I33     },
1422
{"sync_rmb", "",        0x000004cf, 0xffffffff, NODS,                   0,               I33     },
1423
{"sync_wmb", "",        0x0000010f, 0xffffffff, NODS,                   0,               I33     },
1424
{"sync",    "",         0x0000000f, 0xffffffff, NODS,                   0,               I2|G1   },
1425
{"sync",    "1",        0x0000000f, 0xfffff83f, NODS,                   0,               I32     },
1426
{"sync.p",  "",         0x0000040f, 0xffffffff, NODS,                   0,               I2      },
1427
{"sync.l",  "",         0x0000000f, 0xffffffff, NODS,                   0,               I2      },
1428 18 khays
{"synci",   "o(b)",     0x041f0000, 0xfc1f0000, SM|RD_b,                0,               I33     },
1429
{"syscall", "",         0x0000000c, 0xffffffff, TRAP,                   0,               I1      },
1430
{"syscall", "B",        0x0000000c, 0xfc00003f, TRAP,                   0,               I1      },
1431
{"teqi",    "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,              0,               I2      },
1432
{"teq",     "s,t",      0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP,         0,               I2      },
1433
{"teq",     "s,t,q",    0x00000034, 0xfc00003f, RD_s|RD_t|TRAP,         0,               I2      },
1434
{"teq",     "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,              0,               I2      }, /* teqi */
1435
{"teq",     "s,I",      0,    (int) M_TEQ_I,     INSN_MACRO,             0,               I2      },
1436
{"tgei",    "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,              0,               I2      },
1437
{"tge",     "s,t",      0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP,         0,               I2      },
1438
{"tge",     "s,t,q",    0x00000030, 0xfc00003f, RD_s|RD_t|TRAP,         0,               I2      },
1439
{"tge",     "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,              0,               I2      }, /* tgei */
1440
{"tge",     "s,I",      0,    (int) M_TGE_I,    INSN_MACRO,              0,               I2      },
1441
{"tgeiu",   "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,              0,               I2      },
1442
{"tgeu",    "s,t",      0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP,         0,               I2      },
1443
{"tgeu",    "s,t,q",    0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,         0,               I2      },
1444
{"tgeu",    "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,              0,               I2      }, /* tgeiu */
1445
{"tgeu",    "s,I",      0,    (int) M_TGEU_I,    INSN_MACRO,             0,               I2      },
1446
{"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,               0,               I1      },
1447
{"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,               0,               I1      },
1448
{"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,               0,               I1      },
1449
{"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,               0,               I1      },
1450
{"tlti",    "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,              0,               I2      },
1451
{"tlt",     "s,t",      0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,         0,               I2      },
1452
{"tlt",     "s,t,q",    0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,         0,               I2      },
1453
{"tlt",     "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,              0,               I2      }, /* tlti */
1454
{"tlt",     "s,I",      0,    (int) M_TLT_I,     INSN_MACRO,             0,               I2      },
1455
{"tltiu",   "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,              0,               I2      },
1456
{"tltu",    "s,t",      0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP,         0,               I2      },
1457
{"tltu",    "s,t,q",    0x00000033, 0xfc00003f, RD_s|RD_t|TRAP,         0,               I2      },
1458
{"tltu",    "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,              0,               I2      }, /* tltiu */
1459
{"tltu",    "s,I",      0,    (int) M_TLTU_I,    INSN_MACRO,             0,               I2      },
1460
{"tnei",    "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,              0,               I2      },
1461
{"tne",     "s,t",      0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP,         0,               I2      },
1462
{"tne",     "s,t,q",    0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,         0,               I2      },
1463
{"tne",     "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,              0,               I2      }, /* tnei */
1464
{"tne",     "s,I",      0,    (int) M_TNE_I,     INSN_MACRO,             0,               I2      },
1465
{"trunc.l.d", "D,S",    0x46200009, 0xffff003f, WR_D|RD_S|FP_D,         0,               I3_33   },
1466
{"trunc.l.s", "D,S",    0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               I3_33   },
1467
{"trunc.w.d", "D,S",    0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               I2      },
1468
{"trunc.w.d", "D,S,x",  0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,               I2      },
1469
{"trunc.w.d", "D,S,t",  0,    (int) M_TRUNCWD,   INSN_MACRO,             INSN2_M_FP_S|INSN2_M_FP_D, I1 },
1470
{"trunc.w.s", "D,S",    0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,               I2      },
1471
{"trunc.w.s", "D,S,x",  0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,               I2      },
1472
{"trunc.w.s", "D,S,t",  0,    (int) M_TRUNCWS,   INSN_MACRO,             INSN2_M_FP_S,   I1      },
1473
{"uld",     "t,o(b)",   0,    (int) M_ULD,       INSN_MACRO,             0,               I3      },
1474
{"uld",     "t,A(b)",   0,    (int) M_ULD_A,     INSN_MACRO,             0,               I3      },
1475
{"ulh",     "t,o(b)",   0,    (int) M_ULH,       INSN_MACRO,             0,               I1      },
1476
{"ulh",     "t,A(b)",   0,    (int) M_ULH_A,     INSN_MACRO,             0,               I1      },
1477
{"ulhu",    "t,o(b)",   0,    (int) M_ULHU,      INSN_MACRO,             0,               I1      },
1478
{"ulhu",    "t,A(b)",   0,    (int) M_ULHU_A,    INSN_MACRO,             0,               I1      },
1479
{"ulw",     "t,o(b)",   0,    (int) M_ULW,       INSN_MACRO,             0,               I1      },
1480
{"ulw",     "t,A(b)",   0,    (int) M_ULW_A,     INSN_MACRO,             0,               I1      },
1481
{"usd",     "t,o(b)",   0,    (int) M_USD,       INSN_MACRO,             0,               I3      },
1482
{"usd",     "t,A(b)",   0,    (int) M_USD_A,     INSN_MACRO,             0,               I3      },
1483
{"ush",     "t,o(b)",   0,    (int) M_USH,       INSN_MACRO,             0,               I1      },
1484
{"ush",     "t,A(b)",   0,    (int) M_USH_A,     INSN_MACRO,             0,               I1      },
1485
{"usw",     "t,o(b)",   0,    (int) M_USW,       INSN_MACRO,             0,               I1      },
1486
{"usw",     "t,A(b)",   0,    (int) M_USW_A,     INSN_MACRO,             0,               I1      },
1487
{"v3mulu",  "d,v,t",    0x70000011, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               IOCT    },
1488
{"vmm0",    "d,v,t",    0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               IOCT    },
1489
{"vmulu",   "d,v,t",    0x7000000f, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               IOCT    },
1490
{"wach.ob", "Y",        0x7a00003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX|SB1  },
1491
{"wach.ob", "S",        0x4a00003e, 0xffff07ff, RD_S,                   0,               N54     },
1492
{"wach.qh", "Y",        0x7a20003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX      },
1493
{"wacl.ob", "Y,Z",      0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1494
{"wacl.ob", "S,T",      0x4800003e, 0xffe007ff, RD_S|RD_T,              0,               N54     },
1495
{"wacl.qh", "Y,Z",      0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1496 158 khays
{"wait",    "",         0x42000020, 0xffffffff, NODS,                   0,               I3_32   },
1497
{"wait",    "J",        0x42000020, 0xfe00003f, NODS,                   0,               I32|N55 },
1498
{"waiti",   "",         0x42000020, 0xffffffff, NODS,                   0,               L1      },
1499 18 khays
{"wrpgpr",  "d,w",      0x41c00000, 0xffe007ff, RD_t,                   0,               I33     },
1500
{"wsbh",    "d,w",      0x7c0000a0, 0xffe007ff, WR_d|RD_t,              0,               I33     },
1501
{"xor",     "d,v,t",    0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I1      },
1502
{"xor",     "t,r,I",    0,    (int) M_XOR_I,     INSN_MACRO,             0,               I1      },
1503
{"xor", "D,S,T",        0x47800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1504
{"xor", "D,S,T",        0x4b800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1505
{"xor.ob",  "X,Y,Q",    0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX|SB1  },
1506
{"xor.ob",  "D,S,T",    0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
1507
{"xor.ob",  "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T,         0,               N54     },
1508
{"xor.ob",  "D,S,k",    0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },
1509
{"xor.qh",  "X,Y,Q",    0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },
1510
{"xori",    "t,r,i",    0x38000000, 0xfc000000, WR_t|RD_s,              0,               I1      },
1511 158 khays
{"yield",   "s",        0x7c000009, 0xfc1fffff, NODS|RD_s,              0,               MT32    },
1512
{"yield",   "d,s",      0x7c000009, 0xfc1f07ff, NODS|WR_d|RD_s,         0,               MT32    },
1513 18 khays
 
1514
/* User Defined Instruction.  */
1515
{"udi0",     "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1516
{"udi0",     "s,t,+2",  0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1517
{"udi0",     "s,+3",    0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1518
{"udi0",     "+4",      0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1519
{"udi1",     "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1520
{"udi1",     "s,t,+2",  0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1521
{"udi1",     "s,+3",    0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1522
{"udi1",     "+4",      0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1523
{"udi2",     "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1524
{"udi2",     "s,t,+2",  0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1525
{"udi2",     "s,+3",    0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1526
{"udi2",     "+4",      0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1527
{"udi3",     "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1528
{"udi3",     "s,t,+2",  0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1529
{"udi3",     "s,+3",    0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1530
{"udi3",     "+4",      0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1531
{"udi4",     "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1532
{"udi4",     "s,t,+2",  0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1533
{"udi4",     "s,+3",    0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1534
{"udi4",     "+4",      0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1535
{"udi5",     "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1536
{"udi5",     "s,t,+2",  0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1537
{"udi5",     "s,+3",    0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1538
{"udi5",     "+4",      0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1539
{"udi6",     "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1540
{"udi6",     "s,t,+2",  0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1541
{"udi6",     "s,+3",    0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1542
{"udi6",     "+4",      0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1543
{"udi7",     "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1544
{"udi7",     "s,t,+2",  0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1545
{"udi7",     "s,+3",    0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1546
{"udi7",     "+4",      0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1547
{"udi8",     "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1548
{"udi8",     "s,t,+2",  0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1549
{"udi8",     "s,+3",    0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1550
{"udi8",     "+4",      0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1551
{"udi9",     "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1552
{"udi9",      "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1553
{"udi9",     "s,+3",    0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1554
{"udi9",     "+4",      0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1555
{"udi10",    "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1556
{"udi10",    "s,t,+2",  0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1557
{"udi10",    "s,+3",    0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1558
{"udi10",    "+4",      0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1559
{"udi11",    "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1560
{"udi11",    "s,t,+2",  0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1561
{"udi11",    "s,+3",    0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1562
{"udi11",    "+4",      0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1563
{"udi12",    "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1564
{"udi12",    "s,t,+2",  0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1565
{"udi12",    "s,+3",    0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1566
{"udi12",    "+4",      0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1567
{"udi13",    "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1568
{"udi13",    "s,t,+2",  0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1569
{"udi13",    "s,+3",    0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1570
{"udi13",    "+4",      0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1571
{"udi14",    "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1572
{"udi14",    "s,t,+2",  0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1573
{"udi14",    "s,+3",    0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1574
{"udi14",    "+4",      0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1575
{"udi15",    "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1576
{"udi15",    "s,t,+2",  0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1577
{"udi15",    "s,+3",    0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1578
{"udi15",    "+4",      0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,               I33     },
1579
 
1580
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
1581
   instructions so they are here for the latters to take precedence.  */
1582
{"bc2f",    "p",        0x49000000, 0xffff0000, CBD|RD_CC,              0,               I1      },
1583
{"bc2f",    "N,p",      0x49000000, 0xffe30000, CBD|RD_CC,              0,               I32     },
1584
{"bc2fl",   "p",        0x49020000, 0xffff0000, CBL|RD_CC,              0,               I2|T3   },
1585
{"bc2fl",   "N,p",      0x49020000, 0xffe30000, CBL|RD_CC,              0,               I32     },
1586
{"bc2t",    "p",        0x49010000, 0xffff0000, CBD|RD_CC,              0,               I1      },
1587
{"bc2t",    "N,p",      0x49010000, 0xffe30000, CBD|RD_CC,              0,               I32     },
1588
{"bc2tl",   "p",        0x49030000, 0xffff0000, CBL|RD_CC,              0,               I2|T3   },
1589
{"bc2tl",   "N,p",      0x49030000, 0xffe30000, CBL|RD_CC,              0,               I32     },
1590
{"cfc2",    "t,G",      0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,         0,               I1      },
1591
{"ctc2",    "t,G",      0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,               I1      },
1592
{"dmfc2",   "t,i",      0x48200000, 0xffe00000, LCD|WR_t|RD_C2,         0,               IOCT    },
1593
{"dmfc2",   "t,G",      0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,         0,               I3      },
1594
{"dmfc2",   "t,G,H",    0x48200000, 0xffe007f8, LCD|WR_t|RD_C2,         0,               I64     },
1595
{"dmtc2",   "t,i",      0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,               IOCT    },
1596
{"dmtc2",   "t,G",      0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,               I3      },
1597
{"dmtc2",   "t,G,H",    0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,               I64     },
1598
{"mfc2",    "t,G",      0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,         0,               I1      },
1599
{"mfc2",    "t,G,H",    0x48000000, 0xffe007f8, LCD|WR_t|RD_C2,         0,               I32     },
1600
{"mfhc2",   "t,G",      0x48600000, 0xffe007ff, LCD|WR_t|RD_C2,         0,               I33     },
1601
{"mfhc2",   "t,G,H",    0x48600000, 0xffe007f8, LCD|WR_t|RD_C2,         0,               I33     },
1602
{"mfhc2",   "t,i",      0x48600000, 0xffe00000, LCD|WR_t|RD_C2,         0,               I33     },
1603
{"mtc2",    "t,G",      0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,               I1      },
1604
{"mtc2",    "t,G,H",    0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,               I32     },
1605
{"mthc2",   "t,G",      0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,               I33     },
1606
{"mthc2",   "t,G,H",    0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,               I33     },
1607
{"mthc2",   "t,i",      0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,               I33     },
1608
 
1609
/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
1610
   instructions, so they are here for the latters to take precedence.  */
1611
{"bc3f",    "p",        0x4d000000, 0xffff0000, CBD|RD_CC,              0,               I1      },
1612
{"bc3fl",   "p",        0x4d020000, 0xffff0000, CBL|RD_CC,              0,               I2|T3   },
1613
{"bc3t",    "p",        0x4d010000, 0xffff0000, CBD|RD_CC,              0,               I1      },
1614
{"bc3tl",   "p",        0x4d030000, 0xffff0000, CBL|RD_CC,              0,               I2|T3   },
1615
{"cfc3",    "t,G",      0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3,         0,               I1      },
1616
{"ctc3",    "t,G",      0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC,         0,               I1      },
1617
{"dmfc3",   "t,G",      0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3,         0,               I3      },
1618
{"dmtc3",   "t,G",      0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,               I3      },
1619
{"mfc3",    "t,G",      0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3,         0,               I1      },
1620
{"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3,         0,               I32     },
1621
{"mtc3",    "t,G",      0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,               I1      },
1622
{"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,               I32     },
1623
 
1624
  /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
1625
     4010 any more, so move this insn out of the way.  If the object
1626
     format gave us more info, we could do this right.  */
1627
{"addciu",  "t,r,j",    0x70000000, 0xfc000000, WR_t|RD_s,              0,               L1      },
1628
/* MIPS DSP ASE */
1629
{"absq_s.ph", "d,t",    0x7c000252, 0xffe007ff, WR_d|RD_t,              0,               D32     },
1630
{"absq_s.pw", "d,t",    0x7c000456, 0xffe007ff, WR_d|RD_t,              0,               D64     },
1631
{"absq_s.qh", "d,t",    0x7c000256, 0xffe007ff, WR_d|RD_t,              0,               D64     },
1632
{"absq_s.w", "d,t",     0x7c000452, 0xffe007ff, WR_d|RD_t,              0,               D32     },
1633
{"addq.ph", "d,s,t",    0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1634
{"addq.pw", "d,s,t",    0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1635
{"addq.qh", "d,s,t",    0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1636
{"addq_s.ph", "d,s,t",  0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1637
{"addq_s.pw", "d,s,t",  0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1638
{"addq_s.qh", "d,s,t",  0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1639
{"addq_s.w", "d,s,t",   0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1640
{"addsc",   "d,s,t",    0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1641
{"addu.ob", "d,s,t",    0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1642
{"addu.qb", "d,s,t",    0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1643
{"addu_s.ob", "d,s,t",  0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1644
{"addu_s.qb", "d,s,t",  0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1645
{"addwc",   "d,s,t",    0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1646
{"bitrev",  "d,t",      0x7c0006d2, 0xffe007ff, WR_d|RD_t,              0,               D32     },
1647
{"bposge32", "p",       0x041c0000, 0xffff0000, CBD,                    0,               D32     },
1648
{"bposge64", "p",       0x041d0000, 0xffff0000, CBD,                    0,               D64     },
1649
{"cmp.eq.ph", "s,t",    0x7c000211, 0xfc00ffff, RD_s|RD_t,              0,               D32     },
1650
{"cmp.eq.pw", "s,t",    0x7c000415, 0xfc00ffff, RD_s|RD_t,              0,               D64     },
1651
{"cmp.eq.qh", "s,t",    0x7c000215, 0xfc00ffff, RD_s|RD_t,              0,               D64     },
1652
{"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t,        0,               D64     },
1653
{"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t,        0,               D32     },
1654
{"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t,        0,               D64     },
1655
{"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t,        0,               D32     },
1656
{"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t,        0,               D64     },
1657
{"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t,        0,               D32     },
1658
{"cmp.le.ph", "s,t",    0x7c000291, 0xfc00ffff, RD_s|RD_t,              0,               D32     },
1659
{"cmp.le.pw", "s,t",    0x7c000495, 0xfc00ffff, RD_s|RD_t,              0,               D64     },
1660
{"cmp.le.qh", "s,t",    0x7c000295, 0xfc00ffff, RD_s|RD_t,              0,               D64     },
1661
{"cmp.lt.ph", "s,t",    0x7c000251, 0xfc00ffff, RD_s|RD_t,              0,               D32     },
1662
{"cmp.lt.pw", "s,t",    0x7c000455, 0xfc00ffff, RD_s|RD_t,              0,               D64     },
1663
{"cmp.lt.qh", "s,t",    0x7c000255, 0xfc00ffff, RD_s|RD_t,              0,               D64     },
1664
{"cmpu.eq.ob", "s,t",   0x7c000015, 0xfc00ffff, RD_s|RD_t,              0,               D64     },
1665
{"cmpu.eq.qb", "s,t",   0x7c000011, 0xfc00ffff, RD_s|RD_t,              0,               D32     },
1666
{"cmpu.le.ob", "s,t",   0x7c000095, 0xfc00ffff, RD_s|RD_t,              0,               D64     },
1667
{"cmpu.le.qb", "s,t",   0x7c000091, 0xfc00ffff, RD_s|RD_t,              0,               D32     },
1668
{"cmpu.lt.ob", "s,t",   0x7c000055, 0xfc00ffff, RD_s|RD_t,              0,               D64     },
1669
{"cmpu.lt.qb", "s,t",   0x7c000051, 0xfc00ffff, RD_s|RD_t,              0,               D32     },
1670
{"dextpdp", "t,7,6",    0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,               D64     },
1671
{"dextpdpv", "t,7,s",   0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,              D64     },
1672
{"dextp",   "t,7,6",    0x7c0000bc, 0xfc00e7ff, WR_t|RD_a,              0,               D64     },
1673
{"dextpv",  "t,7,s",    0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,               D64     },
1674
{"dextr.l", "t,7,6",    0x7c00043c, 0xfc00e7ff, WR_t|RD_a,              0,               D64     },
1675
{"dextr_r.l", "t,7,6",  0x7c00053c, 0xfc00e7ff, WR_t|RD_a,              0,               D64     },
1676
{"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a,              0,               D64     },
1677
{"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a,              0,               D64     },
1678
{"dextr_r.w", "t,7,6",  0x7c00013c, 0xfc00e7ff, WR_t|RD_a,              0,               D64     },
1679
{"dextr_s.h", "t,7,6",  0x7c0003bc, 0xfc00e7ff, WR_t|RD_a,              0,               D64     },
1680
{"dextrv.l", "t,7,s",   0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,               D64     },
1681
{"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,               D64     },
1682
{"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s,        0,               D64     },
1683
{"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s,        0,               D64     },
1684
{"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,               D64     },
1685
{"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,               D64     },
1686
{"dextrv.w", "t,7,s",   0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,               D64     },
1687
{"dextr.w", "t,7,6",    0x7c00003c, 0xfc00e7ff, WR_t|RD_a,              0,               D64     },
1688
{"dinsv",   "t,s",      0x7c00000d, 0xfc00ffff, WR_t|RD_s,              0,               D64     },
1689
{"dmadd",   "7,s,t",    0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,               D64     },
1690
{"dmaddu",  "7,s,t",    0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,               D64     },
1691
{"dmsub",   "7,s,t",    0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,               D64     },
1692
{"dmsubu",  "7,s,t",    0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,               D64     },
1693
{"dmthlip", "s,7",      0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,               D64     },
1694
{"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,               D64     },
1695
{"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,               D32     },
1696
{"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,               D32     },
1697
{"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,               D64     },
1698
{"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,               D64     },
1699
{"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,               D64     },
1700
{"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,               D32     },
1701
{"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,               D32     },
1702
{"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,               D64     },
1703
{"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,               D32     },
1704
{"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,               D32     },
1705
{"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,               D64     },
1706
{"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,               D64     },
1707
{"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,               D64     },
1708
{"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,               D32     },
1709
{"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,               D32     },
1710
{"dshilo",  "7,:",      0x7c0006bc, 0xfc07e7ff, MOD_a,                  0,               D64     },
1711
{"dshilov", "7,s",      0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s,             0,               D64     },
1712
{"extpdp",  "t,7,6",    0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,               D32     },
1713
{"extpdpv", "t,7,s",    0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,              D32     },
1714
{"extp",    "t,7,6",    0x7c0000b8, 0xfc00e7ff, WR_t|RD_a,              0,               D32     },
1715
{"extpv",   "t,7,s",    0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,               D32     },
1716
{"extr_rs.w", "t,7,6",  0x7c0001b8, 0xfc00e7ff, WR_t|RD_a,              0,               D32     },
1717
{"extr_r.w", "t,7,6",   0x7c000138, 0xfc00e7ff, WR_t|RD_a,              0,               D32     },
1718
{"extr_s.h", "t,7,6",   0x7c0003b8, 0xfc00e7ff, WR_t|RD_a,              0,               D32     },
1719
{"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,               D32     },
1720
{"extrv_r.w", "t,7,s",  0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,               D32     },
1721
{"extrv_s.h", "t,7,s",  0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,               D32     },
1722
{"extrv.w", "t,7,s",    0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,               D32     },
1723
{"extr.w",  "t,7,6",    0x7c000038, 0xfc00e7ff, WR_t|RD_a,              0,               D32     },
1724
{"insv",    "t,s",      0x7c00000c, 0xfc00ffff, WR_t|RD_s,              0,               D32     },
1725
{"lbux",    "d,t(b)",   0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,               D32     },
1726
{"ldx",     "d,t(b)",   0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,               D64     },
1727
{"lhx",     "d,t(b)",   0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,               D32     },
1728
{"lwx",     "d,t(b)",   0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,               D32     },
1729
{"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,               D32     },
1730
{"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,               D32     },
1731
{"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,               D64     },
1732
{"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,               D64     },
1733
{"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,               D64     },
1734
{"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,               D64     },
1735
{"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,               D64     },
1736
{"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,               D64     },
1737
{"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,               D32     },
1738
{"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,               D32     },
1739
{"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,               D64     },
1740
{"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,               D64     },
1741
{"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,               D64     },
1742
{"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,               D64     },
1743
{"modsub",  "d,s,t",    0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1744
{"mthlip",  "s,7",      0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,               D32     },
1745
{"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D64     },
1746
{"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D64     },
1747
{"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,            D32     },
1748
{"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,            D32     },
1749
{"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D32     },
1750
{"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D32     },
1751
{"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D64     },
1752
{"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D64     },
1753
{"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,               D32     },
1754
{"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,               D64     },
1755
{"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,               D64     },
1756
{"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,               D32     },
1757
{"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,               D64     },
1758
{"packrl.ph", "d,s,t",  0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1759
{"packrl.pw", "d,s,t",  0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1760
{"pick.ob", "d,s,t",    0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1761
{"pick.ph", "d,s,t",    0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1762
{"pick.pw", "d,s,t",    0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1763
{"pick.qb", "d,s,t",    0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1764
{"pick.qh", "d,s,t",    0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1765
{"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t,            0,               D64     },
1766
{"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t,             0,               D64     },
1767
{"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t,            0,               D64     },
1768
{"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t,             0,               D64     },
1769
{"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t,            0,               D64     },
1770
{"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t,            0,               D64     },
1771
{"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t,           0,               D32     },
1772
{"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t,            0,               D32     },
1773
{"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t,           0,               D32     },
1774
{"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t,            0,               D32     },
1775
{"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t,           0,               D64     },
1776
{"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t,            0,               D64     },
1777
{"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t,           0,               D64     },
1778
{"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t,            0,               D64     },
1779
{"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t,              0,               D32     },
1780
{"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t,              0,               D32     },
1781
{"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t,            0,               D32     },
1782
{"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t,             0,               D32     },
1783
{"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t,            0,               D32     },
1784
{"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t,             0,               D32     },
1785
{"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t,            0,               D64     },
1786
{"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t,             0,               D64     },
1787
{"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t,            0,               D64     },
1788
{"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t,             0,               D64     },
1789
{"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t,       0,               D64     },
1790
{"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t,        0,               D32     },
1791
{"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t,        0,               D64     },
1792
{"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t,       0,               D32     },
1793
{"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t,       0,               D64     },
1794
{"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t,     0,               D32     },
1795
{"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t,    0,               D64     },
1796
{"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t,    0,               D64     },
1797
{"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t,    0,               D32     },
1798
{"raddu.l.ob", "d,s",   0x7c000514, 0xfc1f07ff, WR_d|RD_s,              0,               D64     },
1799
{"raddu.w.qb", "d,s",   0x7c000510, 0xfc1f07ff, WR_d|RD_s,              0,               D32     },
1800
{"rddsp",   "d",        0x7fff04b8, 0xffff07ff, WR_d,                   0,               D32     },
1801
{"rddsp",   "d,'",      0x7c0004b8, 0xffc007ff, WR_d,                   0,               D32     },
1802
{"repl.ob", "d,5",      0x7c000096, 0xff0007ff, WR_d,                   0,               D64     },
1803
{"repl.ph", "d,@",      0x7c000292, 0xfc0007ff, WR_d,                   0,               D32     },
1804
{"repl.pw", "d,@",      0x7c000496, 0xfc0007ff, WR_d,                   0,               D64     },
1805
{"repl.qb", "d,5",      0x7c000092, 0xff0007ff, WR_d,                   0,               D32     },
1806
{"repl.qh", "d,@",      0x7c000296, 0xfc0007ff, WR_d,                   0,               D64     },
1807
{"replv.ob", "d,t",     0x7c0000d6, 0xffe007ff, WR_d|RD_t,              0,               D64     },
1808
{"replv.ph", "d,t",     0x7c0002d2, 0xffe007ff, WR_d|RD_t,              0,               D32     },
1809
{"replv.pw", "d,t",     0x7c0004d6, 0xffe007ff, WR_d|RD_t,              0,               D64     },
1810
{"replv.qb", "d,t",     0x7c0000d2, 0xffe007ff, WR_d|RD_t,              0,               D32     },
1811
{"replv.qh", "d,t",     0x7c0002d6, 0xffe007ff, WR_d|RD_t,              0,               D64     },
1812
{"shilo",   "7,0",      0x7c0006b8, 0xfc0fe7ff, MOD_a,                  0,               D32     },
1813
{"shilov",  "7,s",      0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s,             0,               D32     },
1814
{"shll.ob", "d,t,3",    0x7c000017, 0xff0007ff, WR_d|RD_t,              0,               D64     },
1815
{"shll.ph", "d,t,4",    0x7c000213, 0xfe0007ff, WR_d|RD_t,              0,               D32     },
1816
{"shll.pw", "d,t,6",    0x7c000417, 0xfc0007ff, WR_d|RD_t,              0,               D64     },
1817
{"shll.qb", "d,t,3",    0x7c000013, 0xff0007ff, WR_d|RD_t,              0,               D32     },
1818
{"shll.qh", "d,t,4",    0x7c000217, 0xfe0007ff, WR_d|RD_t,              0,               D64     },
1819
{"shll_s.ph", "d,t,4",  0x7c000313, 0xfe0007ff, WR_d|RD_t,              0,               D32     },
1820
{"shll_s.pw", "d,t,6",  0x7c000517, 0xfc0007ff, WR_d|RD_t,              0,               D64     },
1821
{"shll_s.qh", "d,t,4",  0x7c000317, 0xfe0007ff, WR_d|RD_t,              0,               D64     },
1822
{"shll_s.w", "d,t,6",   0x7c000513, 0xfc0007ff, WR_d|RD_t,              0,               D32     },
1823
{"shllv.ob", "d,t,s",   0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1824
{"shllv.ph", "d,t,s",   0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1825
{"shllv.pw", "d,t,s",   0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1826
{"shllv.qb", "d,t,s",   0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1827
{"shllv.qh", "d,t,s",   0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1828
{"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1829
{"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1830
{"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1831
{"shllv_s.w", "d,t,s",  0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1832
{"shra.ph", "d,t,4",    0x7c000253, 0xfe0007ff, WR_d|RD_t,              0,               D32     },
1833
{"shra.pw", "d,t,6",    0x7c000457, 0xfc0007ff, WR_d|RD_t,              0,               D64     },
1834
{"shra.qh", "d,t,4",    0x7c000257, 0xfe0007ff, WR_d|RD_t,              0,               D64     },
1835
{"shra_r.ph", "d,t,4",  0x7c000353, 0xfe0007ff, WR_d|RD_t,              0,               D32     },
1836
{"shra_r.pw", "d,t,6",  0x7c000557, 0xfc0007ff, WR_d|RD_t,              0,               D64     },
1837
{"shra_r.qh", "d,t,4",  0x7c000357, 0xfe0007ff, WR_d|RD_t,              0,               D64     },
1838
{"shra_r.w", "d,t,6",   0x7c000553, 0xfc0007ff, WR_d|RD_t,              0,               D32     },
1839
{"shrav.ph", "d,t,s",   0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1840
{"shrav.pw", "d,t,s",   0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1841
{"shrav.qh", "d,t,s",   0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1842
{"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1843
{"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1844
{"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1845
{"shrav_r.w", "d,t,s",  0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1846
{"shrl.ob", "d,t,3",    0x7c000057, 0xff0007ff, WR_d|RD_t,              0,               D64     },
1847
{"shrl.qb", "d,t,3",    0x7c000053, 0xff0007ff, WR_d|RD_t,              0,               D32     },
1848
{"shrlv.ob", "d,t,s",   0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1849
{"shrlv.qb", "d,t,s",   0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1850
{"subq.ph", "d,s,t",    0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1851
{"subq.pw", "d,s,t",    0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1852
{"subq.qh", "d,s,t",    0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1853
{"subq_s.ph", "d,s,t",  0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1854
{"subq_s.pw", "d,s,t",  0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1855
{"subq_s.qh", "d,s,t",  0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1856
{"subq_s.w", "d,s,t",   0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1857
{"subu.ob", "d,s,t",    0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1858
{"subu.qb", "d,s,t",    0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1859
{"subu_s.ob", "d,s,t",  0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D64     },
1860
{"subu_s.qb", "d,s,t",  0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               D32     },
1861
{"wrdsp",   "s",        0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA,          0,               D32     },
1862
{"wrdsp",   "s,8",      0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA,          0,               D32     },
1863
/* MIPS DSP ASE Rev2 */
1864
{"absq_s.qb", "d,t",    0x7c000052, 0xffe007ff, WR_d|RD_t,              0,              D33      },
1865
{"addu.ph", "d,s,t",    0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1866
{"addu_s.ph", "d,s,t",  0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1867
{"adduh.qb", "d,s,t",   0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1868
{"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1869
{"append",  "t,s,h",    0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33      },
1870
{"balign",  "t,s,I",    0,    (int) M_BALIGN,    INSN_MACRO,             0,              D33      },
1871
{"balign",  "t,s,2",    0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s,         0,              D33      },
1872
{"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33      },
1873
{"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33      },
1874
{"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33      },
1875
{"dpa.w.ph", "7,s,t",   0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33      },
1876
{"dps.w.ph", "7,s,t",   0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33      },
1877
{"mul.ph",  "d,s,t",    0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33      },
1878
{"mul_s.ph", "d,s,t",   0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33      },
1879
{"mulq_rs.w", "d,s,t",  0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33      },
1880
{"mulq_s.ph", "d,s,t",  0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33      },
1881
{"mulq_s.w", "d,s,t",   0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33      },
1882
{"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33      },
1883
{"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D33      },
1884
{"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s,     0,              D33      },
1885
{"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s,   0,              D33      },
1886
{"prepend", "t,s,h",    0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33      },
1887
{"shra.qb", "d,t,3",    0x7c000113, 0xff0007ff, WR_d|RD_t,              0,              D33      },
1888
{"shra_r.qb", "d,t,3",  0x7c000153, 0xff0007ff, WR_d|RD_t,              0,              D33      },
1889
{"shrav.qb", "d,t,s",   0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1890
{"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1891
{"shrl.ph", "d,t,4",    0x7c000653, 0xfe0007ff, WR_d|RD_t,              0,              D33      },
1892
{"shrlv.ph", "d,t,s",   0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1893
{"subu.ph", "d,s,t",    0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1894
{"subu_s.ph", "d,s,t",  0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1895
{"subuh.qb", "d,s,t",   0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1896
{"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1897
{"addqh.ph", "d,s,t",   0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1898
{"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1899
{"addqh.w", "d,s,t",    0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1900
{"addqh_r.w", "d,s,t",  0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1901
{"subqh.ph", "d,s,t",   0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1902
{"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1903
{"subqh.w", "d,s,t",    0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1904
{"subqh_r.w", "d,s,t",  0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33      },
1905
{"dpax.w.ph", "7,s,t",  0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33      },
1906
{"dpsx.w.ph", "7,s,t",  0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33      },
1907
{"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D33      },
1908
{"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D33      },
1909
{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D33      },
1910
{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D33      },
1911
/* Move bc0* after mftr and mttr to avoid opcode collision.  */
1912
{"bc0f",    "p",        0x41000000, 0xffff0000, CBD|RD_CC,              0,               I1      },
1913
{"bc0fl",   "p",        0x41020000, 0xffff0000, CBL|RD_CC,              0,               I2|T3   },
1914
{"bc0t",    "p",        0x41010000, 0xffff0000, CBD|RD_CC,              0,               I1      },
1915
{"bc0tl",   "p",        0x41030000, 0xffff0000, CBL|RD_CC,              0,               I2|T3   },
1916
/* ST Microelectronics Loongson-2E and -2F.  */
1917
{"mult.g",      "d,s,t",        0x7c000018,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2E    },
1918
{"mult.g",      "d,s,t",        0x70000010,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2F    },
1919
{"gsmult",      "d,s,t",        0x70000010,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL3A    },
1920
{"multu.g",     "d,s,t",        0x7c000019,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2E    },
1921
{"multu.g",     "d,s,t",        0x70000012,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2F    },
1922
{"gsmultu",     "d,s,t",        0x70000012,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL3A    },
1923
{"dmult.g",     "d,s,t",        0x7c00001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2E    },
1924
{"dmult.g",     "d,s,t",        0x70000011,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2F    },
1925
{"gsdmult",     "d,s,t",        0x70000011,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL3A    },
1926
{"dmultu.g",    "d,s,t",        0x7c00001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2E    },
1927
{"dmultu.g",    "d,s,t",        0x70000013,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2F    },
1928
{"gsdmultu",    "d,s,t",        0x70000013,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL3A    },
1929
{"div.g",       "d,s,t",        0x7c00001a,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2E    },
1930
{"div.g",       "d,s,t",        0x70000014,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2F    },
1931
{"gsdiv",       "d,s,t",        0x70000014,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL3A    },
1932
{"divu.g",      "d,s,t",        0x7c00001b,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2E    },
1933
{"divu.g",      "d,s,t",        0x70000016,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2F    },
1934
{"gsdivu",      "d,s,t",        0x70000016,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL3A    },
1935
{"ddiv.g",      "d,s,t",        0x7c00001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2E    },
1936
{"ddiv.g",      "d,s,t",        0x70000015,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2F    },
1937
{"gsddiv",      "d,s,t",        0x70000015,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL3A    },
1938
{"ddivu.g",     "d,s,t",        0x7c00001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2E    },
1939
{"ddivu.g",     "d,s,t",        0x70000017,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2F    },
1940
{"gsddivu",     "d,s,t",        0x70000017,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL3A    },
1941
{"mod.g",       "d,s,t",        0x7c000022,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2E    },
1942
{"mod.g",       "d,s,t",        0x7000001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2F    },
1943
{"gsmod",       "d,s,t",        0x7000001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL3A    },
1944
{"modu.g",      "d,s,t",        0x7c000023,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2E    },
1945
{"modu.g",      "d,s,t",        0x7000001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2F    },
1946
{"gsmodu",      "d,s,t",        0x7000001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL3A    },
1947
{"dmod.g",      "d,s,t",        0x7c000026,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2E    },
1948
{"dmod.g",      "d,s,t",        0x7000001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2F    },
1949
{"gsdmod",      "d,s,t",        0x7000001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL3A    },
1950
{"dmodu.g",     "d,s,t",        0x7c000027,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2E    },
1951
{"dmodu.g",     "d,s,t",        0x7000001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL2F    },
1952
{"gsdmodu",     "d,s,t",        0x7000001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,       IL3A    },
1953
{"packsshb",    "D,S,T",        0x47400002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1954
{"packsshb",    "D,S,T",        0x4b400002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1955
{"packsswh",    "D,S,T",        0x47200002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1956
{"packsswh",    "D,S,T",        0x4b200002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1957
{"packushb",    "D,S,T",        0x47600002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1958
{"packushb",    "D,S,T",        0x4b600002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1959
{"paddb",       "D,S,T",        0x47c00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1960
{"paddb",       "D,S,T",        0x4bc00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1961
{"paddh",       "D,S,T",        0x47400000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1962
{"paddh",       "D,S,T",        0x4b400000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1963
{"paddw",       "D,S,T",        0x47600000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1964
{"paddw",       "D,S,T",        0x4b600000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1965
{"paddd",       "D,S,T",        0x47e00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1966
{"paddd",       "D,S,T",        0x4be00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1967
{"paddsb",      "D,S,T",        0x47800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1968
{"paddsb",      "D,S,T",        0x4b800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1969
{"paddsh",      "D,S,T",        0x47000000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1970
{"paddsh",      "D,S,T",        0x4b000000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1971
{"paddusb",     "D,S,T",        0x47a00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1972
{"paddusb",     "D,S,T",        0x4ba00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1973
{"paddush",     "D,S,T",        0x47200000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1974
{"paddush",     "D,S,T",        0x4b200000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1975
{"pandn",       "D,S,T",        0x47e00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1976
{"pandn",       "D,S,T",        0x4be00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1977
{"pavgb",       "D,S,T",        0x46600000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1978
{"pavgb",       "D,S,T",        0x4b200008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1979
{"pavgh",       "D,S,T",        0x46400000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1980
{"pavgh",       "D,S,T",        0x4b000008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1981
{"pcmpeqb",     "D,S,T",        0x46c00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1982
{"pcmpeqb",     "D,S,T",        0x4b800009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1983
{"pcmpeqh",     "D,S,T",        0x46800001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1984
{"pcmpeqh",     "D,S,T",        0x4b400009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1985
{"pcmpeqw",     "D,S,T",        0x46400001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1986
{"pcmpeqw",     "D,S,T",        0x4b000009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1987
{"pcmpgtb",     "D,S,T",        0x46e00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1988
{"pcmpgtb",     "D,S,T",        0x4ba00009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1989
{"pcmpgth",     "D,S,T",        0x46a00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1990
{"pcmpgth",     "D,S,T",        0x4b600009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1991
{"pcmpgtw",     "D,S,T",        0x46600001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1992
{"pcmpgtw",     "D,S,T",        0x4b200009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1993
{"pextrh",      "D,S,T",        0x45c00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1994
{"pextrh",      "D,S,T",        0x4b40000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1995
{"pinsrh_0",    "D,S,T",        0x47800003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1996
{"pinsrh_0",    "D,S,T",        0x4b800003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1997
{"pinsrh_1",    "D,S,T",        0x47a00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
1998
{"pinsrh_1",    "D,S,T",        0x4ba00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
1999
{"pinsrh_2",    "D,S,T",        0x47c00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2000
{"pinsrh_2",    "D,S,T",        0x4bc00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2001
{"pinsrh_3",    "D,S,T",        0x47e00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2002
{"pinsrh_3",    "D,S,T",        0x4be00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2003
{"pmaddhw",     "D,S,T",        0x45e00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2004
{"pmaddhw",     "D,S,T",        0x4b60000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2005
{"pmaxsh",      "D,S,T",        0x46800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2006
{"pmaxsh",      "D,S,T",        0x4b400008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2007
{"pmaxub",      "D,S,T",        0x46c00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2008
{"pmaxub",      "D,S,T",        0x4b800008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2009
{"pminsh",      "D,S,T",        0x46a00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2010
{"pminsh",      "D,S,T",        0x4b600008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2011
{"pminub",      "D,S,T",        0x46e00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2012
{"pminub",      "D,S,T",        0x4ba00008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2013
{"pmovmskb",    "D,S",          0x46a00005,     0xffff003f,     RD_S|WR_D|FP_D, 0,       IL2E    },
2014
{"pmovmskb",    "D,S",          0x4ba0000f,     0xffff003f,     RD_S|WR_D|FP_D, 0,       IL2F|IL3A       },
2015
{"pmulhuh",     "D,S,T",        0x46e00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2016
{"pmulhuh",     "D,S,T",        0x4ba0000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2017
{"pmulhh",      "D,S,T",        0x46a00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2018
{"pmulhh",      "D,S,T",        0x4b60000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2019
{"pmullh",      "D,S,T",        0x46800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2020
{"pmullh",      "D,S,T",        0x4b40000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2021
{"pmuluw",      "D,S,T",        0x46c00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2022
{"pmuluw",      "D,S,T",        0x4b80000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2023
{"pasubub",     "D,S,T",        0x45a00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2024
{"pasubub",     "D,S,T",        0x4b20000d,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2025
{"biadd",       "D,S",          0x46800005,     0xffff003f,     RD_S|WR_D|FP_D, 0,       IL2E    },
2026
{"biadd",       "D,S",          0x4b80000f,     0xffff003f,     RD_S|WR_D|FP_D, 0,       IL2F|IL3A       },
2027
{"pshufh",      "D,S,T",        0x47000002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2028
{"pshufh",      "D,S,T",        0x4b000002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2029
{"psllh",       "D,S,T",        0x46600002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2030
{"psllh",       "D,S,T",        0x4b20000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2031
{"psllw",       "D,S,T",        0x46400002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2032
{"psllw",       "D,S,T",        0x4b00000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2033
{"psrah",       "D,S,T",        0x46a00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2034
{"psrah",       "D,S,T",        0x4b60000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2035
{"psraw",       "D,S,T",        0x46800003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2036
{"psraw",       "D,S,T",        0x4b40000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2037
{"psrlh",       "D,S,T",        0x46600003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2038
{"psrlh",       "D,S,T",        0x4b20000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2039
{"psrlw",       "D,S,T",        0x46400003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2040
{"psrlw",       "D,S,T",        0x4b00000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2041
{"psubb",       "D,S,T",        0x47c00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2042
{"psubb",       "D,S,T",        0x4bc00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2043
{"psubh",       "D,S,T",        0x47400001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2044
{"psubh",       "D,S,T",        0x4b400001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2045
{"psubw",       "D,S,T",        0x47600001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2046
{"psubw",       "D,S,T",        0x4b600001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2047
{"psubd",       "D,S,T",        0x47e00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2048
{"psubd",       "D,S,T",        0x4be00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2049
{"psubsb",      "D,S,T",        0x47800001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2050
{"psubsb",      "D,S,T",        0x4b800001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2051
{"psubsh",      "D,S,T",        0x47000001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2052
{"psubsh",      "D,S,T",        0x4b000001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2053
{"psubusb",     "D,S,T",        0x47a00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2054
{"psubusb",     "D,S,T",        0x4ba00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2055
{"psubush",     "D,S,T",        0x47200001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2056
{"psubush",     "D,S,T",        0x4b200001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2057
{"punpckhbh",   "D,S,T",        0x47600003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2058
{"punpckhbh",   "D,S,T",        0x4b600003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2059
{"punpckhhw",   "D,S,T",        0x47200003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2060
{"punpckhhw",   "D,S,T",        0x4b200003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2061
{"punpckhwd",   "D,S,T",        0x46e00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2062
{"punpckhwd",   "D,S,T",        0x4ba0000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2063
{"punpcklbh",   "D,S,T",        0x47400003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2064
{"punpcklbh",   "D,S,T",        0x4b400003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2065
{"punpcklhw",   "D,S,T",        0x47000003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2066
{"punpcklhw",   "D,S,T",        0x4b000003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2067
{"punpcklwd",   "D,S,T",        0x46c00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },
2068
{"punpcklwd",   "D,S,T",        0x4b80000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },
2069
{"sequ",        "S,T",          0x46800032,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,       IL2E    },
2070
{"sequ",        "S,T",          0x4b80000c,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,       IL2F|IL3A       },
2071
/* No hazard protection on coprocessor instructions--they shouldn't
2072
   change the state of the processor and if they do it's up to the
2073
   user to put in nops as necessary.  These are at the end so that the
2074
   disassembler recognizes more specific versions first.  */
2075
{"c0",      "C",        0x42000000, 0xfe000000, CP,                     0,               I1      },
2076
{"c1",      "C",        0x46000000, 0xfe000000, FP_S,                   0,               I1      },
2077
{"c2",      "C",        0x4a000000, 0xfe000000, CP,                     0,               I1      },
2078
{"c3",      "C",        0x4e000000, 0xfe000000, CP,                     0,               I1      },
2079
{"cop0",     "C",       0,    (int) M_COP0,      INSN_MACRO,             0,               I1      },
2080
{"cop1",     "C",       0,    (int) M_COP1,      INSN_MACRO,             INSN2_M_FP_S,   I1      },
2081
{"cop2",     "C",       0,    (int) M_COP2,      INSN_MACRO,             0,               I1      },
2082
{"cop3",     "C",       0,    (int) M_COP3,      INSN_MACRO,             0,               I1      }
2083
};
2084
 
2085
#define MIPS_NUM_OPCODES \
2086
        ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
2087
const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
2088
 
2089
/* const removed from the following to allow for dynamic extensions to the
2090
 * built-in instruction set. */
2091
struct mips_opcode *mips_opcodes =
2092
  (struct mips_opcode *) mips_builtin_opcodes;
2093
int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
2094
#undef MIPS_NUM_OPCODES

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