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/* mips-opc.c -- MIPS opcode list.

   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002

   2003, 2004, 2005, 2006, 2007, 2008, 2009  Free Software Foundation, Inc.

   Contributed by Ralph Campbell and OSF

   Commented and modified by Ian Lance Taylor, Cygnus Support

   Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.

   MIPS-3D, MDMX, and MIPS32 Release 2 support added by Broadcom

   Corporation (SiByte).

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3, or (at your option)

   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT

   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public

   License for more details.

   You should have received a copy of the GNU General Public License

   along with this file; see the file COPYING.  If not, write to the

   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,

   MA 02110-1301, USA.  */

#include <stdio.h>

#include "sysdep.h"

#include "opcode/mips.h"

/* Short hand so the lines aren't too long.  */

#define LDD     INSN_LOAD_MEMORY_DELAY

#define LCD     INSN_LOAD_COPROC_DELAY

#define UBD     INSN_UNCOND_BRANCH_DELAY

#define CBD     INSN_COND_BRANCH_DELAY

#define COD     INSN_COPROC_MOVE_DELAY

#define CLD     INSN_COPROC_MEMORY_DELAY

#define CBL     INSN_COND_BRANCH_LIKELY

#define NODS    INSN_NO_DELAY_SLOT

#define TRAP    INSN_NO_DELAY_SLOT

#define SM      INSN_STORE_MEMORY

#define WR_d    INSN_WRITE_GPR_D

#define WR_t    INSN_WRITE_GPR_T

#define WR_31   INSN_WRITE_GPR_31

#define WR_D    INSN_WRITE_FPR_D

#define WR_T    INSN_WRITE_FPR_T

#define WR_S    INSN_WRITE_FPR_S

#define RD_s    INSN_READ_GPR_S

#define RD_b    INSN_READ_GPR_S

#define RD_t    INSN_READ_GPR_T

#define RD_S    INSN_READ_FPR_S

#define RD_T    INSN_READ_FPR_T

#define RD_R    INSN_READ_FPR_R

#define WR_CC   INSN_WRITE_COND_CODE

#define RD_CC   INSN_READ_COND_CODE

#define RD_C0   INSN_COP

#define RD_C1   INSN_COP

#define RD_C2   INSN_COP

#define RD_C3   INSN_COP

#define WR_C0   INSN_COP

#define WR_C1   INSN_COP

#define WR_C2   INSN_COP

#define WR_C3   INSN_COP

#define CP      INSN_COP

#define WR_HI   INSN_WRITE_HI

#define RD_HI   INSN_READ_HI

#define MOD_HI  WR_HI|RD_HI

#define WR_LO   INSN_WRITE_LO

#define RD_LO   INSN_READ_LO

#define MOD_LO  WR_LO|RD_LO

#define WR_HILO WR_HI|WR_LO

#define RD_HILO RD_HI|RD_LO

#define MOD_HILO WR_HILO|RD_HILO

#define IS_M    INSN_MULT

#define WR_MACC INSN2_WRITE_MDMX_ACC

#define RD_MACC INSN2_READ_MDMX_ACC

#define I1      INSN_ISA1

#define I2      INSN_ISA2

#define I3      INSN_ISA3

#define I4      INSN_ISA4

#define I5      INSN_ISA5

#define I32     INSN_ISA32

#define I64     INSN_ISA64

#define I33     INSN_ISA32R2

#define I65     INSN_ISA64R2

#define I3_32   INSN_ISA3_32

#define I3_33   INSN_ISA3_32R2

#define I4_32   INSN_ISA4_32

#define I4_33   INSN_ISA4_32R2

#define I5_33   INSN_ISA5_32R2

/* MIPS64 MIPS-3D ASE support.  */

#define M3D     INSN_MIPS3D

/* MIPS32 SmartMIPS ASE support.  */

#define SMT     INSN_SMARTMIPS

/* MIPS64 MDMX ASE support.  */

#define MX      INSN_MDMX

#define IL2E    (INSN_LOONGSON_2E)

#define IL2F    (INSN_LOONGSON_2F)

#define IL3A    (INSN_LOONGSON_3A)

#define P3      INSN_4650

#define L1      INSN_4010

#define V1      (INSN_4100 | INSN_4111 | INSN_4120)

#define T3      INSN_3900

#define M1      INSN_10000

#define SB1     INSN_SB1

#define N411    INSN_4111

#define N412    INSN_4120

#define N5      (INSN_5400 | INSN_5500)

#define N54     INSN_5400

#define N55     INSN_5500

#define IOCT    (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2)

#define IOCTP   (INSN_OCTEONP | INSN_OCTEON2)

#define IOCT2   INSN_OCTEON2

#define XLR     INSN_XLR

#define G1      (T3             \

                 )

#define G2      (T3             \

                 )

#define G3      (I4             \

                 )

/* MIPS DSP ASE support.

   NOTE:

   1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3).  $ac0 is the pair

   of original HI and LO.  $ac1, $ac2 and $ac3 are new registers, and have

   the same structure as $ac0 (HI + LO).  For DSP instructions that write or

   read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a

   (RD_HILO) attributes, such that HILO dependencies are maintained

   conservatively.

   2. For some mul. instructions that use integer registers as destinations

   but destroy HI+LO as side-effect, we add WR_HILO to their attributes.

   3. MIPS DSP ASE includes a new DSP control register, which has 6 fields

   (ccond, outflag, EFI, c, scount, pos).  Many DSP instructions read or write

   certain fields of the DSP control register.  For simplicity, we decide not

   to track dependencies of these fields.

   However, "bposge32" is a branch instruction that depends on the "pos"

   field.  In order to make sure that GAS does not reorder DSP instructions

   that writes the "pos" field and "bposge32", we add DSP_VOLA

   (INSN_NO_DELAY_SLOT) attribute to those instructions that write the "pos"

   field.  */

#define WR_a    WR_HILO /* Write dsp accumulators (reuse WR_HILO)  */

#define RD_a    RD_HILO /* Read dsp accumulators (reuse RD_HILO)  */

#define MOD_a   WR_a|RD_a

#define DSP_VOLA INSN_NO_DELAY_SLOT

#define D32     INSN_DSP

#define D33     INSN_DSPR2

#define D64     INSN_DSP64

/* MIPS MT ASE support.  */

#define MT32    INSN_MT

/* Loongson support.  */

#define WR_z    INSN2_WRITE_GPR_Z

#define WR_Z    INSN2_WRITE_FPR_Z

#define RD_z    INSN2_READ_GPR_Z

#define RD_Z    INSN2_READ_FPR_Z

#define RD_d    INSN2_READ_GPR_D

/* MIPS MCU (MicroController) ASE support.  */

#define MC      INSN_MCU

/* The order of overloaded instructions matters.  Label arguments and

   register arguments look the same. Instructions that can have either

   for arguments must apear in the correct order in this table for the

   assembler to pick the right one. In other words, entries with

   immediate operands must apear after the same instruction with

   registers.

   Because of the lookup algorithm used, entries with the same opcode

   name must be contiguous.

   Many instructions are short hand for other instructions (i.e., The

   jal <register> instruction is short for jalr <register>).  */

const struct mips_opcode mips_builtin_opcodes[] =

{

/* These instructions appear first so that the disassembler will find

   them first.  The assemblers uses a hash table based on the

   instruction name anyhow.  */

/* name,    args,       match,      mask,       pinfo,                  pinfo2,         membership */

{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                   0,               I4_32|G3        },

{"pref",    "k,A(b)",   0,    (int) M_PREF_AB,   INSN_MACRO,             0,               I4_32|G3        },

{"prefx",   "h,t(b)",   0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S,         0,               I4_33   },

{"nop",     "",         0x00000000, 0xffffffff, 0,               INSN2_ALIAS,    I1      }, /* sll */

{"ssnop",   "",         0x00000040, 0xffffffff, 0,               INSN2_ALIAS,    I1      }, /* sll */

{"ehb",     "",         0x000000c0, 0xffffffff, 0,               INSN2_ALIAS,    I1      }, /* sll */

{"li",      "t,j",      0x24000000, 0xffe00000, WR_t,                   INSN2_ALIAS,    I1      }, /* addiu */

{"li",      "t,i",      0x34000000, 0xffe00000, WR_t,                   INSN2_ALIAS,    I1      }, /* ori */

{"li",      "t,I",      0,    (int) M_LI,        INSN_MACRO,             0,               I1      },

{"move",    "d,s",      0,    (int) M_MOVE,      INSN_MACRO,             0,               I1      },

{"move",    "d,s",      0x0000002d, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I3      },/* daddu */

{"move",    "d,s",      0x00000021, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I1      },/* addu */

{"move",    "d,s",      0x00000025, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I1      },/* or */

{"b",       "p",        0x10000000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1      },/* beq 0,0 */

{"b",       "p",        0x04010000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1      },/* bgez 0 */

{"bal",     "p",        0x04110000, 0xffff0000, UBD|WR_31,              INSN2_ALIAS,    I1      },/* bgezal 0*/

/* Loongson specific instructions.  Loongson 3A redefines the Coprocessor 2

   instructions.  Put them here so that disassembler will find them first.

   The assemblers uses a hash table based on the instruction name anyhow.  */

{"campi",       "d,s",          0x70000075,     0xfc1f07ff,     WR_d|RD_s,      0,       IL3A    },

{"campv",       "d,s",          0x70000035,     0xfc1f07ff,     WR_d|RD_s,      0,       IL3A    },

{"camwi",       "d,s,t",        0x700000b5,     0xfc0007ff,     RD_s|RD_t,      RD_d,   IL3A    },

{"ramri",       "d,s",          0x700000f5,     0xfc1f07ff,     WR_d|RD_s,      0,       IL3A    },

{"gsle",        "s,t",          0x70000026,     0xfc00ffff,     RD_s|RD_t,      0,       IL3A    },

{"gsgt",        "s,t",          0x70000027,     0xfc00ffff,     RD_s|RD_t,      0,       IL3A    },

{"gslble",      "t,b,d",        0xc8000010,     0xfc0007ff,     WR_t|RD_b|LDD,  RD_d,   IL3A    },

{"gslbgt",      "t,b,d",        0xc8000011,     0xfc0007ff,     WR_t|RD_b|LDD,  RD_d,   IL3A    },

{"gslhle",      "t,b,d",        0xc8000012,     0xfc0007ff,     WR_t|RD_b|LDD,  RD_d,   IL3A    },

{"gslhgt",      "t,b,d",        0xc8000013,     0xfc0007ff,     WR_t|RD_b|LDD,  RD_d,   IL3A    },

{"gslwle",      "t,b,d",        0xc8000014,     0xfc0007ff,     WR_t|RD_b|LDD,  RD_d,   IL3A    },

{"gslwgt",      "t,b,d",        0xc8000015,     0xfc0007ff,     WR_t|RD_b|LDD,  RD_d,   IL3A    },

{"gsldle",      "t,b,d",        0xc8000016,     0xfc0007ff,     WR_t|RD_b|LDD,  RD_d,   IL3A    },

{"gsldgt",      "t,b,d",        0xc8000017,     0xfc0007ff,     WR_t|RD_b|LDD,  RD_d,   IL3A    },

{"gssble",      "t,b,d",        0xe8000010,     0xfc0007ff,     RD_t|RD_b|SM,   RD_d,   IL3A    },

{"gssbgt",      "t,b,d",        0xe8000011,     0xfc0007ff,     RD_t|RD_b|SM,   RD_d,   IL3A    },

{"gsshle",      "t,b,d",        0xe8000012,     0xfc0007ff,     RD_t|RD_b|SM,   RD_d,   IL3A    },

{"gsshgt",      "t,b,d",        0xe8000013,     0xfc0007ff,     RD_t|RD_b|SM,   RD_d,   IL3A    },

{"gsswle",      "t,b,d",        0xe8000014,     0xfc0007ff,     RD_t|RD_b|SM,   RD_d,   IL3A    },

{"gsswgt",      "t,b,d",        0xe8000015,     0xfc0007ff,     RD_t|RD_b|SM,   RD_d,   IL3A    },

{"gssdle",      "t,b,d",        0xe8000016,     0xfc0007ff,     RD_t|RD_b|SM,   RD_d,   IL3A    },

{"gssdgt",      "t,b,d",        0xe8000017,     0xfc0007ff,     RD_t|RD_b|SM,   RD_d,   IL3A    },

{"gslwlec1",    "T,b,d",        0xc8000018,     0xfc0007ff,     WR_T|RD_b|LDD,  RD_d,   IL3A    },

{"gslwgtc1",    "T,b,d",        0xc8000019,     0xfc0007ff,     WR_T|RD_b|LDD,  RD_d,   IL3A    },

{"gsldlec1",    "T,b,d",        0xc800001a,     0xfc0007ff,     WR_T|RD_b|LDD,  RD_d,   IL3A    },

{"gsldgtc1",    "T,b,d",        0xc800001b,     0xfc0007ff,     WR_T|RD_b|LDD,  RD_d,   IL3A    },

{"gsswlec1",    "T,b,d",        0xe800001c,     0xfc0007ff,     RD_T|RD_b|SM,   RD_d,   IL3A    },

{"gsswgtc1",    "T,b,d",        0xe800001d,     0xfc0007ff,     RD_T|RD_b|SM,   RD_d,   IL3A    },

{"gssdlec1",    "T,b,d",        0xe800001e,     0xfc0007ff,     RD_T|RD_b|SM,   RD_d,   IL3A    },

{"gssdgtc1",    "T,b,d",        0xe800001f,     0xfc0007ff,     RD_T|RD_b|SM,   RD_d,   IL3A    },

{"gslwlc1",     "T,+a(b)",      0xc8000004,     0xfc00c03f,     WR_T|RD_b|LDD,  0,       IL3A    },

{"gslwrc1",     "T,+a(b)",      0xc8000005,     0xfc00c03f,     WR_T|RD_b|LDD,  0,       IL3A    },

{"gsldlc1",     "T,+a(b)",      0xc8000006,     0xfc00c03f,     WR_T|RD_b|LDD,  0,       IL3A    },

{"gsldrc1",     "T,+a(b)",      0xc8000007,     0xfc00c03f,     WR_T|RD_b|LDD,  0,       IL3A    },

{"gsswlc1",     "T,+a(b)",      0xe8000004,     0xfc00c03f,     RD_T|RD_b|SM,   0,       IL3A    },

{"gsswrc1",     "T,+a(b)",      0xe8000005,     0xfc00c03f,     RD_T|RD_b|SM,   0,       IL3A    },

{"gssdlc1",     "T,+a(b)",      0xe8000006,     0xfc00c03f,     RD_T|RD_b|SM,   0,       IL3A    },

{"gssdrc1",     "T,+a(b)",      0xe8000007,     0xfc00c03f,     RD_T|RD_b|SM,   0,       IL3A    },

{"gslbx",       "t,+b(b,d)",    0xd8000000,     0xfc000007,     WR_t|RD_b|LDD,  RD_d,   IL3A    },

{"gslhx",       "t,+b(b,d)",    0xd8000001,     0xfc000007,     WR_t|RD_b|LDD,  RD_d,   IL3A    },

{"gslwx",       "t,+b(b,d)",    0xd8000002,     0xfc000007,     WR_t|RD_b|LDD,  RD_d,   IL3A    },

{"gsldx",       "t,+b(b,d)",    0xd8000003,     0xfc000007,     WR_t|RD_b|LDD,  RD_d,   IL3A    },

{"gssbx",       "t,+b(b,d)",    0xf8000000,     0xfc000007,     RD_t|RD_b|SM,   RD_d,   IL3A    },

{"gsshx",       "t,+b(b,d)",    0xf8000001,     0xfc000007,     RD_t|RD_b|SM,   RD_d,   IL3A    },

{"gsswx",       "t,+b(b,d)",    0xf8000002,     0xfc000007,     RD_t|RD_b|SM,   RD_d,   IL3A    },

{"gssdx",       "t,+b(b,d)",    0xf8000003,     0xfc000007,     RD_t|RD_b|SM,   RD_d,   IL3A    },

{"gslwxc1",     "T,+b(b,d)",    0xd8000006,     0xfc000007,     WR_T|RD_b|LDD,  RD_d,   IL3A    },

{"gsldxc1",     "T,+b(b,d)",    0xd8000007,     0xfc000007,     WR_T|RD_b|LDD,  RD_d,   IL3A    },

{"gsswxc1",     "T,+b(b,d)",    0xf8000006,     0xfc000007,     RD_T|RD_b|SM,   RD_d,   IL3A    },

{"gssdxc1",     "T,+b(b,d)",    0xf8000007,     0xfc000007,     RD_T|RD_b|SM,   RD_d,   IL3A    },

{"gslq",        "+z,t,+c(b)",   0xc8000020,     0xfc008020,     WR_t|RD_b|LDD,  WR_z,   IL3A    },

{"gssq",        "+z,t,+c(b)",   0xe8000020,     0xfc008020,     RD_t|RD_b|SM,   RD_z,   IL3A    },

{"gslqc1",      "+Z,T,+c(b)",   0xc8008020,     0xfc008020,     WR_T|RD_b|LDD,  WR_Z,   IL3A    },

{"gssqc1",      "+Z,T,+c(b)",   0xe8008020,     0xfc008020,     RD_T|RD_b|SM,   RD_Z,   IL3A    },

{"abs",     "d,v",      0,    (int) M_ABS,       INSN_MACRO,             0,               I1      },

{"abs.s",   "D,V",      0x46000005, 0xffff003f, WR_D|RD_S|FP_S,         0,               I1      },

{"abs.d",   "D,V",      0x46200005, 0xffff003f, WR_D|RD_S|FP_D,         0,               I1      },

{"abs.ps",  "D,V",      0x46c00005, 0xffff003f, WR_D|RD_S|FP_D,         0,               I5_33|IL2F      },

{"abs.ps",  "D,V",      0x45600005, 0xffff003f, WR_D|RD_S|FP_D,         0,               IL2E    },

{"aclr",    "\\,~(b)",  0x04070000, 0xfc1f8000, SM|RD_b|NODS,           0,               MC      },

{"aclr",    "\\,o(b)",  0,    (int) M_ACLR_OB,   INSN_MACRO,             0,               MC      },

{"aclr",    "\\,A(b)",  0,    (int) M_ACLR_AB,   INSN_MACRO,             0,               MC      },

{"add",     "d,v,t",    0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I1      },

{"add",     "t,r,I",    0,    (int) M_ADD_I,     INSN_MACRO,             0,               I1      },

{"add", "D,S,T",        0x45c00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2E    },

{"add", "D,S,T",        0x4b40000c,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2F|IL3A       },

{"add.s",   "D,V,T",    0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,               I1      },

{"add.d",   "D,V,T",    0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               I1      },

{"add.ob",  "X,Y,Q",    0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX|SB1  },

{"add.ob",  "D,S,T",    0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },

{"add.ob",  "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T,         0,               N54     },

{"add.ob",  "D,S,k",    0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },

{"add.ps",  "D,V,T",    0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               I5_33|IL2F      },

{"add.ps",  "D,V,T",    0x45600000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               IL2E    },

{"add.qh",  "X,Y,Q",    0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },

{"adda.ob", "Y,Q",      0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },

{"adda.qh", "Y,Q",      0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },

{"addi",    "t,r,j",    0x20000000, 0xfc000000, WR_t|RD_s,              0,               I1      },

{"addiu",   "t,r,j",    0x24000000, 0xfc000000, WR_t|RD_s,              0,               I1      },

{"addl.ob", "Y,Q",      0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },

{"addl.qh", "Y,Q",      0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },

{"addr.ps", "D,S,T",    0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,               M3D     },

{"addu",    "d,v,t",    0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I1      },

{"addu",    "t,r,I",    0,    (int) M_ADDU_I,    INSN_MACRO,             0,               I1      },

{"addu",        "D,S,T",        0x45800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2E    },

{"addu",        "D,S,T",        0x4b00000c,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,       IL2F|IL3A       },

{"alni.ob", "X,Y,Z,O",  0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,               MX|SB1  },

{"alni.ob", "D,S,T,%",  0x48000018, 0xff00003f, WR_D|RD_S|RD_T,         0,               N54     },

{"alni.qh", "X,Y,Z,O",  0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },

{"alnv.ps", "D,V,T,s",  0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,             I5_33   },

{"alnv.ob", "X,Y,Z,s",  0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,             MX|SB1  },

{"alnv.qh", "X,Y,Z,s",  0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,             MX      },

{"and",     "d,v,t",    0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               I1      },

{"and",     "t,r,I",    0,    (int) M_AND_I,     INSN_MACRO,             0,               I1      },

{"and", "D,S,T",        0x47c00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2E    },

{"and", "D,S,T",        0x4bc00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,       IL2F|IL3A       },

{"and.ob",  "X,Y,Q",    0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX|SB1  },

{"and.ob",  "D,S,T",    0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },

{"and.ob",  "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T,         0,               N54     },

{"and.ob",  "D,S,k",    0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,               N54     },

{"and.qh",  "X,Y,Q",    0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,               MX      },

{"andi",    "t,r,i",    0x30000000, 0xfc000000, WR_t|RD_s,              0,               I1      },

{"aset",    "\\,~(b)",  0x04078000, 0xfc1f8000, SM|RD_b|NODS,           0,               MC      },

{"aset",    "\\,o(b)",  0,    (int) M_ASET_OB,   INSN_MACRO,             0,               MC      },

{"aset",    "\\,A(b)",  0,    (int) M_ASET_AB,   INSN_MACRO,             0,               MC      },

{"baddu",   "d,v,t",    0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t,         0,               IOCT    },

/* b is at the top of the table.  */

/* bal is at the top of the table.  */

{"bbit032", "s,+x,p",   0xd8000000, 0xfc000000, RD_s|CBD,               0,               IOCT    },

{"bbit0",   "s,+X,p",   0xd8000000, 0xfc000000, RD_s|CBD,               0,               IOCT    }, /* bbit032 */

{"bbit0",   "s,+x,p",   0xc8000000, 0xfc000000, RD_s|CBD,               0,               IOCT    },

{"bbit132", "s,+x,p",   0xf8000000, 0xfc000000, RD_s|CBD,               0,               IOCT    },

{"bbit1",   "s,+X,p",   0xf8000000, 0xfc000000, RD_s|CBD,               0,               IOCT    }, /* bbit132 */

{"bbit1",   "s,+x,p",   0xe8000000, 0xfc000000, RD_s|CBD,               0,               IOCT    },

/* bc0[tf]l? are at the bottom of the table.  */

{"bc1any2f", "N,p",     0x45200000, 0xffe30000, CBD|RD_CC|FP_S,         0,               M3D     },

{"bc1any2t", "N,p",     0x45210000, 0xffe30000, CBD|RD_CC|FP_S,         0,               M3D     },

{"bc1any4f", "N,p",     0x45400000, 0xffe30000, CBD|RD_CC|FP_S,         0,               M3D     },

{"bc1any4t", "N,p",     0x45410000, 0xffe30000, CBD|RD_CC|FP_S,         0,               M3D     },

{"bc1f",    "p",        0x45000000, 0xffff0000, CBD|RD_CC|FP_S,         0,               I1      },

{"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S,         0,               I4_32   },

{"bc1fl",   "p",        0x45020000, 0xffff0000, CBL|RD_CC|FP_S,         0,               I2|T3   },

{"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S,         0,               I4_32   },

{"bc1t",    "p",        0x45010000, 0xffff0000, CBD|RD_CC|FP_S,         0,               I1      },

{"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S,         0,               I4_32   },

{"bc1tl",   "p",        0x45030000, 0xffff0000, CBL|RD_CC|FP_S,         0,               I2|T3   },

{"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S,         0,               I4_32   },

/* bc2* are at the bottom of the table.  */

/* bc3* are at the bottom of the table.  */

{"beqz",    "s,p",      0x10000000, 0xfc1f0000, CBD|RD_s,               0,               I1      },

{"beqzl",   "s,p",      0x50000000, 0xfc1f0000, CBL|RD_s,               0,               I2|T3   },

{"beq",     "s,t,p",    0x10000000, 0xfc000000, CBD|RD_s|RD_t,          0,               I1      },

{"beq",     "s,I,p",    0,    (int) M_BEQ_I,     INSN_MACRO,             0,               I1      },

{"beql",    "s,t,p",    0x50000000, 0xfc000000, CBL|RD_s|RD_t,          0,               I2|T3   },

{"beql",    "s,I,p",    0,    (int) M_BEQL_I,    INSN_MACRO,             0,               I2|T3   },

{"bge",     "s,t,p",    0,    (int) M_BGE,       INSN_MACRO,             0,               I1      },

{"bge",     "s,I,p",    0,    (int) M_BGE_I,     INSN_MACRO,             0,               I1      },

{"bgel",    "s,t,p",    0,    (int) M_BGEL,      INSN_MACRO,             0,               I2|T3   },

{"bgel",    "s,I,p",    0,    (int) M_BGEL_I,    INSN_MACRO,             0,               I2|T3   },

{"bgeu",    "s,t,p",    0,    (int) M_BGEU,      INSN_MACRO,             0,               I1      },

{"bgeu",    "s,I,p",    0,    (int) M_BGEU_I,    INSN_MACRO,             0,               I1      },

{"bgeul",   "s,t,p",    0,    (int) M_BGEUL,     INSN_MACRO,             0,               I2|T3   },

{"bgeul",   "s,I,p",    0,    (int) M_BGEUL_I,   INSN_MACRO,             0,               I2|T3   },

{"bgez",    "s,p",      0x04010000, 0xfc1f0000, CBD|RD_s,               0,               I1      },

{"bgezl",   "s,p",      0x04030000, 0xfc1f0000, CBL|RD_s,               0,               I2|T3   },

{"bgezal",  "s,p",      0x04110000, 0xfc1f0000, CBD|RD_s|WR_31,         0,               I1      },

{"bgezall", "s,p",      0x04130000, 0xfc1f0000, CBL|RD_s|WR_31,         0,               I2|T3   },

{"bgt",     "s,t,p",    0,    (int) M_BGT,       INSN_MACRO,             0,               I1      },

{"bgt",     "s,I,p",    0,    (int) M_BGT_I,     INSN_MACRO,             0,               I1      },

{"bgtl",    "s,t,p",    0,    (int) M_BGTL,      INSN_MACRO,             0,               I2|T3   },

{"bgtl",    "s,I,p",    0,    (int) M_BGTL_I,    INSN_MACRO,             0,               I2|T3   },

{"bgtu",    "s,t,p",    0,    (int) M_BGTU,      INSN_MACRO,             0,               I1      },

{"bgtu",    "s,I,p",    0,    (int) M_BGTU_I,    INSN_MACRO,             0,               I1      },

{"bgtul",   "s,t,p",    0,    (int) M_BGTUL,     INSN_MACRO,             0,               I2|T3   },

{"bgtul",   "s,I,p",    0,    (int) M_BGTUL_I,   INSN_MACRO,             0,               I2|T3   },

{"bgtz",    "s,p",      0x1c000000, 0xfc1f0000, CBD|RD_s,               0,               I1      },

{"bgtzl",   "s,p",      0x5c000000, 0xfc1f0000, CBL|RD_s,               0,               I2|T3   },

{"ble",     "s,t,p",    0,    (int) M_BLE,       INSN_MACRO,             0,               I1      },

{"ble",     "s,I,p",    0,    (int) M_BLE_I,     INSN_MACRO,             0,               I1      },

{"blel",    "s,t,p",    0,    (int) M_BLEL,      INSN_MACRO,             0,               I2|T3   },

{"blel",    "s,I,p",    0,    (int) M_BLEL_I,    INSN_MACRO,             0,               I2|T3   },

{"bleu",    "s,t,p",    0,    (int) M_BLEU,      INSN_MACRO,             0,               I1      },

{"bleu",    "s,I,p",    0,    (int) M_BLEU_I,    INSN_MACRO,             0,               I1      },

{"bleul",   "s,t,p",    0,    (int) M_BLEUL,     INSN_MACRO,             0,               I2|T3   },

{"bleul",   "s,I,p",    0,    (int) M_BLEUL_I,   INSN_MACRO,             0,               I2|T3   },

{"blez",    "s,p",      0x18000000, 0xfc1f0000, CBD|RD_s,               0,               I1      },

{"blezl",   "s,p",      0x58000000, 0xfc1f0000, CBL|RD_s,               0,               I2|T3   },

{"blt",     "s,t,p",    0,    (int) M_BLT,       INSN_MACRO,             0,               I1      },

{"blt",     "s,I,p",    0,    (int) M_BLT_I,     INSN_MACRO,             0,               I1      },

{"bltl",    "s,t,p",    0,    (int) M_BLTL,      INSN_MACRO,             0,               I2|T3   },

{"bltl",    "s,I,p",    0,    (int) M_BLTL_I,    INSN_MACRO,             0,               I2|T3   },

{"bltu",    "s,t,p",    0,    (int) M_BLTU,      INSN_MACRO,             0,               I1      },

{"bltu",    "s,I,p",    0,    (int) M_BLTU_I,    INSN_MACRO,             0,               I1      },

{"bltul",   "s,t,p",    0,    (int) M_BLTUL,     INSN_MACRO,             0,               I2|T3   },

{"bltul",   "s,I,p",    0,    (int) M_BLTUL_I,   INSN_MACRO,             0,               I2|T3   },

{"bltz",    "s,p",      0x04000000, 0xfc1f0000, CBD|RD_s,               0,               I1      },

{"bltzl",   "s,p",      0x04020000, 0xfc1f0000, CBL|RD_s,               0,               I2|T3   },

{"bltzal",  "s,p",      0x04100000, 0xfc1f0000, CBD|RD_s|WR_31,         0,               I1      },

{"bltzall", "s,p",      0x04120000, 0xfc1f0000, CBL|RD_s|WR_31,         0,               I2|T3   },

{"bnez",    "s,p",      0x14000000, 0xfc1f0000, CBD|RD_s,               0,               I1      },

{"bnezl",   "s,p",      0x54000000, 0xfc1f0000, CBL|RD_s,               0,               I2|T3   },

{"bne",     "s,t,p",    0x14000000, 0xfc000000, CBD|RD_s|RD_t,          0,               I1      },

{"bne",     "s,I,p",    0,    (int) M_BNE_I,     INSN_MACRO,             0,               I1      },

{"bnel",    "s,t,p",    0x54000000, 0xfc000000, CBL|RD_s|RD_t,          0,               I2|T3   },

{"bnel",    "s,I,p",    0,    (int) M_BNEL_I,    INSN_MACRO,             0,               I2|T3   },

{"break",   "",         0x0000000d, 0xffffffff, TRAP,                   0,               I1      },

{"break",   "c",        0x0000000d, 0xfc00ffff, TRAP,                   0,               I1      },

{"break",   "c,q",      0x0000000d, 0xfc00003f, TRAP,                   0,               I1      },

{"c.f.d",   "S,T",      0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },

{"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },

{"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },

{"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },

{"c.f.ps",  "S,T",      0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },

{"c.f.ps",  "S,T",      0x45600030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },

{"c.f.ps",  "M,S,T",    0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },

{"c.un.d",  "S,T",      0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },

{"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },

{"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },

{"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },

{"c.un.ps", "S,T",      0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33|IL2F      },

{"c.un.ps", "S,T",      0x45600031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               IL2E    },

{"c.un.ps", "M,S,T",    0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I5_33   },

{"c.eq.d",  "S,T",      0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,               I1      },

{"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,               I4_32   },

{"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,               I1      },

{"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,               I4_32   },