OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [opcodes/] [score7-dis.c] - Blame information for rev 160

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 18 khays
/* Instruction printing code for Score
2
   Copyright 2009 Free Software Foundation, Inc.
3
   Contributed by:
4
   Brain.lin (brain.lin@sunplusct.com)
5
   Mei Ligang (ligang@sunnorth.com.cn)
6
   Pei-Lin Tsai (pltsai@sunplus.com)
7
 
8
   This file is part of the GNU opcodes library.
9
 
10
   This library is free software; you can redistribute it and/or modify
11
   it under the terms of the GNU General Public License as published by
12
   the Free Software Foundation; either version 3, or (at your option)
13
   any later version.
14
 
15
   It is distributed in the hope that it will be useful, but WITHOUT
16
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
18
   License for more details.
19
 
20
   You should have received a copy of the GNU General Public License
21
   along with this file; see the file COPYING.  If not, write to the
22
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
23
   MA 02110-1301, USA.  */
24
 
25
#include "sysdep.h"
26
#include "dis-asm.h"
27
#define DEFINE_TABLE
28
#include "opintl.h"
29
#include "bfd.h"
30
 
31
/* FIXME: This shouldn't be done here.  */
32
#include "elf-bfd.h"
33
#include "elf/internal.h"
34
#include "elf/score.h"
35
 
36
#ifndef streq
37
#define streq(a,b)    (strcmp ((a), (b)) == 0)
38
#endif
39
 
40
#ifndef strneq
41
#define strneq(a,b,n)    (strncmp ((a), (b), (n)) == 0)
42
#endif
43
 
44
#ifndef NUM_ELEM
45
#define NUM_ELEM(a)     (sizeof (a) / sizeof (a)[0])
46
#endif
47
 
48
struct score_opcode
49
{
50
  unsigned long value;
51
  unsigned long mask;            /* Recognise instruction if (op & mask) == value.  */
52
  char *assembler;        /* Disassembly string.  */
53
};
54
 
55
/* Note: There is a partial ordering in this table - it must be searched from
56
   the top to obtain a correct match.  */
57
 
58
static struct score_opcode score_opcodes[] =
59
{
60
  /* Score Instructions.  */
61
  {0x3800000a, 0x3e007fff, "abs\t\t%20-24r, %15-19r"},
62
  {0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"},
63
  {0x00000010, 0x3e0003ff, "add\t\t%20-24r, %15-19r, %10-14r"},
64
  {0x00000011, 0x3e0003ff, "add.c\t\t%20-24r, %15-19r, %10-14r"},
65
  {0x38000048, 0x3e0003ff, "add.s\t\t%20-24r, %15-19r, %10-14r"},
66
  {0x00000012, 0x3e0003ff, "addc\t\t%20-24r, %15-19r, %10-14r"},
67
  {0x00000013, 0x3e0003ff, "addc.c\t\t%20-24r, %15-19r, %10-14r"},
68
  {0x02000000, 0x3e0e0001, "addi\t\t%20-24r, %1-16i"},
69
  {0x02000001, 0x3e0e0001, "addi.c\t\t%20-24r, %1-16i"},
70
  {0x0a000000, 0x3e0e0001, "addis\t\t%20-24r, %1-16d(0x%1-16x)"},
71
  {0x0a000001, 0x3e0e0001, "addis.c\t\t%20-24r, %1-16d(0x%1-16x)"},
72
  {0x10000000, 0x3e000001, "addri\t\t%20-24r, %15-19r, %1-14i"},
73
  {0x10000001, 0x3e000001, "addri.c\t\t%20-24r, %15-19r, %1-14i"},
74
  {0x00000009, 0x0000700f, "addc!\t\t%8-11r, %4-7r"},
75
  {0x00002000, 0x0000700f, "add!\t\t%8-11r, %4-7r"},
76
  {0x00006000, 0x00007087, "addei!\t\t%8-11r, %3-6d"},
77
  {0x00000020, 0x3e0003ff, "and\t\t%20-24r, %15-19r, %10-14r"},
78
  {0x00000021, 0x3e0003ff, "and.c\t\t%20-24r, %15-19r, %10-14r"},
79
  {0x02080000, 0x3e0e0001, "andi\t\t%20-24r, 0x%1-16x"},
80
  {0x02080001, 0x3e0e0001, "andi.c\t\t%20-24r, 0x%1-16x"},
81
  {0x0a080000, 0x3e0e0001, "andis\t\t%20-24r, 0x%1-16x"},
82
  {0x0a080001, 0x3e0e0001, "andis.c\t\t%20-24r, 0x%1-16x"},
83
  {0x18000000, 0x3e000001, "andri\t\t%20-24r, %15-19r, 0x%1-14x"},
84
  {0x18000001, 0x3e000001, "andri.c\t\t%20-24r, %15-19r,0x%1-14x"},
85
  {0x00002004, 0x0000700f, "and!\t\t%8-11r, %4-7r"},
86
  {0x08000000, 0x3e007c01, "bcs\t\t%b"},
87
  {0x08000400, 0x3e007c01, "bcc\t\t%b"},
88
  {0x08003800, 0x3e007c01, "bcnz\t\t%b"},
89
  {0x08000001, 0x3e007c01, "bcsl\t\t%b"},
90
  {0x08000401, 0x3e007c01, "bccl\t\t%b"},
91
  {0x08003801, 0x3e007c01, "bcnzl\t\t%b"},
92
  {0x00004000, 0x00007f00, "bcs!\t\t%b"},
93
  {0x00004100, 0x00007f00, "bcc!\t\t%b"},
94
  {0x00004e00, 0x00007f00, "bcnz!\t\t%b"},
95
  {0x08001000, 0x3e007c01, "beq\t\t%b"},
96
  {0x08001001, 0x3e007c01, "beql\t\t%b"},
97
  {0x00004400, 0x00007f00, "beq!\t\t%b"},
98
  {0x08000800, 0x3e007c01, "bgtu\t\t%b"},
99
  {0x08001800, 0x3e007c01, "bgt\t\t%b"},
100
  {0x08002000, 0x3e007c01, "bge\t\t%b"},
101
  {0x08000801, 0x3e007c01, "bgtul\t\t%b"},
102
  {0x08001801, 0x3e007c01, "bgtl\t\t%b"},
103
  {0x08002001, 0x3e007c01, "bgel\t\t%b"},
104
  {0x00004200, 0x00007f00, "bgtu!\t\t%b"},
105
  {0x00004600, 0x00007f00, "bgt!\t\t%b"},
106
  {0x00004800, 0x00007f00, "bge!\t\t%b"},
107
  {0x00000029, 0x3e0003ff, "bitclr.c\t%20-24r, %15-19r, 0x%10-14x"},
108
  {0x0000002b, 0x3e0003ff, "bitset.c\t%20-24r, %15-19r, 0x%10-14x"},
109
  {0x0000002d, 0x3e0003ff, "bittst.c\t%15-19r, 0x%10-14x"},
110
  {0x0000002f, 0x3e0003ff, "bittgl.c\t%20-24r, %15-19r, 0x%10-14x"},
111
  {0x00006004, 0x00007007, "bitclr!\t\t%8-11r, 0x%3-7x"},
112
  {0x3800000c, 0x3e0003ff, "bitrev\t\t%20-24r, %15-19r,%10-14r"},
113
  {0x00006005, 0x00007007, "bitset!\t\t%8-11r, 0x%3-7x"},
114
  {0x00006006, 0x00007007, "bittst!\t\t%8-11r, 0x%3-7x"},
115
  {0x00006007, 0x00007007, "bittgl!\t\t%8-11r, 0x%3-7x"},
116
  {0x08000c00, 0x3e007c01, "bleu\t\t%b"},
117
  {0x08001c00, 0x3e007c01, "ble\t\t%b"},
118
  {0x08002400, 0x3e007c01, "blt\t\t%b"},
119
  {0x08000c01, 0x3e007c01, "bleul\t\t%b"},
120
  {0x08001c01, 0x3e007c01, "blel\t\t%b"},
121
  {0x08002401, 0x3e007c01, "bltl\t\t%b"},
122
  {0x08003c01, 0x3e007c01, "bl\t\t%b"},
123
  {0x00004300, 0x00007f00, "bleu!\t\t%b"},
124
  {0x00004700, 0x00007f00, "ble!\t\t%b"},
125
  {0x00004900, 0x00007f00, "blt!\t\t%b"},
126
  {0x08002800, 0x3e007c01, "bmi\t\t%b"},
127
  {0x08002801, 0x3e007c01, "bmil\t\t%b"},
128
  {0x00004a00, 0x00007f00, "bmi!\t\t%b"},
129
  {0x08001400, 0x3e007c01, "bne\t\t%b"},
130
  {0x08001401, 0x3e007c01, "bnel\t\t%b"},
131
  {0x00004500, 0x00007f00, "bne!\t\t%b"},
132
  {0x08002c00, 0x3e007c01, "bpl\t\t%b"},
133
  {0x08002c01, 0x3e007c01, "bpll\t\t%b"},
134
  {0x00004b00, 0x00007f00, "bpl!\t\t%b"},
135
  {0x00000008, 0x3e007fff, "brcs\t\t%15-19r"},
136
  {0x00000408, 0x3e007fff, "brcc\t\t%15-19r"},
137
  {0x00000808, 0x3e007fff, "brgtu\t\t%15-19r"},
138
  {0x00000c08, 0x3e007fff, "brleu\t\t%15-19r"},
139
  {0x00001008, 0x3e007fff, "breq\t\t%15-19r"},
140
  {0x00001408, 0x3e007fff, "brne\t\t%15-19r"},
141
  {0x00001808, 0x3e007fff, "brgt\t\t%15-19r"},
142
  {0x00001c08, 0x3e007fff, "brle\t\t%15-19r"},
143
  {0x00002008, 0x3e007fff, "brge\t\t%15-19r"},
144
  {0x00002408, 0x3e007fff, "brlt\t\t%15-19r"},
145
  {0x00002808, 0x3e007fff, "brmi\t\t%15-19r"},
146
  {0x00002c08, 0x3e007fff, "brpl\t\t%15-19r"},
147
  {0x00003008, 0x3e007fff, "brvs\t\t%15-19r"},
148
  {0x00003408, 0x3e007fff, "brvc\t\t%15-19r"},
149
  {0x00003808, 0x3e007fff, "brcnz\t\t%15-19r"},
150
  {0x00003c08, 0x3e007fff, "br\t\t%15-19r"},
151
  {0x00000009, 0x3e007fff, "brcsl\t\t%15-19r"},
152
  {0x00000409, 0x3e007fff, "brccl\t\t%15-19r"},
153
  {0x00000809, 0x3e007fff, "brgtul\t\t%15-19r"},
154
  {0x00000c09, 0x3e007fff, "brleul\t\t%15-19r"},
155
  {0x00001009, 0x3e007fff, "breql\t\t%15-19r"},
156
  {0x00001409, 0x3e007fff, "brnel\t\t%15-19r"},
157
  {0x00001809, 0x3e007fff, "brgtl\t\t%15-19r"},
158
  {0x00001c09, 0x3e007fff, "brlel\t\t%15-19r"},
159
  {0x00002009, 0x3e007fff, "brgel\t\t%15-19r"},
160
  {0x00002409, 0x3e007fff, "brltl\t\t%15-19r"},
161
  {0x00002809, 0x3e007fff, "brmil\t\t%15-19r"},
162
  {0x00002c09, 0x3e007fff, "brpll\t\t%15-19r"},
163
  {0x00003009, 0x3e007fff, "brvsl\t\t%15-19r"},
164
  {0x00003409, 0x3e007fff, "brvcl\t\t%15-19r"},
165
  {0x00003809, 0x3e007fff, "brcnzl\t\t%15-19r"},
166
  {0x00003c09, 0x3e007fff, "brl\t\t%15-19r"},
167
  {0x00000004, 0x00007f0f, "brcs!\t\t%4-7r"},
168
  {0x00000104, 0x00007f0f, "brcc!\t\t%4-7r"},
169
  {0x00000204, 0x00007f0f, "brgtu!\t\t%4-7r"},
170
  {0x00000304, 0x00007f0f, "brleu!\t\t%4-7r"},
171
  {0x00000404, 0x00007f0f, "breq!\t\t%4-7r"},
172
  {0x00000504, 0x00007f0f, "brne!\t\t%4-7r"},
173
  {0x00000604, 0x00007f0f, "brgt!\t\t%4-7r"},
174
  {0x00000704, 0x00007f0f, "brle!\t\t%4-7r"},
175
  {0x00000804, 0x00007f0f, "brge!\t\t%4-7r"},
176
  {0x00000904, 0x00007f0f, "brlt!\t\t%4-7r"},
177
  {0x00000a04, 0x00007f0f, "brmi!\t\t%4-7r"},
178
  {0x00000b04, 0x00007f0f, "brpl!\t\t%4-7r"},
179
  {0x00000c04, 0x00007f0f, "brvs!\t\t%4-7r"},
180
  {0x00000d04, 0x00007f0f, "brvc!\t\t%4-7r"},
181
  {0x00000e04, 0x00007f0f, "brcnz!\t\t%4-7r"},
182
  {0x00000f04, 0x00007f0f, "br!\t\t%4-7r"},
183
  {0x0000000c, 0x00007f0f, "brcsl!\t\t%4-7r"},
184
  {0x0000010c, 0x00007f0f, "brccl!\t\t%4-7r"},
185
  {0x0000020c, 0x00007f0f, "brgtul!\t\t%4-7r"},
186
  {0x0000030c, 0x00007f0f, "brleul!\t\t%4-7r"},
187
  {0x0000040c, 0x00007f0f, "breql!\t\t%4-7r"},
188
  {0x0000050c, 0x00007f0f, "brnel!\t\t%4-7r"},
189
  {0x0000060c, 0x00007f0f, "brgtl!\t\t%4-7r"},
190
  {0x0000070c, 0x00007f0f, "brlel!\t\t%4-7r"},
191
  {0x0000080c, 0x00007f0f, "brgel!\t\t%4-7r"},
192
  {0x0000090c, 0x00007f0f, "brltl!\t\t%4-7r"},
193
  {0x00000a0c, 0x00007f0f, "brmil!\t\t%4-7r"},
194
  {0x00000b0c, 0x00007f0f, "brpll!\t\t%4-7r"},
195
  {0x00000c0c, 0x00007f0f, "brvsl!\t\t%4-7r"},
196
  {0x00000d0c, 0x00007f0f, "brvcl!\t\t%4-7r"},
197
  {0x00000e0c, 0x00007f0f, "brcnzl!\t\t%4-7r"},
198
  {0x00000f0c, 0x00007f0f, "brl!\t\t%4-7r"},
199
  {0x08003000, 0x3e007c01, "bvs\t\t%b"},
200
  {0x08003400, 0x3e007c01, "bvc\t\t%b"},
201
  {0x08003001, 0x3e007c01, "bvsl\t\t%b"},
202
  {0x08003401, 0x3e007c01, "bvcl\t\t%b"},
203
  {0x00004c00, 0x00007f00, "bvs!\t\t%b"},
204
  {0x00004d00, 0x00007f00, "bvc!\t\t%b"},
205
  {0x00004f00, 0x00007f00, "b!\t\t%b"},
206
  {0x08003c00, 0x3e007c01, "b\t\t%b"},
207
  {0x30000000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
208
  {0x30100000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
209
  {0x30200000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
210
  {0x30300000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
211
  {0x30400000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
212
  {0x30800000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
213
  {0x30900000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
214
  {0x30a00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
215
  {0x30b00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
216
  {0x30c00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
217
  {0x30d00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
218
  {0x30e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
219
  {0x31000000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
220
  {0x31100000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
221
  {0x31800000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
222
  {0x31a00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
223
  {0x31b00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
224
  {0x31c00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
225
  {0x31d00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
226
  {0x31e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
227
  {0x31f00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"},
228
  {0x38000000, 0x3ff003ff, "mad\t\t%15-19r, %10-14r"},
229
  {0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"},
230
  {0x38000080, 0x3ff003ff, "mad.f\t\t%15-19r, %10-14r"},
231
  {0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"},
232
  {0x38000021, 0x3ff003ff, "msbu\t\t%15-19r, %10-14r"},
233
  {0x38000081, 0x3ff003ff, "msb.f\t\t%15-19r, %10-14r"},
234
  {0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"},
235
  {0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"},
236
  {0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"},
237
  {0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"},
238
  {0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"},
239
  {0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"},
240
  {0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"},
241
  {0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"},
242
  {0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"},
243
  {0x38000006, 0x3e0003ff, "min\t\t%20-24r, %15-19r, %10-14r"},
244
  {0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"},
245
  {0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"},
246
  {0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"},
247
  {0x380000c4, 0x3ff003ff, "msbl.fs\t\t%15-19r, %10-14r"},
248
  {0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"},
249
  {0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"},
250
  {0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"},
251
  {0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"},
252
  {0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"},
253
  {0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"},
254
  {0x3800000d, 0x3e007fff, "clz\t\t%20-24r, %15-19r"},
255
  {0x38000000, 0x3e000000, "ceinst\t\t%20-24d, %15-19r, %10-14r, %5-9d, %0-4d"},
256
  {0x00000019, 0x3ff003ff, "cmpteq.c\t\t%15-19r, %10-14r"},
257
  {0x00100019, 0x3ff003ff, "cmptmi.c\t\t%15-19r, %10-14r"},
258
  {0x00300019, 0x3ff003ff, "cmp.c\t\t%15-19r, %10-14r"},
259
  {0x0000001b, 0x3ff07fff, "cmpzteq.c\t%15-19r"},
260
  {0x0010001b, 0x3ff07fff, "cmpztmi.c\t%15-19r"},
261
  {0x0030001b, 0x3ff07fff, "cmpz.c\t\t%15-19r"},
262
  {0x02040001, 0x3e0e0001, "cmpi.c\t\t%20-24r, %1-16i"},
263
  {0x00002003, 0x0000700f, "cmp!\t\t%8-11r, %4-7r"},
264
  {0x0c00000c, 0x3e00001f, "cop1\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"},
265
  {0x0c000014, 0x3e00001f, "cop2\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"},
266
  {0x0c00001c, 0x3e00001f, "cop3\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"},
267
  {0x00000044, 0x3e0003ff, "div\t\t%15-19r, %10-14r"},
268
  {0x00000046, 0x3e0003ff, "divu\t\t%15-19r, %10-14r"},
269
  {0x0c0000a4, 0x3e0003ff, "drte"},
270
  {0x00000058, 0x3e0003ff, "extsb\t\t%20-24r, %15-19r"},
271
  {0x00000059, 0x3e0003ff, "extsb.c\t\t%20-24r, %15-19r"},
272
  {0x0000005a, 0x3e0003ff, "extsh\t\t%20-24r, %15-19r"},
273
  {0x0000005b, 0x3e0003ff, "extsh.c\t\t%20-24r, %15-19r"},
274
  {0x0000005c, 0x3e0003ff, "extzb\t\t%20-24r, %15-19r"},
275
  {0x0000005d, 0x3e0003ff, "extzb.c\t\t%20-24r, %15-19r"},
276
  {0x0000005e, 0x3e0003ff, "extzh\t\t%20-24r, %15-19r"},
277
  {0x0000005f, 0x3e0003ff, "extzh.c\t\t%20-24r, %15-19r"},
278
  {0x04000001, 0x3e000001, "jl\t\t%j"},
279
  {0x00003001, 0x00007001, "jl!\t\t%j"},
280
  {0x00003000, 0x00007001, "j!\t\t%j"},
281
  {0x04000000, 0x3e000001, "j\t\t%j"},
282
  {0x26000000, 0x3e000000, "lb\t\t%20-24r, [%15-19r, %0-14i]"},
283
  {0x2c000000, 0x3e000000, "lbu\t\t%20-24r, [%15-19r, %0-14i]"},
284
  {0x06000003, 0x3e000007, "lb\t\t%20-24r, [%15-19r, %3-14i]+"},
285
  {0x06000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r, %3-14i]+"},
286
  {0x0e000003, 0x3e000007, "lb\t\t%20-24r, [%15-19r]+, %3-14i"},
287
  {0x0e000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r]+, %3-14i"},
288
  {0x0000200b, 0x0000700f, "lbu!\t\t%8-11r, [%4-7r]"},
289
  {0x00007003, 0x00007007, "lbup!\t\t%8-11r, %3-7d"},
290
  {0x00000060, 0x3e0003ff, "lcb\t\t[%15-19r]+"},
291
  {0x00000062, 0x3e0003ff, "lcw\t\t%20-24r, [%15-19r]+"},
292
  {0x00000066, 0x3e0003ff, "lce\t\t%20-24r, [%15-19r]+"},
293
  {0x0c00000a, 0x3e00001f, "ldc1\t\tc%15-19r, [%20-24r, %5-14i]"},
294
  {0x0c000012, 0x3e00001f, "ldc2\t\tc%15-19r, [%20-24r, %5-14i]"},
295
  {0x0c00001a, 0x3e00001f, "ldc3\t\tc%15-19r, [%20-24r, %5-14i]"},
296
  {0x22000000, 0x3e000000, "lh\t\t%20-24r, [%15-19r, %0-14i]"},
297
  {0x24000000, 0x3e000000, "lhu\t\t%20-24r, [%15-19r, %0-14i]"},
298
  {0x06000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r, %3-14i]+"},
299
  {0x06000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r, %3-14i]+"},
300
  {0x0e000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r]+, %3-14i"},
301
  {0x0e000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r]+, %3-14i"},
302
  {0x00002009, 0x0000700f, "lh!\t\t%8-11r, [%4-7r]"},
303
  {0x00007001, 0x00007007, "lhp!\t\t%8-11r, %3-7d1"},
304
  {0x020c0000, 0x3e0e0000, "ldi\t\t%20-24r, 0x%1-16x(%1-16i)"},
305
  {0x0a0c0000, 0x3e0e0000, "ldis\t\t%20-24r, 0x%1-16x(%1-16i)"},
306
  {0x00005000, 0x00007000, "ldiu!\t\t%8-11r, %0-7d"},
307
  {0x0000000c, 0x3e0003ff, "alw\t\t%20-24r, [%15-19r]"},
308
  {0x20000000, 0x3e000000, "lw\t\t%20-24r, [%15-19r, %0-14i]"},
309
  {0x06000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r, %3-14i]+"},
310
  {0x0e000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r]+, %3-14i"},
311
  {0x00002008, 0x0000700f, "lw!\t\t%8-11r, [%4-7r]"},
312
  {0x00007000, 0x00007007, "lwp!\t\t%8-11r, %3-7d2"},
313
  {0x0000100b, 0x0000700f, "madh.fs!\t\t%8-11r, %4-7r"},
314
  {0x0000100a, 0x0000700f, "madl.fs!\t\t%8-11r, %4-7r"},
315
  {0x00001005, 0x0000700f, "madu!\t\t%8-11r, %4-7r"},
316
  {0x00001004, 0x0000700f, "mad.f!\t\t%8-11r, %4-7r"},
317
  {0x00001009, 0x0000700f, "mazh.f!\t\t%8-11r, %4-7r"},
318
  {0x00001008, 0x0000700f, "mazl.f!\t\t%8-11r, %4-7r"},
319
  {0x00000448, 0x3e007fff, "mfcel\t\t%20-24r"},
320
  {0x00001001, 0x00007f0f, "mfcel!\t\t%4-7r"},
321
  {0x00000848, 0x3e007fff, "mfceh\t\t%20-24r"},
322
  {0x00001101, 0x00007f0f, "mfceh!\t\t%4-7r"},
323
  {0x00000c48, 0x3e007fff, "mfcehl\t\t%20-24r, %15-19r"},
324
  {0x00000048, 0x3e0003ff, "mfce\t\t%20-24r, er%10-14d"},
325
  {0x00000050, 0x3e0003ff, "mfsr\t\t%20-24r, sr%10-14d"},
326
  {0x0c000001, 0x3e00001f, "mfcr\t\t%20-24r, c%15-19r"},
327
  {0x0c000009, 0x3e00001f, "mfc1\t\t%20-24r, c%15-19r"},
328
  {0x0c000011, 0x3e00001f, "mfc2\t\t%20-24r, c%15-19r"},
329
  {0x0c000019, 0x3e00001f, "mfc3\t\t%20-24r, c%15-19r"},
330
  {0x0c00000f, 0x3e00001f, "mfcc1\t\t%20-24r, c%15-19r"},
331
  {0x0c000017, 0x3e00001f, "mfcc2\t\t%20-24r, c%15-19r"},
332
  {0x0c00001f, 0x3e00001f, "mfcc3\t\t%20-24r, c%15-19r"},
333
  {0x00000002, 0x0000700f, "mhfl!\t\t%8-11R, %4-7r"},
334
  {0x00000001, 0x0000700f, "mlfh!\t\t%8-11r, %4-7R"},
335
  {0x00001006, 0x0000700f, "msb.f!\t\t%8-11r, %4-7r"},
336
  {0x0000100f, 0x0000700f, "msbh.fs!\t\t%8-11r, %4-7r"},
337
  {0x0000100e, 0x0000700f, "msbl.fs!\t\t%8-11r, %4-7r"},
338
  {0x00001007, 0x0000700f, "msbu!\t\t%8-11r, %4-7r"},
339
  {0x0000100d, 0x0000700f, "mszh.f!\t\t%8-11r, %4-7r"},
340
  {0x0000100c, 0x0000700f, "mszl.f!\t\t%8-11r, %4-7r"},
341
  {0x0000044a, 0x3e007fff, "mtcel\t\t%20-24r"},
342
  {0x00001000, 0x00007f0f, "mtcel!\t\t%4-7r"},
343
  {0x0000084a, 0x3e007fff, "mtceh\t\t%20-24r"},
344
  {0x00001100, 0x00007f0f, "mtceh!\t\t%4-7r"},
345
  {0x00000c4a, 0x3e007fff, "mtcehl\t\t%20-24r, %15-19r"},
346
  {0x0000004a, 0x3e0003ff, "mtce\t\t%20-24r, er%10-14d"},
347
  {0x00000052, 0x3e0003ff, "mtsr\t\t%15-19r, sr%10-14d"},
348
  {0x0c000000, 0x3e00001f, "mtcr\t\t%20-24r, c%15-19r"},
349
  {0x0c000008, 0x3e00001f, "mtc1\t\t%20-24r, c%15-19r"},
350
  {0x0c000010, 0x3e00001f, "mtc2\t\t%20-24r, c%15-19r"},
351
  {0x0c000018, 0x3e00001f, "mtc3\t\t%20-24r, c%15-19r"},
352
  {0x0c00000e, 0x3e00001f, "mtcc1\t\t%20-24r, c%15-19r"},
353
  {0x0c000016, 0x3e00001f, "mtcc2\t\t%20-24r, c%15-19r"},
354
  {0x0c00001e, 0x3e00001f, "mtcc3\t\t%20-24r, c%15-19r"},
355
  {0x00000040, 0x3e0003ff, "mul\t\t%15-19r, %10-14r"},
356
  {0x00000040, 0x3e0003ff, "maz\t\t%15-19r, %10-14r"},
357
  {0x00000041, 0x3e0003ff, "mul.f\t\t%15-19r, %10-14r"},
358
  {0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"},
359
  {0x00001002, 0x0000700f, "mul.f!\t\t%8-11r, %4-7r"},
360
  {0x00000042, 0x3e0003ff, "mulu\t\t%15-19r, %10-14r"},
361
  {0x00000042, 0x3e0003ff, "mazu\t\t%15-19r, %10-14r"},
362
  {0x00001003, 0x0000700f, "mulu!\t\t%8-11r, %4-7r"},
363
  {0x00000056, 0x3e007fff, "mvcs\t\t%20-24r, %15-19r"},
364
  {0x00000456, 0x3e007fff, "mvcc\t\t%20-24r, %15-19r"},
365
  {0x00000856, 0x3e007fff, "mvgtu\t\t%20-24r, %15-19r"},
366
  {0x00000c56, 0x3e007fff, "mvleu\t\t%20-24r, %15-19r"},
367
  {0x00001056, 0x3e007fff, "mveq\t\t%20-24r, %15-19r"},
368
  {0x00001456, 0x3e007fff, "mvne\t\t%20-24r, %15-19r"},
369
  {0x00001856, 0x3e007fff, "mvgt\t\t%20-24r, %15-19r"},
370
  {0x00001c56, 0x3e007fff, "mvle\t\t%20-24r, %15-19r"},
371
  {0x00002056, 0x3e007fff, "mvge\t\t%20-24r, %15-19r"},
372
  {0x00002456, 0x3e007fff, "mvlt\t\t%20-24r, %15-19r"},
373
  {0x00002856, 0x3e007fff, "mvmi\t\t%20-24r, %15-19r"},
374
  {0x00002c56, 0x3e007fff, "mvpl\t\t%20-24r, %15-19r"},
375
  {0x00003056, 0x3e007fff, "mvvs\t\t%20-24r, %15-19r"},
376
  {0x00003456, 0x3e007fff, "mvvc\t\t%20-24r, %15-19r"},
377
  {0x00003c56, 0x3e007fff, "mv\t\t%20-24r, %15-19r"},
378
  {0x00000003, 0x0000700f, "mv!\t\t%8-11r, %4-7r"},
379
  {0x0000001e, 0x3e0003ff, "neg\t\t%20-24r, %10-14r"},
380
  {0x0000001f, 0x3e0003ff, "neg.c\t\t%20-24r, %10-14r"},
381
  {0x00002002, 0x0000700f, "neg!\t\t%8-11r, %4-7r"},
382
  {0x00000000, 0x3e0003ff, "nop"},
383
  {0x00000024, 0x3e0003ff, "not\t\t%20-24r, %15-19r"},
384
  {0x00000025, 0x3e0003ff, "not.c\t\t%20-24r, %15-19r"},
385
  {0x00000000, 0x0000700f, "nop!"},
386
  {0x00002006, 0x0000700f, "not!\t\t%8-11r, %4-7r"},
387
  {0x00000022, 0x3e0003ff, "or\t\t%20-24r, %15-19r, %10-14r"},
388
  {0x00000023, 0x3e0003ff, "or.c\t\t%20-24r, %15-19r, %10-14r"},
389
  {0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"},
390
  {0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"},
391
  {0x0a0a0000, 0x3e0e0001, "oris\t\t%20-24r, 0x%1-16x"},
392
  {0x0a0a0001, 0x3e0e0001, "oris.c\t\t%20-24r, 0x%1-16x"},
393
  {0x1a000000, 0x3e000001, "orri\t\t%20-24r, %15-19r, 0x%1-14x"},
394
  {0x1a000001, 0x3e000001, "orri.c\t\t%20-24r, %15-19r, 0x%1-14x"},
395
  {0x00002005, 0x0000700f, "or!\t\t%8-11r, %4-7r"},
396
  {0x0000000a, 0x3e0003ff, "pflush"},
397
  {0x0000208a, 0x0000708f, "pop!\t\t%8-11R, [%4-6r]"},
398
  {0x0000200a, 0x0000700f, "pop!\t\t%8-11r, [%4-7r]"},
399
  {0x0000208e, 0x0000708f, "push!\t\t%8-11R, [%4-6r]"},
400
  {0x0000200e, 0x0000700f, "push!\t\t%8-11r, [%4-7r]"},
401
  {0x00000038, 0x3e0003ff, "ror\t\t%20-24r, %15-19r, %10-14r"},
402
  {0x00000039, 0x3e0003ff, "ror.c\t\t%20-24r, %15-19r, %10-14r"},
403
  {0x0000003b, 0x3e0003ff, "rorc.c\t\t%20-24r, %15-19r, %10-14r"},
404
  {0x0000003c, 0x3e0003ff, "rol\t\t%20-24r, %15-19r, %10-14r"},
405
  {0x0000003d, 0x3e0003ff, "rol.c\t\t%20-24r, %15-19r, %10-14r"},
406
  {0x0000003f, 0x3e0003ff, "rolc.c\t\t%20-24r, %15-19r, %10-14r"},
407
  {0x00000078, 0x3e0003ff, "rori\t\t%20-24r, %15-19r, %10-14d"},
408
  {0x00000079, 0x3e0003ff, "rori.c\t\t%20-24r, %15-19r, %10-14d"},
409
  {0x0000007b, 0x3e0003ff, "roric.c\t\t%20-24r, %15-19r, %10-14d"},
410
  {0x0000007c, 0x3e0003ff, "roli\t\t%20-24r, %15-19r, %10-14d"},
411
  {0x0000007d, 0x3e0003ff, "roli.c\t\t%20-24r, %15-19r, %10-14d"},
412
  {0x0000007f, 0x3e0003ff, "rolic.c\t\t%20-24r, %15-19r, %10-14d"},
413
  {0x0c000084, 0x3e0003ff, "rte"},
414
  {0x2e000000, 0x3e000000, "sb\t\t%20-24r, [%15-19r, %0-14i]"},
415
  {0x06000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r, %3-14i]+"},
416
  {0x0e000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r]+, %3-14i"},
417
  {0x0000200f, 0x0000700f, "sb!\t\t%8-11r, [%4-7r]"},
418
  {0x00007007, 0x00007007, "sbp!\t\t%8-11r, %3-7d"},
419
  {0x0000000e, 0x3e0003ff, "asw\t\t%20-24r, [%15-19r]"},
420
  {0x00000068, 0x3e0003ff, "scb\t\t%20-24r, [%15-19r]+"},
421
  {0x0000006a, 0x3e0003ff, "scw\t\t%20-24r, [%15-19r]+"},
422
  {0x0000006e, 0x3e0003ff, "sce\t\t[%15-19r]+"},
423
  {0x00000006, 0x3e0003ff, "sdbbp\t\t%15-19d"},
424
  {0x00006002, 0x00007007, "sdbbp!\t\t%3-7d"},
425
  {0x2a000000, 0x3e000000, "sh\t\t%20-24r, [%15-19r, %0-14i]"},
426
  {0x06000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r, %3-14i]+"},
427
  {0x0e000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r]+, %3-14i"},
428
  {0x0000200d, 0x0000700f, "sh!\t\t%8-11r, [%4-7r]"},
429
  {0x00007005, 0x00007007, "shp!\t\t%8-11r, %3-7d1"},
430
  {0x0c0000c4, 0x3e0003ff, "sleep"},
431
  {0x00000030, 0x3e0003ff, "sll\t\t%20-24r, %15-19r, %10-14r"},
432
  {0x00000031, 0x3e0003ff, "sll.c\t\t%20-24r, %15-19r, %10-14r"},
433
  {0x00000070, 0x3e0003ff, "slli\t\t%20-24r, %15-19r, %10-14d"},
434
  {0x00000071, 0x3e0003ff, "slli.c\t\t%20-24r, %15-19r, %10-14d"},
435
  {0x00000008, 0x0000700f, "sll!\t\t%8-11r, %4-7r"},
436
  {0x00006001, 0x00007007, "slli!\t\t%8-11r, %3-7d"},
437
  {0x00000034, 0x3e0003ff, "srl\t\t%20-24r, %15-19r, %10-14r"},
438
  {0x00000035, 0x3e0003ff, "srl.c\t\t%20-24r, %15-19r, %10-14r"},
439
  {0x00000036, 0x3e0003ff, "sra\t\t%20-24r, %15-19r, %10-14r"},
440
  {0x00000037, 0x3e0003ff, "sra.c\t\t%20-24r, %15-19r, %10-14r"},
441
  {0x00000074, 0x3e0003ff, "srli\t\t%20-24r, %15-19r, %10-14d"},
442
  {0x00000075, 0x3e0003ff, "srli.c\t\t%20-24r, %15-19r, %10-14d"},
443
  {0x00000076, 0x3e0003ff, "srai\t\t%20-24r, %15-19r, %10-14d"},
444
  {0x00000077, 0x3e0003ff, "srai.c\t\t%20-24r, %15-19r, %10-14d"},
445
  {0x0000000a, 0x0000700f, "srl!\t\t%8-11r, %4-7r"},
446
  {0x00006003, 0x00007007, "srli!\t\t%8-11r, %3-7d"},
447
  {0x0000000b, 0x0000700f, "sra!\t\t%8-11r, %4-7r"},
448
  {0x0c00000b, 0x3e00001f, "stc1\t\tc%15-19r, [%20-24r, %5-14i]"},
449
  {0x0c000013, 0x3e00001f, "stc2\t\tc%15-19r, [%20-24r, %5-14i]"},
450
  {0x0c00001b, 0x3e00001f, "stc3\t\tc%15-19r, [%20-24r, %5-14i]"},
451
  {0x00000014, 0x3e0003ff, "sub\t\t%20-24r, %15-19r, %10-14r"},
452
  {0x00000015, 0x3e0003ff, "sub.c\t\t%20-24r, %15-19r, %10-14r"},
453
  {0x00000016, 0x3e0003ff, "subc\t\t%20-24r, %15-19r, %10-14r"},
454
  {0x00000017, 0x3e0003ff, "subc.c\t\t%20-24r, %15-19r, %10-14r"},
455
  {0x00002001, 0x0000700f, "sub!\t\t%8-11r, %4-7r"},
456
  {0x00006080, 0x00007087, "subei!\t\t%8-11r, %3-6d"},
457
  {0x28000000, 0x3e000000, "sw\t\t%20-24r, [%15-19r, %0-14i]"},
458
  {0x06000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r, %3-14i]+"},
459
  {0x0e000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r]+, %3-14i"},
460
  {0x0000200c, 0x0000700f, "sw!\t\t%8-11r, [%4-7r]"},
461
  {0x00007004, 0x00007007, "swp!\t\t%8-11r, %3-7d2"},
462
  {0x00000002, 0x3e0003ff, "syscall\t\t%10-24d"},
463
  {0x00000054, 0x3e007fff, "tcs"},
464
  {0x00000454, 0x3e007fff, "tcc"},
465
  {0x00003854, 0x3e007fff, "tcnz"},
466
  {0x00000005, 0x00007f0f, "tcs!"},
467
  {0x00000105, 0x00007f0f, "tcc!"},
468
  {0x00000e05, 0x00007f0f, "tcnz!"},
469
  {0x00001054, 0x3e007fff, "teq"},
470
  {0x00000405, 0x00007f0f, "teq!"},
471
  {0x00000854, 0x3e007fff, "tgtu"},
472
  {0x00001854, 0x3e007fff, "tgt"},
473
  {0x00002054, 0x3e007fff, "tge"},
474
  {0x00000205, 0x00007f0f, "tgtu!"},
475
  {0x00000605, 0x00007f0f, "tgt!"},
476
  {0x00000805, 0x00007f0f, "tge!"},
477
  {0x00000c54, 0x3e007fff, "tleu"},
478
  {0x00001c54, 0x3e007fff, "tle"},
479
  {0x00002454, 0x3e007fff, "tlt"},
480
  {0x0c000004, 0x3e0003ff, "stlb"},
481
  {0x0c000024, 0x3e0003ff, "mftlb"},
482
  {0x0c000044, 0x3e0003ff, "mtptlb"},
483
  {0x0c000064, 0x3e0003ff, "mtrtlb"},
484
  {0x00000305, 0x00007f0f, "tleu!"},
485
  {0x00000705, 0x00007f0f, "tle!"},
486
  {0x00000905, 0x00007f0f, "tlt!"},
487
  {0x00002854, 0x3e007fff, "tmi"},
488
  {0x00000a05, 0x00007f0f, "tmi!"},
489
  {0x00001454, 0x3e007fff, "tne"},
490
  {0x00000505, 0x00007f0f, "tne!"},
491
  {0x00002c54, 0x3e007fff, "tpl"},
492
  {0x00000b05, 0x00007f0f, "tpl!"},
493
  {0x00000004, 0x3e007fff, "trapcs\t\t%15-19d"},
494
  {0x00000404, 0x3e007fff, "trapcc\t\t%15-19d"},
495
  {0x00000804, 0x3e007fff, "trapgtu\t\t%15-19d"},
496
  {0x00000c04, 0x3e007fff, "trapleu\t\t%15-19d"},
497
  {0x00001004, 0x3e007fff, "trapeq\t\t%15-19d"},
498
  {0x00001404, 0x3e007fff, "trapne\t\t%15-19d"},
499
  {0x00001804, 0x3e007fff, "trapgt\t\t%15-19d"},
500
  {0x00001c04, 0x3e007fff, "traple\t\t%15-19d"},
501
  {0x00002004, 0x3e007fff, "trapge\t\t%15-19d"},
502
  {0x00002404, 0x3e007fff, "traplt\t\t%15-19d"},
503
  {0x00002804, 0x3e007fff, "trapmi\t\t%15-19d"},
504
  {0x00002c04, 0x3e007fff, "trappl\t\t%15-19d"},
505
  {0x00003004, 0x3e007fff, "trapvs\t\t%15-19d"},
506
  {0x00003404, 0x3e007fff, "trapvc\t\t%15-19d"},
507
  {0x00003c04, 0x3e007fff, "trap\t\t%15-19d"},
508
  {0x00003c54, 0x3e007fff, "tset"},
509
  {0x00000f05, 0x00007f0f, "tset!"},
510
  {0x00003054, 0x3e007fff, "tvs"},
511
  {0x00003454, 0x3e007fff, "tvc"},
512
  {0x00000c05, 0x00007f0f, "tvs!"},
513
  {0x00000d05, 0x00007f0f, "tvc!"},
514
  {0x00000026, 0x3e0003ff, "xor\t\t%20-24r, %15-19r, %10-14r"},
515
  {0x00000027, 0x3e0003ff, "xor.c\t\t%20-24r, %15-19r, %10-14r"},
516
  {0x00002007, 0x0000700f, "xor!\t\t%8-11r, %4-7r"}
517
};
518
 
519
typedef struct
520
{
521
  const char *name;
522
  const char *description;
523
  const char *reg_names[32];
524
} score_regname;
525
 
526
static score_regname regnames[] =
527
{
528
  {"gcc", "Select register names used by GCC",
529
  {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
530
   "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20",
531
   "r21", "r22", "r23", "r24", "r25", "r26", "r27", "gp", "r29", "r30", "r31"}},
532
};
533
 
534
static unsigned int regname_selected = 0;
535
 
536
#define NUM_SCORE_REGNAMES  NUM_ELEM (regnames)
537
#define score_regnames      regnames[regname_selected].reg_names
538
 
539
/* s3_s7: opcodes and export prototypes.  */
540
int
541
s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little);
542
 
543
/* Print one instruction from PC on INFO->STREAM.
544
   Return the size of the instruction.  */
545
static int
546
print_insn_score32 (bfd_vma pc, struct disassemble_info *info, long given)
547
{
548
  struct score_opcode *insn;
549
  void *stream = info->stream;
550
  fprintf_ftype func = info->fprintf_func;
551
 
552
  for (insn = score_opcodes; insn->assembler; insn++)
553
    {
554
      if ((insn->mask & 0xffff0000) && (given & insn->mask) == insn->value)
555
        {
556
          char *c;
557
 
558
          for (c = insn->assembler; *c; c++)
559
            {
560
              if (*c == '%')
561
                {
562
                  switch (*++c)
563
                    {
564
                    case 'j':
565
                      {
566
                        int target;
567
 
568
                        if (info->flags & INSN_HAS_RELOC)
569
                          pc = 0;
570
                        target = (pc & 0xfe000000) | (given & 0x01fffffe);
571
                        (*info->print_address_func) (target, info);
572
                      }
573
                      break;
574
                    case 'b':
575
                      {
576
                        /* Sign-extend a 20-bit number.  */
577
#define SEXT20(x)       ((((x) & 0xfffff) ^ (~ 0x7ffff)) + 0x80000)
578
                        int disp = ((given & 0x01ff8000) >> 5) | (given & 0x3fe);
579
                        int target = (pc + SEXT20 (disp));
580
 
581
                        (*info->print_address_func) (target, info);
582
                      }
583
                      break;
584
                    case '0':
585
                    case '1':
586
                    case '2':
587
                    case '3':
588
                    case '4':
589
                    case '5':
590
                    case '6':
591
                    case '7':
592
                    case '8':
593
                    case '9':
594
                      {
595
                        int bitstart = *c++ - '0';
596
                        int bitend = 0;
597
 
598
                        while (*c >= '0' && *c <= '9')
599
                          bitstart = (bitstart * 10) + *c++ - '0';
600
 
601
                        switch (*c)
602
                          {
603
                          case '-':
604
                            c++;
605
                            while (*c >= '0' && *c <= '9')
606
                              bitend = (bitend * 10) + *c++ - '0';
607
 
608
                            if (!bitend)
609
                              abort ();
610
 
611
                            switch (*c)
612
                              {
613
                              case 'r':
614
                                {
615
                                  long reg;
616
 
617
                                  reg = given >> bitstart;
618
                                  reg &= (2 << (bitend - bitstart)) - 1;
619
 
620
                                  func (stream, "%s", score_regnames[reg]);
621
                                }
622
                                break;
623
                              case 'd':
624
                                {
625
                                  long reg;
626
 
627
                                  reg = given >> bitstart;
628
                                  reg &= (2 << (bitend - bitstart)) - 1;
629
 
630
                                  func (stream, "%ld", reg);
631
                                }
632
                                break;
633
                              case 'i':
634
                                {
635
                                  long reg;
636
 
637
                                  reg = given >> bitstart;
638
                                  reg &= (2 << (bitend - bitstart)) - 1;
639
                                  reg = ((reg ^ (1 << (bitend - bitstart))) -
640
                                        (1 << (bitend - bitstart)));
641
 
642
                                  if (((given & insn->mask) == 0x0c00000a)      /* ldc1  */
643
                                      || ((given & insn->mask) == 0x0c000012)   /* ldc2  */
644
                                      || ((given & insn->mask) == 0x0c00001c)   /* ldc3  */
645
                                      || ((given & insn->mask) == 0x0c00000b)   /* stc1  */
646
                                      || ((given & insn->mask) == 0x0c000013)   /* stc2  */
647
                                      || ((given & insn->mask) == 0x0c00001b))  /* stc3  */
648
                                    reg <<= 2;
649
 
650
                                  func (stream, "%ld", reg);
651
                                }
652
                                break;
653
                              case 'x':
654
                                {
655
                                  long reg;
656
 
657
                                  reg = given >> bitstart;
658
                                  reg &= (2 << (bitend - bitstart)) - 1;
659
 
660
                                  func (stream, "%lx", reg);
661
                                }
662
                                break;
663
                              default:
664
                                abort ();
665
                              }
666
                            break;
667
                          case '`':
668
                            c++;
669
                            if ((given & (1 << bitstart)) == 0)
670
                              func (stream, "%c", *c);
671
                            break;
672
                          case '\'':
673
                            c++;
674
                            if ((given & (1 << bitstart)) != 0)
675
                              func (stream, "%c", *c);
676
                            break;
677
                          default:
678
                            abort ();
679
                          }
680
                        break;
681
                      }
682
                    default:
683
                      abort ();
684
                    }
685
                }
686
              else
687
                func (stream, "%c", *c);
688
            }
689
          return 4;
690
        }
691
    }
692
 
693
#if (SCORE_SIMULATOR_ACTIVE)
694
  func (stream, _("<illegal instruction>"));
695
  return 4;
696
#endif
697
 
698
  abort ();
699
}
700
 
701
static void
702
print_insn_parallel_sym (struct disassemble_info *info)
703
{
704
  void *stream = info->stream;
705
  fprintf_ftype func = info->fprintf_func;
706
 
707
  /* 10:       0000            nop!
708
     4 space + 1 colon + 1 space + 1 tab + 8 opcode + 2 space + 1 tab.
709
     FIXME: the space number is not accurate.  */
710
  func (stream, "%s", " ||\n      \t          \t");
711
}
712
 
713
/* Print one instruction from PC on INFO->STREAM.
714
   Return the size of the instruction.  */
715
static int
716
print_insn_score16 (bfd_vma pc, struct disassemble_info *info, long given)
717
{
718
  struct score_opcode *insn;
719
  void *stream = info->stream;
720
  fprintf_ftype func = info->fprintf_func;
721
 
722
  given &= 0xffff;
723
  for (insn = score_opcodes; insn->assembler; insn++)
724
    {
725
      if (!(insn->mask & 0xffff0000) && (given & insn->mask) == insn->value)
726
        {
727
          char *c = insn->assembler;
728
 
729
          info->bytes_per_chunk = 2;
730
          info->bytes_per_line = 4;
731
          given &= 0xffff;
732
 
733
          for (; *c; c++)
734
            {
735
              if (*c == '%')
736
                {
737
                  switch (*++c)
738
                    {
739
 
740
                    case 'j':
741
                      {
742
                        int target;
743
 
744
                        if (info->flags & INSN_HAS_RELOC)
745
                          pc = 0;
746
 
747
                        target = (pc & 0xfffff000) | (given & 0x00000ffe);
748
                        (*info->print_address_func) (target, info);
749
                      }
750
                      break;
751
                    case 'b':
752
                      {
753
                        /* Sign-extend a 9-bit number.  */
754
#define SEXT9(x)           ((((x) & 0x1ff) ^ (~ 0xff)) + 0x100)
755
                        int disp = (given & 0xff) << 1;
756
                        int target = (pc + SEXT9 (disp));
757
 
758
                        (*info->print_address_func) (target, info);
759
                      }
760
                      break;
761
 
762
                    case '0':
763
                    case '1':
764
                    case '2':
765
                    case '3':
766
                    case '4':
767
                    case '5':
768
                    case '6':
769
                    case '7':
770
                    case '8':
771
                    case '9':
772
                      {
773
                        int bitstart = *c++ - '0';
774
                        int bitend = 0;
775
 
776
                        while (*c >= '0' && *c <= '9')
777
                          bitstart = (bitstart * 10) + *c++ - '0';
778
 
779
                        switch (*c)
780
                          {
781
                          case '-':
782
                            {
783
                              long reg;
784
 
785
                              c++;
786
                              while (*c >= '0' && *c <= '9')
787
                                bitend = (bitend * 10) + *c++ - '0';
788
                              if (!bitend)
789
                                abort ();
790
                              reg = given >> bitstart;
791
                              reg &= (2 << (bitend - bitstart)) - 1;
792
                              switch (*c)
793
                                {
794
                                case 'R':
795
                                  func (stream, "%s", score_regnames[reg + 16]);
796
                                  break;
797
                                case 'r':
798
                                  func (stream, "%s", score_regnames[reg]);
799
                                  break;
800
                                case 'd':
801
                                  if (*(c + 1) == '\0')
802
                                    func (stream, "%ld", reg);
803
                                  else
804
                                    {
805
                                      c++;
806
                                      if (*c == '1')
807
                                        func (stream, "%ld", reg << 1);
808
                                      else if (*c == '2')
809
                                        func (stream, "%ld", reg << 2);
810
                                    }
811
                                  break;
812
 
813
                                case 'x':
814
                                  if (*(c + 1) == '\0')
815
                                    func (stream, "%lx", reg);
816
                                  else
817
                                    {
818
                                      c++;
819
                                      if (*c == '1')
820
                                        func (stream, "%lx", reg << 1);
821
                                      else if (*c == '2')
822
                                        func (stream, "%lx", reg << 2);
823
                                    }
824
                                  break;
825
                                case 'i':
826
                                  reg = ((reg ^ (1 << bitend)) - (1 << bitend));
827
                                  func (stream, "%ld", reg);
828
                                  break;
829
                                default:
830
                                  abort ();
831
                                }
832
                            }
833
                            break;
834
 
835
                          case '\'':
836
                            c++;
837
                            if ((given & (1 << bitstart)) != 0)
838
                              func (stream, "%c", *c);
839
                            break;
840
                          default:
841
                            abort ();
842
                          }
843
                      }
844
                      break;
845
                    default:
846
                      abort ();
847
                    }
848
                }
849
              else
850
                func (stream, "%c", *c);
851
            }
852
 
853
          return 2;
854
        }
855
    }
856
#if (SCORE_SIMULATOR_ACTIVE)
857
  func (stream, _("<illegal instruction>"));
858
  return 2;
859
#endif
860
  /* No match.  */
861
  abort ();
862
}
863
 
864
/*****************************************************************************/
865
/* s3_s7: exported functions.  */
866
 
867
/* NOTE: There are no checks in these routines that
868
   the relevant number of data bytes exist.  */
869
int
870
s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
871
{
872
  unsigned char b[4];
873
  long given;
874
  long ridparity;
875
  int status;
876
  bfd_boolean insn_pce_p = FALSE;
877
  bfd_boolean insn_16_p = FALSE;
878
 
879
  info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
880
 
881
  if (pc & 0x2)
882
    {
883
      info->bytes_per_chunk = 2;
884
      status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
885
      b[3] = b[2] = 0;
886
      insn_16_p = TRUE;
887
    }
888
  else
889
    {
890
      info->bytes_per_chunk = 4;
891
      status = info->read_memory_func (pc, (bfd_byte *) & b[0], 4, info);
892
      if (status != 0)
893
        {
894
          info->bytes_per_chunk = 2;
895
          status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
896
          b[3] = b[2] = 0;
897
          insn_16_p = TRUE;
898
        }
899
    }
900
 
901
  if (status != 0)
902
    {
903
      info->memory_error_func (status, pc, info);
904
      return -1;
905
    }
906
 
907
  if (little)
908
    {
909
      given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
910
    }
911
  else
912
    {
913
      given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
914
    }
915
 
916
  if ((given & 0x80008000) == 0x80008000)
917
    {
918
      insn_pce_p = FALSE;
919
      insn_16_p = FALSE;
920
    }
921
  else if ((given & 0x8000) == 0x8000)
922
    {
923
      insn_pce_p = TRUE;
924
    }
925
  else
926
    {
927
      insn_16_p = TRUE;
928
    }
929
 
930
  /* 16 bit instruction.  */
931
  if (insn_16_p)
932
    {
933
      if (little)
934
        {
935
          given = b[0] | (b[1] << 8);
936
        }
937
      else
938
        {
939
          given = (b[0] << 8) | b[1];
940
        }
941
 
942
      status = print_insn_score16 (pc, info, given);
943
    }
944
  /* pce instruction.  */
945
  else if (insn_pce_p)
946
    {
947
      long other;
948
 
949
      other = given & 0xFFFF;
950
      given = (given & 0xFFFF0000) >> 16;
951
 
952
      status = print_insn_score16 (pc, info, given);
953
      print_insn_parallel_sym (info);
954
      status += print_insn_score16 (pc, info, other);
955
      /* disassemble_bytes() will output 4 byte per chunk for pce instructio.  */
956
      info->bytes_per_chunk = 4;
957
    }
958
  /* 32 bit instruction.  */
959
  else
960
    {
961
      /* Get rid of parity.  */
962
      ridparity = (given & 0x7FFF);
963
      ridparity |= (given & 0x7FFF0000) >> 1;
964
      given = ridparity;
965
      status = print_insn_score32 (pc, info, given);
966
    }
967
 
968
  return status;
969
}
970
 
971
/*****************************************************************************/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.