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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<html>
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<head>
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<meta http-equiv="Content-Type" content="text/html; charset=windows-1255">
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<title>Open FreeList Readme</title>
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</head>
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<body>
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<h1>General Description</h1>
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<p>
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The Open FreeList module is used to manage a set of variable sized packets inside a fixed memory block.
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The memory block is partitioned into fixed sized chunks and each packet uses one or more chunks.
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The module offers three possible actions:
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<ol>
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<li>Write a packet into memory</li>
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<li>Read a packet from memory</li>
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<li>Release a packet</li>
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</ol>
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</p>
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<h1>Using the Module</h1>
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<h2>Parameters</h2>
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<table border="1">
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<col align="left"/>
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<col align="left"/>
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<col align="center"/>
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<col align="center"/>
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<tr>
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<th>Name</th>
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<th>Description</th>
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<th>Unit</th>
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<th>Default Value</th>
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</tr>
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<tr>
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<td>RAM_W</td>
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<td>Memory block width</td>
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<td>bits</td>
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<td>128</td>
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</tr>
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<tr>
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<td>RAM_E</td>
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<td>Memory block extra data</td>
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<td>bits</td>
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<td>0</td>
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</tr>
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<tr>
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<td>RAM_S</td>
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<td>Memory block size</td>
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<td>KBytes</td>
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<td>64</td>
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</tr>
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<tr>
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<td>CHK_S</td>
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<td>Chunk size</td>
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<td>Bytes</td>
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<td>128</td>
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</tr>
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<tr>
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<td>RAM_TYPE</td>
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<td>Memory block type</td>
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<td>string</td>
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<td>"MRAM"</td>
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</tr>
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<tr>
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<td>FL_AEMPTY_LVL</td>
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<td>FreeList almost empty level</td>
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<td>#</td>
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<td>2</td>
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</tr>
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</table>
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<h2>Interface</h2>
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<table border="1">
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<col align="left"/>
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<col align="center"/>
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<col align="center"/>
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<col align="left"/>
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<tr>
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<th>Name</th>
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<th>Direction</th>
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<th>Width</th>
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<th>Description</th>
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</tr>
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<tr>
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<td colspan="4" align="center"><b>global signals</b></td>
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</tr>
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<tr>
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<td>reset_n</td>
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<td>input</td>
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<td>1</td>
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<td>async reset (active low)</td>
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</tr>
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<tr>
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<td>clk</td>
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<td>input</td>
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<td>1</td>
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<td>clock</td>
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</tr>
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<tr>
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<td colspan="4" align="center"><b>write interface</b></td>
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</tr>
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<tr>
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<td>fl_q</td>
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<td>output</td>
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<td>clog(#_of_chunks)</td>
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<td>first chunk number for a new packet.<br />capture this value and use it to read/release the packet</td>
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</tr>
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<tr>
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<td>fl_aempty</td>
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<td>output</td>
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<td>1</td>
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<td>indicates that the number of chunks reached the almost empty level</td>
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</tr>
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<tr>
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<td>fl_empty</td>
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<td>output</td>
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<td>1</td>
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<td>no more chunks available. do not write any more</td>
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</tr>
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<tr>
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<td>wren</td>
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<td>input</td>
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<td>1</td>
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<td>write pulse. writes the data on din into the memory block</td>
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</tr>
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<tr>
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<td>din</td>
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<td>input</td>
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<td>RAM_W+RAM_E</td>
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<td>data to write into memory block</td>
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</tr>
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<tr>
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<td>eop</td>
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<td>input</td>
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<td>1</td>
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<td>end-of-packet indication. assert on last write of packet</td>
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</tr>
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<tr>
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<td colspan="4" align="center"><b>read interface</b></td>
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</tr>
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<tr>
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<td>chunk_num</td>
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<td>input</td>
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<td>clog(#_of_chunks)</td>
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<td>first chunk in a packet to be read or released</td>
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</tr>
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<tr>
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<td>load_req</td>
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<td>input</td>
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<td>1</td>
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<td>request to read a packet starting at chunk number 'chunk_num'</td>
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</tr>
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<tr>
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<td>rel_req</td>
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<td>input</td>
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<td>1</td>
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<td>request to release a packet starting at chunk number 'chunk_num'.<br />also required after a packet is read</td>
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</tr>
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<tr>
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<td>load_rel_ack</td>
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<td>output</td>
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<td>1</td>
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<td>acknowledge a read or release request</td>
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</tr>
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<tr>
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<td>rden</td>
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<td>input</td>
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<td>1</td>
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<td>read request. data on 'dout' is valid one clock later</td>
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</tr>
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<tr>
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<td>dout</td>
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<td>output</td>
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<td>RAM_W+RAM_E</td>
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<td>data read from memory block</td>
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</tr>
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</table>
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<h2>Operations</h2>
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<h3>Write</h3>
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<p>
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To write a packet, do the following:
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<ul>
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<li>make sure 'fl_empty' is de-asserted</li>
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<li>capture the value on 'fl_q'. it will be used later to reference this packet</li>
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<li>while 'fl_empty' is not asserted do:</li>
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<ul>
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<li>write the next data line in 'din'</li>
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<li>assert 'wren'</li>
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<li>on the last line of the packet, assert 'eop' as well</li>
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</ul>
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</ul>
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</p>
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<h3>Read</h3>
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<p>
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To read a packet that was previously written, do the following:
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<ul>
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<li>set 'chunk_num' to the value of the first chunk in the packet.<br />
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this value was obtained from 'fl_q' when the packet was written</li>
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<li>assert 'load_req'</li>
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<li>when 'load_rel_ack' is asserted, for each line of data do:</li>
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<ul>
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<li>assert 'rden'</li>
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<li>capture 'dout' one cycle later</li>
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</ul>
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</ul>
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To determine the last line of data, you could:
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<ul>
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<li>store the packet length in an external structure</li>
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<li>use the extra bits in the memory block to hold an indication such as end-of-packet</li>
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</ul>
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</p>
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<p>
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Note that the 'eop' indication that is written in the write operation is not available on a read operation.
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</p>
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<p>
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<i>Important:</i> after a read is complete, a release operation must be explicitly performed.
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There is no need to set the 'chunk_num' value after a read operation.
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The chunks are released when the packet is read, but the last chunk requires an explicit release operation.
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</p>
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<h3>Release</h3>
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<p>A packet can be released under two circumstances:
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<ol>
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<li>when a read is complete, a release must be issued</li>
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<li>if a packet is not needed, it can be released without reading it</li>
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</ol>
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To release a packet, do the following:
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<ul>
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<li>set 'chunk_num' to the first chunk of the packet (not required after a read)</li>
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<li>assert 'rel_req'</li>
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<li>when 'load_rel_ack' is asserted, you are done</li>
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</ul>
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</p>
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<h2>Memories</h2>
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<p>
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Three memories are used in this module:
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<ol>
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<li>ram - dual port memory. two cycles to read</li>
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<li>free_list - single clock lookahead FIFO</li>
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<li>link_list - dual port memory. two cycles to read</li>
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</ol>
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The target architecture is Altera Sratix. There should be matching memory blocks in other architectures.
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</p>
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<p><br /><br /></p>
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<p>
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Code: Alex Manash - Crescendo Networks<br />
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Docs: Amit Fridman - Crescendo Networks
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</p>
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</body>
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</html>
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