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amif2000 |
/*******************************************************************************
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MODULE NAME: altsyncram3
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DESCRIPTION
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This module is a parametrized dual port ram with a registered output port
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It is optional to define it's input address and output address and it's
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depth.
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REVISION HISTORY
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05FEB03 First Created -ac-
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*******************************************************************************/
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module altsyncram3
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(
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data,
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byteena,
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rd_aclr,
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rdaddress,
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rdclock,
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rdclocken,
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rden,
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wraddress,
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wrclock,
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wrclocken,
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wren,
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q);
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parameter A_WIDTH = 288;
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parameter A_WIDTHAD = 9;
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parameter B_WIDTH = A_WIDTH;
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parameter B_WIDTHAD = A_WIDTHAD;
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parameter A_NUMWORDS = 1<<A_WIDTHAD;
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parameter B_NUMWORDS = 1<<B_WIDTHAD;
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parameter RAM_TYPE = "AUTO";
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parameter BYTE_ENA = 1;
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parameter USE_RDEN = 1;
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parameter TYPE = RAM_TYPE == "M4K" | RAM_TYPE == "M9K"? "M9K":
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RAM_TYPE == "M512" | RAM_TYPE == "MLAB"? "MLAB":
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RAM_TYPE == "M-RAM" | RAM_TYPE == "M144K"? "M144K":
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"AUTO";
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parameter REG_B = "CLOCK1";
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input [A_WIDTH-1:0] data;
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input [BYTE_ENA-1 :0] byteena;
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input rd_aclr;
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input [B_WIDTHAD-1:0] rdaddress;
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input rdclock;
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input rdclocken;
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input rden;
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input [A_WIDTHAD-1:0] wraddress;
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input wrclock;
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input wrclocken;
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input wren;
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output [B_WIDTH-1:0] q;
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wire [B_WIDTH-1:0] sub_wire0;
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wire [B_WIDTH-1:0] q = sub_wire0[B_WIDTH-1:0];
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wire [BYTE_ENA-1 :0] byteena_wire = BYTE_ENA==1 ? 1'b1 : byteena;
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wire rden_wire = USE_RDEN ? rden : 1'b1;
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altsyncram altsyncram_component (
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.clocken0(wrclocken),
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.clocken1(rdclocken),
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.wren_a(wren),
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.clock0(wrclock),
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.aclr1 (rd_aclr),
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.clock1(rdclock),
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.address_a(wraddress),
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.address_b(rdaddress),
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.rden_b(rden_wire),
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.data_a(data),
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.q_b(sub_wire0),
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.aclr0 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (byteena_wire),
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.byteena_b (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({B_WIDTH{1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.address_aclr_b = "CLEAR1",
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altsyncram_component.address_reg_b = "CLOCK1",
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altsyncram_component.clock_enable_input_a = "NORMAL",
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altsyncram_component.clock_enable_input_b = "NORMAL",
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altsyncram_component.clock_enable_output_b = "NORMAL",
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altsyncram_component.intended_device_family = "Stratix III",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = A_NUMWORDS,
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altsyncram_component.numwords_b = B_NUMWORDS,
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altsyncram_component.operation_mode = "DUAL_PORT",
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altsyncram_component.outdata_aclr_b = "CLEAR1",
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altsyncram_component.outdata_reg_b = REG_B,
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.ram_block_type = TYPE,
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altsyncram_component.rdcontrol_reg_b = "CLOCK1",
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altsyncram_component.widthad_a = A_WIDTHAD,
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altsyncram_component.widthad_b = B_WIDTHAD,
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altsyncram_component.width_a = A_WIDTH,
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altsyncram_component.width_b = B_WIDTH,
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altsyncram_component.width_byteena_a = BYTE_ENA;
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endmodule // altsyncram3
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