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[/] [open_free_list/] [trunk/] [sim/] [tb_open_free_list.v] - Blame information for rev 2

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`timescale 1ns/1ps
 
module tb_open_free_list;
 
reg                     reset_n;
reg                     clk;
wire      [8:0]  fl_q;
wire                    fl_aempty;
wire                    fl_empty;
reg                             wren;
reg          [71:0] din;
reg                             eop;
reg               [8:0] chunk_num;
reg                             load_req;
reg                             rel_req;
wire                    load_rel_ack;
reg                             rden;
wire     [71:0] dout;
 
reg       [8:0] pkt1_chunk;
reg       [8:0] pkt2_chunk;
reg       [8:0] pkt3_chunk;
 
open_free_list open_free_list(
  .reset_n(reset_n),
  .clk(clk),
  .fl_q(fl_q),
  .fl_aempty(fl_aempty),
  .fl_empty(fl_empty),
  .wren(wren),
  .din(din),
  .eop(eop),
  .chunk_num(chunk_num),
  .load_req(load_req),
  .rel_req(rel_req),
  .load_rel_ack(load_rel_ack),
  .rden(rden),
  .dout(dout)
);
defparam
        open_free_list.RAM_W = 64,
        open_free_list.RAM_E = 8;
 
initial // reset
begin
    reset_n <= 1'b0;
    #1000 reset_n <= 1'b1;
end
 
initial // clock
        clk <= 1'b0;
always
        #5 clk <= ~clk;
 
initial // init all signals
begin
    wren      <= 1'b0;
    din       <= 72'b0;
    eop       <= 1'b0;
    chunk_num <= 9'b0;
    load_req  <= 1'b0;
    rel_req   <= 1'b0;
    rden      <= 1'b0;
end
 
initial // test
begin
    #2000;
    @(posedge clk);
 
    // write a short packet
    pkt1_chunk <= fl_q;
    din <= 72'h000001020304050607;
    wren <= 1'b1;
    @(posedge clk);
    din <= 72'h0108090a0b0c0d0e0f;
    eop <= 1'b1;
    @(posedge clk);
    wren <= 1'b0;
    eop <= 1'b0;
 
    #1000;
    @(posedge clk);
 
    // write a longer packet
    pkt2_chunk <= fl_q;
    din <= 72'h800001020304050607;
    wren <= 1'b1;
    @(posedge clk);
    din <= 72'h8008090a0b0c0d0e0f;
    @(posedge clk);
    din <= 72'h801011121314151617;
    @(posedge clk);
    din <= 72'h8018191a1b1c1d1e1f;
    @(posedge clk);
    din <= 72'h802021222324252627;
    @(posedge clk);
    din <= 72'h8028292a2b2c2d2e2f;
    @(posedge clk);
    din <= 72'h803031323334353637;
    @(posedge clk);
    din <= 72'h8038393a3b3c3d3e3f;
    @(posedge clk);
    din <= 72'h804041424344454647;
    @(posedge clk);
    din <= 72'h8048494a4b4c4d4e4f;
    @(posedge clk);
    din <= 72'h805051525354555657;
    @(posedge clk);
    din <= 72'h8058595a5b5c5d5e5f;
    @(posedge clk);
    din <= 72'h806061626364656667;
    @(posedge clk);
    din <= 72'h8068696a6b6c6d6e6f;
    @(posedge clk);
    din <= 72'h807071727374757677;
    @(posedge clk);
    din <= 72'h8078797a7b7c7d7e7f;
    @(posedge clk);
    din <= 72'h818081828384858687;
    eop <= 1'b1;
    @(posedge clk);
    wren <= 1'b0;
    eop <= 1'b0;
 
    #1000;
    @(posedge clk);
 
    // read the first packet
    chunk_num <= pkt1_chunk;
    load_req <= 1'b1;
    @(posedge load_rel_ack);
    load_req <= 1'b0;
    @(posedge clk);
    rden <= 1'b1;
    @(posedge clk);
    @(posedge clk);
    rden <= 1'b0;
    rel_req <= 1'b1;
    @(posedge load_rel_ack);
    rel_req <= 1'b0;
 
    #1000;
    @(posedge clk);
 
    // write a 3rd packet (short)
    pkt3_chunk <= fl_q;
    din <= 72'hc00001020304050607;
    wren <= 1'b1;
    @(posedge clk);
    din <= 72'hc108090a0b0c0d0e0f;
    eop <= 1'b1;
    @(posedge clk);
    wren <= 1'b0;
    eop <= 1'b0;
 
    #1000;
    @(posedge clk);
 
    // release the third packet without reading
    chunk_num <= pkt3_chunk;
    rel_req <= 1'b1;
    @(posedge load_rel_ack);
    rel_req <= 1'b0;
 
    #1000;
    @(posedge clk);
 
    // read a few lines of packet 2 and then release it
    chunk_num <= pkt2_chunk;
    load_req <= 1'b1;
    @(posedge load_rel_ack);
    load_req <= 1'b0;
    @(posedge clk);
    rden <= 1'b1;
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    rden <= 1'b0;
    rel_req <= 1'b1;
    @(posedge load_rel_ack);
    rel_req <= 1'b0;
end
 
endmodule // tb_open_free_list

Line No.	Rev	Author	Line
1	2	amif2000	`timescale 1ns/1ps
2
3			`module tb_open_free_list;`
4
5			`reg reset_n;`
6			`reg clk;`
7			`wire [8:0] fl_q;`
8			`wire fl_aempty;`
9			`wire fl_empty;`
10			`reg wren;`
11			`reg [71:0] din;`
12			`reg eop;`
13			`reg [8:0] chunk_num;`
14			`reg load_req;`
15			`reg rel_req;`
16			`wire load_rel_ack;`
17			`reg rden;`
18			`wire [71:0] dout;`
19
20			`reg [8:0] pkt1_chunk;`
21			`reg [8:0] pkt2_chunk;`
22			`reg [8:0] pkt3_chunk;`
23
24			`open_free_list open_free_list(`
25			`.reset_n(reset_n),`
26			`.clk(clk),`
27			`.fl_q(fl_q),`
28			`.fl_aempty(fl_aempty),`
29			`.fl_empty(fl_empty),`
30			`.wren(wren),`
31			`.din(din),`
32			`.eop(eop),`
33			`.chunk_num(chunk_num),`
34			`.load_req(load_req),`
35			`.rel_req(rel_req),`
36			`.load_rel_ack(load_rel_ack),`
37			`.rden(rden),`
38			`.dout(dout)`
39			`);`
40			`defparam`
41			`open_free_list.RAM_W = 64,`
42			`open_free_list.RAM_E = 8;`
43
44			`initial // reset`
45			`begin`
46			`reset_n <= 1'b0;`
47			`#1000 reset_n <= 1'b1;`
48			`end`
49
50			`initial // clock`
51			`clk <= 1'b0;`
52			`always`
53			`#5 clk <= ~clk;`
54
55			`initial // init all signals`
56			`begin`
57			`wren <= 1'b0;`
58			`din <= 72'b0;`
59			`eop <= 1'b0;`
60			`chunk_num <= 9'b0;`
61			`load_req <= 1'b0;`
62			`rel_req <= 1'b0;`
63			`rden <= 1'b0;`
64			`end`
65
66			`initial // test`
67			`begin`
68			`#2000;`
69			`@(posedge clk);`
70
71			`// write a short packet`
72			`pkt1_chunk <= fl_q;`
73			`din <= 72'h000001020304050607;`
74			`wren <= 1'b1;`
75			`@(posedge clk);`
76			`din <= 72'h0108090a0b0c0d0e0f;`
77			`eop <= 1'b1;`
78			`@(posedge clk);`
79			`wren <= 1'b0;`
80			`eop <= 1'b0;`
81
82			`#1000;`
83			`@(posedge clk);`
84
85			`// write a longer packet`
86			`pkt2_chunk <= fl_q;`
87			`din <= 72'h800001020304050607;`
88			`wren <= 1'b1;`
89			`@(posedge clk);`
90			`din <= 72'h8008090a0b0c0d0e0f;`
91			`@(posedge clk);`
92			`din <= 72'h801011121314151617;`
93			`@(posedge clk);`
94			`din <= 72'h8018191a1b1c1d1e1f;`
95			`@(posedge clk);`
96			`din <= 72'h802021222324252627;`
97			`@(posedge clk);`
98			`din <= 72'h8028292a2b2c2d2e2f;`
99			`@(posedge clk);`
100			`din <= 72'h803031323334353637;`
101			`@(posedge clk);`
102			`din <= 72'h8038393a3b3c3d3e3f;`
103			`@(posedge clk);`
104			`din <= 72'h804041424344454647;`
105			`@(posedge clk);`
106			`din <= 72'h8048494a4b4c4d4e4f;`
107			`@(posedge clk);`
108			`din <= 72'h805051525354555657;`
109			`@(posedge clk);`
110			`din <= 72'h8058595a5b5c5d5e5f;`
111			`@(posedge clk);`
112			`din <= 72'h806061626364656667;`
113			`@(posedge clk);`
114			`din <= 72'h8068696a6b6c6d6e6f;`
115			`@(posedge clk);`
116			`din <= 72'h807071727374757677;`
117			`@(posedge clk);`
118			`din <= 72'h8078797a7b7c7d7e7f;`
119			`@(posedge clk);`
120			`din <= 72'h818081828384858687;`
121			`eop <= 1'b1;`
122			`@(posedge clk);`
123			`wren <= 1'b0;`
124			`eop <= 1'b0;`
125
126			`#1000;`
127			`@(posedge clk);`
128
129			`// read the first packet`
130			`chunk_num <= pkt1_chunk;`
131			`load_req <= 1'b1;`
132			`@(posedge load_rel_ack);`
133			`load_req <= 1'b0;`
134			`@(posedge clk);`
135			`rden <= 1'b1;`
136			`@(posedge clk);`
137			`@(posedge clk);`
138			`rden <= 1'b0;`
139			`rel_req <= 1'b1;`
140			`@(posedge load_rel_ack);`
141			`rel_req <= 1'b0;`
142
143			`#1000;`
144			`@(posedge clk);`
145
146			`// write a 3rd packet (short)`
147			`pkt3_chunk <= fl_q;`
148			`din <= 72'hc00001020304050607;`
149			`wren <= 1'b1;`
150			`@(posedge clk);`
151			`din <= 72'hc108090a0b0c0d0e0f;`
152			`eop <= 1'b1;`
153			`@(posedge clk);`
154			`wren <= 1'b0;`
155			`eop <= 1'b0;`
156
157			`#1000;`
158			`@(posedge clk);`
159
160			`// release the third packet without reading`
161			`chunk_num <= pkt3_chunk;`
162			`rel_req <= 1'b1;`
163			`@(posedge load_rel_ack);`
164			`rel_req <= 1'b0;`
165
166			`#1000;`
167			`@(posedge clk);`
168
169			`// read a few lines of packet 2 and then release it`
170			`chunk_num <= pkt2_chunk;`
171			`load_req <= 1'b1;`
172			`@(posedge load_rel_ack);`
173			`load_req <= 1'b0;`
174			`@(posedge clk);`
175			`rden <= 1'b1;`
176			`@(posedge clk);`
177			`@(posedge clk);`
178			`@(posedge clk);`
179			`@(posedge clk);`
180			`rden <= 1'b0;`
181			`rel_req <= 1'b1;`
182			`@(posedge load_rel_ack);`
183			`rel_req <= 1'b0;`
184			`end`
185
186			`endmodule // tb_open_free_list`

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[/] [open_free_list/] [trunk/] [sim/] [tb_open_free_list.v] - Blame information for rev 2