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--////////////////////////////////////////////////////////////////////

--//                                                              ////

--// search_item.vhd                                              ////

--//                                                              ////

--// This file is part of the open_hitter opencores effort.       ////

--// <http://www.opencores.org/cores/open_hitter/>                ////

--//                                                              ////

--// Module Description:                                          ////

--// Simulation program (non-synthesizable)                       ////

--// Drives auto regression tests via NSEW button actions and     ////

--// NSEW LED reporting                                           ////

--// target env: ghdl <attrib required>                           ////

--//                                                              ////

--// To Do:                                                       ////

--//                                                              ////

--// Author(s):                                                   ////

--// - Stephen Hawes                                              ////

--//                                                              ////

--////////////////////////////////////////////////////////////////////

--//                                                              ////

--// Copyright (C) 2015 Stephen Hawes and OPENCORES.ORG           ////

--//                                                              ////

--// This source file may be used and distributed without         ////

--// restriction provided that this copyright statement is not    ////

--// removed from the file and that any derivative work contains  ////

--// the original copyright notice and the associated disclaimer. ////

--//                                                              ////

--// This source file is free software; you can redistribute it   ////

--// and/or modify it under the terms of the GNU Lesser General   ////

--// Public License as published by the Free Software Foundation; ////

--// either version 2.1 of the License, or (at your option) any   ////

--// later version.                                               ////

--//                                                              ////

--// This source is distributed in the hope that it will be       ////

--// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

--// PURPOSE. See the GNU Lesser General Public License for more  ////

--// details.                                                     ////

--//                                                              ////

--// You should have received a copy of the GNU Lesser General    ////

--// Public License along with this source; if not, download it   ////

--// from <http://www.opencores.org/lgpl.shtml>                   ////

--//                                                              ////

--////////////////////////////////////////////////////////////////////

--//

--// \$Id\$  TAKE OUT THE \'s and this comment in order to get this to work

--//

--// CVS Revision History

--//

--// \$Log\$  TAKE OUT THE \'s and this comment in order to get this to work

--//

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.ALL;

use std.textio.all; --  Imports the standard textio package.

entity search_item_wrapper is

end search_item_wrapper;

architecture behaviour of search_item_wrapper is

   component search_item

   port (

        RX_CLK: in std_logic;

        -- control flag(s) on the incoming bus

           b1_px_valid: in std_logic;

        -- pxdata: in price_packet

           b1_px_type: in std_logic_vector(4 downto 0);

           b1_buy_sell: in std_logic_vector(2 downto 0);   -- 111 buy, 000 sell

           b1_px: in std_logic_vector(15 downto 0);     -- price

           b1_qty: in std_logic_vector(15 downto 0);    -- quantity

           b1_sec: in std_logic_vector(55 downto 0);    -- 7x 8bits securities identifier

           b1_id: in std_logic_vector(15 downto 0);    -- unique/identifier/counter

        -- pxdata: out price_packet

           b2_px_type: out std_logic_vector(4 downto 0);

           b2_buy_sell: out std_logic_vector(2 downto 0);   -- 111 buy, 000 sell

           b2_px: out std_logic_vector(15 downto 0);     -- price

           b2_qty: out std_logic_vector(15 downto 0);    -- quantity

           b2_sec: out std_logic_vector(55 downto 0);    -- 7x 8bits securities identifier

           b2_id: out std_logic_vector(15 downto 0)      -- unique/identifier/counter

   );

   end component;

   for search_item_0: search_item use entity work.search_item;

        signal RX_CLK: std_logic;

        -- control flag(s) on the incoming bus

           signal b1_px_valid: std_logic;

        -- pxdata: in price_packet

           signal b1_px_type: std_logic_vector(4 downto 0);

           signal b1_buy_sell: std_logic_vector(2 downto 0);   -- 111 buy, 000 sell

           signal b1_px: std_logic_vector(15 downto 0);     -- price

           signal b1_qty: std_logic_vector(15 downto 0);    -- quantity

           signal b1_sec: std_logic_vector(55 downto 0);    -- 7x 8bits securities identifier

           signal b1_id: std_logic_vector(15 downto 0);    -- unique/identifier/counter

        -- pxdata: out price_packet

           signal b2_px_type: std_logic_vector(4 downto 0);

           signal b2_buy_sell: std_logic_vector(2 downto 0);   -- 111 buy, 000 sell

           signal b2_px: std_logic_vector(15 downto 0);     -- price

           signal b2_qty: std_logic_vector(15 downto 0);    -- quantity

           signal b2_sec: std_logic_vector(55 downto 0);    -- 7x 8bits securities identifier

           signal b2_id: std_logic_vector(15 downto 0);     -- unique/identifier/counter

   begin

        search_item_0: search_item port map (

           RX_CLK => RX_CLK,

           -- control flag(s) on the incoming bus

              b1_px_valid => b1_px_valid,

           -- pxdata: in price_packet

              b1_px_type => b1_px_type,

              b1_buy_sell => b1_buy_sell,

              b1_px => b1_px,

              b1_qty => b1_qty,

              b1_sec => b1_sec,

              b1_id => b1_id,

           -- pxdata: out price_packet

              b2_px_type => b2_px_type,

              b2_buy_sell => b2_buy_sell,

              b2_px => b2_px,

              b2_qty => b2_qty,

              b2_sec => b2_sec,

              b2_id => b2_id

           );

   process

        variable l : line;

        type input_pattern_type is record

           -- control flag(s) on the incoming bus

              b1_px_valid: std_logic;

           -- pxdata: in price_packet

              b1_px_type: std_logic_vector(4 downto 0);

              b1_buy_sell: std_logic_vector(2 downto 0);   -- 111 buy, 000 sell

              b1_px: std_logic_vector(15 downto 0);     -- price

              b1_qty: std_logic_vector(15 downto 0);    -- quantity

              b1_sec: std_logic_vector(55 downto 0);    -- 7x 8bits securities identifier

              b1_id: std_logic_vector(15 downto 0);    -- unique/identifier/counter

         end record;

         type output_pattern_type is record

            -- pxdata: out price_packet

              b2_px_type: std_logic_vector(4 downto 0);

              b2_buy_sell: std_logic_vector(2 downto 0);   -- 111 buy, 000 sell

              b2_px: std_logic_vector(15 downto 0);     -- price

              b2_qty: std_logic_vector(15 downto 0);    -- quantity

              b2_sec: std_logic_vector(55 downto 0);    -- 7x 8bits securities identifier

              b2_id: std_logic_vector(15 downto 0);      -- unique/identifier/counter

         end record;

         --  The patterns to apply.

         constant px1: std_logic_vector(15 downto 0) := (others => 'Z');

         constant qty1: std_logic_vector(15 downto 0) := (others => 'Z');

         constant sec1: std_logic_vector(55 downto 0) := (others => 'Z');

         constant id1: std_logic_vector(15 downto 0) := (others => 'Z');

         type input_pattern_array is array (natural range <>) of input_pattern_type;

--           constant input_patterns : input_pattern_array :=

--             ( ('0', std_logic_vector'("ZZZZ"), std_logic_vector'("ZZZ"), px1, qty1, sec1, id1),

--               ('0', std_logic_vector'("ZZZZ"), std_logic_vector'("ZZZ"), px1, qty1, sec1, id1) );

         type output_pattern_array is array (natural range <>) of output_pattern_type;

--           constant output_patterns : output_pattern_array :=

--             ( (std_logic_vector'("ZZZZ"), std_logic_vector'("ZZZ"), (others => 'Z'), (others => 'Z'), (others => 'Z'), (others => 'Z')),

--               (std_logic_vector'("ZZZZ"), std_logic_vector'("ZZZ"), (others => 'Z'), (others => 'Z'), (others => 'Z'), (others => 'Z')) );

   begin

        write (l, String'("Exercising search_item"));

        writeline (output, l);

           --  Check each pattern.

       --    for i in patterns'range loop

              --  Set the inputs.

       --       i0 <= patterns(i).i0;

       --       i1 <= patterns(i).i1;

       --       ci <= patterns(i).ci;

              --  Wait for the results.

       --       wait for 1 ns;

              --  Check the outputs.

       --       assert s = patterns(i).s

       --          report "bad sum value" severity error;

       --       assert co = patterns(i).co

      --           report "bad carray out value" severity error;

       --    end loop;

      --     assert false report "end of test" severity note;

           --  Wait forever; this will finish the simulation.

      --     wait;

        write (l, String'("Done search_item"));

        writeline (output, l);

        wait;

        end process;

     end behaviour;