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[/] [openarty/] [trunk/] [arty.xdc] - Blame information for rev 5

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1 5 dgisselq 
## This file is a general .xdc for the ARTY Rev. B
2 
## To use it in a project:
3 
## - uncomment the lines corresponding to used pins
4 
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
5 
 
6 
# Config setup
7 
set_property CFGBVS VCCO [current_design]
8 
set_property CONFIG_VOLTAGE 3.3 [current_design]
9 
 
10 
## Clock signal
11 
 
12 
set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { i_clk_100mhz }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
13 
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { i_clk_100mhz }];
14 
 
15 
##Switches
16 
 
17 
set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { i_sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
18 
set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { i_sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
19 
set_property -dict { PACKAGE_PIN C10   IOSTANDARD LVCMOS33 } [get_ports { i_sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
20 
set_property -dict { PACKAGE_PIN A10   IOSTANDARD LVCMOS33 } [get_ports { i_sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
21 
 
22 
##RGB LEDs
23 
 
24 
set_property -dict { PACKAGE_PIN E1    IOSTANDARD LVCMOS33 } [get_ports { o_clr_led0[0] }]; #IO_L18N_T2_35 Sch=led0_b
25 
set_property -dict { PACKAGE_PIN F6    IOSTANDARD LVCMOS33 } [get_ports { o_clr_led0[1] }]; #IO_L19N_T3_VREF_35 Sch=led0_g
26 
set_property -dict { PACKAGE_PIN G6    IOSTANDARD LVCMOS33 } [get_ports { o_clr_led0[2] }]; #IO_L19P_T3_35 Sch=led0_r
27 
set_property -dict { PACKAGE_PIN G4    IOSTANDARD LVCMOS33 } [get_ports { o_clr_led1[0] }]; #IO_L20P_T3_35 Sch=led1_b
28 
set_property -dict { PACKAGE_PIN J4    IOSTANDARD LVCMOS33 } [get_ports { o_clr_led1[1] }]; #IO_L21P_T3_DQS_35 Sch=led1_g
29 
set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { o_clr_led1[2] }]; #IO_L20N_T3_35 Sch=led1_r
30 
set_property -dict { PACKAGE_PIN H4    IOSTANDARD LVCMOS33 } [get_ports { o_clr_led2[0] }]; #IO_L21N_T3_DQS_35 Sch=led2_b
31 
set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { o_clr_led2[1] }]; #IO_L22N_T3_35 Sch=led2_g
32 
set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { o_clr_led2[2] }]; #IO_L22P_T3_35 Sch=led2_r
33 
set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { o_clr_led3[0] }]; #IO_L23P_T3_35 Sch=led3_b
34 
set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { o_clr_led3[1] }]; #IO_L24P_T3_35 Sch=led3_g
35 
set_property -dict { PACKAGE_PIN K1    IOSTANDARD LVCMOS33 } [get_ports { o_clr_led3[2] }]; #IO_L23N_T3_35 Sch=led3_r
36 
 
37 
##LEDs
38 
 
39 
set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports { o_led[0] }]; #IO_L24N_T3_35 Sch=led[4]
40 
set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS33 } [get_ports { o_led[1] }]; #IO_25_35 Sch=led[5]
41 
set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { o_led[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
42 
set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { o_led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
43 
 
44 
##Buttons
45 
 
46 
set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { i_btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
47 
set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS33 } [get_ports { i_btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
48 
set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS33 } [get_ports { i_btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
49 
set_property -dict { PACKAGE_PIN B8    IOSTANDARD LVCMOS33 } [get_ports { i_btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
50 
 
51 
##Pmod Header JA: PModCLS (bottom)
52 
 
53 
#set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1]
54 
#set_property -dict { PACKAGE_PIN B11   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2]
55 
#set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L4N_T0_15 Sch=ja[3]
56 
#set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L6P_T0_15 Sch=ja[4]
57 
#-- set_property -dict { PACKAGE_PIN D13   IOSTANDARD LVCMOS33 } [get_ports { o_cls_ss_n }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
58 
#-- set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { o_cls_mosi }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
59 
#-- set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { i_cls_miso }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
60 
#-- set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { o_cls_sck }]; #IO_25_15 Sch=ja[10]
61 
 
62 
##Pmod Header JB: OLEDrgb
63 
 
64 
set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { o_oled_cs_n }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
65 
set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { o_oled_mosi }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
66 
#set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { i_oled_nc }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
67 
set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { o_oled_sck }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
68 
set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { o_oled_dcn }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
69 
set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { o_oled_reset_n }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
70 
set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { o_oled_vccen }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
71 
set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { o_oled_pmoden }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
72 
 
73 
##Pmod Header JC: GPS (top), UART (bottom)
74 
 
75 
set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { i_gps_3df }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
76 
set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { o_gps_tx }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
77 
set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { i_gps_rx }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
78 
set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { i_gps_pps }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
79 
set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { i_aux_rts }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
80 
set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { o_aux_tx }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
81 
set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { i_aux_rx }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
82 
set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { o_aux_cts }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
83 
 
84 
##Pmod Header JD: SD-Card
85 
 
86 
set_property -dict { PACKAGE_PIN D4    IOSTANDARD LVCMOS33 } [get_ports { io_sd[3] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
87 
set_property -dict { PACKAGE_PIN D3    IOSTANDARD LVCMOS33 } [get_ports { io_sd_cmd }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
88 
set_property -dict { PACKAGE_PIN F4    IOSTANDARD LVCMOS33 } [get_ports { io_sd[0] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
89 
set_property -dict { PACKAGE_PIN F3    IOSTANDARD LVCMOS33 } [get_ports { o_sd_sck }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
90 
set_property -dict { PACKAGE_PIN E2    IOSTANDARD LVCMOS33 } [get_ports { io_sd[1] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
91 
set_property -dict { PACKAGE_PIN D2    IOSTANDARD LVCMOS33 } [get_ports { io_sd[2] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
92 
set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { i_sd_cs }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
93 
set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { i_sd_wp }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
94 
 
95 
##USB-UART Interface
96 
# THESE ARE CORRECT
97 
set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { o_uart_tx }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
98 
set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { i_uart_rx }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
99 
#
100 
 
101 
##ChipKit Single Ended Analog Inputs
102 
##NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5).
103 
##      These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins ck_io[14-19].
104 
 
105 
#set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0]
106 
#set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0]
107 
#set_property -dict { PACKAGE_PIN A5    IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1]
108 
#set_property -dict { PACKAGE_PIN A6    IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[1] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1]
109 
#set_property -dict { PACKAGE_PIN B4    IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[2] }]; #IO_L7N_T1_AD6N_35 Sch=ck_an_n[2]
110 
#set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[2] }]; #IO_L7P_T1_AD6P_35 Sch=ck_an_p[2]
111 
#set_property -dict { PACKAGE_PIN A1    IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[3] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3]
112 
#set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[3] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3]
113 
#set_property -dict { PACKAGE_PIN B2    IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[4] }]; #IO_L10N_T1_AD15N_35 Sch=ck_an_n[4]
114 
#set_property -dict { PACKAGE_PIN B3    IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[4] }]; #IO_L10P_T1_AD15P_35 Sch=ck_an_p[4]
115 
#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[5] }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[5]
116 
#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[5] }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[5]
117 
 
118 
##ChipKit Digital I/O Low
119 
 
120 
#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { ck_io[0] }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
121 
#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { ck_io[1] }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
122 
#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { ck_io[2] }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
123 
#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { ck_io[3] }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
124 
#set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { ck_io[4] }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
125 
#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { ck_io[5] }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
126 
#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { ck_io[6] }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
127 
#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { ck_io[7] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
128 
#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { ck_io[8] }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8]
129 
#set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { ck_io[9] }]; #IO_L10P_T1_D14_14 Sch=ck_io[9]
130 
#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { ck_io[10] }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10]
131 
#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { ck_io[11] }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11]
132 
#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ck_io[12] }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12]
133 
#set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { ck_io[13] }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13]
134 
 
135 
##ChipKit Digital I/O On Outer Analog Header
136 
##NOTE: These pins should be used when using the analog header signals A0-A5 as digital I/O (Chipkit digital pins 14-19)
137 
 
138 
#set_property -dict { PACKAGE_PIN F5    IOSTANDARD LVCMOS33 } [get_ports { ck_io[14] }]; #IO_0_35 Sch=ck_a[0]
139 
#set_property -dict { PACKAGE_PIN D8    IOSTANDARD LVCMOS33 } [get_ports { ck_io[15] }]; #IO_L4P_T0_35 Sch=ck_a[1]
140 
#set_property -dict { PACKAGE_PIN C7    IOSTANDARD LVCMOS33 } [get_ports { ck_io[16] }]; #IO_L4N_T0_35 Sch=ck_a[2]
141 
#set_property -dict { PACKAGE_PIN E7    IOSTANDARD LVCMOS33 } [get_ports { ck_io[17] }]; #IO_L6P_T0_35 Sch=ck_a[3]
142 
#set_property -dict { PACKAGE_PIN D7    IOSTANDARD LVCMOS33 } [get_ports { ck_io[18] }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4]
143 
#set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { ck_io[19] }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5]
144 
 
145 
##ChipKit Digital I/O On Inner Analog Header
146 
##NOTE: These pins will need to be connected to the XADC core when used as differential analog inputs (Chipkit analog pins A6-A11)
147 
 
148 
#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { ck_io[20] }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12]
149 
#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { ck_io[21] }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12]
150 
#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { ck_io[22] }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13]
151 
#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { ck_io[23] }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13]
152 
#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { ck_io[24] }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14]
153 
#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { ck_io[25] }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14]
154 
 
155 
##ChipKit Digital I/O High
156 
 
157 
#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { ck_io[26] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
158 
#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { ck_io[27] }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
159 
#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { ck_io[28] }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
160 
#set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { ck_io[29] }]; #IO_25_14 Sch=ck_io[29]
161 
#set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { ck_io[30] }]; #IO_0_14 Sch=ck_io[30]
162 
#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { ck_io[31] }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
163 
#set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { ck_io[32] }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
164 
#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { ck_io[33] }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
165 
#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ck_io[34] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
166 
#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { ck_io[35] }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
167 
#set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { ck_io[36] }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
168 
#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { ck_io[37] }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
169 
#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { ck_io[38] }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
170 
#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { ck_io[39] }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
171 
#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { ck_io[40] }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
172 
#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { ck_io[41] }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
173 
 
174 
## ChipKit SPI
175 
 
176 
#set_property -dict { PACKAGE_PIN G1    IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
177 
#set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
178 
#set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
179 
#set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
180 
 
181 
## ChipKit I2C
182 
 
183 
#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
184 
#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
185 
#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
186 
#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
187 
 
188 
##Misc. ChipKit signals
189 
 
190 
#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
191 
set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { i_reset_btn }]; #IO_L16P_T2_35 Sch=ck_rst
192 
 
193 
##SMSC Ethernet PHY
194 
 
195 
#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
196 
#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
197 
set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { o_eth_mdclk }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
198 
set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { io_eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
199 
#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
200 
#set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
201 
#set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
202 
#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
203 
#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
204 
#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
205 
#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
206 
#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
207 
#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
208 
#set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
209 
#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
210 
#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
211 
#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
212 
#set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
213 
#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
214 
 
215 
##Quad SPI Flash
216 
 
217 
set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { o_qspi_cs_n }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
218 
set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dat[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
219 
set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dat[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
220 
set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dat[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
221 
set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dat[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
222 
set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { o_qspi_sck }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
223 
 
224 
##Power Measurements
225 
 
226 
#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33     } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
227 
#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33     } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
228 
#set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33     } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
229 
#set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33     } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
230 
#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33     } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
231 
#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33     } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
232 
#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33     } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
233 
#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33     } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
234 
 
235 
## Memory
236 
 
237 
# Memory address lines
238 
set_property -dict { PACKAGE_PIN R2   IOSTANDARD SSTL135     } [get_ports { o_ddr_addr[0] }];
239 
set_property -dict { PACKAGE_PIN M6   IOSTANDARD SSTL135     } [get_ports { o_ddr_addr[1] }];
240 
set_property -dict { PACKAGE_PIN N4   IOSTANDARD SSTL135     } [get_ports { o_ddr_addr[2] }];
241 
set_property -dict { PACKAGE_PIN T1   IOSTANDARD SSTL135     } [get_ports { o_ddr_addr[3] }];
242 
set_property -dict { PACKAGE_PIN N6   IOSTANDARD SSTL135     } [get_ports { o_ddr_addr[4] }];
243 
set_property -dict { PACKAGE_PIN R7   IOSTANDARD SSTL135     } [get_ports { o_ddr_addr[5] }];
244 
set_property -dict { PACKAGE_PIN V6   IOSTANDARD SSTL135     } [get_ports { o_ddr_addr[6] }];
245 
set_property -dict { PACKAGE_PIN U7   IOSTANDARD SSTL135     } [get_ports { o_ddr_addr[7] }];
246 
set_property -dict { PACKAGE_PIN R8   IOSTANDARD SSTL135     } [get_ports { o_ddr_addr[8] }];
247 
set_property -dict { PACKAGE_PIN V7   IOSTANDARD SSTL135     } [get_ports { o_ddr_addr[9] }];
248 
set_property -dict { PACKAGE_PIN R6   IOSTANDARD SSTL135     } [get_ports { o_ddr_addr[10] }];
249 
set_property -dict { PACKAGE_PIN U6   IOSTANDARD SSTL135     } [get_ports { o_ddr_addr[11] }];
250 
set_property -dict { PACKAGE_PIN T6   IOSTANDARD SSTL135     } [get_ports { o_ddr_addr[12] }];
251 
set_property -dict { PACKAGE_PIN T8   IOSTANDARD SSTL135     } [get_ports { o_ddr_addr[13] }];
252 
set_property -dict { PACKAGE_PIN R1   IOSTANDARD SSTL135     } [get_ports { o_ddr_ba[0] }];
253 
set_property -dict { PACKAGE_PIN P4   IOSTANDARD SSTL135     } [get_ports { o_ddr_ba[1] }];
254 
set_property -dict { PACKAGE_PIN P2   IOSTANDARD SSTL135     } [get_ports { o_ddr_ba[2] }];
255 
#
256 
set_property -dict { PACKAGE_PIN M4   IOSTANDARD SSTL135     } [get_ports { o_ddr_cas_n }];
257 
# Clock lines
258 
set_property -dict { PACKAGE_PIN V9   IOSTANDARD DIFF_SSTL135     } [get_ports { o_ddr_ck_n }];
259 
set_property -dict { PACKAGE_PIN U9   IOSTANDARD DIFF_SSTL135     } [get_ports { o_ddr_ck_p }];
260 
#
261 
set_property -dict { PACKAGE_PIN N5   IOSTANDARD SSTL135     } [get_ports { o_ddr_cke }];
262 
set_property -dict { PACKAGE_PIN U8   IOSTANDARD SSTL135     } [get_ports { o_ddr_cs_n }];
263 
set_property -dict { PACKAGE_PIN L1   IOSTANDARD SSTL135     } [get_ports { o_ddr_dm[0] }];
264 
set_property -dict { PACKAGE_PIN U1   IOSTANDARD SSTL135     } [get_ports { o_ddr_dm[1] }];
265 
# Data (DQ) lines
266 
set_property -dict { PACKAGE_PIN K5   IOSTANDARD SSTL135     } [get_ports { io_ddr_data[0] }];
267 
set_property -dict { PACKAGE_PIN L3   IOSTANDARD SSTL135     } [get_ports { io_ddr_data[1] }];
268 
set_property -dict { PACKAGE_PIN K3   IOSTANDARD SSTL135     } [get_ports { io_ddr_data[2] }];
269 
set_property -dict { PACKAGE_PIN L6   IOSTANDARD SSTL135     } [get_ports { io_ddr_data[3] }];
270 
set_property -dict { PACKAGE_PIN M3   IOSTANDARD SSTL135     } [get_ports { io_ddr_data[4] }];
271 
set_property -dict { PACKAGE_PIN M1   IOSTANDARD SSTL135     } [get_ports { io_ddr_data[5] }];
272 
set_property -dict { PACKAGE_PIN L4   IOSTANDARD SSTL135     } [get_ports { io_ddr_data[6] }];
273 
set_property -dict { PACKAGE_PIN M2   IOSTANDARD SSTL135     } [get_ports { io_ddr_data[7] }];
274 
set_property -dict { PACKAGE_PIN V4   IOSTANDARD SSTL135     } [get_ports { io_ddr_data[8] }];
275 
set_property -dict { PACKAGE_PIN T5   IOSTANDARD SSTL135     } [get_ports { io_ddr_data[9] }];
276 
set_property -dict { PACKAGE_PIN U4   IOSTANDARD SSTL135     } [get_ports { io_ddr_data[10] }];
277 
set_property -dict { PACKAGE_PIN V5   IOSTANDARD SSTL135     } [get_ports { io_ddr_data[11] }];
278 
set_property -dict { PACKAGE_PIN V1   IOSTANDARD SSTL135     } [get_ports { io_ddr_data[12] }];
279 
set_property -dict { PACKAGE_PIN T3   IOSTANDARD SSTL135     } [get_ports { io_ddr_data[13] }];
280 
set_property -dict { PACKAGE_PIN U3   IOSTANDARD SSTL135     } [get_ports { io_ddr_data[14] }];
281 
set_property -dict { PACKAGE_PIN R3   IOSTANDARD SSTL135     } [get_ports { io_ddr_data[15] }];
282 
# DQS
283 
set_property -dict { PACKAGE_PIN N1   IOSTANDARD DIFF_SSTL135     } [get_ports { io_ddr_dqs_n[0] }];
284 
set_property -dict { PACKAGE_PIN V2   IOSTANDARD DIFF_SSTL135     } [get_ports { io_ddr_dqs_n[1] }];
285 
set_property -dict { PACKAGE_PIN N2   IOSTANDARD DIFF_SSTL135     } [get_ports { io_ddr_dqs_p[0] }];
286 
set_property -dict { PACKAGE_PIN U2   IOSTANDARD DIFF_SSTL135     } [get_ports { io_ddr_dqs_p[1] }];
287 
set_property -dict { PACKAGE_PIN R5   IOSTANDARD SSTL135     } [get_ports { o_ddr_odt }];
288 
set_property -dict { PACKAGE_PIN P3   IOSTANDARD SSTL135     } [get_ports { o_ddr_ras_n }];
289 
set_property -dict { PACKAGE_PIN K6   IOSTANDARD SSTL135     } [get_ports { o_ddr_reset_n }];
290 
set_property -dict { PACKAGE_PIN P5   IOSTANDARD SSTL135     } [get_ports { o_ddr_we_n }];
291 
#Internal VREF
292 
set_property INTERNAL_VREF 0.675 [ get_iobanks 34 ];

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