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[/] [openarty/] [trunk/] [migmem.xdc] - Blame information for rev 29

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1 29 dgisselq 
# A list of memory associated pins, suitable for ingesting into Xilinx's
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# Memory Interface Generator.
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## Memory
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# Memory address lines
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set_property PACKAGE_PIN R2 [get_ports {ddr3_addr[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}]
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set_property PACKAGE_PIN M6 [get_ports {ddr3_addr[1]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}]
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set_property PACKAGE_PIN N4 [get_ports {ddr3_addr[2]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}]
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set_property PACKAGE_PIN T1 [get_ports {ddr3_addr[3]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}]
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set_property PACKAGE_PIN N6 [get_ports {ddr3_addr[4]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}]
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set_property PACKAGE_PIN R7 [get_ports {ddr3_addr[5]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}]
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set_property PACKAGE_PIN V6 [get_ports {ddr3_addr[6]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}]
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set_property PACKAGE_PIN U7 [get_ports {ddr3_addr[7]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}]
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set_property PACKAGE_PIN R8 [get_ports {ddr3_addr[8]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}]
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set_property PACKAGE_PIN V7 [get_ports {ddr3_addr[9]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}]
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set_property PACKAGE_PIN R6 [get_ports {ddr3_addr[10]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}]
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set_property PACKAGE_PIN U6 [get_ports {ddr3_addr[11]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}]
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set_property PACKAGE_PIN T6 [get_ports {ddr3_addr[12]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}]
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set_property PACKAGE_PIN T8 [get_ports {ddr3_addr[13]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}]
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set_property PACKAGE_PIN R1 [get_ports {ddr3_ba[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}]
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set_property PACKAGE_PIN P4 [get_ports {ddr3_ba[1]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}]
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set_property PACKAGE_PIN P2 [get_ports {ddr3_ba[2]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}]
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#
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set_property PACKAGE_PIN M4 [get_ports ddr3_cas_n]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n]
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# Clock lines
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set_property PACKAGE_PIN U9 [get_ports {ddr3_ck_p[0]}]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_ck_p[0]}]
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set_property PACKAGE_PIN V9 [get_ports {ddr3_ck_n[0]}]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_ck_n[0]}]
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#
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set_property PACKAGE_PIN N5 [get_ports {ddr3_cke[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_cke[0]}]
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#
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set_property PACKAGE_PIN U8 [get_ports {ddr3_cs_n[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_cs_n[0]}]
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set_property PACKAGE_PIN L1 [get_ports {ddr3_dm[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}]
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set_property PACKAGE_PIN U1 [get_ports {ddr3_dm[1]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}]
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# Data (DQ) lines
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set_property PACKAGE_PIN K5 [get_ports {ddr3_dq[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}]
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set_property PACKAGE_PIN L3 [get_ports {ddr3_dq[1]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}]
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set_property PACKAGE_PIN K3 [get_ports {ddr3_dq[2]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}]
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set_property PACKAGE_PIN L6 [get_ports {ddr3_dq[3]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}]
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set_property PACKAGE_PIN M3 [get_ports {ddr3_dq[4]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}]
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set_property PACKAGE_PIN M1 [get_ports {ddr3_dq[5]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}]
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set_property PACKAGE_PIN L4 [get_ports {ddr3_dq[6]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}]
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set_property PACKAGE_PIN M2 [get_ports {ddr3_dq[7]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}]
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set_property PACKAGE_PIN V4 [get_ports {ddr3_dq[8]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}]
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set_property PACKAGE_PIN T5 [get_ports {ddr3_dq[9]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}]
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set_property PACKAGE_PIN U4 [get_ports {ddr3_dq[10]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}]
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set_property PACKAGE_PIN V5 [get_ports {ddr3_dq[11]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}]
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set_property PACKAGE_PIN V1 [get_ports {ddr3_dq[12]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}]
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set_property PACKAGE_PIN T3 [get_ports {ddr3_dq[13]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}]
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set_property PACKAGE_PIN U3 [get_ports {ddr3_dq[14]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}]
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set_property PACKAGE_PIN R3 [get_ports {ddr3_dq[15]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}]
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# DQS
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set_property PACKAGE_PIN N1 [get_ports {ddr3_dqs_n[0]}]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[0]}]
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set_property PACKAGE_PIN V2 [get_ports {ddr3_dqs_n[1]}]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[1]}]
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set_property PACKAGE_PIN N2 [get_ports {ddr3_dqs_p[0]}]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[0]}]
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set_property PACKAGE_PIN U2 [get_ports {ddr3_dqs_p[1]}]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[1]}]
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set_property PACKAGE_PIN R5 [get_ports {ddr3_odt[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_odt[0]}]
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set_property PACKAGE_PIN R5 [get_ports { ddr3_odt[0]}]
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set_property IOSTANDARD SSTL135 [get_ports { ddr3_odt[0]}]
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set_property PACKAGE_PIN P3 [get_ports ddr3_ras_n]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n]
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set_property PACKAGE_PIN K6 [get_ports ddr3_reset_n]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n]
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set_property PACKAGE_PIN P5 [get_ports ddr3_we_n]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n]
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#Internal VREF
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set_property INTERNAL_VREF 0.675 [get_iobanks 34]
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