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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: addecrc.v
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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// Purpose: To (optionally) add a CRC to a stream of nibbles. The CRC
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// is calculated from the stream.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module addecrc(i_clk, i_ce, i_en, i_cancel, i_v, i_d, o_v, o_d);
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localparam INVERT = 1; // Proper operation requires INVERT=1
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input i_clk, i_ce, i_en, i_cancel;
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input i_v;
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input [3:0] i_d;
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output reg o_v;
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output reg [3:0] o_d;
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reg [7:0] r_p;
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reg [31:0] r_crc;
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wire [3:0] lownibble;
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wire [31:0] shifted_crc;
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assign lownibble = r_crc[3:0] ^ i_d;
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assign shifted_crc = { 4'h0, r_crc[31:4] };
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initial o_v = 1'b0;
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always @(posedge i_clk)
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if (i_ce)
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begin
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if (((!i_v)&&(!o_v))||(i_cancel))
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begin
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r_crc <= (INVERT==0)? 32'h00 : 32'hffffffff;
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r_p <= 8'hff;
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end else if (i_v)
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begin
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o_v <= i_v;
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r_p <= 8'hff;
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o_d <= i_d;
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`define CRCBIT8 32'hedb88320
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`define CRCBIT4 32'h76dc4190
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`define CRCBIT2 32'h3b6e20c8
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`define CRCBIT1 32'h1db71064
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// 0xedb88320 . 76dc4190 . 3b6e20c8 . 1db71064 . 0edb8832
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case(lownibble)
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4'h0: r_crc <= shifted_crc;
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4'h1: r_crc <= shifted_crc ^ `CRCBIT1;
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4'h2: r_crc <= shifted_crc ^ `CRCBIT2;
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4'h3: r_crc <= shifted_crc ^ `CRCBIT2 ^ `CRCBIT1;
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4'h4: r_crc <= shifted_crc ^ `CRCBIT4;
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4'h5: r_crc <= shifted_crc ^ `CRCBIT4 ^ `CRCBIT1;
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4'h6: r_crc <= shifted_crc ^ `CRCBIT4 ^ `CRCBIT2;
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4'h7: r_crc <= shifted_crc ^ `CRCBIT4 ^ `CRCBIT2 ^ `CRCBIT1;
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4'h8: r_crc <= shifted_crc ^ `CRCBIT8;
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4'h9: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT1;
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4'ha: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT2;
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4'hb: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT2 ^ `CRCBIT1;
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4'hc: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT4;
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4'hd: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT4 ^ `CRCBIT1;
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4'he: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT4 ^ `CRCBIT2;
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4'hf: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT4 ^ `CRCBIT2 ^ `CRCBIT1;
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default: r_crc <= { 4'h0, r_crc[31:4] };
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endcase
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end else begin
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r_p <= { r_p[6:0], 1'b0 };
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o_v <= (i_en)?r_p[7]:1'b0;
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o_d <= r_crc[3:0] ^ ((INVERT==0)? 4'h0:4'hf);
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r_crc <= { 4'h0, r_crc[31:4] };
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end
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end
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endmodule
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