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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: addepad.v
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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// Purpose: To force the minimum packet size of an ethernet frame to be
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// a minimum of 64 bytes. This assumes that the CRC will be
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// adding 32-bits to the packet after us, so instead of padding to
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// 64 bytes, we'll pad to 60 bytes instead. If the user is providing
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// their own CRC, they'll need to adjust the padding themselves.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module addepad(i_clk, i_ce, i_en, i_cancel, i_v, i_d, o_v, o_d);
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input i_clk, i_ce, i_en, i_cancel;
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input i_v; // Valid
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input [3:0] i_d; // Data nibble
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output reg o_v;
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output reg [3:0] o_d;
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// 60 bytes translates to 120 nibbles, so let's keep track of our
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// minimum number of nibbles to transmit
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reg [119:0] r_v;
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initial r_v = 120'hff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
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initial o_v = 1'b0;
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always @(posedge i_clk)
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if (i_ce)
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begin
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if (((!i_v)&&(!o_v))||(i_cancel))
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begin
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r_v <= 120'hff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
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o_v <= 1'b0;
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end else if (i_v)
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begin
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o_v <= i_v;
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r_v <= { r_v[118:0], 1'b0 };
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end else begin
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o_v <= r_v[119];
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r_v <= { r_v[118:0], 1'b0 };
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end
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if (i_v)
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o_d <= i_d;
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else
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o_d <= 4'h0;
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end
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endmodule
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