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////////////////////////////////////////////////////////////////////////////////

//

// Filename:    busmaster.v

//

// Project:     OpenArty, an entirely open SoC based upon the Arty platform

//

// Purpose:     This is the "bus interconnect", herein called the "busmaster".

//              This module connects all the devices on the Wishbone bus

//              within this project together.  It is created by hand, not

//      automatically.

//

// Creator:     Dan Gisselquist, Ph.D.

//              Gisselquist Technology, LLC

//

////////////////////////////////////////////////////////////////////////////////

//

// Copyright (C) 2015-2017, Gisselquist Technology, LLC

//

// This program is free software (firmware): you can redistribute it and/or

// modify it under the terms of  the GNU General Public License as published

// by the Free Software Foundation, either version 3 of the License, or (at

// your option) any later version.

//

// This program is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// for more details.

//

// You should have received a copy of the GNU General Public License along

// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no

// target there if the PDF file isn't present.)  If not, see

// <http://www.gnu.org/licenses/> for a copy.

//

// License:     GPL, v3, as defined and found on www.gnu.org,

//              http://www.gnu.org/licenses/gpl.html

//

//

////////////////////////////////////////////////////////////////////////////////

//

//

`define NO_ZIP_WBU_DELAY

`define ZIPCPU

//

//

`define SDCARD_ACCESS

`define ETHERNET_ACCESS

`ifndef VERILATOR

`define ICAPE_ACCESS

`endif

`define FLASH_ACCESS

`define SDRAM_ACCESS

`define GPS_CLOCK

`ifdef  VERILATOR

`define GPSTB

`endif

//      UART_ACCESS and GPS_UART have both been placed within fastio

//              `define UART_ACCESS

//              `define GPS_UART

`define RTC_ACCESS

`define OLEDRGB_ACCESS

//

//

//

//

//

// Now, conditional compilation based upon what capabilities we have turned

// on

//

`ifdef  ZIPCPU

`define ZIP_SYSTEM

`ifndef ZIP_SYSTEM

`define ZIP_BONES

`endif  // ZIP_SYSTEM

`endif  // ZipCPU

//

//

// SCOPE POSITION ZERO

//

`ifdef  FLASH_ACCESS

// `define      FLASH_SCOPE     // Position zero

`endif

`ifdef ZIPCPU

`ifndef FLASH_SCOPE

`define CPU_SCOPE       // Position zero

`endif

`endif

//

// SCOPE POSITION ONE

//

// `define      GPS_SCOPE       // Position one

// `ifdef ICAPE_ACCESS

// `define      CFG_SCOPE       // Position one

// `endif

// `define      WBU_SCOPE

//

// SCOPE POSITION TWO

//

`ifdef  SDRAM_ACCESS

// `define      SDRAM_SCOPE             // Position two

`endif

//

// SCOPE POSITION THREE

//

`ifdef  ETHERNET_ACCESS

`define ENET_SCOPE

`endif

//

//

module  busmaster(i_clk, i_rst,

                // CNC

                i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,

                // Boad I/O

                i_sw, i_btn, o_led,

                o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,

                // PMod I/O

                i_aux_rx, o_aux_tx, i_aux_cts_n, o_aux_rts_n, i_gps_rx, o_gps_tx,

                // The Quad SPI Flash

                o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,

                //

                // The DDR3 SDRAM

                //

                // The actual wires need to be controlled from the device

                // dependent file.  In order to keep this device independent,

                // we export only the wishbone interface to the RAM.

                //

                // o_ddr_ck_p, o_ddr_ck_n, o_ddr_reset_n, o_ddr_cke,

                // o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,

                // o_ddr_ba, o_ddr_addr, o_ddr_odt, o_ddr_dm,

                // o_ddr_dqs, i_ddr_data, o_ddr_data,

                //

                // These wires allow us to push how we deal with the RAM

                // to the next level up, where they'll be use to interact

                // with a Xilinx specific core.

                o_ram_cyc, o_ram_stb, o_ram_we, o_ram_addr, o_ram_wdata, o_ram_sel,

                        i_ram_ack, i_ram_stall, i_ram_rdata, i_ram_err,

                        i_ram_dbg,

                // The SD Card

                o_sd_sck, o_sd_cmd, o_sd_data, i_sd_cmd, i_sd_data, i_sd_detect,

                // Ethernet control (packets) lines

                o_net_reset_n, i_net_rx_clk, i_net_col, i_net_crs, i_net_dv,

                        i_net_rxd, i_net_rxerr,

                i_net_tx_clk, o_net_tx_en, o_net_txd,

                // Ethernet control (MDIO) lines

                o_mdclk, o_mdio, o_mdwe, i_mdio,

                // OLED Control interface (roughly SPI)

                o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,

                o_oled_reset_n, o_oled_vccen, o_oled_pmoden,

                // The GPS PMod

                i_gps_pps, i_gps_3df,

                // Other GPIO wires

                i_gpio, o_gpio

                );

        parameter       ZA=28, ZIPINTS=14, RESET_ADDRESS=32'h01380000,

                        NGPI = 4, NGPO = 1;

        input                   i_clk, i_rst;

        // The bus commander, via an external uart port

        input                   i_rx_stb;

        input           [7:0]    i_rx_data;

        output  wire            o_tx_stb;

        output  wire    [7:0]    o_tx_data;

        input                   i_tx_busy;

        // I/O to/from board level devices

        input           [3:0]    i_sw;   // 16 switch bus

        input           [3:0]    i_btn;  // 5 Buttons

        output  wire    [3:0]    o_led;  // 16 wide LED's

        output  wire    [2:0]    o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3;

        // PMod UARTs

        input                   i_aux_rx, i_aux_cts_n;

        output  wire            o_aux_tx, o_aux_rts_n;

        input                   i_gps_rx;

        output  wire            o_gps_tx;

        // Quad-SPI flash control

        output  wire            o_qspi_cs_n, o_qspi_sck;

        output  wire    [3:0]    o_qspi_dat;

        input           [3:0]    i_qspi_dat;

        output  wire    [1:0]    o_qspi_mod;

        //

        // DDR3 RAM controller

        //

        // These would be our RAM control lines.  However, these are device,

        // implementation, and architecture dependent, rather than just simply

        // logic dependent.  Therefore, this interface as it exists cannot

        // exist here.  Instead, we export a device independent wishbone to

        // the RAM rather than the RAM wires themselves.

        // output       wire    o_ddr_ck_p, o_ddr_ck_n,o_ddr_reset_n, o_ddr_cke,

        //              o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;

        // output       wire    [2:0]   o_ddr_ba;

        // output       wire    [13:0]  o_ddr_addr;

        // output       wire            o_ddr_odt;

        // output       wire    [1:0]   o_ddr_dm;

        // output       wire    [1:0]   o_ddr_dqs;

        // input        wire    [15:0]  i_ddr_data;

        // output       wire    [15:0]  o_ddr_data;

        //

        output  wire            o_ram_cyc, o_ram_stb, o_ram_we;

        output  wire    [25:0]   o_ram_addr;

        output  wire    [31:0]   o_ram_wdata;

        output  wire    [3:0]    o_ram_sel;

        input                   i_ram_ack, i_ram_stall;

        input           [31:0]   i_ram_rdata;

        input                   i_ram_err;

        input           [31:0]   i_ram_dbg;

        // The SD Card

        output  wire            o_sd_sck;

        output  wire            o_sd_cmd;

        output  wire    [3:0]    o_sd_data;

        input                   i_sd_cmd;

        input           [3:0]    i_sd_data;

        input                   i_sd_detect;

        // Ethernet control

        output  wire            o_net_reset_n;

        input                   i_net_rx_clk, i_net_col, i_net_crs, i_net_dv;

        input           [3:0]    i_net_rxd;

        input                   i_net_rxerr;

        input                   i_net_tx_clk;

        output  wire            o_net_tx_en;

        output  wire    [3:0]    o_net_txd;

        // Ethernet control (MDIO)

        output  wire            o_mdclk, o_mdio, o_mdwe;

        input                   i_mdio;

        // OLEDRGB interface

        output  wire            o_oled_sck, o_oled_cs_n, o_oled_mosi,

                                o_oled_dcn, o_oled_reset_n, o_oled_vccen,

                                o_oled_pmoden;

        // GPS PMod (GPS UART above)

        input                   i_gps_pps;

        input                   i_gps_3df;

        // Other GPIO wires

        input   [(NGPI-1):0]     i_gpio;

        output  wire    [(NGPO-1):0]     o_gpio;

        //

        //

        // Master wishbone wires

        //

        //

        wire            wb_cyc, wb_stb, wb_we, wb_stall, wb_err, ram_err;

        wire    [31:0]           wb_data;

        wire    [(ZA-1):0]       wb_addr;

        wire    [3:0]    wb_sel;

        reg             wb_ack;

        reg     [31:0]   wb_idata;

        // Interrupts

        wire            gpio_int, oled_int, flash_int, scop_int;

        wire            enet_tx_int, enet_rx_int, sdcard_int, rtc_int, rtc_pps,

                        auxrxf_int, auxtxf_int, gpsrxf_int, gpstxf_int,

                        auxrx_int, auxtx_int, gpsrx_int, gpstx_int,

                        sw_int, btn_int;

        //

        //

        // First BUS master source: The UART

        //

        //

        wire    [31:0]   dwb_idata;

        // Wires going to devices

        wire            wbu_cyc, wbu_stb, wbu_we;

        wire    [31:0]   wbu_addr, wbu_data;

        wire    [3:0]    wbu_sel;

        // and then coming from devices

        wire            wbu_ack, wbu_stall, wbu_err;

        wire    [31:0]   wbu_idata;

        // And then headed back home

        wire    w_bus_interrupt;

        // Oh, and the debug control for the ZIP CPU

        wire            wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;

        wire    [31:0]   zip_dbg_data;

`ifdef  WBU_SCOPE

        wire    [31:0]   wbu_debug;

`endif

        wbubus  genbus(i_clk, i_rx_stb, i_rx_data,

                        wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,

                        (wbu_zip_sel)?zip_dbg_ack:wbu_ack,

                        (wbu_zip_sel)?zip_dbg_stall:wbu_stall,

                                wbu_err,

                                (wbu_zip_sel)?zip_dbg_data:wbu_idata,

                        w_bus_interrupt,

                        o_tx_stb, o_tx_data, i_tx_busy

                        // , wbu_debug

                        );

        assign  wbu_sel = 4'hf;

`ifdef  WBU_SCOPE

        // assign       o_dbg = (wbu_ack)&&(wbu_cyc);

        assign  wbu_debug = { wbu_cyc, wbu_stb, wbu_we, wbu_ack, wbu_stall,

                                wbu_err, wbu_zip_sel,

                                wbu_addr[8:0],

                                wbu_data[7:0],

                                wbu_idata[7:0] };

`endif

        wire    zip_cpu_int; // True if the CPU suddenly halts

`ifdef  ZIPCPU

        // Are we trying to access the ZipCPU?  Such accesses must be special,

        // because they must succeed regardless of whether or not the ZipCPU

        // is on the bus.  Hence, we trap them here.

        assign  wbu_zip_sel = (wbu_addr[27]);

        //

        //

        // Second BUS master source: The ZipCPU

        //

        //

        wire                    zip_cyc, zip_stb, zip_we;

        wire    [(ZA-1):0]       zip_addr;

        wire    [31:0]           zip_data, zip_scope_data;

        wire    [3:0]            zip_sel;

        // and then coming from devices

        wire            zip_ack, zip_stall, zip_err;

`ifdef  ZIP_SYSTEM

        wire    [(ZIPINTS-1):0]  zip_interrupt_vec = {

                // Lazy(ier) interrupts

                        gpstx_int, gpsrx_int,

                        auxtx_int, auxrx_int,

                        rtc_ppd,

                // Fast interrupts

                oled_int, w_bus_interrupt,

                        gpstxf_int, gpsrxf_int,

                        auxtxf_int, auxrxf_int,

                        enet_tx_int, enet_rx_int, rtc_pps

                };

        zipsystem #(    .RESET_ADDRESS(RESET_ADDRESS),

                        .ADDRESS_WIDTH(ZA),

                        .LGICACHE(10),

                        .START_HALTED(1),

                        .EXTERNAL_INTERRUPTS(ZIPINTS))

                swic(i_clk, i_rst,

                        // Zippys wishbone interface

                        zip_cyc, zip_stb, zip_we, zip_addr, zip_data, zip_sel,

                                zip_ack, zip_stall, dwb_idata, zip_err,

                        zip_interrupt_vec, zip_cpu_int,

                        // Debug wishbone interface

                        ((wbu_cyc)&&(wbu_zip_sel)),

                                ((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],

                                wbu_data,

                                zip_dbg_ack, zip_dbg_stall, zip_dbg_data

`ifdef  CPU_SCOPE

                        , zip_scope_data

`endif

                        );

`else // ZIP_SYSTEM

        wire    w_zip_cpu_int_ignored;

        zipbones #(     .RESET_ADDRESS(RESET_ADDRESS),

                        .ADDRESS_WIDTH(ZA),

                        .LGICACHE(10),

                        .START_HALTED(1))

                swic(i_clk, i_rst,

                        // Zippys wishbone interface

                        zip_cyc, zip_stb, zip_we, zip_addr, zip_data, zip_sel,

                                zip_ack, zip_stall, dwb_idata, zip_err,

                        w_bus_interrupt, w_zip_cpu_int_ignored,

                        // Debug wishbone interface

                        ((wbu_cyc)&&(wbu_zip_sel)),

                                ((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],

                                wbu_data,

                                zip_dbg_ack, zip_dbg_stall, zip_dbg_data

`ifdef  CPU_SCOPE

                        , zip_scope_data

`endif

                        );

        assign  zip_cpu_int = 1'b0;

`endif  // ZIP_SYSTEM v ZIP_BONES

        //

        //

        // And an arbiter to decide who gets to access the bus

        //

        //

        wire    dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;

        wire    [(ZA-1):0]       dwb_addr;

        wire    [31:0]           dwb_odata;

        wire    [3:0]            dwb_sel;

        wbpriarbiter #(32,ZA) wbu_zip_arbiter(i_clk,

                // The ZIP CPU Master -- Gets the priority slot

                zip_cyc, zip_stb, zip_we, zip_addr, zip_data, zip_sel,

                        zip_ack, zip_stall, zip_err,

                // The UART interface Master

                (wbu_cyc)&&(!wbu_zip_sel), (wbu_stb)&&(!wbu_zip_sel), wbu_we,

                        wbu_addr[(ZA-1):0], wbu_data, wbu_sel,

                        wbu_ack, wbu_stall, wbu_err,

                // Common bus returns

                dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata, dwb_sel,

                        dwb_ack, dwb_stall, dwb_err);

        //

        //

        // And because the ZIP CPU and the Arbiter create an unacceptable

        // delay, we fail timing.  So we add in a delay cycle ...

        //

        //

        assign  wbu_idata = dwb_idata;

        busdelay #(ZA)  wbu_zip_delay(i_clk,

                        dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata, dwb_sel,

                                dwb_ack, dwb_stall, dwb_idata, dwb_err,

                        wb_cyc, wb_stb, wb_we, wb_addr, wb_data, wb_sel,

                                wb_ack, wb_stall, wb_idata, wb_err);

`else   // ZIPCPU

        assign  zip_cpu_int = 1'b0; // No CPU here to halt

        assign  wbu_zip_sel = 1'b0;

        // If there's no ZipCPU, there's no need for a Zip/WB-Uart bus delay.

        // We can go directly from the WB-Uart master bus to the master bus

        // itself.

        assign  wb_cyc    = wbu_cyc;

        assign  wb_stb    = wbu_stb;

        assign  wb_we     = wbu_we;

        assign  wb_addr   = wbu_addr;

        assign  wb_data   = wbu_data;

        assign  wb_sel    = wbu_sel;

        assign  wbu_idata = wb_idata;

        assign  wbu_ack   = wb_ack;

        assign  wbu_stall = wb_stall;

        assign  wbu_err   = wb_err;

        // The CPU never halts if it doesn't exist, so set this interrupt to

        // zero.

        assign  zip_cpu_int= 1'b0;

`endif  // ZIPCPU

        //

        // Peripheral select lines.

        //

        // These lines will be true during any wishbone cycle whose address

        // line selects the given I/O peripheral.  The none_sel and many_sel

        // lines are used to detect problems, such as when no device is

        // selected or many devices are selected.  Such problems will lead to

        // bus errors (below).

        //

        wire    io_sel, scop_sel, rtc_sel, oled_sel, uart_sel, gpsu_sel,

                        sdcard_sel, gps_sel, netp_sel, mio_sel, cfg_sel,

                        ram_sel, flash_sel, flctl_sel, mem_sel, netb_sel,

                        none_sel, many_sel;

        wire    idle_n;

`ifdef  ZERO_ON_IDLE

        assign idle_n = wb_stb;

`else

        assign idle_n = 1'b1;

`endif

        wire    [4:0]    skipaddr;

        assign  skipaddr = { wb_addr[26], wb_addr[22], wb_addr[15], wb_addr[11],

                                ~wb_addr[8] };

        assign  ram_sel   = (idle_n)&&(skipaddr[4]);

        assign  flash_sel = (idle_n)&&(skipaddr[4:3]==2'b01);

        assign  mem_sel   = (idle_n)&&(skipaddr[4:2]==3'b001);

        assign  netb_sel  = (idle_n)&&(skipaddr[4:1]==4'b0001);

        assign  io_sel    = (idle_n)&&(~|skipaddr)&&(wb_addr[7:5]==3'b00_0);

        assign  scop_sel  = (idle_n)&&(~|skipaddr)&&(wb_addr[7:3]==5'b00_100);

        assign  rtc_sel   = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1010);

        assign  oled_sel  = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1011);

        assign  uart_sel  = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1100);

        assign  gpsu_sel  = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1101);

        assign  sdcard_sel= (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1110);

        //assign unused_  = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1111);

        assign  gps_sel   = (idle_n)&&(~|skipaddr)&&((wb_addr[7:2]==6'b01_0000)

                                                    ||(wb_addr[7:3]==5'b01_001));

        assign  netp_sel  = (idle_n)&&(~|skipaddr)&&(wb_addr[7:3]==5'b01_010);

        assign  mio_sel   = (idle_n)&&(~|skipaddr)&&(wb_addr[7:5]==3'b01_1);

        assign  flctl_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:5]==3'b10_0);

        assign  cfg_sel   = (idle_n)&&(~|skipaddr)&&(wb_addr[7:5]==3'b10_1);

        wire    skiperr;

        assign  skiperr = (idle_n)&&((|wb_addr[(ZA-1):27])

                                ||(~skipaddr[4])&&(|wb_addr[25:23])

                                ||(skipaddr[4:3]==2'b00)&&(|wb_addr[21:16])

                                ||(skipaddr[4:2]==3'b000)&&(|wb_addr[14:12])

                                ||(skipaddr[4:1]==4'b0000)&&(|wb_addr[10:9])

                                ||(skipaddr[4:0]==5'b00001));

        //

        // Peripheral acknowledgement lines

        //

        // These are only a touch more confusing, since the flash device will

        // ACK for both flctl_sel (the control line select), as well as the

        // flash_sel (the memory line select).  Hence we have one fewer ack

        // line.

        wire    io_ack, rtc_ack, oled_ack, uart_ack, gpsu_ack, sdcard_ack,

                        gps_ack, net_ack, mio_ack, cfg_ack,

                        mem_ack, flash_ack, ram_ack;

        reg     many_ack, slow_many_ack;

        reg     slow_ack, scop_ack;

        wire    [4:0]    ack_list;

        assign  ack_list = { ram_ack, flash_ack, mem_ack, net_ack, slow_ack };

        initial many_ack = 1'b0;

        always @(posedge i_clk)

                many_ack <= ((ack_list != 5'h10)

                        &&(ack_list != 5'h8)

                        &&(ack_list != 5'h4)

                        &&(ack_list != 5'h2)

                        &&(ack_list != 5'h1)

                        &&(ack_list != 5'h0));

        wire    [9:0] slow_ack_list;

        assign slow_ack_list = { cfg_ack, mio_ack, gps_ack, uart_ack, gpsu_ack,

                        sdcard_ack, rtc_ack, scop_ack, oled_ack, io_ack };

        initial slow_many_ack = 1'b0;

        always @(posedge i_clk)

                slow_many_ack <= ((slow_ack_list != 10'h200)

                        &&(slow_ack_list != 10'h100)

                        &&(slow_ack_list != 10'h080)

                        &&(slow_ack_list != 10'h040)

                        &&(slow_ack_list != 10'h020)

                        &&(slow_ack_list != 10'h010)

                        &&(slow_ack_list != 10'h008)

                        &&(slow_ack_list != 10'h004)

                        &&(slow_ack_list != 10'h002)

                        &&(slow_ack_list != 10'h001)

                        &&(slow_ack_list != 10'h000));

        always @(posedge i_clk)

                wb_ack <= (wb_cyc)&&(|ack_list);

        always @(posedge i_clk)

                slow_ack <= (wb_cyc)&&(|slow_ack_list);

        //

        // Peripheral data lines

        //

        wire    [31:0]   io_data, rtc_data, oled_data, uart_data, gpsu_data,

                        sdcard_data,

                        net_data, gps_data, mio_data, cfg_data,

                        mem_data, flash_data, ram_data;

        reg     [31:0]   slow_data, scop_data;

        // 4 control lines, 5x32 data lines ...

        always @(posedge i_clk)

                if ((ram_ack)||(flash_ack))

                        wb_idata <= (ram_ack)?ram_data:flash_data;

                else if ((mem_ack)||(net_ack))

                        wb_idata <= (mem_ack)?mem_data:net_data;

                else

                        wb_idata <= slow_data;

        // 9 control lines, 10x32 data lines

        always @(posedge i_clk)

                if ((cfg_ack)||(mio_ack))

                        slow_data <= (cfg_ack) ? cfg_data : mio_data;

                else if ((uart_ack)||(gpsu_ack))

                        slow_data <= (uart_ack)?uart_data : gpsu_data;

                else if ((sdcard_ack)||(rtc_ack))

                        slow_data <= (sdcard_ack)?sdcard_data : rtc_data;

                else if ((scop_ack)|(oled_ack))

                        slow_data <= (scop_ack)?scop_data:oled_data;

                else

                        slow_data <= (gps_ack) ? gps_data : io_data;

        //

        // Peripheral stall lines

        //

        // As per the wishbone spec, these cannot be clocked or delayed.  They

        // *must* be done via combinatorial logic.

        //

        wire    io_stall, scop_stall, oled_stall,

                        rtc_stall, sdcard_stall, uart_stall, gpsu_stall,

                        net_stall, gps_stall, mio_stall, cfg_stall, netb_stall,

                        mem_stall, flash_stall, ram_stall,

                        many_stall;

        assign  wb_stall = (wb_cyc)&&(

                        ((io_sel)&&(io_stall))          // Never stalls

                        ||((scop_sel)&&(scop_stall))    // Never stalls

                        ||((rtc_sel)&&(rtc_stall))      // Never stalls

                        ||((oled_sel)&&(oled_stall))    // Never stalls

                        ||((uart_sel)&&(uart_stall))    // Never stalls

                        ||((gpsu_sel)&&(gpsu_stall))    // Never stalls

                        ||((sdcard_sel)&&(sdcard_stall))// Never stalls

                        ||((netp_sel)&&(net_stall))     // Never stalls

                        ||((gps_sel)&&(gps_stall))      //(maybe? never stalls?)

                        ||((mio_sel)&&(mio_stall))

                        ||((cfg_sel)&&(cfg_stall))

                        ||((netb_sel)&&(net_stall))     // Never stalls

                        ||((mem_sel)&&(mem_stall))      // Never stalls

                        ||((flash_sel|flctl_sel)&&(flash_stall))

                        ||((ram_sel)&&(ram_stall)));

        //

        // Bus Error calculation(s)

        //

        // Selecting nothing is only an error if the strobe line is high as well

        // as the cycle line.  However, this is captured within the wb_err

        // logic itself, so we can ignore it for a line or two.

        assign  none_sel = ( //(skiperr)||

                                (~|{ io_sel, scop_sel, flctl_sel, rtc_sel,

                                        sdcard_sel, netp_sel, gps_sel,

                                        oled_sel,

                                        mio_sel, cfg_sel, netb_sel, mem_sel,

                                        flash_sel,ram_sel }));

        //

        // Selecting multiple devices at once is a design flaw that should

        // never happen.  Hence, if this logic won't build, we won't include

        // it.  Still, having this logic in place has saved my tush more than

        // once.

        //

        reg     [(ZA-1):0]       sel_addr;

        always @(posedge i_clk)