Subversion Repositories openarty

///////////////////////////////////////////////////////////////////////////////

//

// Filename:    zipcpu.v

//

// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core

//

// Purpose:     This is the top level module holding the core of the Zip CPU

//              together.  The Zip CPU is designed to be as simple as possible.

//      (actual implementation aside ...)  The instruction set is about as

//      RISC as you can get, there are only 16 instruction types supported.

//      Please see the accompanying spec.pdf file for a description of these

//      instructions.

//

//      All instructions are 32-bits wide.  All bus accesses, both address and

//      data, are 32-bits over a wishbone bus.

//

//      The Zip CPU is fully pipelined with the following pipeline stages:

//

//              1. Prefetch, returns the instruction from memory. 

//

//              2. Instruction Decode

//

//              3. Read Operands

//

//              4. Apply Instruction

//

//              4. Write-back Results

//

//      Further information about the inner workings of this CPU may be

//      found in the spec.pdf file.  (The documentation within this file

//      had become out of date and out of sync with the spec.pdf, so look

//      to the spec.pdf for accurate and up to date information.)

//

//

//      In general, the pipelining is controlled by three pieces of logic

//      per stage: _ce, _stall, and _valid.  _valid means that the stage

//      holds a valid instruction.  _ce means that the instruction from the

//      previous stage is to move into this one, and _stall means that the

//      instruction from the previous stage may not move into this one.

//      The difference between these control signals allows individual stages

//      to propagate instructions independently.  In general, the logic works

//      as:

//

//

//      assign  (n)_ce = (n-1)_valid && (~(n)_stall)

//

//

//      always @(posedge i_clk)

//              if ((i_rst)||(clear_pipeline))

//                      (n)_valid = 0

//              else if (n)_ce

//                      (n)_valid = 1

//              else if (n+1)_ce

//                      (n)_valid = 0

//

//      assign (n)_stall = (  (n-1)_valid && ( pipeline hazard detection )  )

//                      || (  (n)_valid && (n+1)_stall );

//

//      and ...

//

//      always @(posedge i_clk)

//              if (n)_ce

//                      (n)_variable = ... whatever logic for this stage

//

//      Note that a stage can stall even if no instruction is loaded into

//      it.

//

//

// Creator:     Dan Gisselquist, Ph.D.

//              Gisselquist Technology, LLC

//

///////////////////////////////////////////////////////////////////////////////

//

// Copyright (C) 2015-2016, Gisselquist Technology, LLC

//

// This program is free software (firmware): you can redistribute it and/or

// modify it under the terms of  the GNU General Public License as published

// by the Free Software Foundation, either version 3 of the License, or (at

// your option) any later version.

//

// This program is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// for more details.

//

// License:     GPL, v3, as defined and found on www.gnu.org,

//              http://www.gnu.org/licenses/gpl.html

//

//

///////////////////////////////////////////////////////////////////////////////

//

// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined

// fetches are more complicated and therefore use more FPGA resources, while

// single fetches will cause the CPU to stall for about 5 stalls each 

// instruction cycle, effectively reducing the instruction count per clock to

// about 0.2.  However, the area cost may be worth it.  Consider:

//

//      Slice LUTs              ZipSystem       ZipCPU

//      Single Fetching         2521            1734

//      Pipelined fetching      2796            2046

//

//

//

`define CPU_CC_REG      4'he

`define CPU_PC_REG      4'hf

`define CPU_CLRCACHE_BIT 14     // Floating point error flag, set on error

`define CPU_PHASE_BIT   13      // Floating point error flag, set on error

`define CPU_FPUERR_BIT  12      // Floating point error flag, set on error

`define CPU_DIVERR_BIT  11      // Divide error flag, set on divide by zero

`define CPU_BUSERR_BIT  10      // Bus error flag, set on error

`define CPU_TRAP_BIT    9       // User TRAP has taken place

`define CPU_ILL_BIT     8       // Illegal instruction

`define CPU_BREAK_BIT   7

`define CPU_STEP_BIT    6       // Will step one or two (VLIW) instructions

`define CPU_GIE_BIT     5

`define CPU_SLEEP_BIT   4

// Compile time defines

//

`include "cpudefs.v"

//

//

module  zipcpuhs(i_clk, i_rst, i_interrupt,

                // Debug interface

                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,

                        o_dbg_stall, o_dbg_reg, o_dbg_cc,

                        o_break,

                // CPU interface to the wishbone bus

                o_wb_gbl_cyc, o_wb_gbl_stb,

                        o_wb_lcl_cyc, o_wb_lcl_stb,

                        o_wb_we, o_wb_addr, o_wb_data,

                        i_wb_ack, i_wb_stall, i_wb_data,

                        i_wb_err,

                // Accounting/CPU usage interface

                o_op_stall, o_pf_stall, o_i_count

`ifdef  DEBUG_SCOPE

                , o_debug

`endif

                );

        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,

                        LGICACHE=6;

`ifdef  OPT_MULTIPLY

        parameter       IMPLEMENT_MPY = `OPT_MULTIPLY;

`else

        parameter       IMPLEMENT_MPY = 0;

`endif

`ifdef  OPT_DIVIDE

        parameter       IMPLEMENT_DIVIDE = 1;

`else

        parameter       IMPLEMENT_DIVIDE = 0;

`endif

`ifdef  OPT_IMPLEMENT_FPU

        parameter       IMPLEMENT_FPU = 1,

`else

        parameter       IMPLEMENT_FPU = 0,

`endif

                        IMPLEMENT_LOCK=1;

`ifdef  OPT_EARLY_BRANCHING

        parameter       EARLY_BRANCHING = 1;

`else

        parameter       EARLY_BRANCHING = 0;

`endif

        parameter       AW=ADDRESS_WIDTH;

        input                   i_clk, i_rst, i_interrupt;

        // Debug interface -- inputs

        input                   i_halt, i_clear_pf_cache;

        input           [4:0]    i_dbg_reg;

        input                   i_dbg_we;

        input           [31:0]   i_dbg_data;

        // Debug interface -- outputs

        output  wire            o_dbg_stall;

        output  reg     [31:0]   o_dbg_reg;

        output  reg     [3:0]    o_dbg_cc;

        output  wire            o_break;

        // Wishbone interface -- outputs

        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;

        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;

        output  wire    [(AW-1):0]       o_wb_addr;

        output  wire    [31:0]   o_wb_data;

        // Wishbone interface -- inputs

        input                   i_wb_ack, i_wb_stall;

        input           [31:0]   i_wb_data;

        input                   i_wb_err;

        // Accounting outputs ... to help us count stalls and usage

        output  wire            o_op_stall;

        output  wire            o_pf_stall;

        output  wire            o_i_count;

        //

`ifdef  DEBUG_SCOPE

        output  reg     [31:0]   o_debug;

`endif

        // Registers

        //

        //      The distributed RAM style comment is necessary on the

        // SPARTAN6 with XST to prevent XST from oversimplifying the register

        // set and in the process ruining everything else.  It basically

        // optimizes logic away, to where it no longer works.  The logic

        // as described herein will work, this just makes sure XST implements

        // that logic.

        //

        (* ram_style = "distributed" *)

        reg     [31:0]   regset [0:31];

        // Condition codes

        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z

        reg     [3:0]    flags, iflags;

        wire    [14:0]   w_uflags, w_iflags;

        reg             trap, break_en, step, gie, sleep, r_halted,

                        break_pending;

        wire            w_clear_icache;

`ifdef  OPT_ILLEGAL_INSTRUCTION

        reg             ill_err_u, ill_err_i;

`else

        wire            ill_err_u, ill_err_i;

`endif

        reg             ubreak;

        reg             ibus_err_flag, ubus_err_flag;

        wire            idiv_err_flag, udiv_err_flag;

        wire            ifpu_err_flag, ufpu_err_flag;

        wire            ihalt_phase, uhalt_phase;

        // The master chip enable

        wire            master_ce;

        //

        //

        //      PIPELINE STAGE #1 :: Prefetch

        //              Variable declarations

        //

        reg     [(AW-1):0]       pf_pc;

        reg     new_pc;

        wire    clear_pipeline;

        assign  clear_pipeline = new_pc;

        wire            dcd_stalled;

        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;

        wire    [(AW-1):0]       pf_addr;

        wire    [31:0]           pf_data;

        wire    [31:0]           instruction;

        wire    [(AW-1):0]       instruction_pc;

        wire    pf_valid, instruction_gie, pf_illegal;

        //

        //

        //      PIPELINE STAGE #2 :: Instruction Decode

        //              Variable declarations

        //

        //

        wire            op_stall, dcd_ce, dcd_phase;

        wire    [3:0]    dcdOp;

        wire    [4:0]    dcd_iA, dcd_iB, dcd_iR;

        wire            dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;

        wire    [3:0]    dcdF;

        wire            dcd_wR, dcd_rA, dcd_rB,

                                dcdALU, dcdM, dcdDV, dcdFP,

                                dcdF_wr, dcd_gie, dcd_break, dcd_lock,

                                dcd_pipe, dcd_ljmp;

        reg     [1:0]    r_dcdvalid;

        wire            dcd_valid;

        wire    [(AW-1):0]       dcd_pc;

        wire    [31:0]   dcd_I;

        wire            dcd_zI; // true if dcdI == 0

        wire    dcdA_stall, dcdB_stall, dcdF_stall;

        wire    dcd_illegal;

        wire                    dcd_early_branch;

        wire    [(AW-1):0]       dcd_branch_pc;

        //

        //

        //      PIPELINE STAGE #3a :: Read Operands

        //              Variable declarations

        //

        //

        //

        // Now, let's read our operands

        reg             opa_valid, opa_DV, opa_FP, opa_ALU, opa_M,

                        opa_rA, opa_rB;

        reg     [4:0]    alu_reg;

        reg     [3:0]    opa_opn;

        reg     [4:0]    opa_R, opa_iA;

        reg     [31:0]   r_opa_B;

        reg     [(AW-1):0]       opa_pc;

        wire    [31:0]   opA_nowait, opa_Bnowait, opa_A, opa_B, opa_I;

        reg             opa_wR, opa_ccR, opa_wF, opa_gie;

        wire    [13:0]   opa_Fl;

        reg     [5:0]    r_opa_F;

        wire    [7:0]    opa_F;

        wire            opa_ce, opa_phase, opa_pipe;

        // Some pipeline control wires

        reg     opa_A_alu, opa_A_mem;

        reg     opa_B_alu, opa_B_mem;

`ifdef  OPT_ILLEGAL_INSTRUCTION

        reg     opa_illegal;

`else

        wire    opa_illegal;

        assign  opa_illegal = 1'b0;

`endif

        reg     opa_break;

        reg     opa_lock;

        //

        //

        //      PIPELINE STAGE #3b :: Read Operands

        //              Variable declarations

        //

        //

        //

        // Now, let's read our operands

        reg     [3:0]    opb_opn;

        reg             opb_valid, opb_valid_mem, opb_valid_alu;

        reg             opb_valid_div, opb_valid_fpu;

        reg     [4:0]    opb_R;

        reg     [31:0]   r_opb_A, r_opb_B;

        reg     [(AW-1):0]       opb_pc;

        wire    [31:0]   opb_A_nowait, opb_B_nowait, opb_A, opb_B;

        reg             opb_wR, opb_ccR, opb_wF, opb_gie;

        wire    [13:0]   opb_Fl;

        reg     [5:0]    r_opb_F;

        wire    [7:0]    opb_F;

        wire            opb_ce, opb_phase, opb_pipe;

        // Some pipeline control wires

        reg     opb_A_alu, opb_A_mem;

        reg     opb_B_alu, opb_B_mem;

`ifdef  OPT_ILLEGAL_INSTRUCTION

        reg     opb_illegal;

`else

        wire    opb_illegal;

        assign  opb_illegal = 1'b0;

`endif

        reg     opb_break;

        reg     opb_lock;

        //

        //

        //      PIPELINE STAGE #4 :: ALU / Memory / Divide

        //              Variable declarations

        //

        //

        reg     [(AW-1):0]       alu_pc;

        reg             r_alu_pc_valid, mem_pc_valid;

        wire            alu_pc_valid;

        wire            alu_phase;

        wire            alu_ce, alu_stall;

        wire    [31:0]   alu_result;

        wire    [3:0]    alu_flags;

        wire            alu_valid, alu_busy;

        wire            set_cond;

        reg             alu_wr, alF_wr, alu_gie;

        wire            alu_illegal_op;

        wire            alu_illegal;

        wire    mem_ce, mem_stalled;

        wire    mem_pipe_stalled;

        wire    mem_valid, mem_ack, mem_stall, mem_err, bus_err,

                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;

        wire    [4:0]            mem_wreg;

        wire                    mem_busy, mem_rdbusy;

        wire    [(AW-1):0]       mem_addr;

        wire    [31:0]           mem_data, mem_result;

        wire    div_ce, div_error, div_busy, div_valid;

        wire    [31:0]   div_result;

        wire    [3:0]    div_flags;

        assign  div_ce = (master_ce)&&(~clear_pipeline)&&(opb_valid_div)

                                &&(~stage_busy)&&(set_cond);

        wire    fpu_ce, fpu_error, fpu_busy, fpu_valid;

        wire    [31:0]   fpu_result;

        wire    [3:0]    fpu_flags;

        assign  fpu_ce = (master_ce)&&(~clear_pipeline)&&(opb_valid_fpu)

                                &&(~stage_busy)&&(set_cond);

        //

        //

        //      PIPELINE STAGE #5 :: Write-back

        //              Variable declarations

        //

        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;

        wire    [4:0]    wr_reg_id;

        wire    [31:0]   wr_gpreg_vl, wr_spreg_vl;

        wire    w_switch_to_interrupt, w_release_from_interrupt;

        reg     [(AW-1):0]       upc, ipc;

        //

        //      MASTER: clock enable.

        //

        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep);

        //

        //      PIPELINE STAGE #1 :: Prefetch

        //              Calculate stall conditions

        //

        //      These are calculated externally, within the prefetch module.

        //

        //

        //      PIPELINE STAGE #2 :: Instruction Decode

        //              Calculate stall conditions

        assign          dcd_ce = ((~dcd_valid)||(~dcd_stalled))&&(~clear_pipeline);

        assign          dcd_stalled = (dcd_valid)&&(op_stall);

        //

        //      PIPELINE STAGE #3 :: Read Operands

        //              Calculate stall conditions

        wire    op_lock_stall;

        assign  op_stall = (opvalid)&&( // Only stall if we're loaded w/validins

                        // Stall if we're stopped, and not allowed to execute

                        // an instruction

                        // (~master_ce)         // Already captured in alu_stall

                        //

                        // Stall if going into the ALU and the ALU is stalled

                        //      i.e. if the memory is busy, or we are single

                        //      stepping.  This also includes our stalls for

                        //      op_break and op_lock, so we don't need to

                        //      include those as well here.

                        // This also includes whether or not the divide or

                        // floating point units are busy.

                        (alu_stall)

                        //

                        // Stall if we are going into memory with an operation

                        //      that cannot be pipelined, and the memory is

                        //      already busy

                        ||(mem_stalled) // &&(opvalid_mem) part of mem_stalled

                        )

                        ||(dcd_valid)&&(

                                // Stall if we need to wait for an operand A

                                // to be ready to read

                                (dcdA_stall)

                                // Likewise for B, also includes logic

                                // regarding immediate offset (register must

                                // be in register file if we need to add to

                                // an immediate)

                                ||(dcdB_stall)

                                // Or if we need to wait on flags to work on the

                                // CC register

                                ||(dcdF_stall)

                        );

        assign  opa_ce = ((dcd_valid)||(dcd_illegal))&&(~opa_stall);

        //

        //      PIPELINE STAGE #4 :: ALU / Memory

        //              Calculate stall conditions

        //

        // 1. Basic stall is if the previous stage is valid and the next is

        //      busy.  

        // 2. Also stall if the prior stage is valid and the master clock enable

        //      is de-selected

        // 3. Stall if someone on the other end is writing the CC register,

        //      since we don't know if it'll put us to sleep or not.

        // 4. Last case: Stall if we would otherwise move a break instruction

        //      through the ALU.  Break instructions are not allowed through

        //      the ALU.

        assign  alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2

                        // Old case #3--this isn't an ALU stall though ...

                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)

                                &&(wr_write_cc)) // Case 3

                        ||((opvalid)&&(op_lock)&&(op_lock_stall))

                        ||((opvalid)&&(op_break))

                        ||(div_busy)||(fpu_busy);

        assign  alu_ce = (master_ce)&&(stage_ce)&&(opvalid_alu)&&(~clear_pipeline);

        assign  stage_ce = (~div_busy)&&(~alu_busy)&&(~mem_rdbusy)&&(~fpu_busy);

        //

        //

        // Note: if you change the conditions for mem_ce, you must also change

        // alu_pc_valid.

        //

        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)

                        &&(~clear_pipeline);

        assign  mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(

                                (mem_pipe_stalled)

                                ||((~op_pipe)&&(mem_busy))

                                ||(div_busy)

                                ||(fpu_busy)

                                // Stall waiting for flags to be valid

                                // Or waiting for a write to the PC register

                                // Or CC register, since that can change the

                                //  PC as well

                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)

                                        &&((wr_write_pc)||(wr_write_cc)))));

        //

        //

        //      PIPELINE STAGE #1 :: Prefetch

        //

        //

        fastcache #(LGICACHE, ADDRESS_WIDTH)

                pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),

                                        i_clear_pf_cache,

                                // dcd_pc,

                                ~dcd_stalled,

                                ((dcd_early_branch)&&(~clear_pipeline))

                                        ? dcd_branch_pc:pf_pc,

                                instruction, instruction_pc, pf_valid,

                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,

                                        pf_ack, pf_stall, pf_err, i_wb_data,

                                pf_illegal);

        assign  instruction_gie = gie;

        //

        // The ifastdec decoder takes two clocks to decode an instruction.

        // Therefore, to determine if a decoded instruction is valid, we

        // need to wait two clocks from pf_valid.  Hence, we dump this into

        // a pipeline below.

        //

        initial r_dcdvalid = 2'b00;

        always @(posedge i_clk)

                if ((i_rst)||(clear_pipeline)||(w_clear_icache))

                        r_dcdvalid <= 2'b00;

                else if (dcd_ce)

                        r_dcdvalid <= { r_dcdvalid[0], pf_valid };

                else if (opa_ce)

                        r_dcdvalid <= 1'b0;

        assign  dcd_valid = r_dcdvalid[1];

        ifastdec #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,

                        IMPLEMENT_FPU)

                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),

                        dcd_ce, dcd_stalled, instruction, instruction_gie,

                        instruction_pc, pf_valid, pf_illegal, dcd_phase,

                        dcd_illegal, dcd_pc, dcd_gie,

                        { dcdR_cc, dcdR_pc, dcd_iR },

                        { dcdA_cc, dcdA_pc, dcd_iA },

                        { dcdB_cc, dcdB_pc, dcd_iB },

                        dcd_I, dcd_zI, dcdF, dcdF_wr, dcdOp,

                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,

                        dcd_wR,dcd_rA, dcd_rB,

                        dcd_early_branch,

                        dcd_branch_pc, dcd_ljmp,

                        dcd_pipe);

        reg             r_op_pipe;

        initial r_op_pipe = 1'b0;

        // To be a pipeable operation, there must be 

        //      two valid adjacent instructions

        //      Both must be memory instructions

        //      Both must be writes, or both must be reads

        //      Both operations must be to the same identical address,

        //              or at least a single (one) increment above that address

        //

        // However ... we need to know this before this clock, hence this is

        // calculated in the instruction decoder.

        always @(posedge i_clk)

                if (op_ce)

                        r_op_pipe <= dcd_pipe;

                else if (mem_ce) // Clear us any time an op_ is clocked in

                        r_op_pipe <= 1'b0;

        assign  op_pipe = r_op_pipe;

        //

        //

        //      PIPELINE STAGE #3 :: Read Operands (Registers)

        //

        //

        assign  w_opA = regset[dcd_iA];

        assign  w_opB = regset[dcd_iB];

        wire    [8:0]    w_cpu_info;

        assign  w_cpu_info = {

`ifdef  OPT_ILLEGAL_INSTRUCTION

        1'b1,

`else

        1'b0,

`endif

        1'b1,

`ifdef  OPT_DIVIDE

        1'b1,

`else

        1'b0,

`endif

`ifdef  OPT_IMPLEMENT_FPU

        1'b1,

`else

        1'b0,

`endif

        1'b1, 1'b1,

`ifdef  OPT_EARLY_BRANCHING

        1'b1,

`else

        1'b0,

`endif

        1'b1,

`ifdef  OPT_VLIW

        1'b1

`else

        1'b0

`endif

        };

        wire    [31:0]   w_pcA_v;

        generate

        if (AW < 32)

                assign  w_pcA_v = {{(32-AW){1'b0}}, (dcd_iA[4] == dcd_gie)?dcd_pc:upc };

        else

                assign  w_pcA_v = (dcd_iA[4] == dcd_gie)?dcd_pc:upc;

        endgenerate

        reg     [4:0]    opa_Aid, opa_Bid;

        reg             opa_Ard, opa_Brd;

        always @(posedge i_clk)

                if (opa_ce)

                begin

                        opa_iA <= dcd_iA;

                        opa_iB <= dcd_iB;

                        opa_rA <= dcd_rA;

                        opa_rB <= dcd_rB;

                end

        always @(posedge i_clk)

                if (opa_ce)

                begin

                        if ((wr_reg_ce)&&(wr_reg_id == dcd_iA))

                                r_opA <= wr_gpreg_vl;

                        else if (dcdA_pc)

                                r_opA <= w_pcA_v;

                        else if (dcdA_cc)

                                r_opA <= { w_cpu_info, w_opA[22:15], (dcd_iA[4])?w_uflags:w_iflags };

                        else

                                r_opA <= w_opA;

                end else if ((wr_reg_ce)&&(wr_reg_id == opa_iA)&&(opa_rA))

                                r_opA <= wr_gpreg_vl;

        wire    [31:0]   w_opBnI, w_pcB_v;

        generate

        if (AW < 32)

                assign  w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };

        else

                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;

        endgenerate

        always @(posedge i_clk)

                if (opa_ce)

                begin

                        opa_B <= (~dcdB_rd) ? 32'h00

                        : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_gpreg_vl

                        : ((dcdB_pc) ? w_pcB_v

                        : ((dcdB_cc) ? { w_cpu_info, w_opB[22:14], // w_opB[31:14],

                                (dcdB[4])?w_uflags:w_iflags}

                        : w_opB)));

                        opa_I <= dcd_I;

                end

//

//      B-Inflight

//

//      We cannot read the B register if it is "in-flight", that is if the

//      result register of any previous instruction still needs to be written.

//

//      reg     [31:0]  opa_b_inflight;

//      always @(posedge i_clk)

//              if ((i_reset)||(clear_pipeline))

//                      opa_b_inflight <= 32'h00;